Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7188218

1

T1

19

T2

15

T4

4356

auto[1]

2739680

1

T1

19

T2

30

T4

3151

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2865244

1

T1

16

T2

21

T4

4580

auto[1]

7062654

1

T1

22

T2

24

T4

2927

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5740448

1

T1

19

T2

21

T4

2402

auto[1]

4187450

1

T1

19

T2

24

T4

5105

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	8095006	1			T1	10		T2	10		T4	6930
fifo_depth[1]	315894	1			T4	130		T5	57		T9	319
fifo_depth[2]	246744	1			T4	136		T5	76		T9	282
fifo_depth[3]	190715	1			T4	87		T5	59		T9	304
fifo_depth[4]	157326	1			T4	65		T5	78		T9	304
fifo_depth[5]	134406	1			T4	36		T5	60		T9	326
fifo_depth[6]	125782	1			T4	40		T5	70		T9	304
fifo_depth[7]	110982	1			T4	40		T5	76		T9	301

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1832892

1

T1

28

T2

35

T4

577

auto[1]

8095006

1

T1

10

T2

10

T4

6930

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9915583

1

T1

38

T2

43

T4

7507

auto[1]

12315

1

T2

2

T20

1

T10

1

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

78463

1

T1

3

T2

2

T4

79

auto[0]

auto[0]

auto[0]

auto[1]

79425

1

T1

3

T2

5

T6

34

auto[0]

auto[0]

auto[1]

auto[0]

778970

1

T1

5

T2

5

T4

63

auto[0]

auto[0]

auto[1]

auto[1]

81429

1

T1

4

T2

5

T6

100

auto[0]

auto[1]

auto[0]

auto[0]

209355

1

T1

2

T2

1

T6

53

auto[0]

auto[1]

auto[0]

auto[1]

206276

1

T1

5

T2

9

T4

320

auto[0]

auto[1]

auto[1]

auto[0]

194630

1

T1

3

T2

3

T4

69

auto[0]

auto[1]

auto[1]

auto[1]

204344

1

T1

3

T2

5

T4

46

auto[1]

auto[0]

auto[0]

auto[0]

284768

1

T4

650

T6

673

T7

5237

auto[1]

auto[0]

auto[0]

auto[1]

276391

1

T2

1

T4

833

T6

492

auto[1]

auto[0]

auto[1]

auto[0]

3901606

1

T1

3

T2

1

T4

339

auto[1]

auto[0]

auto[1]

auto[1]

259396

1

T1

1

T2

2

T4

438

auto[1]

auto[1]

auto[0]

auto[0]

897023

1

T1

1

T4

1642

T5

3796

auto[1]

auto[1]

auto[0]

auto[1]

833543

1

T1

2

T2

3

T4

1056

auto[1]

auto[1]

auto[1]

auto[0]

843403

1

T1

2

T2

3

T4

1514

auto[1]

auto[1]

auto[1]

auto[1]

798876

1

T1

1

T4

458

T5

1110

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

361725

1

T1

3

T2

2

T4

729

auto[0]

auto[0]

auto[0]

auto[1]

354920

1

T1

3

T2

6

T4

833

auto[0]

auto[0]

auto[1]

auto[0]

4678530

1

T1

8

T2

6

T4

402

auto[0]

auto[0]

auto[1]

auto[1]

339709

1

T1

5

T2

7

T4

438

auto[0]

auto[1]

auto[0]

auto[0]

1104392

1

T1

3

T2

1

T4

1642

auto[0]

auto[1]

auto[0]

auto[1]

1038103

1

T1

7

T2

11

T4

1376

auto[0]

auto[1]

auto[1]

auto[0]

1037474

1

T1

5

T2

5

T4

1583

auto[0]

auto[1]

auto[1]

auto[1]

1000730

1

T1

4

T2

5

T4

504

auto[1]

auto[0]

auto[0]

auto[0]

1506

1

T25

11

T26

61

T36

98

auto[1]

auto[0]

auto[0]

auto[1]

896

1

T26

43

T32

1

T36

153

auto[1]

auto[0]

auto[1]

auto[0]

2046

1

T20

1

T33

2

T35

1

auto[1]

auto[0]

auto[1]

auto[1]

1116

1

T10

1

T25

1

T26

6

auto[1]

auto[1]

auto[0]

auto[0]

1986

1

T25

498

T36

14

T112

32

auto[1]

auto[1]

auto[0]

auto[1]

1716

1

T2

1

T25

1

T26

37

auto[1]

auto[1]

auto[1]

auto[0]

559

1

T2

1

T32

1

T36

13

auto[1]

auto[1]

auto[1]

auto[1]

2490

1

T25

2

T26

40

T34

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	284768	1			T4	650		T6	673		T7	5237
fifo_depth[0]	auto[0]	auto[0]	auto[1]	276391	1			T2	1		T4	833		T6	492
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3901606	1			T1	3		T2	1		T4	339
fifo_depth[0]	auto[0]	auto[1]	auto[1]	259396	1			T1	1		T2	2		T4	438
fifo_depth[0]	auto[1]	auto[0]	auto[0]	897023	1			T1	1		T4	1642		T5	3796
fifo_depth[0]	auto[1]	auto[0]	auto[1]	833543	1			T1	2		T2	3		T4	1056
fifo_depth[0]	auto[1]	auto[1]	auto[0]	843403	1			T1	2		T2	3		T4	1514
fifo_depth[0]	auto[1]	auto[1]	auto[1]	798876	1			T1	1		T4	458		T5	1110
fifo_depth[1]	auto[0]	auto[0]	auto[0]	8962	1			T4	23		T6	24		T7	47
fifo_depth[1]	auto[0]	auto[0]	auto[1]	8414	1			T6	17		T7	45		T88	1
fifo_depth[1]	auto[0]	auto[1]	auto[0]	199680	1			T4	20		T6	20		T7	1988
fifo_depth[1]	auto[0]	auto[1]	auto[1]	8407	1			T6	54		T7	119		T88	5
fifo_depth[1]	auto[1]	auto[0]	auto[0]	23532	1			T6	24		T7	72		T8	6
fifo_depth[1]	auto[1]	auto[0]	auto[1]	22195	1			T4	43		T9	28		T6	10
fifo_depth[1]	auto[1]	auto[1]	auto[0]	22310	1			T4	29		T6	3		T7	15
fifo_depth[1]	auto[1]	auto[1]	auto[1]	22394	1			T4	15		T5	57		T9	291
fifo_depth[2]	auto[0]	auto[0]	auto[0]	7337	1			T4	25		T6	6		T7	16
fifo_depth[2]	auto[0]	auto[0]	auto[1]	7110	1			T6	10		T7	20		T18	18
fifo_depth[2]	auto[0]	auto[1]	auto[0]	143661	1			T4	29		T6	15		T7	656
fifo_depth[2]	auto[0]	auto[1]	auto[1]	7089	1			T6	25		T7	85		T88	4
fifo_depth[2]	auto[1]	auto[0]	auto[0]	20819	1			T6	16		T7	46		T8	5
fifo_depth[2]	auto[1]	auto[0]	auto[1]	19937	1			T4	46		T9	22		T6	4
fifo_depth[2]	auto[1]	auto[1]	auto[0]	20247	1			T4	24		T6	1		T7	15
fifo_depth[2]	auto[1]	auto[1]	auto[1]	20544	1			T4	12		T5	76		T9	260
fifo_depth[3]	auto[0]	auto[0]	auto[0]	5522	1			T4	15		T6	3		T7	12
fifo_depth[3]	auto[0]	auto[0]	auto[1]	5262	1			T6	6		T7	9		T18	5
fifo_depth[3]	auto[0]	auto[1]	auto[0]	104255	1			T4	11		T6	4		T7	171
fifo_depth[3]	auto[0]	auto[1]	auto[1]	5330	1			T6	11		T7	16		T88	4
fifo_depth[3]	auto[1]	auto[0]	auto[0]	18084	1			T6	9		T7	16		T88	17
fifo_depth[3]	auto[1]	auto[0]	auto[1]	17317	1			T4	35		T9	21		T6	2
fifo_depth[3]	auto[1]	auto[1]	auto[0]	17267	1			T4	14		T6	2		T7	11
fifo_depth[3]	auto[1]	auto[1]	auto[1]	17678	1			T4	12		T5	59		T9	283
fifo_depth[4]	auto[0]	auto[0]	auto[0]	5075	1			T4	15		T6	2		T7	3
fifo_depth[4]	auto[0]	auto[0]	auto[1]	4937	1			T6	1		T7	2		T18	5
fifo_depth[4]	auto[0]	auto[1]	auto[0]	74394	1			T4	3		T6	1		T7	42
fifo_depth[4]	auto[0]	auto[1]	auto[1]	5241	1			T6	8		T7	15		T88	18
fifo_depth[4]	auto[1]	auto[0]	auto[0]	17130	1			T6	4		T7	19		T88	22
fifo_depth[4]	auto[1]	auto[0]	auto[1]	16876	1			T4	42		T9	19		T6	1
fifo_depth[4]	auto[1]	auto[1]	auto[0]	16451	1			T4	2		T6	3		T7	9
fifo_depth[4]	auto[1]	auto[1]	auto[1]	17222	1			T4	3		T5	78		T9	285
fifo_depth[5]	auto[0]	auto[0]	auto[0]	4164	1			T4	1		T7	4		T25	34
fifo_depth[5]	auto[0]	auto[0]	auto[1]	3950	1			T18	2		T25	2		T26	13
fifo_depth[5]	auto[0]	auto[1]	auto[0]	59705	1			T6	1		T7	11		T19	1363
fifo_depth[5]	auto[0]	auto[1]	auto[1]	4180	1			T6	1		T7	6		T88	3
fifo_depth[5]	auto[1]	auto[0]	auto[0]	15642	1			T7	5		T8	1		T88	9
fifo_depth[5]	auto[1]	auto[0]	auto[1]	15710	1			T4	33		T9	30		T6	1
fifo_depth[5]	auto[1]	auto[1]	auto[0]	15080	1			T7	6		T8	1		T70	100
fifo_depth[5]	auto[1]	auto[1]	auto[1]	15975	1			T4	2		T5	60		T9	296
fifo_depth[6]	auto[0]	auto[0]	auto[0]	4216	1			T7	5		T25	30		T26	17
fifo_depth[6]	auto[0]	auto[0]	auto[1]	3865	1			T18	1		T25	2		T26	14
fifo_depth[6]	auto[0]	auto[1]	auto[0]	50968	1			T7	2		T19	1254		T98	1072
fifo_depth[6]	auto[0]	auto[1]	auto[1]	4219	1			T6	1		T7	6		T88	4
fifo_depth[6]	auto[1]	auto[0]	auto[0]	15806	1			T7	7		T88	3		T71	94
fifo_depth[6]	auto[1]	auto[0]	auto[1]	15774	1			T4	38		T9	23		T7	4
fifo_depth[6]	auto[1]	auto[1]	auto[0]	15287	1			T7	1		T70	84		T88	4
fifo_depth[6]	auto[1]	auto[1]	auto[1]	15647	1			T4	2		T5	70		T9	281
fifo_depth[7]	auto[0]	auto[0]	auto[0]	3898	1			T7	1		T25	35		T26	10
fifo_depth[7]	auto[0]	auto[0]	auto[1]	3267	1			T26	16		T72	28		T63	25
fifo_depth[7]	auto[0]	auto[1]	auto[0]	40855	1			T7	2		T19	1033		T88	1
fifo_depth[7]	auto[0]	auto[1]	auto[1]	3943	1			T7	3		T88	6		T25	8
fifo_depth[7]	auto[1]	auto[0]	auto[0]	14954	1			T7	2		T71	100		T25	40
fifo_depth[7]	auto[1]	auto[0]	auto[1]	14983	1			T4	40		T9	29		T7	1
fifo_depth[7]	auto[1]	auto[1]	auto[0]	14309	1			T7	3		T70	74		T88	2
fifo_depth[7]	auto[1]	auto[1]	auto[1]	14773	1			T5	76		T9	272		T7	1