Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15397583	1			T1	96		T2	617		T4	30483
all_pins[1]	15397583	1			T1	96		T2	617		T4	30483
all_pins[2]	15397583	1			T1	96		T2	617		T4	30483

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	38522196	1			T1	236		T2	1786		T4	68266
values[0x1]	7670553	1			T1	52		T2	65		T4	23183
transitions[0x0=>0x1]	7670394	1			T1	52		T2	65		T4	23183
transitions[0x1=>0x0]	7670402	1			T1	52		T2	65		T4	23183

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15358777	1			T1	64		T2	572		T4	30477
all_pins[0]	values[0x1]	38806	1			T1	32		T2	45		T4	6
all_pins[0]	transitions[0x0=>0x1]	38734	1			T1	32		T2	45		T4	6
all_pins[0]	transitions[0x1=>0x0]	7631380	1			T1	20		T2	20		T4	23177
all_pins[1]	values[0x0]	15397280	1			T1	96		T2	617		T4	30483
all_pins[1]	values[0x1]	303	1			T26	1		T27	2		T40	4
all_pins[1]	transitions[0x0=>0x1]	259	1			T26	1		T27	2		T40	3
all_pins[1]	transitions[0x1=>0x0]	38762	1			T1	32		T2	45		T4	6
all_pins[2]	values[0x0]	7766139	1			T1	76		T2	597		T4	7306
all_pins[2]	values[0x1]	7631444	1			T1	20		T2	20		T4	23177
all_pins[2]	transitions[0x0=>0x1]	7631401	1			T1	20		T2	20		T4	23177
all_pins[2]	transitions[0x1=>0x0]	260	1			T26	1		T27	2		T40	4