Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 849 1 T27 14 T40 7 T36 21
all_values[1] 849 1 T27 14 T40 7 T36 21
all_values[2] 849 1 T27 14 T40 7 T36 21


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1240 1 T27 23 T40 6 T36 39
auto[1] 1307 1 T27 19 T40 15 T36 24


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 956 1 T27 27 T40 4 T36 26
auto[1] 1591 1 T27 15 T40 17 T36 37


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1467 1 T27 31 T40 8 T36 39
auto[1] 1080 1 T27 11 T40 13 T36 24


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 155 1 T27 6 T36 5 T11 5
all_values[0] auto[0] auto[0] auto[1] 62 1 T36 4 T11 2 T51 1
all_values[0] auto[0] auto[1] auto[0] 170 1 T27 4 T40 1 T36 5
all_values[0] auto[0] auto[1] auto[1] 81 1 T27 1 T11 5 T12 1
all_values[0] auto[1] auto[0] auto[1] 188 1 T27 1 T40 4 T36 3
all_values[0] auto[1] auto[1] auto[1] 193 1 T27 2 T40 2 T36 4
all_values[1] auto[0] auto[0] auto[0] 156 1 T27 6 T40 1 T36 4
all_values[1] auto[0] auto[0] auto[1] 90 1 T27 1 T36 3 T91 1
all_values[1] auto[0] auto[1] auto[0] 152 1 T27 4 T36 3 T11 3
all_values[1] auto[0] auto[1] auto[1] 111 1 T27 1 T40 2 T36 2
all_values[1] auto[1] auto[0] auto[1] 175 1 T27 1 T36 5 T11 8
all_values[1] auto[1] auto[1] auto[1] 165 1 T27 1 T40 4 T36 4
all_values[2] auto[0] auto[0] auto[0] 168 1 T27 4 T36 8 T91 1
all_values[2] auto[0] auto[0] auto[1] 78 1 T27 1 T36 1 T11 5
all_values[2] auto[0] auto[1] auto[0] 155 1 T27 3 T40 2 T36 1
all_values[2] auto[0] auto[1] auto[1] 89 1 T40 2 T36 3 T11 1
all_values[2] auto[1] auto[0] auto[1] 168 1 T27 3 T40 1 T36 6
all_values[2] auto[1] auto[1] auto[1] 191 1 T27 3 T40 2 T36 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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