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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.85 94.84 92.25 100.00 74.36 89.38 99.49 71.61


Total test records in report: 729
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T532 /workspace/coverage/default/20.hmac_burst_wr.908429480 Jun 09 01:44:28 PM PDT 24 Jun 09 01:45:03 PM PDT 24 9988224376 ps
T533 /workspace/coverage/default/45.hmac_datapath_stress.1240569830 Jun 09 01:46:13 PM PDT 24 Jun 09 01:58:46 PM PDT 24 6470134055 ps
T534 /workspace/coverage/default/49.hmac_long_msg.3107453294 Jun 09 01:46:30 PM PDT 24 Jun 09 01:46:52 PM PDT 24 1149535847 ps
T535 /workspace/coverage/default/42.hmac_long_msg.3054741520 Jun 09 01:45:55 PM PDT 24 Jun 09 01:47:20 PM PDT 24 6100943348 ps
T536 /workspace/coverage/default/0.hmac_error.1349948134 Jun 09 01:43:41 PM PDT 24 Jun 09 01:45:14 PM PDT 24 27605305083 ps
T537 /workspace/coverage/default/7.hmac_long_msg.850472318 Jun 09 01:43:52 PM PDT 24 Jun 09 01:44:57 PM PDT 24 1096814201 ps
T538 /workspace/coverage/default/39.hmac_alert_test.3367078822 Jun 09 01:45:48 PM PDT 24 Jun 09 01:45:48 PM PDT 24 37189156 ps
T539 /workspace/coverage/default/29.hmac_burst_wr.2901240979 Jun 09 01:44:56 PM PDT 24 Jun 09 01:45:54 PM PDT 24 17168142774 ps
T540 /workspace/coverage/default/6.hmac_smoke.134234127 Jun 09 01:43:55 PM PDT 24 Jun 09 01:44:01 PM PDT 24 1085998112 ps
T541 /workspace/coverage/default/29.hmac_stress_all.1783509247 Jun 09 01:45:01 PM PDT 24 Jun 09 01:50:29 PM PDT 24 36739713447 ps
T542 /workspace/coverage/default/10.hmac_alert_test.2302152525 Jun 09 01:44:02 PM PDT 24 Jun 09 01:44:02 PM PDT 24 11367551 ps
T543 /workspace/coverage/default/33.hmac_alert_test.856244827 Jun 09 01:45:22 PM PDT 24 Jun 09 01:45:23 PM PDT 24 11907543 ps
T544 /workspace/coverage/default/18.hmac_test_hmac_vectors.1303039678 Jun 09 01:44:15 PM PDT 24 Jun 09 01:44:16 PM PDT 24 87923836 ps
T545 /workspace/coverage/default/19.hmac_alert_test.1879785220 Jun 09 01:44:22 PM PDT 24 Jun 09 01:44:23 PM PDT 24 43053850 ps
T546 /workspace/coverage/default/49.hmac_wipe_secret.1660909531 Jun 09 01:46:33 PM PDT 24 Jun 09 01:47:50 PM PDT 24 16394151487 ps
T547 /workspace/coverage/default/15.hmac_wipe_secret.3946307871 Jun 09 01:44:11 PM PDT 24 Jun 09 01:44:29 PM PDT 24 1810386638 ps
T548 /workspace/coverage/default/45.hmac_stress_all.3053773265 Jun 09 01:46:13 PM PDT 24 Jun 09 01:53:01 PM PDT 24 28298138073 ps
T549 /workspace/coverage/default/22.hmac_alert_test.3832554321 Jun 09 01:44:33 PM PDT 24 Jun 09 01:44:34 PM PDT 24 48257361 ps
T550 /workspace/coverage/default/4.hmac_smoke.3539587047 Jun 09 01:43:48 PM PDT 24 Jun 09 01:43:55 PM PDT 24 168965121 ps
T551 /workspace/coverage/default/39.hmac_stress_all.648127114 Jun 09 01:45:45 PM PDT 24 Jun 09 02:23:32 PM PDT 24 38679709978 ps
T552 /workspace/coverage/default/42.hmac_stress_all.84083783 Jun 09 01:45:55 PM PDT 24 Jun 09 02:08:48 PM PDT 24 76445437029 ps
T553 /workspace/coverage/default/0.hmac_datapath_stress.678080824 Jun 09 01:43:42 PM PDT 24 Jun 09 01:59:02 PM PDT 24 32977865152 ps
T554 /workspace/coverage/default/14.hmac_alert_test.3996359259 Jun 09 01:44:07 PM PDT 24 Jun 09 01:44:08 PM PDT 24 52581171 ps
T555 /workspace/coverage/default/5.hmac_test_hmac_vectors.2691113160 Jun 09 01:43:52 PM PDT 24 Jun 09 01:43:54 PM PDT 24 301609991 ps
T556 /workspace/coverage/default/0.hmac_long_msg.1346840246 Jun 09 01:43:41 PM PDT 24 Jun 09 01:44:51 PM PDT 24 4901351470 ps
T557 /workspace/coverage/default/26.hmac_alert_test.907335092 Jun 09 01:44:46 PM PDT 24 Jun 09 01:44:47 PM PDT 24 86392767 ps
T558 /workspace/coverage/default/14.hmac_wipe_secret.43093351 Jun 09 01:44:08 PM PDT 24 Jun 09 01:44:37 PM PDT 24 598989926 ps
T559 /workspace/coverage/default/30.hmac_smoke.947007349 Jun 09 01:45:02 PM PDT 24 Jun 09 01:45:07 PM PDT 24 115200478 ps
T560 /workspace/coverage/default/35.hmac_wipe_secret.1084979093 Jun 09 01:45:26 PM PDT 24 Jun 09 01:45:32 PM PDT 24 241353330 ps
T561 /workspace/coverage/default/18.hmac_burst_wr.2015554329 Jun 09 01:44:18 PM PDT 24 Jun 09 01:45:00 PM PDT 24 4421042443 ps
T562 /workspace/coverage/default/31.hmac_test_hmac_vectors.2191543371 Jun 09 01:45:11 PM PDT 24 Jun 09 01:45:12 PM PDT 24 28734223 ps
T563 /workspace/coverage/default/7.hmac_error.4139398073 Jun 09 01:43:53 PM PDT 24 Jun 09 01:46:14 PM PDT 24 20735763948 ps
T564 /workspace/coverage/default/1.hmac_error.4184480208 Jun 09 01:43:39 PM PDT 24 Jun 09 01:45:02 PM PDT 24 44692864044 ps
T565 /workspace/coverage/default/33.hmac_back_pressure.1231868764 Jun 09 01:45:16 PM PDT 24 Jun 09 01:45:54 PM PDT 24 736772252 ps
T566 /workspace/coverage/default/20.hmac_long_msg.353201001 Jun 09 01:44:27 PM PDT 24 Jun 09 01:44:49 PM PDT 24 16505507570 ps
T567 /workspace/coverage/default/45.hmac_alert_test.778426203 Jun 09 01:46:12 PM PDT 24 Jun 09 01:46:12 PM PDT 24 46642993 ps
T568 /workspace/coverage/default/21.hmac_back_pressure.3747918749 Jun 09 01:44:24 PM PDT 24 Jun 09 01:45:11 PM PDT 24 2177819930 ps
T569 /workspace/coverage/default/0.hmac_burst_wr.1994831046 Jun 09 01:43:40 PM PDT 24 Jun 09 01:43:44 PM PDT 24 536163363 ps
T570 /workspace/coverage/default/13.hmac_error.3563449638 Jun 09 01:44:08 PM PDT 24 Jun 09 01:44:41 PM PDT 24 2273584076 ps
T571 /workspace/coverage/default/43.hmac_datapath_stress.809534381 Jun 09 01:46:01 PM PDT 24 Jun 09 01:46:15 PM PDT 24 463913081 ps
T572 /workspace/coverage/default/49.hmac_test_sha_vectors.2209139945 Jun 09 01:46:32 PM PDT 24 Jun 09 01:55:00 PM PDT 24 80356885853 ps
T573 /workspace/coverage/default/28.hmac_back_pressure.209707713 Jun 09 01:44:50 PM PDT 24 Jun 09 01:45:07 PM PDT 24 294753827 ps
T574 /workspace/coverage/default/44.hmac_wipe_secret.15512473 Jun 09 01:46:07 PM PDT 24 Jun 09 01:46:37 PM PDT 24 2015717097 ps
T575 /workspace/coverage/default/9.hmac_back_pressure.800361481 Jun 09 01:43:58 PM PDT 24 Jun 09 01:44:03 PM PDT 24 175172743 ps
T576 /workspace/coverage/default/47.hmac_test_hmac_vectors.1008673997 Jun 09 01:46:27 PM PDT 24 Jun 09 01:46:29 PM PDT 24 56481084 ps
T577 /workspace/coverage/default/28.hmac_stress_all.2909527849 Jun 09 01:44:55 PM PDT 24 Jun 09 01:46:47 PM PDT 24 27916490981 ps
T578 /workspace/coverage/default/5.hmac_burst_wr.2722452858 Jun 09 01:43:46 PM PDT 24 Jun 09 01:43:56 PM PDT 24 348781112 ps
T579 /workspace/coverage/default/11.hmac_error.1616165381 Jun 09 01:44:04 PM PDT 24 Jun 09 01:46:48 PM PDT 24 9267306318 ps
T580 /workspace/coverage/default/14.hmac_back_pressure.1458985620 Jun 09 01:44:07 PM PDT 24 Jun 09 01:44:45 PM PDT 24 1386965754 ps
T581 /workspace/coverage/default/46.hmac_long_msg.1451219588 Jun 09 01:46:16 PM PDT 24 Jun 09 01:47:20 PM PDT 24 4081974625 ps
T582 /workspace/coverage/default/9.hmac_alert_test.4066236504 Jun 09 01:43:58 PM PDT 24 Jun 09 01:43:59 PM PDT 24 32364244 ps
T583 /workspace/coverage/default/10.hmac_long_msg.97706945 Jun 09 01:43:58 PM PDT 24 Jun 09 01:45:55 PM PDT 24 5935311704 ps
T584 /workspace/coverage/default/34.hmac_test_hmac_vectors.4161807753 Jun 09 01:45:20 PM PDT 24 Jun 09 01:45:22 PM PDT 24 76706617 ps
T585 /workspace/coverage/default/15.hmac_long_msg.1471076066 Jun 09 01:44:11 PM PDT 24 Jun 09 01:45:19 PM PDT 24 18834342655 ps
T586 /workspace/coverage/default/28.hmac_alert_test.864331836 Jun 09 01:44:56 PM PDT 24 Jun 09 01:44:57 PM PDT 24 20139687 ps
T587 /workspace/coverage/default/45.hmac_long_msg.3891176818 Jun 09 01:46:07 PM PDT 24 Jun 09 01:46:41 PM PDT 24 1820666930 ps
T588 /workspace/coverage/default/37.hmac_long_msg.3402710834 Jun 09 01:45:32 PM PDT 24 Jun 09 01:46:47 PM PDT 24 14463992699 ps
T589 /workspace/coverage/default/44.hmac_smoke.4270894791 Jun 09 01:46:09 PM PDT 24 Jun 09 01:46:13 PM PDT 24 551169368 ps
T590 /workspace/coverage/default/2.hmac_test_hmac_vectors.3136528363 Jun 09 01:43:50 PM PDT 24 Jun 09 01:43:52 PM PDT 24 37765765 ps
T591 /workspace/coverage/default/3.hmac_test_sha_vectors.438518316 Jun 09 01:43:49 PM PDT 24 Jun 09 01:52:36 PM PDT 24 97726671554 ps
T592 /workspace/coverage/default/29.hmac_datapath_stress.2767018561 Jun 09 01:44:56 PM PDT 24 Jun 09 01:45:36 PM PDT 24 1163480222 ps
T593 /workspace/coverage/default/4.hmac_back_pressure.3076688539 Jun 09 01:43:53 PM PDT 24 Jun 09 01:45:06 PM PDT 24 5546304326 ps
T594 /workspace/coverage/default/26.hmac_wipe_secret.1037644303 Jun 09 01:44:47 PM PDT 24 Jun 09 01:45:11 PM PDT 24 5678625176 ps
T595 /workspace/coverage/default/30.hmac_error.2344965816 Jun 09 01:44:59 PM PDT 24 Jun 09 01:45:23 PM PDT 24 1295156155 ps
T41 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3033284019 Jun 09 12:47:44 PM PDT 24 Jun 09 12:47:45 PM PDT 24 30018856 ps
T42 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1027159457 Jun 09 12:48:00 PM PDT 24 Jun 09 12:48:02 PM PDT 24 41124196 ps
T43 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.4133332767 Jun 09 12:47:56 PM PDT 24 Jun 09 12:56:55 PM PDT 24 102563157151 ps
T44 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1771342433 Jun 09 12:47:44 PM PDT 24 Jun 09 12:47:47 PM PDT 24 76404100 ps
T596 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3977664575 Jun 09 12:48:06 PM PDT 24 Jun 09 12:48:07 PM PDT 24 44662354 ps
T597 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.835139376 Jun 09 12:48:00 PM PDT 24 Jun 09 01:07:21 PM PDT 24 115692824250 ps
T598 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2636151459 Jun 09 12:47:51 PM PDT 24 Jun 09 12:47:53 PM PDT 24 85024092 ps
T599 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1715651138 Jun 09 12:47:39 PM PDT 24 Jun 09 12:47:48 PM PDT 24 5040861334 ps
T600 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1959741360 Jun 09 12:47:54 PM PDT 24 Jun 09 12:47:55 PM PDT 24 13746888 ps
T74 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2596564405 Jun 09 12:47:46 PM PDT 24 Jun 09 12:47:48 PM PDT 24 54786594 ps
T601 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2389832450 Jun 09 12:47:40 PM PDT 24 Jun 09 01:00:50 PM PDT 24 219677169217 ps
T602 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1392191754 Jun 09 12:48:00 PM PDT 24 Jun 09 12:48:01 PM PDT 24 11173707 ps
T603 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2020500683 Jun 09 12:47:55 PM PDT 24 Jun 09 12:47:56 PM PDT 24 165342423 ps
T604 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.873295318 Jun 09 12:47:41 PM PDT 24 Jun 09 12:47:44 PM PDT 24 587339717 ps
T605 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2743591445 Jun 09 12:47:50 PM PDT 24 Jun 09 12:47:53 PM PDT 24 117576204 ps
T75 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.995667228 Jun 09 12:47:54 PM PDT 24 Jun 09 12:47:55 PM PDT 24 38312013 ps
T76 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1934310550 Jun 09 12:47:42 PM PDT 24 Jun 09 12:47:43 PM PDT 24 32132973 ps
T606 /workspace/coverage/cover_reg_top/15.hmac_intr_test.222503958 Jun 09 12:47:50 PM PDT 24 Jun 09 12:47:51 PM PDT 24 20482523 ps
T607 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.530312725 Jun 09 12:47:50 PM PDT 24 Jun 09 12:47:54 PM PDT 24 200989016 ps
T77 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.4287123920 Jun 09 12:47:38 PM PDT 24 Jun 09 12:47:39 PM PDT 24 24205963 ps
T608 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2596615087 Jun 09 12:47:49 PM PDT 24 Jun 09 12:47:53 PM PDT 24 166934890 ps
T609 /workspace/coverage/cover_reg_top/34.hmac_intr_test.4087546029 Jun 09 12:48:03 PM PDT 24 Jun 09 12:48:04 PM PDT 24 18959219 ps
T610 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3600958743 Jun 09 12:47:43 PM PDT 24 Jun 09 12:47:45 PM PDT 24 44383883 ps
T611 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2924717788 Jun 09 12:48:03 PM PDT 24 Jun 09 12:48:04 PM PDT 24 23074453 ps
T612 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.17580740 Jun 09 12:47:42 PM PDT 24 Jun 09 12:47:46 PM PDT 24 147358609 ps
T613 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.935236777 Jun 09 12:47:34 PM PDT 24 Jun 09 12:47:40 PM PDT 24 316150860 ps
T614 /workspace/coverage/cover_reg_top/19.hmac_intr_test.825281699 Jun 09 12:48:00 PM PDT 24 Jun 09 12:48:01 PM PDT 24 14126854 ps
T615 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2381125750 Jun 09 12:48:03 PM PDT 24 Jun 09 12:48:04 PM PDT 24 39848465 ps
T616 /workspace/coverage/cover_reg_top/49.hmac_intr_test.415178918 Jun 09 12:48:04 PM PDT 24 Jun 09 12:48:05 PM PDT 24 39806059 ps
T617 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3258573625 Jun 09 12:47:50 PM PDT 24 Jun 09 12:47:54 PM PDT 24 174671423 ps
T83 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.139449597 Jun 09 12:47:43 PM PDT 24 Jun 09 12:47:54 PM PDT 24 3624875433 ps
T37 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3728380335 Jun 09 12:47:36 PM PDT 24 Jun 09 12:47:41 PM PDT 24 1267692310 ps
T618 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3972353380 Jun 09 12:48:02 PM PDT 24 Jun 09 12:48:05 PM PDT 24 164971780 ps
T619 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2475828281 Jun 09 12:47:56 PM PDT 24 Jun 09 12:47:57 PM PDT 24 30985281 ps
T620 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3972486368 Jun 09 12:48:02 PM PDT 24 Jun 09 12:48:03 PM PDT 24 12134089 ps
T621 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2646217912 Jun 09 12:47:50 PM PDT 24 Jun 09 12:57:38 PM PDT 24 57902409598 ps
T622 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1657667754 Jun 09 12:47:52 PM PDT 24 Jun 09 12:47:54 PM PDT 24 160701384 ps
T623 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3404492013 Jun 09 12:47:43 PM PDT 24 Jun 09 12:47:46 PM PDT 24 309862364 ps
T624 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3035217766 Jun 09 12:47:50 PM PDT 24 Jun 09 12:47:51 PM PDT 24 14943141 ps
T38 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3580472461 Jun 09 12:47:50 PM PDT 24 Jun 09 12:47:55 PM PDT 24 241230479 ps
T625 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1567187350 Jun 09 12:48:01 PM PDT 24 Jun 09 12:48:03 PM PDT 24 13497523 ps
T39 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1075128175 Jun 09 12:47:51 PM PDT 24 Jun 09 12:47:55 PM PDT 24 373069654 ps
T104 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.4073589748 Jun 09 12:47:48 PM PDT 24 Jun 09 12:47:51 PM PDT 24 208798686 ps
T626 /workspace/coverage/cover_reg_top/20.hmac_intr_test.4087562903 Jun 09 12:48:00 PM PDT 24 Jun 09 12:48:01 PM PDT 24 38282754 ps
T627 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.565460514 Jun 09 12:47:49 PM PDT 24 Jun 09 12:47:53 PM PDT 24 82985742 ps
T628 /workspace/coverage/cover_reg_top/9.hmac_intr_test.490815280 Jun 09 12:47:49 PM PDT 24 Jun 09 12:47:50 PM PDT 24 46952534 ps
T629 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2135923302 Jun 09 12:47:53 PM PDT 24 Jun 09 12:47:55 PM PDT 24 42432140 ps
T630 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2626081584 Jun 09 12:47:42 PM PDT 24 Jun 09 12:47:43 PM PDT 24 13390285 ps
T631 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3713350342 Jun 09 12:47:53 PM PDT 24 Jun 09 12:47:56 PM PDT 24 133994108 ps
T632 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2826653396 Jun 09 12:47:51 PM PDT 24 Jun 09 12:47:55 PM PDT 24 69524255 ps
T633 /workspace/coverage/cover_reg_top/17.hmac_intr_test.151214552 Jun 09 12:48:00 PM PDT 24 Jun 09 12:48:01 PM PDT 24 13249092 ps
T634 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2563699789 Jun 09 12:47:40 PM PDT 24 Jun 09 12:47:43 PM PDT 24 73496148 ps
T635 /workspace/coverage/cover_reg_top/18.hmac_intr_test.180883783 Jun 09 12:48:06 PM PDT 24 Jun 09 12:48:07 PM PDT 24 14658396 ps
T636 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1720166658 Jun 09 12:47:41 PM PDT 24 Jun 09 12:47:44 PM PDT 24 819697687 ps
T637 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1650682887 Jun 09 12:47:42 PM PDT 24 Jun 09 12:47:45 PM PDT 24 160712938 ps
T638 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1300321311 Jun 09 12:47:58 PM PDT 24 Jun 09 12:48:02 PM PDT 24 158464289 ps
T639 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2484894296 Jun 09 12:47:40 PM PDT 24 Jun 09 12:47:42 PM PDT 24 134966113 ps
T78 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3664579448 Jun 09 12:47:57 PM PDT 24 Jun 09 12:47:58 PM PDT 24 133452945 ps
T640 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3180812833 Jun 09 12:48:07 PM PDT 24 Jun 09 12:48:11 PM PDT 24 164647212 ps
T641 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3338772017 Jun 09 12:47:59 PM PDT 24 Jun 09 12:48:03 PM PDT 24 156383462 ps
T642 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3633646826 Jun 09 12:48:04 PM PDT 24 Jun 09 12:48:05 PM PDT 24 25378357 ps
T79 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.4040385857 Jun 09 12:47:58 PM PDT 24 Jun 09 12:47:59 PM PDT 24 25026946 ps
T643 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1221458169 Jun 09 12:47:38 PM PDT 24 Jun 09 12:47:39 PM PDT 24 42136165 ps
T102 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3340799564 Jun 09 12:47:56 PM PDT 24 Jun 09 12:47:58 PM PDT 24 58942246 ps
T111 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2526566219 Jun 09 12:47:38 PM PDT 24 Jun 09 12:47:40 PM PDT 24 233739528 ps
T644 /workspace/coverage/cover_reg_top/30.hmac_intr_test.3890947723 Jun 09 12:48:02 PM PDT 24 Jun 09 12:48:03 PM PDT 24 59057319 ps
T645 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2167376556 Jun 09 12:47:52 PM PDT 24 Jun 09 12:47:55 PM PDT 24 113782471 ps
T646 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1034680216 Jun 09 12:47:36 PM PDT 24 Jun 09 12:47:41 PM PDT 24 734653749 ps
T647 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1553612475 Jun 09 12:47:55 PM PDT 24 Jun 09 12:47:57 PM PDT 24 54453325 ps
T648 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1572211800 Jun 09 12:48:03 PM PDT 24 Jun 09 12:48:04 PM PDT 24 14183573 ps
T649 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3603236611 Jun 09 12:48:03 PM PDT 24 Jun 09 12:48:06 PM PDT 24 338094637 ps
T650 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.378230909 Jun 09 12:47:59 PM PDT 24 Jun 09 12:48:01 PM PDT 24 58887945 ps
T651 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2959255529 Jun 09 12:47:56 PM PDT 24 Jun 09 12:47:58 PM PDT 24 78660723 ps
T103 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2064425672 Jun 09 12:47:52 PM PDT 24 Jun 09 12:47:55 PM PDT 24 95245066 ps
T652 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1148563672 Jun 09 12:48:03 PM PDT 24 Jun 09 12:48:04 PM PDT 24 14974980 ps
T653 /workspace/coverage/cover_reg_top/35.hmac_intr_test.283306286 Jun 09 12:48:04 PM PDT 24 Jun 09 12:48:05 PM PDT 24 56954412 ps
T654 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1459480398 Jun 09 12:47:36 PM PDT 24 Jun 09 12:47:38 PM PDT 24 25916459 ps
T655 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.530773535 Jun 09 12:47:41 PM PDT 24 Jun 09 12:47:45 PM PDT 24 151910246 ps
T80 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2014762848 Jun 09 12:47:53 PM PDT 24 Jun 09 12:47:54 PM PDT 24 11783795 ps
T656 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2787072997 Jun 09 12:48:06 PM PDT 24 Jun 09 12:48:07 PM PDT 24 18510935 ps
T657 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1729718408 Jun 09 12:47:41 PM PDT 24 Jun 09 12:47:43 PM PDT 24 29502023 ps
T658 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2712192376 Jun 09 12:47:37 PM PDT 24 Jun 09 12:47:38 PM PDT 24 69765315 ps
T659 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1528012284 Jun 09 12:47:53 PM PDT 24 Jun 09 12:47:58 PM PDT 24 1284447855 ps
T660 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1302039155 Jun 09 12:47:56 PM PDT 24 Jun 09 12:47:59 PM PDT 24 180128832 ps
T661 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2878084515 Jun 09 12:47:43 PM PDT 24 Jun 09 12:47:44 PM PDT 24 11426374 ps
T662 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2030886766 Jun 09 12:47:37 PM PDT 24 Jun 09 12:47:42 PM PDT 24 116903810 ps
T81 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1479703626 Jun 09 12:47:45 PM PDT 24 Jun 09 12:47:46 PM PDT 24 137069500 ps
T663 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3043196466 Jun 09 12:48:08 PM PDT 24 Jun 09 12:48:10 PM PDT 24 32001285 ps
T82 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2059418369 Jun 09 12:47:51 PM PDT 24 Jun 09 12:47:52 PM PDT 24 28843317 ps
T664 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2763347165 Jun 09 12:48:00 PM PDT 24 Jun 09 12:48:01 PM PDT 24 35478992 ps
T665 /workspace/coverage/cover_reg_top/31.hmac_intr_test.2408277162 Jun 09 12:48:06 PM PDT 24 Jun 09 12:48:07 PM PDT 24 45649532 ps
T666 /workspace/coverage/cover_reg_top/2.hmac_intr_test.1054213318 Jun 09 12:47:40 PM PDT 24 Jun 09 12:47:41 PM PDT 24 20578016 ps
T667 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1567438083 Jun 09 12:47:53 PM PDT 24 Jun 09 12:47:55 PM PDT 24 21135032 ps
T668 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2351796754 Jun 09 12:47:45 PM PDT 24 Jun 09 12:48:02 PM PDT 24 1097740463 ps
T84 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.337844670 Jun 09 12:47:40 PM PDT 24 Jun 09 12:47:52 PM PDT 24 4381729619 ps
T669 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1916918656 Jun 09 12:47:57 PM PDT 24 Jun 09 12:48:00 PM PDT 24 477224030 ps
T670 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3703910164 Jun 09 12:47:53 PM PDT 24 Jun 09 12:47:55 PM PDT 24 274447415 ps
T671 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4265060684 Jun 09 12:48:07 PM PDT 24 Jun 09 12:48:10 PM PDT 24 47802463 ps
T672 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.134250339 Jun 09 12:47:38 PM PDT 24 Jun 09 12:47:40 PM PDT 24 32672114 ps
T673 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.19660184 Jun 09 12:47:57 PM PDT 24 Jun 09 12:48:00 PM PDT 24 113861127 ps
T85 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2369551163 Jun 09 12:47:45 PM PDT 24 Jun 09 12:47:54 PM PDT 24 1772132154 ps
T105 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.27990978 Jun 09 12:47:49 PM PDT 24 Jun 09 12:47:54 PM PDT 24 475822667 ps
T674 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.436059543 Jun 09 12:47:54 PM PDT 24 Jun 09 12:47:56 PM PDT 24 196724650 ps
T675 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2534353168 Jun 09 12:47:36 PM PDT 24 Jun 09 12:47:43 PM PDT 24 364496477 ps
T676 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2538761598 Jun 09 12:48:04 PM PDT 24 Jun 09 12:48:05 PM PDT 24 50463539 ps
T677 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.713543509 Jun 09 12:47:48 PM PDT 24 Jun 09 12:47:51 PM PDT 24 47839891 ps
T678 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1404551300 Jun 09 12:48:02 PM PDT 24 Jun 09 12:48:03 PM PDT 24 21549594 ps
T679 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2364508020 Jun 09 12:47:54 PM PDT 24 Jun 09 12:47:55 PM PDT 24 19108778 ps
T680 /workspace/coverage/cover_reg_top/39.hmac_intr_test.2300332467 Jun 09 12:48:02 PM PDT 24 Jun 09 12:48:03 PM PDT 24 16550029 ps
T681 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3763850720 Jun 09 12:47:53 PM PDT 24 Jun 09 12:47:55 PM PDT 24 26129713 ps
T682 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1436380584 Jun 09 12:48:01 PM PDT 24 Jun 09 12:48:02 PM PDT 24 24238306 ps
T110 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.428361457 Jun 09 12:47:42 PM PDT 24 Jun 09 12:47:45 PM PDT 24 196961535 ps
T683 /workspace/coverage/cover_reg_top/46.hmac_intr_test.2132658927 Jun 09 12:48:02 PM PDT 24 Jun 09 12:48:03 PM PDT 24 20493389 ps
T684 /workspace/coverage/cover_reg_top/7.hmac_intr_test.731618128 Jun 09 12:47:49 PM PDT 24 Jun 09 12:47:50 PM PDT 24 28594589 ps
T685 /workspace/coverage/cover_reg_top/24.hmac_intr_test.4244613411 Jun 09 12:48:03 PM PDT 24 Jun 09 12:48:05 PM PDT 24 14595591 ps
T686 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1618556023 Jun 09 12:47:35 PM PDT 24 Jun 09 12:47:37 PM PDT 24 36308392 ps
T687 /workspace/coverage/cover_reg_top/38.hmac_intr_test.1225922414 Jun 09 12:48:02 PM PDT 24 Jun 09 12:48:03 PM PDT 24 14035636 ps
T688 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3384566494 Jun 09 12:47:49 PM PDT 24 Jun 09 12:47:52 PM PDT 24 64430237 ps
T689 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3666249765 Jun 09 12:47:37 PM PDT 24 Jun 09 12:47:39 PM PDT 24 91297546 ps
T106 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.425483332 Jun 09 12:47:49 PM PDT 24 Jun 09 12:47:52 PM PDT 24 157883565 ps
T690 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1274353345 Jun 09 12:47:48 PM PDT 24 Jun 09 12:47:51 PM PDT 24 37068599 ps
T691 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.75767591 Jun 09 12:47:56 PM PDT 24 Jun 09 12:47:58 PM PDT 24 112506181 ps
T108 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3851665046 Jun 09 12:47:50 PM PDT 24 Jun 09 12:47:54 PM PDT 24 980165878 ps
T692 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2563394168 Jun 09 12:47:46 PM PDT 24 Jun 09 12:47:49 PM PDT 24 784500028 ps
T693 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1656523764 Jun 09 12:47:44 PM PDT 24 Jun 09 12:47:46 PM PDT 24 172248447 ps
T694 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2829139346 Jun 09 12:48:02 PM PDT 24 Jun 09 12:48:03 PM PDT 24 25587544 ps
T695 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2205407882 Jun 09 12:48:08 PM PDT 24 Jun 09 12:48:08 PM PDT 24 29863498 ps
T86 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3658750404 Jun 09 12:47:48 PM PDT 24 Jun 09 12:47:49 PM PDT 24 32444971 ps
T107 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.212714309 Jun 09 12:47:53 PM PDT 24 Jun 09 12:47:57 PM PDT 24 610201940 ps
T109 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3279059022 Jun 09 12:47:58 PM PDT 24 Jun 09 12:48:00 PM PDT 24 92953528 ps
T696 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2933211377 Jun 09 12:47:52 PM PDT 24 Jun 09 12:47:55 PM PDT 24 111449882 ps
T697 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1208472772 Jun 09 12:47:40 PM PDT 24 Jun 09 12:47:41 PM PDT 24 22776190 ps
T698 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1810282127 Jun 09 12:47:56 PM PDT 24 Jun 09 12:47:59 PM PDT 24 603463922 ps
T699 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3381634910 Jun 09 12:48:01 PM PDT 24 Jun 09 12:48:02 PM PDT 24 60442229 ps
T700 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2998942855 Jun 09 12:47:44 PM PDT 24 Jun 09 12:47:45 PM PDT 24 126739328 ps
T701 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.573194008 Jun 09 12:47:58 PM PDT 24 Jun 09 12:48:00 PM PDT 24 211185629 ps
T702 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1063407968 Jun 09 12:47:39 PM PDT 24 Jun 09 12:47:40 PM PDT 24 26679070 ps
T703 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4116771254 Jun 09 12:47:41 PM PDT 24 Jun 09 12:47:45 PM PDT 24 123410527 ps
T704 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3517427124 Jun 09 12:48:03 PM PDT 24 Jun 09 12:48:04 PM PDT 24 16491541 ps
T705 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2856595517 Jun 09 12:48:00 PM PDT 24 Jun 09 12:48:01 PM PDT 24 161010928 ps
T706 /workspace/coverage/cover_reg_top/40.hmac_intr_test.575193080 Jun 09 12:48:05 PM PDT 24 Jun 09 12:48:05 PM PDT 24 57304704 ps
T707 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3339267373 Jun 09 12:47:54 PM PDT 24 Jun 09 12:47:57 PM PDT 24 69490063 ps
T708 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1309954618 Jun 09 12:47:53 PM PDT 24 Jun 09 12:47:54 PM PDT 24 14803268 ps
T709 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.414711250 Jun 09 12:47:57 PM PDT 24 Jun 09 12:48:01 PM PDT 24 136685615 ps
T710 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1785999305 Jun 09 12:47:54 PM PDT 24 Jun 09 12:47:58 PM PDT 24 1035964326 ps
T711 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2936627026 Jun 09 12:47:41 PM PDT 24 Jun 09 12:47:43 PM PDT 24 558883421 ps
T712 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2314935937 Jun 09 12:47:35 PM PDT 24 Jun 09 12:47:36 PM PDT 24 142732480 ps
T713 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2873968328 Jun 09 12:47:46 PM PDT 24 Jun 09 12:47:48 PM PDT 24 107838420 ps
T714 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.4199499106 Jun 09 12:47:52 PM PDT 24 Jun 09 12:47:53 PM PDT 24 31743616 ps
T715 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2387249978 Jun 09 12:48:06 PM PDT 24 Jun 09 12:48:11 PM PDT 24 123234259 ps
T716 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2176854947 Jun 09 12:47:43 PM PDT 24 Jun 09 12:47:51 PM PDT 24 611309602 ps
T717 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1067535853 Jun 09 12:47:49 PM PDT 24 Jun 09 12:47:52 PM PDT 24 85520112 ps
T718 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1202042883 Jun 09 12:48:02 PM PDT 24 Jun 09 12:48:03 PM PDT 24 13640918 ps
T719 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1633774689 Jun 09 12:47:50 PM PDT 24 Jun 09 12:47:53 PM PDT 24 433428517 ps
T720 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2108019042 Jun 09 12:47:39 PM PDT 24 Jun 09 12:47:41 PM PDT 24 209269155 ps
T87 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.4239721019 Jun 09 12:47:38 PM PDT 24 Jun 09 12:47:39 PM PDT 24 22890042 ps
T721 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1405611830 Jun 09 12:47:49 PM PDT 24 Jun 09 12:47:51 PM PDT 24 29790300 ps
T722 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1961139965 Jun 09 12:47:57 PM PDT 24 Jun 09 12:47:59 PM PDT 24 93649968 ps
T723 /workspace/coverage/cover_reg_top/47.hmac_intr_test.2230571233 Jun 09 12:48:04 PM PDT 24 Jun 09 12:48:05 PM PDT 24 27278185 ps
T724 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3044252224 Jun 09 12:47:46 PM PDT 24 Jun 09 12:47:53 PM PDT 24 1457510885 ps
T725 /workspace/coverage/cover_reg_top/12.hmac_intr_test.4064632946 Jun 09 12:47:54 PM PDT 24 Jun 09 12:47:56 PM PDT 24 65587084 ps
T726 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3402676567 Jun 09 12:47:56 PM PDT 24 Jun 09 12:47:57 PM PDT 24 13346763 ps
T727 /workspace/coverage/cover_reg_top/27.hmac_intr_test.3527189699 Jun 09 12:48:04 PM PDT 24 Jun 09 12:48:05 PM PDT 24 43705221 ps
T728 /workspace/coverage/cover_reg_top/22.hmac_intr_test.2776003992 Jun 09 12:47:59 PM PDT 24 Jun 09 12:48:00 PM PDT 24 12489548 ps
T729 /workspace/coverage/cover_reg_top/14.hmac_intr_test.617537864 Jun 09 12:47:54 PM PDT 24 Jun 09 12:47:55 PM PDT 24 51464526 ps

Test location /workspace/coverage/default/45.hmac_wipe_secret.2561717146
Short name T6
Test name
Test status
Simulation time 12573853761 ps
CPU time 54.18 seconds
Started Jun 09 01:46:12 PM PDT 24
Finished Jun 09 01:47:06 PM PDT 24
Peak memory 200520 kb
Host smart-dc45209a-07ec-4c96-9d41-f36e79d15bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561717146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2561717146
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/177.hmac_stress_all_with_rand_reset.2789248319
Short name T11
Test name
Test status
Simulation time 174940028322 ps
CPU time 3144.53 seconds
Started Jun 09 01:47:47 PM PDT 24
Finished Jun 09 02:40:12 PM PDT 24
Peak memory 822244 kb
Host smart-697e8b91-b2f8-482f-85ce-a533648d22d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2789248319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.hmac_stress_all_with_rand_reset.2789248319
Directory /workspace/177.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2722433186
Short name T7
Test name
Test status
Simulation time 120654990034 ps
CPU time 1541.06 seconds
Started Jun 09 01:45:05 PM PDT 24
Finished Jun 09 02:10:46 PM PDT 24
Peak memory 248544 kb
Host smart-e19808c0-87bf-4a12-9c83-3755e41a525e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722433186 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2722433186
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/109.hmac_stress_all_with_rand_reset.4145098967
Short name T14
Test name
Test status
Simulation time 54925446626 ps
CPU time 1844.61 seconds
Started Jun 09 01:47:03 PM PDT 24
Finished Jun 09 02:17:48 PM PDT 24
Peak memory 798720 kb
Host smart-4fd6aa1d-13ea-4996-be96-bd3df04d8d7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4145098967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.hmac_stress_all_with_rand_reset.4145098967
Directory /workspace/109.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.4084303045
Short name T24
Test name
Test status
Simulation time 223558426 ps
CPU time 1.03 seconds
Started Jun 09 01:43:47 PM PDT 24
Finished Jun 09 01:43:49 PM PDT 24
Peak memory 219992 kb
Host smart-5b7527f5-90ab-4f4c-9916-4fe8dbfd95d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084303045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.4084303045
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2064425672
Short name T103
Test name
Test status
Simulation time 95245066 ps
CPU time 2.89 seconds
Started Jun 09 12:47:52 PM PDT 24
Finished Jun 09 12:47:55 PM PDT 24
Peak memory 199292 kb
Host smart-9beb5dd9-ba29-4ab0-8631-4daaceddda96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064425672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2064425672
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2596564405
Short name T74
Test name
Test status
Simulation time 54786594 ps
CPU time 0.9 seconds
Started Jun 09 12:47:46 PM PDT 24
Finished Jun 09 12:47:48 PM PDT 24
Peak memory 199064 kb
Host smart-3d593b73-cf7c-469d-b233-8d185d25526c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596564405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2596564405
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1372956977
Short name T25
Test name
Test status
Simulation time 523874113 ps
CPU time 27.39 seconds
Started Jun 09 01:44:05 PM PDT 24
Finished Jun 09 01:44:32 PM PDT 24
Peak memory 200480 kb
Host smart-110f0e41-2179-4e8d-9729-d87d5182e251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372956977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1372956977
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1449237003
Short name T57
Test name
Test status
Simulation time 176584326861 ps
CPU time 1924.8 seconds
Started Jun 09 01:46:08 PM PDT 24
Finished Jun 09 02:18:13 PM PDT 24
Peak memory 712348 kb
Host smart-46f18208-e044-4c8d-a998-11c32a08b571
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449237003 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1449237003
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.4073589748
Short name T104
Test name
Test status
Simulation time 208798686 ps
CPU time 3.11 seconds
Started Jun 09 12:47:48 PM PDT 24
Finished Jun 09 12:47:51 PM PDT 24
Peak memory 199348 kb
Host smart-4f8b222f-a8ed-4b8f-bae9-2f362ac21039
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073589748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.4073589748
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3032419209
Short name T90
Test name
Test status
Simulation time 208528010864 ps
CPU time 3263.27 seconds
Started Jun 09 01:45:40 PM PDT 24
Finished Jun 09 02:40:04 PM PDT 24
Peak memory 684076 kb
Host smart-6c63eccd-7c81-4f0a-b8cb-d86d5856ed8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032419209 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3032419209
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1585121860
Short name T116
Test name
Test status
Simulation time 40547592 ps
CPU time 0.58 seconds
Started Jun 09 01:44:09 PM PDT 24
Finished Jun 09 01:44:10 PM PDT 24
Peak memory 195360 kb
Host smart-d8bf7b8e-2203-4b39-8d36-a29ba5d81b29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585121860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1585121860
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2995466035
Short name T9
Test name
Test status
Simulation time 4711233969 ps
CPU time 352.07 seconds
Started Jun 09 01:44:22 PM PDT 24
Finished Jun 09 01:50:15 PM PDT 24
Peak memory 487180 kb
Host smart-99b14701-6355-4db6-8c27-bb95e10c7db2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2995466035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2995466035
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1585095085
Short name T91
Test name
Test status
Simulation time 310908478679 ps
CPU time 1441.96 seconds
Started Jun 09 01:43:40 PM PDT 24
Finished Jun 09 02:07:43 PM PDT 24
Peak memory 697424 kb
Host smart-016f384c-58ad-43e9-ab7e-ce2e75ce908f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585095085 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1585095085
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1532226466
Short name T92
Test name
Test status
Simulation time 175671455362 ps
CPU time 2035.43 seconds
Started Jun 09 01:46:07 PM PDT 24
Finished Jun 09 02:20:02 PM PDT 24
Peak memory 774736 kb
Host smart-dc53fb8c-d838-4054-9f04-e6f8601ebc98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532226466 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1532226466
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3851665046
Short name T108
Test name
Test status
Simulation time 980165878 ps
CPU time 2.94 seconds
Started Jun 09 12:47:50 PM PDT 24
Finished Jun 09 12:47:54 PM PDT 24
Peak memory 199328 kb
Host smart-c012a12c-fb99-40d0-a0fd-a591048b022e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851665046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3851665046
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1725995595
Short name T515
Test name
Test status
Simulation time 271348815708 ps
CPU time 1342.22 seconds
Started Jun 09 01:44:06 PM PDT 24
Finished Jun 09 02:06:29 PM PDT 24
Peak memory 670540 kb
Host smart-397559fd-a66b-4d4e-bcb6-91c0da24c1e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725995595 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1725995595
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3580472461
Short name T38
Test name
Test status
Simulation time 241230479 ps
CPU time 4.25 seconds
Started Jun 09 12:47:50 PM PDT 24
Finished Jun 09 12:47:55 PM PDT 24
Peak memory 199356 kb
Host smart-6c57c4e6-73b7-4fb5-ae3b-fede0a798468
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580472461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3580472461
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/142.hmac_stress_all_with_rand_reset.284910800
Short name T13
Test name
Test status
Simulation time 90506867534 ps
CPU time 84.57 seconds
Started Jun 09 01:47:20 PM PDT 24
Finished Jun 09 01:48:44 PM PDT 24
Peak memory 217132 kb
Host smart-a65ab326-df28-4ea6-874a-a1c00646195e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=284910800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.hmac_stress_all_with_rand_reset.284910800
Directory /workspace/142.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1715651138
Short name T599
Test name
Test status
Simulation time 5040861334 ps
CPU time 9.34 seconds
Started Jun 09 12:47:39 PM PDT 24
Finished Jun 09 12:47:48 PM PDT 24
Peak memory 199264 kb
Host smart-9727984d-87d9-415a-98ad-b95fed2739b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715651138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1715651138
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2534353168
Short name T675
Test name
Test status
Simulation time 364496477 ps
CPU time 5.67 seconds
Started Jun 09 12:47:36 PM PDT 24
Finished Jun 09 12:47:43 PM PDT 24
Peak memory 199080 kb
Host smart-f3422f61-039c-4eae-b341-06e48d99fe06
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534353168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2534353168
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.4239721019
Short name T87
Test name
Test status
Simulation time 22890042 ps
CPU time 0.96 seconds
Started Jun 09 12:47:38 PM PDT 24
Finished Jun 09 12:47:39 PM PDT 24
Peak memory 198544 kb
Host smart-1080c3b1-69b9-431d-b8ae-a1ea35a17390
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239721019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.4239721019
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2389832450
Short name T601
Test name
Test status
Simulation time 219677169217 ps
CPU time 789.67 seconds
Started Jun 09 12:47:40 PM PDT 24
Finished Jun 09 01:00:50 PM PDT 24
Peak memory 224056 kb
Host smart-b922cd8e-2fc5-4d96-9e3b-f6c64c2b0d95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389832450 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2389832450
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2314935937
Short name T712
Test name
Test status
Simulation time 142732480 ps
CPU time 0.74 seconds
Started Jun 09 12:47:35 PM PDT 24
Finished Jun 09 12:47:36 PM PDT 24
Peak memory 197024 kb
Host smart-9345ea98-248b-4ba0-b106-bb45bac632ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314935937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2314935937
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2712192376
Short name T658
Test name
Test status
Simulation time 69765315 ps
CPU time 0.56 seconds
Started Jun 09 12:47:37 PM PDT 24
Finished Jun 09 12:47:38 PM PDT 24
Peak memory 193720 kb
Host smart-4fa460df-fe55-4cc9-a633-0d5137a0e932
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712192376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2712192376
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3666249765
Short name T689
Test name
Test status
Simulation time 91297546 ps
CPU time 1.72 seconds
Started Jun 09 12:47:37 PM PDT 24
Finished Jun 09 12:47:39 PM PDT 24
Peak memory 199348 kb
Host smart-a422ed0f-f027-44c2-90f0-d0f4c6afafb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666249765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3666249765
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1034680216
Short name T646
Test name
Test status
Simulation time 734653749 ps
CPU time 4.53 seconds
Started Jun 09 12:47:36 PM PDT 24
Finished Jun 09 12:47:41 PM PDT 24
Peak memory 199400 kb
Host smart-26f6ef8d-5365-40a9-bb49-5dc812dfa83c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034680216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1034680216
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3728380335
Short name T37
Test name
Test status
Simulation time 1267692310 ps
CPU time 4.12 seconds
Started Jun 09 12:47:36 PM PDT 24
Finished Jun 09 12:47:41 PM PDT 24
Peak memory 199308 kb
Host smart-fedb5824-b2e0-49f3-a67c-28d79670d490
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728380335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3728380335
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.935236777
Short name T613
Test name
Test status
Simulation time 316150860 ps
CPU time 5.69 seconds
Started Jun 09 12:47:34 PM PDT 24
Finished Jun 09 12:47:40 PM PDT 24
Peak memory 199512 kb
Host smart-b0253310-e566-4bfb-bc86-61d9f16fa535
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935236777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.935236777
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2030886766
Short name T662
Test name
Test status
Simulation time 116903810 ps
CPU time 5.17 seconds
Started Jun 09 12:47:37 PM PDT 24
Finished Jun 09 12:47:42 PM PDT 24
Peak memory 197812 kb
Host smart-81c52845-9f84-4e3e-a152-f03169ae49a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030886766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2030886766
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1618556023
Short name T686
Test name
Test status
Simulation time 36308392 ps
CPU time 0.8 seconds
Started Jun 09 12:47:35 PM PDT 24
Finished Jun 09 12:47:37 PM PDT 24
Peak memory 197776 kb
Host smart-01c2d60d-f127-4f72-8796-f9efa7b8ef2b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618556023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1618556023
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.134250339
Short name T672
Test name
Test status
Simulation time 32672114 ps
CPU time 1.87 seconds
Started Jun 09 12:47:38 PM PDT 24
Finished Jun 09 12:47:40 PM PDT 24
Peak memory 199420 kb
Host smart-a742358f-4ceb-4875-8d20-e9bea6190534
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134250339 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.134250339
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.4287123920
Short name T77
Test name
Test status
Simulation time 24205963 ps
CPU time 0.87 seconds
Started Jun 09 12:47:38 PM PDT 24
Finished Jun 09 12:47:39 PM PDT 24
Peak memory 199068 kb
Host smart-59581b2b-ecc1-4cc5-a0cf-71f6b17b70d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287123920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.4287123920
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1221458169
Short name T643
Test name
Test status
Simulation time 42136165 ps
CPU time 0.64 seconds
Started Jun 09 12:47:38 PM PDT 24
Finished Jun 09 12:47:39 PM PDT 24
Peak memory 194224 kb
Host smart-62382146-4070-4757-a435-e241b677264f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221458169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1221458169
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2936627026
Short name T711
Test name
Test status
Simulation time 558883421 ps
CPU time 1.35 seconds
Started Jun 09 12:47:41 PM PDT 24
Finished Jun 09 12:47:43 PM PDT 24
Peak memory 199340 kb
Host smart-f0e30600-0ef5-469e-8bc0-6915f8c4f355
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936627026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2936627026
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1459480398
Short name T654
Test name
Test status
Simulation time 25916459 ps
CPU time 1.35 seconds
Started Jun 09 12:47:36 PM PDT 24
Finished Jun 09 12:47:38 PM PDT 24
Peak memory 199388 kb
Host smart-13ca2a20-1f63-4804-959d-d036bcd367e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459480398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1459480398
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2526566219
Short name T111
Test name
Test status
Simulation time 233739528 ps
CPU time 1.89 seconds
Started Jun 09 12:47:38 PM PDT 24
Finished Jun 09 12:47:40 PM PDT 24
Peak memory 199340 kb
Host smart-ca4ff614-5f87-4c6d-b662-3392dc937382
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526566219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2526566219
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3703910164
Short name T670
Test name
Test status
Simulation time 274447415 ps
CPU time 1.81 seconds
Started Jun 09 12:47:53 PM PDT 24
Finished Jun 09 12:47:55 PM PDT 24
Peak memory 199388 kb
Host smart-3414e4ec-cbf4-4e03-a6e2-063df1c1ca8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703910164 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3703910164
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2014762848
Short name T80
Test name
Test status
Simulation time 11783795 ps
CPU time 0.66 seconds
Started Jun 09 12:47:53 PM PDT 24
Finished Jun 09 12:47:54 PM PDT 24
Peak memory 196936 kb
Host smart-4ed9ebf4-5e22-4ab7-affd-699834f83714
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014762848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2014762848
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1309954618
Short name T708
Test name
Test status
Simulation time 14803268 ps
CPU time 0.64 seconds
Started Jun 09 12:47:53 PM PDT 24
Finished Jun 09 12:47:54 PM PDT 24
Peak memory 194312 kb
Host smart-b0a46467-cda4-45e8-a3a4-a043adddb50e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309954618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1309954618
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2167376556
Short name T645
Test name
Test status
Simulation time 113782471 ps
CPU time 2.3 seconds
Started Jun 09 12:47:52 PM PDT 24
Finished Jun 09 12:47:55 PM PDT 24
Peak memory 199360 kb
Host smart-98848743-7607-4a63-95b4-23d2c33d6735
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167376556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2167376556
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1553612475
Short name T647
Test name
Test status
Simulation time 54453325 ps
CPU time 1.55 seconds
Started Jun 09 12:47:55 PM PDT 24
Finished Jun 09 12:47:57 PM PDT 24
Peak memory 199168 kb
Host smart-bc6bf277-cd1d-4acb-8013-71ccc37ca2cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553612475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1553612475
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3713350342
Short name T631
Test name
Test status
Simulation time 133994108 ps
CPU time 2.34 seconds
Started Jun 09 12:47:53 PM PDT 24
Finished Jun 09 12:47:56 PM PDT 24
Peak memory 207568 kb
Host smart-d8486899-2b4e-4d12-bfaa-52f2e415d601
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713350342 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3713350342
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1567438083
Short name T667
Test name
Test status
Simulation time 21135032 ps
CPU time 0.79 seconds
Started Jun 09 12:47:53 PM PDT 24
Finished Jun 09 12:47:55 PM PDT 24
Peak memory 197152 kb
Host smart-d159f06d-ec61-496b-bbe3-1ba81cbc364a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567438083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1567438083
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1959741360
Short name T600
Test name
Test status
Simulation time 13746888 ps
CPU time 0.74 seconds
Started Jun 09 12:47:54 PM PDT 24
Finished Jun 09 12:47:55 PM PDT 24
Peak memory 194284 kb
Host smart-ce649758-da7b-4e5b-b100-eff980d8818f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959741360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1959741360
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2743591445
Short name T605
Test name
Test status
Simulation time 117576204 ps
CPU time 2.35 seconds
Started Jun 09 12:47:50 PM PDT 24
Finished Jun 09 12:47:53 PM PDT 24
Peak memory 199304 kb
Host smart-923d5d25-9c79-4653-a37c-6330632e8ad8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743591445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2743591445
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2933211377
Short name T696
Test name
Test status
Simulation time 111449882 ps
CPU time 2.73 seconds
Started Jun 09 12:47:52 PM PDT 24
Finished Jun 09 12:47:55 PM PDT 24
Peak memory 199424 kb
Host smart-c3a9581c-9f53-4ab0-8763-2a2a9fa117ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933211377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2933211377
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.27990978
Short name T105
Test name
Test status
Simulation time 475822667 ps
CPU time 4.23 seconds
Started Jun 09 12:47:49 PM PDT 24
Finished Jun 09 12:47:54 PM PDT 24
Peak memory 199356 kb
Host smart-5ee10af8-76f3-482b-88ce-1d52ffc54ea5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27990978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.27990978
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1785999305
Short name T710
Test name
Test status
Simulation time 1035964326 ps
CPU time 2.27 seconds
Started Jun 09 12:47:54 PM PDT 24
Finished Jun 09 12:47:58 PM PDT 24
Peak memory 199404 kb
Host smart-68171ea0-22ea-467b-b056-8c2a43013451
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785999305 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1785999305
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.436059543
Short name T674
Test name
Test status
Simulation time 196724650 ps
CPU time 0.98 seconds
Started Jun 09 12:47:54 PM PDT 24
Finished Jun 09 12:47:56 PM PDT 24
Peak memory 198968 kb
Host smart-3f491db8-0708-4349-83f8-c66791d06cc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436059543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.436059543
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.4064632946
Short name T725
Test name
Test status
Simulation time 65587084 ps
CPU time 0.62 seconds
Started Jun 09 12:47:54 PM PDT 24
Finished Jun 09 12:47:56 PM PDT 24
Peak memory 194184 kb
Host smart-4bdd1305-6247-4b4e-bf43-bb2030892fe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064632946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.4064632946
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1302039155
Short name T660
Test name
Test status
Simulation time 180128832 ps
CPU time 2.32 seconds
Started Jun 09 12:47:56 PM PDT 24
Finished Jun 09 12:47:59 PM PDT 24
Peak memory 199284 kb
Host smart-a2eed63a-3a9a-4d36-b0be-44f922ab75c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302039155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1302039155
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1810282127
Short name T698
Test name
Test status
Simulation time 603463922 ps
CPU time 3.25 seconds
Started Jun 09 12:47:56 PM PDT 24
Finished Jun 09 12:47:59 PM PDT 24
Peak memory 199384 kb
Host smart-78918994-8b02-4bd9-b2a2-0685e9e4425c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810282127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1810282127
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.212714309
Short name T107
Test name
Test status
Simulation time 610201940 ps
CPU time 3.5 seconds
Started Jun 09 12:47:53 PM PDT 24
Finished Jun 09 12:47:57 PM PDT 24
Peak memory 199348 kb
Host smart-5f634bc9-ef94-4700-82f7-1731d96aeadb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212714309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.212714309
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2135923302
Short name T629
Test name
Test status
Simulation time 42432140 ps
CPU time 1.36 seconds
Started Jun 09 12:47:53 PM PDT 24
Finished Jun 09 12:47:55 PM PDT 24
Peak memory 199400 kb
Host smart-5d3ec516-2ffa-4691-9779-99c5578dc7da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135923302 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2135923302
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.995667228
Short name T75
Test name
Test status
Simulation time 38312013 ps
CPU time 0.99 seconds
Started Jun 09 12:47:54 PM PDT 24
Finished Jun 09 12:47:55 PM PDT 24
Peak memory 198744 kb
Host smart-df31c7b0-1e85-4102-bf04-342884dce795
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995667228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.995667228
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3402676567
Short name T726
Test name
Test status
Simulation time 13346763 ps
CPU time 0.59 seconds
Started Jun 09 12:47:56 PM PDT 24
Finished Jun 09 12:47:57 PM PDT 24
Peak memory 194188 kb
Host smart-538acb79-45e0-4c9e-b108-bdfe67d448aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402676567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3402676567
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1633774689
Short name T719
Test name
Test status
Simulation time 433428517 ps
CPU time 1.97 seconds
Started Jun 09 12:47:50 PM PDT 24
Finished Jun 09 12:47:53 PM PDT 24
Peak memory 199560 kb
Host smart-97be05fb-2428-4ce5-8189-5d7b585632f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633774689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1633774689
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3339267373
Short name T707
Test name
Test status
Simulation time 69490063 ps
CPU time 1.94 seconds
Started Jun 09 12:47:54 PM PDT 24
Finished Jun 09 12:47:57 PM PDT 24
Peak memory 199412 kb
Host smart-e1c134b3-f003-415a-a789-72b91b5e0ae5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339267373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3339267373
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2959255529
Short name T651
Test name
Test status
Simulation time 78660723 ps
CPU time 1.87 seconds
Started Jun 09 12:47:56 PM PDT 24
Finished Jun 09 12:47:58 PM PDT 24
Peak memory 199384 kb
Host smart-b027e9f3-5ea9-41af-b953-803b10f65318
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959255529 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2959255529
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.4199499106
Short name T714
Test name
Test status
Simulation time 31743616 ps
CPU time 0.95 seconds
Started Jun 09 12:47:52 PM PDT 24
Finished Jun 09 12:47:53 PM PDT 24
Peak memory 198392 kb
Host smart-37e5caba-b155-460c-915d-29781fb9a883
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199499106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.4199499106
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.617537864
Short name T729
Test name
Test status
Simulation time 51464526 ps
CPU time 0.65 seconds
Started Jun 09 12:47:54 PM PDT 24
Finished Jun 09 12:47:55 PM PDT 24
Peak memory 194180 kb
Host smart-a5fb006f-c8e2-44b8-a946-35f76e4d4086
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617537864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.617537864
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2020500683
Short name T603
Test name
Test status
Simulation time 165342423 ps
CPU time 1.22 seconds
Started Jun 09 12:47:55 PM PDT 24
Finished Jun 09 12:47:56 PM PDT 24
Peak memory 199076 kb
Host smart-dc0bba8c-5d55-4615-9489-bb8f78674d3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020500683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2020500683
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.75767591
Short name T691
Test name
Test status
Simulation time 112506181 ps
CPU time 1.64 seconds
Started Jun 09 12:47:56 PM PDT 24
Finished Jun 09 12:47:58 PM PDT 24
Peak memory 199436 kb
Host smart-26f0d139-4147-4b33-8b7f-9a7d8a7f1aac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75767591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.75767591
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3603236611
Short name T649
Test name
Test status
Simulation time 338094637 ps
CPU time 2.93 seconds
Started Jun 09 12:48:03 PM PDT 24
Finished Jun 09 12:48:06 PM PDT 24
Peak memory 199176 kb
Host smart-f202f799-f21d-4c16-9aab-062fa89d575d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603236611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3603236611
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.4133332767
Short name T43
Test name
Test status
Simulation time 102563157151 ps
CPU time 538.92 seconds
Started Jun 09 12:47:56 PM PDT 24
Finished Jun 09 12:56:55 PM PDT 24
Peak memory 215696 kb
Host smart-0275d4af-4ff4-4062-a164-0c53d638c6a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133332767 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.4133332767
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.4040385857
Short name T79
Test name
Test status
Simulation time 25026946 ps
CPU time 0.87 seconds
Started Jun 09 12:47:58 PM PDT 24
Finished Jun 09 12:47:59 PM PDT 24
Peak memory 198684 kb
Host smart-a4237fed-d60d-4b91-bb28-7b9c676570e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040385857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.4040385857
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.222503958
Short name T606
Test name
Test status
Simulation time 20482523 ps
CPU time 0.55 seconds
Started Jun 09 12:47:50 PM PDT 24
Finished Jun 09 12:47:51 PM PDT 24
Peak memory 194276 kb
Host smart-e271a5f3-3032-4418-ba01-59e3aed244ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222503958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.222503958
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1027159457
Short name T42
Test name
Test status
Simulation time 41124196 ps
CPU time 1.14 seconds
Started Jun 09 12:48:00 PM PDT 24
Finished Jun 09 12:48:02 PM PDT 24
Peak memory 199088 kb
Host smart-bc5a3aba-5e97-4139-9e84-b73c7589c692
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027159457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1027159457
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.414711250
Short name T709
Test name
Test status
Simulation time 136685615 ps
CPU time 3.78 seconds
Started Jun 09 12:47:57 PM PDT 24
Finished Jun 09 12:48:01 PM PDT 24
Peak memory 199392 kb
Host smart-260c74a3-cb3a-4edc-a8fc-e5aeea8416d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414711250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.414711250
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1075128175
Short name T39
Test name
Test status
Simulation time 373069654 ps
CPU time 3.16 seconds
Started Jun 09 12:47:51 PM PDT 24
Finished Jun 09 12:47:55 PM PDT 24
Peak memory 199320 kb
Host smart-757f18fa-fbad-4100-ac62-10ce5788242e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075128175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1075128175
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4265060684
Short name T671
Test name
Test status
Simulation time 47802463 ps
CPU time 2.8 seconds
Started Jun 09 12:48:07 PM PDT 24
Finished Jun 09 12:48:10 PM PDT 24
Peak memory 207420 kb
Host smart-dd433df9-0caa-4f21-986b-a70ad1cb8181
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265060684 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.4265060684
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2763347165
Short name T664
Test name
Test status
Simulation time 35478992 ps
CPU time 0.7 seconds
Started Jun 09 12:48:00 PM PDT 24
Finished Jun 09 12:48:01 PM PDT 24
Peak memory 196708 kb
Host smart-edb65f3a-58c4-438e-9487-67d4503355e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763347165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2763347165
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2205407882
Short name T695
Test name
Test status
Simulation time 29863498 ps
CPU time 0.6 seconds
Started Jun 09 12:48:08 PM PDT 24
Finished Jun 09 12:48:08 PM PDT 24
Peak memory 194032 kb
Host smart-0d058b87-1e2c-42bc-ad83-427c545937cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205407882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2205407882
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3977664575
Short name T596
Test name
Test status
Simulation time 44662354 ps
CPU time 1.1 seconds
Started Jun 09 12:48:06 PM PDT 24
Finished Jun 09 12:48:07 PM PDT 24
Peak memory 197544 kb
Host smart-eaa0f394-03e6-452c-ad43-21a01b212426
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977664575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3977664575
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.378230909
Short name T650
Test name
Test status
Simulation time 58887945 ps
CPU time 1.6 seconds
Started Jun 09 12:47:59 PM PDT 24
Finished Jun 09 12:48:01 PM PDT 24
Peak memory 199380 kb
Host smart-54bc3caa-32fa-4861-b5f2-c2882009e398
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378230909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.378230909
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2387249978
Short name T715
Test name
Test status
Simulation time 123234259 ps
CPU time 3.94 seconds
Started Jun 09 12:48:06 PM PDT 24
Finished Jun 09 12:48:11 PM PDT 24
Peak memory 199176 kb
Host smart-e90e97b6-a03d-4582-b87d-50990aa4f830
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387249978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2387249978
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.835139376
Short name T597
Test name
Test status
Simulation time 115692824250 ps
CPU time 1160.45 seconds
Started Jun 09 12:48:00 PM PDT 24
Finished Jun 09 01:07:21 PM PDT 24
Peak memory 215876 kb
Host smart-64f5d60e-1c96-4208-8b04-a55741d50dc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835139376 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.835139376
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3664579448
Short name T78
Test name
Test status
Simulation time 133452945 ps
CPU time 0.98 seconds
Started Jun 09 12:47:57 PM PDT 24
Finished Jun 09 12:47:58 PM PDT 24
Peak memory 198684 kb
Host smart-b2ad4c64-1143-4a44-bdcd-a2cd93f2deea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664579448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3664579448
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.151214552
Short name T633
Test name
Test status
Simulation time 13249092 ps
CPU time 0.6 seconds
Started Jun 09 12:48:00 PM PDT 24
Finished Jun 09 12:48:01 PM PDT 24
Peak memory 194204 kb
Host smart-ff2c1fc7-e3bf-4174-bb75-e2658907c92d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151214552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.151214552
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.573194008
Short name T701
Test name
Test status
Simulation time 211185629 ps
CPU time 1.23 seconds
Started Jun 09 12:47:58 PM PDT 24
Finished Jun 09 12:48:00 PM PDT 24
Peak memory 199356 kb
Host smart-5c145ca4-5f76-464c-b759-f95189a892fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573194008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.573194008
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1916918656
Short name T669
Test name
Test status
Simulation time 477224030 ps
CPU time 2.94 seconds
Started Jun 09 12:47:57 PM PDT 24
Finished Jun 09 12:48:00 PM PDT 24
Peak memory 199396 kb
Host smart-0a2d4344-2c05-4074-b38b-d989325f929d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916918656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1916918656
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3340799564
Short name T102
Test name
Test status
Simulation time 58942246 ps
CPU time 1.83 seconds
Started Jun 09 12:47:56 PM PDT 24
Finished Jun 09 12:47:58 PM PDT 24
Peak memory 199356 kb
Host smart-c5b3e042-377f-48f6-9cac-e8d5809bc4f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340799564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3340799564
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3972353380
Short name T618
Test name
Test status
Simulation time 164971780 ps
CPU time 2.8 seconds
Started Jun 09 12:48:02 PM PDT 24
Finished Jun 09 12:48:05 PM PDT 24
Peak memory 199436 kb
Host smart-cc568450-87ad-4d8e-ac6e-ee38ee4ae86a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972353380 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3972353380
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2475828281
Short name T619
Test name
Test status
Simulation time 30985281 ps
CPU time 0.97 seconds
Started Jun 09 12:47:56 PM PDT 24
Finished Jun 09 12:47:57 PM PDT 24
Peak memory 198576 kb
Host smart-0ebad655-ee10-42d5-8b4d-eedce4303a87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475828281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2475828281
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.180883783
Short name T635
Test name
Test status
Simulation time 14658396 ps
CPU time 0.6 seconds
Started Jun 09 12:48:06 PM PDT 24
Finished Jun 09 12:48:07 PM PDT 24
Peak memory 194052 kb
Host smart-10dd9027-c5c8-4cbf-811c-95ec6d438b26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180883783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.180883783
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.19660184
Short name T673
Test name
Test status
Simulation time 113861127 ps
CPU time 2.36 seconds
Started Jun 09 12:47:57 PM PDT 24
Finished Jun 09 12:48:00 PM PDT 24
Peak memory 199276 kb
Host smart-d7bb338d-aede-493d-a87d-5a00de6e447c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19660184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr_
outstanding.19660184
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3180812833
Short name T640
Test name
Test status
Simulation time 164647212 ps
CPU time 3.83 seconds
Started Jun 09 12:48:07 PM PDT 24
Finished Jun 09 12:48:11 PM PDT 24
Peak memory 199216 kb
Host smart-440bbd79-6a7d-4d88-937d-6fa52547169c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180812833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3180812833
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3279059022
Short name T109
Test name
Test status
Simulation time 92953528 ps
CPU time 1.76 seconds
Started Jun 09 12:47:58 PM PDT 24
Finished Jun 09 12:48:00 PM PDT 24
Peak memory 199352 kb
Host smart-5356c9a6-9006-451b-8844-494b27ed7e01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279059022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3279059022
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2856595517
Short name T705
Test name
Test status
Simulation time 161010928 ps
CPU time 1.46 seconds
Started Jun 09 12:48:00 PM PDT 24
Finished Jun 09 12:48:01 PM PDT 24
Peak memory 199412 kb
Host smart-a1e144ba-4d06-4b59-be7c-e8a0a0aad120
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856595517 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2856595517
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1961139965
Short name T722
Test name
Test status
Simulation time 93649968 ps
CPU time 1 seconds
Started Jun 09 12:47:57 PM PDT 24
Finished Jun 09 12:47:59 PM PDT 24
Peak memory 199012 kb
Host smart-c7f768ba-2001-4d13-9bc1-a14c01069793
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961139965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1961139965
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.825281699
Short name T614
Test name
Test status
Simulation time 14126854 ps
CPU time 0.62 seconds
Started Jun 09 12:48:00 PM PDT 24
Finished Jun 09 12:48:01 PM PDT 24
Peak memory 194272 kb
Host smart-bec08789-7a56-4a82-9104-0514acc47b49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825281699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.825281699
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3043196466
Short name T663
Test name
Test status
Simulation time 32001285 ps
CPU time 1.56 seconds
Started Jun 09 12:48:08 PM PDT 24
Finished Jun 09 12:48:10 PM PDT 24
Peak memory 199128 kb
Host smart-78e0089b-bac5-4343-a5d5-629f0224bf96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043196466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3043196466
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1300321311
Short name T638
Test name
Test status
Simulation time 158464289 ps
CPU time 4.3 seconds
Started Jun 09 12:47:58 PM PDT 24
Finished Jun 09 12:48:02 PM PDT 24
Peak memory 199284 kb
Host smart-10ccfb75-0e54-45d8-9523-07cdbd9e0e6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300321311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1300321311
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3338772017
Short name T641
Test name
Test status
Simulation time 156383462 ps
CPU time 3.2 seconds
Started Jun 09 12:47:59 PM PDT 24
Finished Jun 09 12:48:03 PM PDT 24
Peak memory 199352 kb
Host smart-c98144e8-95f8-4420-9cd4-4077701dbb08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338772017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3338772017
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2369551163
Short name T85
Test name
Test status
Simulation time 1772132154 ps
CPU time 9.13 seconds
Started Jun 09 12:47:45 PM PDT 24
Finished Jun 09 12:47:54 PM PDT 24
Peak memory 199320 kb
Host smart-f4766e15-4800-4a15-8608-9eaae828f7a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369551163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2369551163
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.337844670
Short name T84
Test name
Test status
Simulation time 4381729619 ps
CPU time 11.67 seconds
Started Jun 09 12:47:40 PM PDT 24
Finished Jun 09 12:47:52 PM PDT 24
Peak memory 199352 kb
Host smart-e381f0d5-e536-4656-92b6-e6e2aaa2d248
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337844670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.337844670
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1208472772
Short name T697
Test name
Test status
Simulation time 22776190 ps
CPU time 0.96 seconds
Started Jun 09 12:47:40 PM PDT 24
Finished Jun 09 12:47:41 PM PDT 24
Peak memory 199044 kb
Host smart-35c7707b-fe30-4e0e-bfa4-1ebcf19e9753
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208472772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1208472772
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2563699789
Short name T634
Test name
Test status
Simulation time 73496148 ps
CPU time 2.66 seconds
Started Jun 09 12:47:40 PM PDT 24
Finished Jun 09 12:47:43 PM PDT 24
Peak memory 207688 kb
Host smart-c9a5d12a-729d-4d42-9469-a3a22db2fd95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563699789 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2563699789
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1934310550
Short name T76
Test name
Test status
Simulation time 32132973 ps
CPU time 0.68 seconds
Started Jun 09 12:47:42 PM PDT 24
Finished Jun 09 12:47:43 PM PDT 24
Peak memory 196864 kb
Host smart-dc8e8dff-1a04-4f26-b965-d163e55bd327
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934310550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1934310550
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.1054213318
Short name T666
Test name
Test status
Simulation time 20578016 ps
CPU time 0.58 seconds
Started Jun 09 12:47:40 PM PDT 24
Finished Jun 09 12:47:41 PM PDT 24
Peak memory 194264 kb
Host smart-06611336-421a-4aaa-8cff-b6a60d8ce652
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054213318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1054213318
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2108019042
Short name T720
Test name
Test status
Simulation time 209269155 ps
CPU time 1.22 seconds
Started Jun 09 12:47:39 PM PDT 24
Finished Jun 09 12:47:41 PM PDT 24
Peak memory 198140 kb
Host smart-b0336b4a-0ca4-4f81-8bb3-791fdf1f4946
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108019042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2108019042
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1720166658
Short name T636
Test name
Test status
Simulation time 819697687 ps
CPU time 2.13 seconds
Started Jun 09 12:47:41 PM PDT 24
Finished Jun 09 12:47:44 PM PDT 24
Peak memory 199332 kb
Host smart-2632f0ec-4e45-434f-a40d-7290ba47f402
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720166658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1720166658
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1067535853
Short name T717
Test name
Test status
Simulation time 85520112 ps
CPU time 1.95 seconds
Started Jun 09 12:47:49 PM PDT 24
Finished Jun 09 12:47:52 PM PDT 24
Peak memory 199080 kb
Host smart-c0493c67-1a91-42da-9c8c-40ee402a30d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067535853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.1067535853
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.4087562903
Short name T626
Test name
Test status
Simulation time 38282754 ps
CPU time 0.66 seconds
Started Jun 09 12:48:00 PM PDT 24
Finished Jun 09 12:48:01 PM PDT 24
Peak memory 194232 kb
Host smart-3b1d637f-69dd-4754-911b-21d06066f4b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087562903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.4087562903
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1392191754
Short name T602
Test name
Test status
Simulation time 11173707 ps
CPU time 0.61 seconds
Started Jun 09 12:48:00 PM PDT 24
Finished Jun 09 12:48:01 PM PDT 24
Peak memory 194264 kb
Host smart-f1173f4f-4c81-4969-bfa5-f8201ffe85d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392191754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1392191754
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.2776003992
Short name T728
Test name
Test status
Simulation time 12489548 ps
CPU time 0.64 seconds
Started Jun 09 12:47:59 PM PDT 24
Finished Jun 09 12:48:00 PM PDT 24
Peak memory 194256 kb
Host smart-23c34efe-5fcc-4088-b100-6f3f20433d95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776003992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2776003992
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1436380584
Short name T682
Test name
Test status
Simulation time 24238306 ps
CPU time 0.6 seconds
Started Jun 09 12:48:01 PM PDT 24
Finished Jun 09 12:48:02 PM PDT 24
Peak memory 194140 kb
Host smart-bc9e3e4e-054d-4c3c-9af6-89b65c93eb30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436380584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1436380584
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.4244613411
Short name T685
Test name
Test status
Simulation time 14595591 ps
CPU time 0.68 seconds
Started Jun 09 12:48:03 PM PDT 24
Finished Jun 09 12:48:05 PM PDT 24
Peak memory 194216 kb
Host smart-ce1368da-16ac-4c26-a816-c69314bc858b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244613411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.4244613411
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3633646826
Short name T642
Test name
Test status
Simulation time 25378357 ps
CPU time 0.63 seconds
Started Jun 09 12:48:04 PM PDT 24
Finished Jun 09 12:48:05 PM PDT 24
Peak memory 194248 kb
Host smart-a522df8c-c3a4-4e95-a000-28544f19a9de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633646826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3633646826
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1567187350
Short name T625
Test name
Test status
Simulation time 13497523 ps
CPU time 0.61 seconds
Started Jun 09 12:48:01 PM PDT 24
Finished Jun 09 12:48:03 PM PDT 24
Peak memory 194188 kb
Host smart-068e7cfa-7f0b-41d3-a782-536b79d1af55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567187350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1567187350
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3527189699
Short name T727
Test name
Test status
Simulation time 43705221 ps
CPU time 0.66 seconds
Started Jun 09 12:48:04 PM PDT 24
Finished Jun 09 12:48:05 PM PDT 24
Peak memory 194232 kb
Host smart-cb4f80a2-345c-4f39-a8fe-e2bf09181efd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527189699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3527189699
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2829139346
Short name T694
Test name
Test status
Simulation time 25587544 ps
CPU time 0.63 seconds
Started Jun 09 12:48:02 PM PDT 24
Finished Jun 09 12:48:03 PM PDT 24
Peak memory 194188 kb
Host smart-bd7f811b-6538-473c-a3c6-dd6113bc1096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829139346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2829139346
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3972486368
Short name T620
Test name
Test status
Simulation time 12134089 ps
CPU time 0.63 seconds
Started Jun 09 12:48:02 PM PDT 24
Finished Jun 09 12:48:03 PM PDT 24
Peak memory 194224 kb
Host smart-f6231974-9330-45e9-82c6-310f09ca5779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972486368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3972486368
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2176854947
Short name T716
Test name
Test status
Simulation time 611309602 ps
CPU time 8.25 seconds
Started Jun 09 12:47:43 PM PDT 24
Finished Jun 09 12:47:51 PM PDT 24
Peak memory 199296 kb
Host smart-028aed99-7d5d-4e04-ab7c-a99d5ed515b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176854947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2176854947
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2351796754
Short name T668
Test name
Test status
Simulation time 1097740463 ps
CPU time 16.47 seconds
Started Jun 09 12:47:45 PM PDT 24
Finished Jun 09 12:48:02 PM PDT 24
Peak memory 199196 kb
Host smart-94cd1c66-0af3-432a-b1ed-1f64eb50f039
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351796754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2351796754
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1729718408
Short name T657
Test name
Test status
Simulation time 29502023 ps
CPU time 0.92 seconds
Started Jun 09 12:47:41 PM PDT 24
Finished Jun 09 12:47:43 PM PDT 24
Peak memory 199000 kb
Host smart-fd1d9ac2-95bc-4399-8edd-6510eae1c0a3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729718408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1729718408
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1657667754
Short name T622
Test name
Test status
Simulation time 160701384 ps
CPU time 1.59 seconds
Started Jun 09 12:47:52 PM PDT 24
Finished Jun 09 12:47:54 PM PDT 24
Peak memory 199196 kb
Host smart-1ec9b5e5-6c57-4dfa-ae1d-6db900571ae5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657667754 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1657667754
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1063407968
Short name T702
Test name
Test status
Simulation time 26679070 ps
CPU time 0.6 seconds
Started Jun 09 12:47:39 PM PDT 24
Finished Jun 09 12:47:40 PM PDT 24
Peak memory 194252 kb
Host smart-4f7dab4b-48c3-45c6-a86f-785f35cab9ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063407968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1063407968
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.873295318
Short name T604
Test name
Test status
Simulation time 587339717 ps
CPU time 2.49 seconds
Started Jun 09 12:47:41 PM PDT 24
Finished Jun 09 12:47:44 PM PDT 24
Peak memory 199368 kb
Host smart-c5c5f77b-10ca-468d-b10e-4e83e409c099
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873295318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.873295318
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1650682887
Short name T637
Test name
Test status
Simulation time 160712938 ps
CPU time 3.16 seconds
Started Jun 09 12:47:42 PM PDT 24
Finished Jun 09 12:47:45 PM PDT 24
Peak memory 199384 kb
Host smart-65fcd581-8bab-4a14-8731-9f673f457408
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650682887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1650682887
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.530773535
Short name T655
Test name
Test status
Simulation time 151910246 ps
CPU time 2.96 seconds
Started Jun 09 12:47:41 PM PDT 24
Finished Jun 09 12:47:45 PM PDT 24
Peak memory 199348 kb
Host smart-ca142aba-a08f-49c0-9f5d-0f0e3118c36a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530773535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.530773535
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3890947723
Short name T644
Test name
Test status
Simulation time 59057319 ps
CPU time 0.62 seconds
Started Jun 09 12:48:02 PM PDT 24
Finished Jun 09 12:48:03 PM PDT 24
Peak memory 194244 kb
Host smart-1f6c21c9-05e5-47f9-816e-65d0fdcccee7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890947723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3890947723
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2408277162
Short name T665
Test name
Test status
Simulation time 45649532 ps
CPU time 0.62 seconds
Started Jun 09 12:48:06 PM PDT 24
Finished Jun 09 12:48:07 PM PDT 24
Peak memory 194180 kb
Host smart-c91038ea-7d3d-4488-b61e-9e0026b9e2e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408277162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2408277162
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1572211800
Short name T648
Test name
Test status
Simulation time 14183573 ps
CPU time 0.7 seconds
Started Jun 09 12:48:03 PM PDT 24
Finished Jun 09 12:48:04 PM PDT 24
Peak memory 194172 kb
Host smart-de0d2ae9-8737-4420-b002-ca31f52eb494
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572211800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1572211800
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2538761598
Short name T676
Test name
Test status
Simulation time 50463539 ps
CPU time 0.66 seconds
Started Jun 09 12:48:04 PM PDT 24
Finished Jun 09 12:48:05 PM PDT 24
Peak memory 194196 kb
Host smart-35dc7e4f-7f08-434e-b7b8-a2a68dfa3df9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538761598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2538761598
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.4087546029
Short name T609
Test name
Test status
Simulation time 18959219 ps
CPU time 0.6 seconds
Started Jun 09 12:48:03 PM PDT 24
Finished Jun 09 12:48:04 PM PDT 24
Peak memory 194212 kb
Host smart-da846f9f-1ada-488a-a79d-9fc67e1d9114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087546029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.4087546029
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.283306286
Short name T653
Test name
Test status
Simulation time 56954412 ps
CPU time 0.67 seconds
Started Jun 09 12:48:04 PM PDT 24
Finished Jun 09 12:48:05 PM PDT 24
Peak memory 194256 kb
Host smart-b978744d-79ab-4d57-8cec-9906196404fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283306286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.283306286
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3381634910
Short name T699
Test name
Test status
Simulation time 60442229 ps
CPU time 0.62 seconds
Started Jun 09 12:48:01 PM PDT 24
Finished Jun 09 12:48:02 PM PDT 24
Peak memory 194312 kb
Host smart-7a1b8bab-3abf-4ec8-a544-610b9be710a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381634910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3381634910
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1202042883
Short name T718
Test name
Test status
Simulation time 13640918 ps
CPU time 0.66 seconds
Started Jun 09 12:48:02 PM PDT 24
Finished Jun 09 12:48:03 PM PDT 24
Peak memory 194204 kb
Host smart-4e5382b4-79d7-450a-b59c-e4c394c70cfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202042883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1202042883
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1225922414
Short name T687
Test name
Test status
Simulation time 14035636 ps
CPU time 0.62 seconds
Started Jun 09 12:48:02 PM PDT 24
Finished Jun 09 12:48:03 PM PDT 24
Peak memory 194264 kb
Host smart-13217bca-b9d0-46d7-a175-7cc93f395093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225922414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1225922414
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2300332467
Short name T680
Test name
Test status
Simulation time 16550029 ps
CPU time 0.67 seconds
Started Jun 09 12:48:02 PM PDT 24
Finished Jun 09 12:48:03 PM PDT 24
Peak memory 194360 kb
Host smart-80f27cd5-eec9-44d4-98d2-f21f68e9a401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300332467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2300332467
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3044252224
Short name T724
Test name
Test status
Simulation time 1457510885 ps
CPU time 5.95 seconds
Started Jun 09 12:47:46 PM PDT 24
Finished Jun 09 12:47:53 PM PDT 24
Peak memory 199048 kb
Host smart-707c0614-c840-4112-b109-31747fbaacb6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044252224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3044252224
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.139449597
Short name T83
Test name
Test status
Simulation time 3624875433 ps
CPU time 10.94 seconds
Started Jun 09 12:47:43 PM PDT 24
Finished Jun 09 12:47:54 PM PDT 24
Peak memory 198612 kb
Host smart-5dfda08e-b2d7-4c97-9e41-cf6f4fd7bf00
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139449597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.139449597
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2998942855
Short name T700
Test name
Test status
Simulation time 126739328 ps
CPU time 0.87 seconds
Started Jun 09 12:47:44 PM PDT 24
Finished Jun 09 12:47:45 PM PDT 24
Peak memory 198360 kb
Host smart-0bd0920a-8d75-4a4a-a2da-97d1e759f2a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998942855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2998942855
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1771342433
Short name T44
Test name
Test status
Simulation time 76404100 ps
CPU time 2.83 seconds
Started Jun 09 12:47:44 PM PDT 24
Finished Jun 09 12:47:47 PM PDT 24
Peak memory 214860 kb
Host smart-e8fad849-9831-4d40-8f19-8d1dd4aba3e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771342433 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1771342433
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3033284019
Short name T41
Test name
Test status
Simulation time 30018856 ps
CPU time 0.96 seconds
Started Jun 09 12:47:44 PM PDT 24
Finished Jun 09 12:47:45 PM PDT 24
Peak memory 199088 kb
Host smart-0ca16fee-2678-4f5f-a104-6e7153e824e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033284019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3033284019
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2626081584
Short name T630
Test name
Test status
Simulation time 13390285 ps
CPU time 0.62 seconds
Started Jun 09 12:47:42 PM PDT 24
Finished Jun 09 12:47:43 PM PDT 24
Peak memory 194196 kb
Host smart-50ae1479-f743-4af2-8731-6fae60ed184b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626081584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2626081584
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3404492013
Short name T623
Test name
Test status
Simulation time 309862364 ps
CPU time 2.58 seconds
Started Jun 09 12:47:43 PM PDT 24
Finished Jun 09 12:47:46 PM PDT 24
Peak memory 199224 kb
Host smart-0713221f-1e39-49cb-998d-17336fed759e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404492013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3404492013
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2484894296
Short name T639
Test name
Test status
Simulation time 134966113 ps
CPU time 1.99 seconds
Started Jun 09 12:47:40 PM PDT 24
Finished Jun 09 12:47:42 PM PDT 24
Peak memory 199436 kb
Host smart-07640bf7-2451-49be-89b2-4bb24ac46773
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484894296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.2484894296
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4116771254
Short name T703
Test name
Test status
Simulation time 123410527 ps
CPU time 3.4 seconds
Started Jun 09 12:47:41 PM PDT 24
Finished Jun 09 12:47:45 PM PDT 24
Peak memory 199372 kb
Host smart-92f506e1-19e3-4a07-b9f9-064ca8dca2be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116771254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.4116771254
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.575193080
Short name T706
Test name
Test status
Simulation time 57304704 ps
CPU time 0.6 seconds
Started Jun 09 12:48:05 PM PDT 24
Finished Jun 09 12:48:05 PM PDT 24
Peak memory 194196 kb
Host smart-3cf9a434-b14b-47c0-b7a8-179b8fd40ddd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575193080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.575193080
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2924717788
Short name T611
Test name
Test status
Simulation time 23074453 ps
CPU time 0.63 seconds
Started Jun 09 12:48:03 PM PDT 24
Finished Jun 09 12:48:04 PM PDT 24
Peak memory 194256 kb
Host smart-561a74c5-970c-4044-ae67-616d89db54c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924717788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2924717788
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2381125750
Short name T615
Test name
Test status
Simulation time 39848465 ps
CPU time 0.58 seconds
Started Jun 09 12:48:03 PM PDT 24
Finished Jun 09 12:48:04 PM PDT 24
Peak memory 194192 kb
Host smart-1d2ee53a-cb03-4777-b6be-68d7f9989211
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381125750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2381125750
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2787072997
Short name T656
Test name
Test status
Simulation time 18510935 ps
CPU time 0.67 seconds
Started Jun 09 12:48:06 PM PDT 24
Finished Jun 09 12:48:07 PM PDT 24
Peak memory 194232 kb
Host smart-38dc9b8c-2341-4fb2-9d8f-934c53a8c564
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787072997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2787072997
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3517427124
Short name T704
Test name
Test status
Simulation time 16491541 ps
CPU time 0.62 seconds
Started Jun 09 12:48:03 PM PDT 24
Finished Jun 09 12:48:04 PM PDT 24
Peak memory 194128 kb
Host smart-2876a850-ffb6-4e7a-b2a3-cb6242ad3aea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517427124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3517427124
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1404551300
Short name T678
Test name
Test status
Simulation time 21549594 ps
CPU time 0.61 seconds
Started Jun 09 12:48:02 PM PDT 24
Finished Jun 09 12:48:03 PM PDT 24
Peak memory 194464 kb
Host smart-66c26f86-6ef4-4275-8f73-64971c5835ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404551300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1404551300
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.2132658927
Short name T683
Test name
Test status
Simulation time 20493389 ps
CPU time 0.61 seconds
Started Jun 09 12:48:02 PM PDT 24
Finished Jun 09 12:48:03 PM PDT 24
Peak memory 194464 kb
Host smart-a20a8490-f80d-4ac1-a5e9-422d7f800e96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132658927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2132658927
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2230571233
Short name T723
Test name
Test status
Simulation time 27278185 ps
CPU time 0.62 seconds
Started Jun 09 12:48:04 PM PDT 24
Finished Jun 09 12:48:05 PM PDT 24
Peak memory 194136 kb
Host smart-017e58bc-48da-444e-8f8b-9fa63943cc3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230571233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2230571233
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1148563672
Short name T652
Test name
Test status
Simulation time 14974980 ps
CPU time 0.64 seconds
Started Jun 09 12:48:03 PM PDT 24
Finished Jun 09 12:48:04 PM PDT 24
Peak memory 194200 kb
Host smart-1de6aa43-8fd6-4ef9-b7ec-850cf97e712d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148563672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1148563672
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.415178918
Short name T616
Test name
Test status
Simulation time 39806059 ps
CPU time 0.63 seconds
Started Jun 09 12:48:04 PM PDT 24
Finished Jun 09 12:48:05 PM PDT 24
Peak memory 194240 kb
Host smart-2552dd88-7e2c-4959-a82f-5963ecd435aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415178918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.415178918
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2596615087
Short name T608
Test name
Test status
Simulation time 166934890 ps
CPU time 3.54 seconds
Started Jun 09 12:47:49 PM PDT 24
Finished Jun 09 12:47:53 PM PDT 24
Peak memory 199160 kb
Host smart-c9c062a1-a2eb-4eb4-9737-79c6eb83c083
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596615087 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2596615087
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1479703626
Short name T81
Test name
Test status
Simulation time 137069500 ps
CPU time 0.96 seconds
Started Jun 09 12:47:45 PM PDT 24
Finished Jun 09 12:47:46 PM PDT 24
Peak memory 199044 kb
Host smart-ef63e059-e4f1-4287-937a-3a63658ff295
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479703626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1479703626
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2878084515
Short name T661
Test name
Test status
Simulation time 11426374 ps
CPU time 0.59 seconds
Started Jun 09 12:47:43 PM PDT 24
Finished Jun 09 12:47:44 PM PDT 24
Peak memory 194112 kb
Host smart-376be8a4-5b58-4c1f-ac1b-ad4642080519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878084515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2878084515
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3600958743
Short name T610
Test name
Test status
Simulation time 44383883 ps
CPU time 1.22 seconds
Started Jun 09 12:47:43 PM PDT 24
Finished Jun 09 12:47:45 PM PDT 24
Peak memory 199328 kb
Host smart-07efa64d-18e5-4b18-a091-1ff7c145faee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600958743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3600958743
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.17580740
Short name T612
Test name
Test status
Simulation time 147358609 ps
CPU time 3.36 seconds
Started Jun 09 12:47:42 PM PDT 24
Finished Jun 09 12:47:46 PM PDT 24
Peak memory 199352 kb
Host smart-e33c07da-be24-4e30-b726-45dcc4bc5c4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17580740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.17580740
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.428361457
Short name T110
Test name
Test status
Simulation time 196961535 ps
CPU time 1.92 seconds
Started Jun 09 12:47:42 PM PDT 24
Finished Jun 09 12:47:45 PM PDT 24
Peak memory 199276 kb
Host smart-6039f73f-cf55-4f1c-af24-347e6b25d045
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428361457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.428361457
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3258573625
Short name T617
Test name
Test status
Simulation time 174671423 ps
CPU time 3.29 seconds
Started Jun 09 12:47:50 PM PDT 24
Finished Jun 09 12:47:54 PM PDT 24
Peak memory 207712 kb
Host smart-4cedb9d7-334b-4833-9eb5-08febaf482f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258573625 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3258573625
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3763850720
Short name T681
Test name
Test status
Simulation time 26129713 ps
CPU time 0.87 seconds
Started Jun 09 12:47:53 PM PDT 24
Finished Jun 09 12:47:55 PM PDT 24
Peak memory 199052 kb
Host smart-8c7c25b7-f12a-4b80-8594-350cc17426c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763850720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3763850720
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2364508020
Short name T679
Test name
Test status
Simulation time 19108778 ps
CPU time 0.61 seconds
Started Jun 09 12:47:54 PM PDT 24
Finished Jun 09 12:47:55 PM PDT 24
Peak memory 194168 kb
Host smart-3c3347d2-64c1-4017-83cb-beaca6eb8d33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364508020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2364508020
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2636151459
Short name T598
Test name
Test status
Simulation time 85024092 ps
CPU time 2.25 seconds
Started Jun 09 12:47:51 PM PDT 24
Finished Jun 09 12:47:53 PM PDT 24
Peak memory 199240 kb
Host smart-79fbcff8-f0d5-4baf-96c6-55d083b62b66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636151459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2636151459
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1656523764
Short name T693
Test name
Test status
Simulation time 172248447 ps
CPU time 2.35 seconds
Started Jun 09 12:47:44 PM PDT 24
Finished Jun 09 12:47:46 PM PDT 24
Peak memory 199316 kb
Host smart-cfcfe1e7-643d-45ac-929d-af02241d8eb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656523764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1656523764
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.425483332
Short name T106
Test name
Test status
Simulation time 157883565 ps
CPU time 2.79 seconds
Started Jun 09 12:47:49 PM PDT 24
Finished Jun 09 12:47:52 PM PDT 24
Peak memory 199296 kb
Host smart-8950953b-1305-4ee3-afa1-8220c7018d8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425483332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.425483332
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.530312725
Short name T607
Test name
Test status
Simulation time 200989016 ps
CPU time 3.6 seconds
Started Jun 09 12:47:50 PM PDT 24
Finished Jun 09 12:47:54 PM PDT 24
Peak memory 214820 kb
Host smart-6f3e2c73-98cb-4a09-a3e9-30d0ffb83523
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530312725 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.530312725
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1405611830
Short name T721
Test name
Test status
Simulation time 29790300 ps
CPU time 0.96 seconds
Started Jun 09 12:47:49 PM PDT 24
Finished Jun 09 12:47:51 PM PDT 24
Peak memory 198648 kb
Host smart-51f6ee6b-d8f6-4414-aa4a-0e315e056dcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405611830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.1405611830
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.731618128
Short name T684
Test name
Test status
Simulation time 28594589 ps
CPU time 0.61 seconds
Started Jun 09 12:47:49 PM PDT 24
Finished Jun 09 12:47:50 PM PDT 24
Peak memory 194256 kb
Host smart-5f2def62-9296-44f4-93df-334dd8fefd3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731618128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.731618128
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3384566494
Short name T688
Test name
Test status
Simulation time 64430237 ps
CPU time 2.22 seconds
Started Jun 09 12:47:49 PM PDT 24
Finished Jun 09 12:47:52 PM PDT 24
Peak memory 199324 kb
Host smart-10edae4d-7886-4ac4-bd0c-286bfdfefd8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384566494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3384566494
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2826653396
Short name T632
Test name
Test status
Simulation time 69524255 ps
CPU time 3.86 seconds
Started Jun 09 12:47:51 PM PDT 24
Finished Jun 09 12:47:55 PM PDT 24
Peak memory 199380 kb
Host smart-8e71c58f-566d-4535-9676-0c98a5a5f45f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826653396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2826653396
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2873968328
Short name T713
Test name
Test status
Simulation time 107838420 ps
CPU time 1.98 seconds
Started Jun 09 12:47:46 PM PDT 24
Finished Jun 09 12:47:48 PM PDT 24
Peak memory 199372 kb
Host smart-d90533f7-885f-46b7-8be0-45043d9774bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873968328 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2873968328
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2059418369
Short name T82
Test name
Test status
Simulation time 28843317 ps
CPU time 0.92 seconds
Started Jun 09 12:47:51 PM PDT 24
Finished Jun 09 12:47:52 PM PDT 24
Peak memory 199044 kb
Host smart-10c63a90-d3eb-4bd1-861b-fbd760f39b3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059418369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2059418369
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3035217766
Short name T624
Test name
Test status
Simulation time 14943141 ps
CPU time 0.64 seconds
Started Jun 09 12:47:50 PM PDT 24
Finished Jun 09 12:47:51 PM PDT 24
Peak memory 194192 kb
Host smart-1ff519c9-22fb-410e-b40e-cfda6fc7a426
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035217766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3035217766
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1274353345
Short name T690
Test name
Test status
Simulation time 37068599 ps
CPU time 1.75 seconds
Started Jun 09 12:47:48 PM PDT 24
Finished Jun 09 12:47:51 PM PDT 24
Peak memory 199360 kb
Host smart-91dc54d2-febf-45c8-8bf6-3700b863053f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274353345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1274353345
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.565460514
Short name T627
Test name
Test status
Simulation time 82985742 ps
CPU time 4.19 seconds
Started Jun 09 12:47:49 PM PDT 24
Finished Jun 09 12:47:53 PM PDT 24
Peak memory 199376 kb
Host smart-c2a23b0f-1e24-458c-a850-b6aa5b491b36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565460514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.565460514
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2646217912
Short name T621
Test name
Test status
Simulation time 57902409598 ps
CPU time 587.14 seconds
Started Jun 09 12:47:50 PM PDT 24
Finished Jun 09 12:57:38 PM PDT 24
Peak memory 215868 kb
Host smart-3814c9c5-b9a9-465e-abd2-bb077ddb851f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646217912 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2646217912
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3658750404
Short name T86
Test name
Test status
Simulation time 32444971 ps
CPU time 0.98 seconds
Started Jun 09 12:47:48 PM PDT 24
Finished Jun 09 12:47:49 PM PDT 24
Peak memory 199076 kb
Host smart-80b6cab9-f661-4216-b9f2-7314d8b907a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658750404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3658750404
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.490815280
Short name T628
Test name
Test status
Simulation time 46952534 ps
CPU time 0.64 seconds
Started Jun 09 12:47:49 PM PDT 24
Finished Jun 09 12:47:50 PM PDT 24
Peak memory 194224 kb
Host smart-8f4766e7-31f1-47be-8b41-299447773bb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490815280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.490815280
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.713543509
Short name T677
Test name
Test status
Simulation time 47839891 ps
CPU time 2.31 seconds
Started Jun 09 12:47:48 PM PDT 24
Finished Jun 09 12:47:51 PM PDT 24
Peak memory 199308 kb
Host smart-d3cf1eaa-4a2d-4b5f-9a61-774b2763a295
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713543509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.713543509
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1528012284
Short name T659
Test name
Test status
Simulation time 1284447855 ps
CPU time 4.62 seconds
Started Jun 09 12:47:53 PM PDT 24
Finished Jun 09 12:47:58 PM PDT 24
Peak memory 199268 kb
Host smart-2b0412db-c4cf-4dc0-a804-b19e2f5e01a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528012284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1528012284
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2563394168
Short name T692
Test name
Test status
Simulation time 784500028 ps
CPU time 1.95 seconds
Started Jun 09 12:47:46 PM PDT 24
Finished Jun 09 12:47:49 PM PDT 24
Peak memory 199576 kb
Host smart-b44dca7f-25a0-4755-90b7-89345f751883
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563394168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2563394168
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.925077983
Short name T456
Test name
Test status
Simulation time 41573776 ps
CPU time 0.62 seconds
Started Jun 09 01:43:41 PM PDT 24
Finished Jun 09 01:43:42 PM PDT 24
Peak memory 196420 kb
Host smart-661ed888-40c9-416e-9e4c-60e27d80bfb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925077983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.925077983
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.6544440
Short name T244
Test name
Test status
Simulation time 784524383 ps
CPU time 16.55 seconds
Started Jun 09 01:43:40 PM PDT 24
Finished Jun 09 01:43:57 PM PDT 24
Peak memory 208652 kb
Host smart-a1205e34-1e8d-444d-b98a-12d3ad24a3bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=6544440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.6544440
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1994831046
Short name T569
Test name
Test status
Simulation time 536163363 ps
CPU time 3.2 seconds
Started Jun 09 01:43:40 PM PDT 24
Finished Jun 09 01:43:44 PM PDT 24
Peak memory 200344 kb
Host smart-d9410f2a-f870-4f60-b64b-075190479d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994831046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1994831046
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.678080824
Short name T553
Test name
Test status
Simulation time 32977865152 ps
CPU time 919.29 seconds
Started Jun 09 01:43:42 PM PDT 24
Finished Jun 09 01:59:02 PM PDT 24
Peak memory 754984 kb
Host smart-d3940978-fdb7-4a06-8c89-558cebfd323b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=678080824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.678080824
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1349948134
Short name T536
Test name
Test status
Simulation time 27605305083 ps
CPU time 92.39 seconds
Started Jun 09 01:43:41 PM PDT 24
Finished Jun 09 01:45:14 PM PDT 24
Peak memory 200532 kb
Host smart-5fa8a7bd-e9f4-4857-9b47-3cb23f129aa5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349948134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1349948134
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1346840246
Short name T556
Test name
Test status
Simulation time 4901351470 ps
CPU time 69.76 seconds
Started Jun 09 01:43:41 PM PDT 24
Finished Jun 09 01:44:51 PM PDT 24
Peak memory 200488 kb
Host smart-8dab5e19-a37a-456a-844f-a8c3344610ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346840246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1346840246
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1407464494
Short name T31
Test name
Test status
Simulation time 590600440 ps
CPU time 1.01 seconds
Started Jun 09 01:43:42 PM PDT 24
Finished Jun 09 01:43:44 PM PDT 24
Peak memory 219924 kb
Host smart-a3bfa1df-02c9-4f69-b3f3-2e5600154d05
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407464494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1407464494
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.630345049
Short name T285
Test name
Test status
Simulation time 85106009 ps
CPU time 1.72 seconds
Started Jun 09 01:43:37 PM PDT 24
Finished Jun 09 01:43:39 PM PDT 24
Peak memory 200448 kb
Host smart-c739a5de-8e79-40ec-ba7b-0f6306704080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630345049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.630345049
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.733165293
Short name T245
Test name
Test status
Simulation time 56347796267 ps
CPU time 753.38 seconds
Started Jun 09 01:43:41 PM PDT 24
Finished Jun 09 01:56:15 PM PDT 24
Peak memory 234300 kb
Host smart-0af541fb-8ebf-4bcc-b651-c3c6aa50ba7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733165293 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.733165293
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.3084494943
Short name T165
Test name
Test status
Simulation time 436591330 ps
CPU time 1.07 seconds
Started Jun 09 01:43:42 PM PDT 24
Finished Jun 09 01:43:44 PM PDT 24
Peak memory 200256 kb
Host smart-6d64c99e-4821-4ae2-b4cc-0a4f381478db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084494943 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.3084494943
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.1430033591
Short name T271
Test name
Test status
Simulation time 61488382035 ps
CPU time 420.98 seconds
Started Jun 09 01:43:38 PM PDT 24
Finished Jun 09 01:50:40 PM PDT 24
Peak memory 200452 kb
Host smart-bcab167d-f17e-4f28-991e-28fc0777a1f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430033591 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.1430033591
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3402428305
Short name T483
Test name
Test status
Simulation time 4558385350 ps
CPU time 65.67 seconds
Started Jun 09 01:43:41 PM PDT 24
Finished Jun 09 01:44:47 PM PDT 24
Peak memory 200504 kb
Host smart-2676a2ac-3259-472e-a532-bd6a6cc55baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402428305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3402428305
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2872032460
Short name T360
Test name
Test status
Simulation time 15393476 ps
CPU time 0.64 seconds
Started Jun 09 01:43:43 PM PDT 24
Finished Jun 09 01:43:44 PM PDT 24
Peak memory 197128 kb
Host smart-90d01ada-d9f8-4a54-9d1c-37e80763fc33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872032460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2872032460
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2933495525
Short name T293
Test name
Test status
Simulation time 1092989736 ps
CPU time 50.47 seconds
Started Jun 09 01:43:42 PM PDT 24
Finished Jun 09 01:44:33 PM PDT 24
Peak memory 216800 kb
Host smart-dbd68fe8-4523-49f7-a7e1-735aba35e7ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2933495525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2933495525
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.323841909
Short name T100
Test name
Test status
Simulation time 659074922 ps
CPU time 35.25 seconds
Started Jun 09 01:43:39 PM PDT 24
Finished Jun 09 01:44:15 PM PDT 24
Peak memory 200464 kb
Host smart-6cf19fbe-6468-4906-ab8d-f9371d9dcb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323841909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.323841909
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.518531038
Short name T398
Test name
Test status
Simulation time 1806915877 ps
CPU time 399.85 seconds
Started Jun 09 01:43:42 PM PDT 24
Finished Jun 09 01:50:22 PM PDT 24
Peak memory 646284 kb
Host smart-724fc3c4-6871-4038-951c-7ab991d10862
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=518531038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.518531038
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.4184480208
Short name T564
Test name
Test status
Simulation time 44692864044 ps
CPU time 81.75 seconds
Started Jun 09 01:43:39 PM PDT 24
Finished Jun 09 01:45:02 PM PDT 24
Peak memory 200548 kb
Host smart-5271709d-c67a-4cec-87aa-b2cdf6c07cc9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184480208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.4184480208
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.93445842
Short name T372
Test name
Test status
Simulation time 1472251931 ps
CPU time 15.24 seconds
Started Jun 09 01:43:42 PM PDT 24
Finished Jun 09 01:43:58 PM PDT 24
Peak memory 200404 kb
Host smart-362823ed-3fc6-4780-8da8-71fcddf530bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93445842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.93445842
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1531490536
Short name T3
Test name
Test status
Simulation time 67299730 ps
CPU time 0.82 seconds
Started Jun 09 01:43:40 PM PDT 24
Finished Jun 09 01:43:41 PM PDT 24
Peak memory 218820 kb
Host smart-4a32da03-9229-436f-89fc-439b3f7278be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531490536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1531490536
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.1740195096
Short name T353
Test name
Test status
Simulation time 629241159 ps
CPU time 6.61 seconds
Started Jun 09 01:43:39 PM PDT 24
Finished Jun 09 01:43:46 PM PDT 24
Peak memory 200660 kb
Host smart-cd181611-7739-4504-a6e9-62ddd6eaede6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740195096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1740195096
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.966857936
Short name T375
Test name
Test status
Simulation time 150552768 ps
CPU time 1.36 seconds
Started Jun 09 01:43:48 PM PDT 24
Finished Jun 09 01:43:51 PM PDT 24
Peak memory 199544 kb
Host smart-aabaa54f-6e27-4f08-98b7-21daaa5940aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966857936 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_hmac_vectors.966857936
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.2106261640
Short name T222
Test name
Test status
Simulation time 31020722702 ps
CPU time 420.75 seconds
Started Jun 09 01:43:40 PM PDT 24
Finished Jun 09 01:50:41 PM PDT 24
Peak memory 200648 kb
Host smart-35b07451-97bb-4086-acc4-84db41d9acce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106261640 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.2106261640
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.924267247
Short name T304
Test name
Test status
Simulation time 2820706430 ps
CPU time 43.16 seconds
Started Jun 09 01:43:40 PM PDT 24
Finished Jun 09 01:44:24 PM PDT 24
Peak memory 200520 kb
Host smart-5e96a9b3-099d-470a-a09c-062e732ee865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924267247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.924267247
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2302152525
Short name T542
Test name
Test status
Simulation time 11367551 ps
CPU time 0.62 seconds
Started Jun 09 01:44:02 PM PDT 24
Finished Jun 09 01:44:02 PM PDT 24
Peak memory 196100 kb
Host smart-4362501a-4552-45d7-b43c-eb9894efbf7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302152525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2302152525
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.2689017405
Short name T369
Test name
Test status
Simulation time 8534484678 ps
CPU time 74.66 seconds
Started Jun 09 01:43:58 PM PDT 24
Finished Jun 09 01:45:13 PM PDT 24
Peak memory 227964 kb
Host smart-28d358d2-457a-4115-aeb9-1e5f04bce55f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2689017405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2689017405
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3078929303
Short name T486
Test name
Test status
Simulation time 39712494 ps
CPU time 1.25 seconds
Started Jun 09 01:44:00 PM PDT 24
Finished Jun 09 01:44:02 PM PDT 24
Peak memory 200368 kb
Host smart-ecba0db3-7262-4091-acaf-e3184f7d1408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078929303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3078929303
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.3290021511
Short name T491
Test name
Test status
Simulation time 11765670007 ps
CPU time 710.47 seconds
Started Jun 09 01:44:03 PM PDT 24
Finished Jun 09 01:55:54 PM PDT 24
Peak memory 705540 kb
Host smart-aad43309-ce81-45d3-9a43-704468615d00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3290021511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3290021511
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.151830280
Short name T150
Test name
Test status
Simulation time 5680188342 ps
CPU time 60.39 seconds
Started Jun 09 01:44:02 PM PDT 24
Finished Jun 09 01:45:03 PM PDT 24
Peak memory 200584 kb
Host smart-961233e9-d484-46a3-9527-f376f0921ee0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151830280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.151830280
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.97706945
Short name T583
Test name
Test status
Simulation time 5935311704 ps
CPU time 116.2 seconds
Started Jun 09 01:43:58 PM PDT 24
Finished Jun 09 01:45:55 PM PDT 24
Peak memory 200520 kb
Host smart-97965efa-3f16-4ab2-815b-30ca57587c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97706945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.97706945
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.3647645757
Short name T68
Test name
Test status
Simulation time 1481195233 ps
CPU time 3.65 seconds
Started Jun 09 01:43:59 PM PDT 24
Finished Jun 09 01:44:03 PM PDT 24
Peak memory 200440 kb
Host smart-1a9ebf0b-56c4-4846-8746-9b97bd3d526b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647645757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3647645757
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1777631240
Short name T310
Test name
Test status
Simulation time 341802341838 ps
CPU time 1177.69 seconds
Started Jun 09 01:44:05 PM PDT 24
Finished Jun 09 02:03:43 PM PDT 24
Peak memory 676060 kb
Host smart-a4289732-05d4-4a5d-81db-fd5ccd1b688f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777631240 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1777631240
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.3476863617
Short name T513
Test name
Test status
Simulation time 179964901 ps
CPU time 1.23 seconds
Started Jun 09 01:44:00 PM PDT 24
Finished Jun 09 01:44:01 PM PDT 24
Peak memory 200504 kb
Host smart-ab26eb62-b8d4-4c7c-ac07-eac533c89203
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476863617 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.3476863617
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.2256685047
Short name T303
Test name
Test status
Simulation time 38814590973 ps
CPU time 531.69 seconds
Started Jun 09 01:44:02 PM PDT 24
Finished Jun 09 01:52:54 PM PDT 24
Peak memory 200484 kb
Host smart-6b00d292-f7f4-4998-ab0e-4b286a9efeb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256685047 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.2256685047
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2363530466
Short name T186
Test name
Test status
Simulation time 28750891447 ps
CPU time 86.14 seconds
Started Jun 09 01:44:03 PM PDT 24
Finished Jun 09 01:45:30 PM PDT 24
Peak memory 200556 kb
Host smart-1753ccca-7123-4ca4-9d14-1fdc36f73702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363530466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2363530466
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2615216515
Short name T472
Test name
Test status
Simulation time 14724698 ps
CPU time 0.63 seconds
Started Jun 09 01:44:02 PM PDT 24
Finished Jun 09 01:44:03 PM PDT 24
Peak memory 196408 kb
Host smart-6d7e4cac-84f5-4957-b79a-0540b75aab56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615216515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2615216515
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3732681851
Short name T380
Test name
Test status
Simulation time 6416033226 ps
CPU time 38.99 seconds
Started Jun 09 01:44:02 PM PDT 24
Finished Jun 09 01:44:42 PM PDT 24
Peak memory 216848 kb
Host smart-e48f7dad-d5df-437a-8a4a-952574f7334a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3732681851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3732681851
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3403473629
Short name T120
Test name
Test status
Simulation time 240961237 ps
CPU time 4.23 seconds
Started Jun 09 01:44:00 PM PDT 24
Finished Jun 09 01:44:05 PM PDT 24
Peak memory 200396 kb
Host smart-bdbd3aaf-e359-4e7c-883e-414286c8f89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403473629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3403473629
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2024184421
Short name T151
Test name
Test status
Simulation time 9344577810 ps
CPU time 855.91 seconds
Started Jun 09 01:44:03 PM PDT 24
Finished Jun 09 01:58:19 PM PDT 24
Peak memory 761200 kb
Host smart-96d12b70-647a-4c75-a04f-60df120abd7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2024184421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2024184421
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1616165381
Short name T579
Test name
Test status
Simulation time 9267306318 ps
CPU time 163.78 seconds
Started Jun 09 01:44:04 PM PDT 24
Finished Jun 09 01:46:48 PM PDT 24
Peak memory 200448 kb
Host smart-ab71d416-6c05-4595-8d22-1a67ccf7e374
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616165381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1616165381
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.770618495
Short name T236
Test name
Test status
Simulation time 23577828510 ps
CPU time 107.97 seconds
Started Jun 09 01:44:03 PM PDT 24
Finished Jun 09 01:45:51 PM PDT 24
Peak memory 200548 kb
Host smart-b9c38074-d9d9-4406-8063-5148e4b92e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770618495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.770618495
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2590566518
Short name T478
Test name
Test status
Simulation time 448986331 ps
CPU time 6.23 seconds
Started Jun 09 01:44:01 PM PDT 24
Finished Jun 09 01:44:08 PM PDT 24
Peak memory 200432 kb
Host smart-d34978b5-0454-40a1-b220-9c49012c60e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590566518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2590566518
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3347005947
Short name T61
Test name
Test status
Simulation time 133126226602 ps
CPU time 2744.16 seconds
Started Jun 09 01:44:02 PM PDT 24
Finished Jun 09 02:29:47 PM PDT 24
Peak memory 801820 kb
Host smart-665398e2-0569-49ae-b0b2-31c7a87aff37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347005947 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3347005947
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.3911623095
Short name T451
Test name
Test status
Simulation time 30409130 ps
CPU time 1.2 seconds
Started Jun 09 01:44:03 PM PDT 24
Finished Jun 09 01:44:04 PM PDT 24
Peak memory 200432 kb
Host smart-35c04578-ebd9-4ef3-a9bd-209cf52faa37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911623095 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.3911623095
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3447370759
Short name T482
Test name
Test status
Simulation time 17553608996 ps
CPU time 447.78 seconds
Started Jun 09 01:44:03 PM PDT 24
Finished Jun 09 01:51:31 PM PDT 24
Peak memory 200484 kb
Host smart-ec124df8-f50b-47d5-a45a-3bd571a2b5eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447370759 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.3447370759
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.4063356453
Short name T452
Test name
Test status
Simulation time 2980914492 ps
CPU time 39.91 seconds
Started Jun 09 01:44:02 PM PDT 24
Finished Jun 09 01:44:43 PM PDT 24
Peak memory 200548 kb
Host smart-418582e6-2b00-461c-a713-cb6dbf4a2657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063356453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.4063356453
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1221109819
Short name T386
Test name
Test status
Simulation time 618293381 ps
CPU time 38.54 seconds
Started Jun 09 01:44:03 PM PDT 24
Finished Jun 09 01:44:42 PM PDT 24
Peak memory 233412 kb
Host smart-22f88e36-bc18-445b-a40d-0b420d90a1a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1221109819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1221109819
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2602588093
Short name T359
Test name
Test status
Simulation time 14962948552 ps
CPU time 63.36 seconds
Started Jun 09 01:44:04 PM PDT 24
Finished Jun 09 01:45:07 PM PDT 24
Peak memory 200468 kb
Host smart-dda86151-4ff7-413e-bb25-f9426ca2bac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602588093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2602588093
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.940710561
Short name T169
Test name
Test status
Simulation time 10227523227 ps
CPU time 517.37 seconds
Started Jun 09 01:44:03 PM PDT 24
Finished Jun 09 01:52:41 PM PDT 24
Peak memory 521504 kb
Host smart-a0e88d82-4822-4d62-8216-e7c45a93cb87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=940710561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.940710561
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3363413486
Short name T389
Test name
Test status
Simulation time 7921664188 ps
CPU time 98.71 seconds
Started Jun 09 01:44:06 PM PDT 24
Finished Jun 09 01:45:45 PM PDT 24
Peak memory 200512 kb
Host smart-6e24b7d4-210f-4b91-8bbc-58b5354ccacc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363413486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3363413486
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3360463100
Short name T140
Test name
Test status
Simulation time 23529656170 ps
CPU time 87.75 seconds
Started Jun 09 01:44:01 PM PDT 24
Finished Jun 09 01:45:29 PM PDT 24
Peak memory 200528 kb
Host smart-baf94035-1a64-4696-8d82-f5ddfca2c187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360463100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3360463100
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3821987559
Short name T450
Test name
Test status
Simulation time 221494268 ps
CPU time 1.34 seconds
Started Jun 09 01:44:08 PM PDT 24
Finished Jun 09 01:44:10 PM PDT 24
Peak memory 200432 kb
Host smart-88d61ae8-ee14-4c3a-a490-3c4f0d68505b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821987559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3821987559
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1780136461
Short name T94
Test name
Test status
Simulation time 11579188063 ps
CPU time 1091.69 seconds
Started Jun 09 01:44:06 PM PDT 24
Finished Jun 09 02:02:18 PM PDT 24
Peak memory 773480 kb
Host smart-dca66860-d5b8-43e3-b072-bf5148bd95b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780136461 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1780136461
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.1075263491
Short name T404
Test name
Test status
Simulation time 451449021 ps
CPU time 1.21 seconds
Started Jun 09 01:44:05 PM PDT 24
Finished Jun 09 01:44:06 PM PDT 24
Peak memory 200440 kb
Host smart-0f0e99fa-15f0-409a-a439-be0975e51c6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075263491 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.1075263491
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.2808279004
Short name T193
Test name
Test status
Simulation time 85348523723 ps
CPU time 445.32 seconds
Started Jun 09 01:44:07 PM PDT 24
Finished Jun 09 01:51:32 PM PDT 24
Peak memory 200440 kb
Host smart-9ee2ded0-20ca-4f68-ac56-62ffdbec2a84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808279004 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.2808279004
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2101681992
Short name T464
Test name
Test status
Simulation time 5641423220 ps
CPU time 41.13 seconds
Started Jun 09 01:44:05 PM PDT 24
Finished Jun 09 01:44:47 PM PDT 24
Peak memory 200520 kb
Host smart-9c91d81a-f1e9-4f37-816a-5d2a85cf25e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101681992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2101681992
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/121.hmac_stress_all_with_rand_reset.1665520124
Short name T45
Test name
Test status
Simulation time 144299897743 ps
CPU time 4308.26 seconds
Started Jun 09 01:47:07 PM PDT 24
Finished Jun 09 02:58:56 PM PDT 24
Peak memory 845640 kb
Host smart-026f5238-0785-4d73-8abb-1d67888f746b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1665520124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.hmac_stress_all_with_rand_reset.1665520124
Directory /workspace/121.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3458945926
Short name T260
Test name
Test status
Simulation time 30413500 ps
CPU time 0.58 seconds
Started Jun 09 01:44:07 PM PDT 24
Finished Jun 09 01:44:08 PM PDT 24
Peak memory 195376 kb
Host smart-fa710867-edad-4d2a-9886-35a75b4a597f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458945926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3458945926
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.258368030
Short name T435
Test name
Test status
Simulation time 8990597438 ps
CPU time 48.32 seconds
Started Jun 09 01:44:09 PM PDT 24
Finished Jun 09 01:44:57 PM PDT 24
Peak memory 228516 kb
Host smart-6c16f0e8-b1fd-499a-b9d4-685d15dd3898
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=258368030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.258368030
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2166105825
Short name T396
Test name
Test status
Simulation time 32460639676 ps
CPU time 1172.33 seconds
Started Jun 09 01:44:07 PM PDT 24
Finished Jun 09 02:03:40 PM PDT 24
Peak memory 771860 kb
Host smart-19610c04-ba22-4003-8a20-0ea986c1449e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2166105825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2166105825
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3563449638
Short name T570
Test name
Test status
Simulation time 2273584076 ps
CPU time 33 seconds
Started Jun 09 01:44:08 PM PDT 24
Finished Jun 09 01:44:41 PM PDT 24
Peak memory 200480 kb
Host smart-eb3ac3d8-4c5f-479c-98e7-3ab35177bbd6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563449638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3563449638
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2152489034
Short name T413
Test name
Test status
Simulation time 8972405145 ps
CPU time 30.87 seconds
Started Jun 09 01:44:10 PM PDT 24
Finished Jun 09 01:44:41 PM PDT 24
Peak memory 200452 kb
Host smart-cd5502e5-671c-45f8-885f-19be98ea0469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152489034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2152489034
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3031699521
Short name T282
Test name
Test status
Simulation time 137323642 ps
CPU time 4.71 seconds
Started Jun 09 01:44:09 PM PDT 24
Finished Jun 09 01:44:14 PM PDT 24
Peak memory 200620 kb
Host smart-95184adf-c5b0-48c0-89ef-e324865a96b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031699521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3031699521
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.3091940838
Short name T161
Test name
Test status
Simulation time 56818631 ps
CPU time 1.17 seconds
Started Jun 09 01:44:07 PM PDT 24
Finished Jun 09 01:44:09 PM PDT 24
Peak memory 200216 kb
Host smart-d1107569-4c70-46ac-9a61-dd2ddd13eb7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091940838 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.3091940838
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.3551499554
Short name T332
Test name
Test status
Simulation time 75920417600 ps
CPU time 456.67 seconds
Started Jun 09 01:44:05 PM PDT 24
Finished Jun 09 01:51:42 PM PDT 24
Peak memory 200436 kb
Host smart-c1d8c3a3-3015-4e07-91de-daf43f6ecd6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551499554 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.3551499554
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3222066250
Short name T441
Test name
Test status
Simulation time 1940106997 ps
CPU time 8.94 seconds
Started Jun 09 01:44:08 PM PDT 24
Finished Jun 09 01:44:17 PM PDT 24
Peak memory 200424 kb
Host smart-1dd0d5f6-5307-4262-bb44-395bda888e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222066250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3222066250
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.3996359259
Short name T554
Test name
Test status
Simulation time 52581171 ps
CPU time 0.6 seconds
Started Jun 09 01:44:07 PM PDT 24
Finished Jun 09 01:44:08 PM PDT 24
Peak memory 195340 kb
Host smart-6c11a687-6498-43cc-a166-03d433f128c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996359259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3996359259
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1458985620
Short name T580
Test name
Test status
Simulation time 1386965754 ps
CPU time 37.51 seconds
Started Jun 09 01:44:07 PM PDT 24
Finished Jun 09 01:44:45 PM PDT 24
Peak memory 233248 kb
Host smart-03e40c59-4c35-423f-9d20-6d08fa79f1dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1458985620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1458985620
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.319432222
Short name T343
Test name
Test status
Simulation time 2389061860 ps
CPU time 45.62 seconds
Started Jun 09 01:44:06 PM PDT 24
Finished Jun 09 01:44:52 PM PDT 24
Peak memory 200476 kb
Host smart-c5ef6542-0fdf-41c0-930f-46a031bdc8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319432222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.319432222
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.4204460406
Short name T131
Test name
Test status
Simulation time 1011474087 ps
CPU time 274.98 seconds
Started Jun 09 01:44:09 PM PDT 24
Finished Jun 09 01:48:44 PM PDT 24
Peak memory 632072 kb
Host smart-cd499a53-c7dc-4640-ba62-989325824a0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4204460406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.4204460406
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.580136326
Short name T294
Test name
Test status
Simulation time 9428394779 ps
CPU time 166.18 seconds
Started Jun 09 01:44:08 PM PDT 24
Finished Jun 09 01:46:55 PM PDT 24
Peak memory 200548 kb
Host smart-d5405311-7b1a-4703-902d-d3b0daef168e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580136326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.580136326
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1843847610
Short name T437
Test name
Test status
Simulation time 8624759238 ps
CPU time 64.72 seconds
Started Jun 09 01:44:10 PM PDT 24
Finished Jun 09 01:45:15 PM PDT 24
Peak memory 200492 kb
Host smart-62b8072d-f9ef-4a96-8341-6b5a6c1168e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843847610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1843847610
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1164076729
Short name T505
Test name
Test status
Simulation time 1254683911 ps
CPU time 7.23 seconds
Started Jun 09 01:44:06 PM PDT 24
Finished Jun 09 01:44:13 PM PDT 24
Peak memory 200468 kb
Host smart-b7a80116-13ab-4af8-9037-0603859fab2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164076729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1164076729
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.987085308
Short name T524
Test name
Test status
Simulation time 9521488010 ps
CPU time 115.56 seconds
Started Jun 09 01:44:07 PM PDT 24
Finished Jun 09 01:46:03 PM PDT 24
Peak memory 323880 kb
Host smart-ce76117c-7c3f-490b-8686-8bc98d299ad4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987085308 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.987085308
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.3179398164
Short name T322
Test name
Test status
Simulation time 103971968 ps
CPU time 1.16 seconds
Started Jun 09 01:44:11 PM PDT 24
Finished Jun 09 01:44:13 PM PDT 24
Peak memory 200256 kb
Host smart-bc85f6c6-977f-48e6-9f67-eb1d393e6ce9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179398164 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.3179398164
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.2468852708
Short name T425
Test name
Test status
Simulation time 287988761680 ps
CPU time 468.23 seconds
Started Jun 09 01:44:09 PM PDT 24
Finished Jun 09 01:51:57 PM PDT 24
Peak memory 200420 kb
Host smart-115acf4b-e516-4e7b-bcfa-f80459e3175c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468852708 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.2468852708
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.43093351
Short name T558
Test name
Test status
Simulation time 598989926 ps
CPU time 27.7 seconds
Started Jun 09 01:44:08 PM PDT 24
Finished Jun 09 01:44:37 PM PDT 24
Peak memory 200464 kb
Host smart-25778c2c-2f9e-4816-984e-ee18471384ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43093351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.43093351
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3268263525
Short name T449
Test name
Test status
Simulation time 14988941 ps
CPU time 0.59 seconds
Started Jun 09 01:44:10 PM PDT 24
Finished Jun 09 01:44:11 PM PDT 24
Peak memory 197124 kb
Host smart-bf5e4301-fcc7-463f-9793-2dad757f1d8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268263525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3268263525
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3926337181
Short name T97
Test name
Test status
Simulation time 6041596260 ps
CPU time 41.91 seconds
Started Jun 09 01:44:11 PM PDT 24
Finished Jun 09 01:44:53 PM PDT 24
Peak memory 216552 kb
Host smart-3e3ff6b8-697e-4f5d-955d-642ce0074d3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3926337181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3926337181
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1303864848
Short name T143
Test name
Test status
Simulation time 3490855147 ps
CPU time 32.61 seconds
Started Jun 09 01:44:14 PM PDT 24
Finished Jun 09 01:44:47 PM PDT 24
Peak memory 200540 kb
Host smart-df96dfd3-7827-4c64-b7fa-9ca26f4b3055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303864848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1303864848
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.462151545
Short name T247
Test name
Test status
Simulation time 7563685941 ps
CPU time 597.59 seconds
Started Jun 09 01:44:12 PM PDT 24
Finished Jun 09 01:54:10 PM PDT 24
Peak memory 750980 kb
Host smart-7c1ba457-fa23-410c-833c-4112f31c93b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=462151545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.462151545
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2611296598
Short name T514
Test name
Test status
Simulation time 7877815593 ps
CPU time 48.36 seconds
Started Jun 09 01:44:14 PM PDT 24
Finished Jun 09 01:45:02 PM PDT 24
Peak memory 200388 kb
Host smart-84ab816a-9fc4-4187-bad1-edc33bce7739
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611296598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2611296598
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1471076066
Short name T585
Test name
Test status
Simulation time 18834342655 ps
CPU time 68.37 seconds
Started Jun 09 01:44:11 PM PDT 24
Finished Jun 09 01:45:19 PM PDT 24
Peak memory 200540 kb
Host smart-5bc6bbd6-368e-43f5-8edf-89af8c9c8db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471076066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1471076066
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1398449688
Short name T429
Test name
Test status
Simulation time 574730357 ps
CPU time 6.25 seconds
Started Jun 09 01:44:13 PM PDT 24
Finished Jun 09 01:44:20 PM PDT 24
Peak memory 200524 kb
Host smart-65ef0b2f-d43b-4cad-a66f-1e890716f9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398449688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1398449688
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3541425321
Short name T27
Test name
Test status
Simulation time 377748693986 ps
CPU time 3395.49 seconds
Started Jun 09 01:44:13 PM PDT 24
Finished Jun 09 02:40:49 PM PDT 24
Peak memory 744984 kb
Host smart-b7b54bdd-f8c0-4880-8808-1e0ba8180247
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541425321 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3541425321
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.3430827198
Short name T224
Test name
Test status
Simulation time 51530962 ps
CPU time 1.03 seconds
Started Jun 09 01:44:12 PM PDT 24
Finished Jun 09 01:44:13 PM PDT 24
Peak memory 200108 kb
Host smart-4548d38e-52af-41cd-9604-d5e079ab2f52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430827198 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.3430827198
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.2471997418
Short name T201
Test name
Test status
Simulation time 40472098871 ps
CPU time 530.41 seconds
Started Jun 09 01:44:12 PM PDT 24
Finished Jun 09 01:53:03 PM PDT 24
Peak memory 200436 kb
Host smart-6adba7d5-9687-4855-af95-d117d863d079
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471997418 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.2471997418
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3946307871
Short name T547
Test name
Test status
Simulation time 1810386638 ps
CPU time 18.29 seconds
Started Jun 09 01:44:11 PM PDT 24
Finished Jun 09 01:44:29 PM PDT 24
Peak memory 200476 kb
Host smart-2909b68c-a4a4-4ab0-846d-67662461c602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946307871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3946307871
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.63864553
Short name T417
Test name
Test status
Simulation time 13544759 ps
CPU time 0.63 seconds
Started Jun 09 01:44:10 PM PDT 24
Finished Jun 09 01:44:11 PM PDT 24
Peak memory 196392 kb
Host smart-d79a90b0-11ae-4508-bdce-be027ee5ee62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63864553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.63864553
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2828356781
Short name T329
Test name
Test status
Simulation time 143565023 ps
CPU time 1.97 seconds
Started Jun 09 01:44:11 PM PDT 24
Finished Jun 09 01:44:14 PM PDT 24
Peak memory 200396 kb
Host smart-22eb52b0-c0c2-4c3a-827a-52381386ea30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2828356781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2828356781
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.814157227
Short name T211
Test name
Test status
Simulation time 9842762586 ps
CPU time 57.07 seconds
Started Jun 09 01:44:14 PM PDT 24
Finished Jun 09 01:45:11 PM PDT 24
Peak memory 200468 kb
Host smart-9608421c-e6ca-428c-8df1-481e949db874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814157227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.814157227
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.488262746
Short name T300
Test name
Test status
Simulation time 11500640074 ps
CPU time 799.88 seconds
Started Jun 09 01:44:13 PM PDT 24
Finished Jun 09 01:57:33 PM PDT 24
Peak memory 726512 kb
Host smart-a1591422-68b2-4e2f-9c5b-e9f000442172
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=488262746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.488262746
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2267754541
Short name T54
Test name
Test status
Simulation time 31820350929 ps
CPU time 214.67 seconds
Started Jun 09 01:44:10 PM PDT 24
Finished Jun 09 01:47:45 PM PDT 24
Peak memory 200532 kb
Host smart-10ea93b8-1011-4d96-a896-b6328cb3e36b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267754541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2267754541
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3015929257
Short name T308
Test name
Test status
Simulation time 26715889681 ps
CPU time 98.92 seconds
Started Jun 09 01:44:12 PM PDT 24
Finished Jun 09 01:45:51 PM PDT 24
Peak memory 200516 kb
Host smart-f1ffbd79-a1ca-446a-9dbe-4ef1c121ed06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015929257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3015929257
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.194893767
Short name T218
Test name
Test status
Simulation time 63195712 ps
CPU time 2.32 seconds
Started Jun 09 01:44:13 PM PDT 24
Finished Jun 09 01:44:16 PM PDT 24
Peak memory 200428 kb
Host smart-48b0c7a7-5475-4939-96c8-65de6150109e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194893767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.194893767
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.4016325178
Short name T438
Test name
Test status
Simulation time 25156565743 ps
CPU time 2186.19 seconds
Started Jun 09 01:44:12 PM PDT 24
Finished Jun 09 02:20:39 PM PDT 24
Peak memory 762160 kb
Host smart-45752871-b2ef-4d6d-935d-2952a96e8dad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016325178 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.4016325178
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.2313935476
Short name T400
Test name
Test status
Simulation time 312347647 ps
CPU time 1.39 seconds
Started Jun 09 01:44:15 PM PDT 24
Finished Jun 09 01:44:16 PM PDT 24
Peak memory 200472 kb
Host smart-4d84cda9-47f5-4b4a-bc54-b25439c50421
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313935476 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.2313935476
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.3057385475
Short name T318
Test name
Test status
Simulation time 32712542059 ps
CPU time 454.3 seconds
Started Jun 09 01:44:14 PM PDT 24
Finished Jun 09 01:51:48 PM PDT 24
Peak memory 200428 kb
Host smart-a5a9bbe9-2ace-481d-beda-1ac1d20c6f49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057385475 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.3057385475
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.181165400
Short name T352
Test name
Test status
Simulation time 1708153095 ps
CPU time 86.19 seconds
Started Jun 09 01:44:11 PM PDT 24
Finished Jun 09 01:45:38 PM PDT 24
Peak memory 200452 kb
Host smart-73eac9fa-972c-401f-bfde-2a7825994e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181165400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.181165400
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1454205337
Short name T182
Test name
Test status
Simulation time 51588973 ps
CPU time 0.62 seconds
Started Jun 09 01:44:17 PM PDT 24
Finished Jun 09 01:44:18 PM PDT 24
Peak memory 197124 kb
Host smart-935ccc59-b80d-4283-b4ee-1467dd2e76e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454205337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1454205337
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3514414436
Short name T20
Test name
Test status
Simulation time 172580336 ps
CPU time 10.3 seconds
Started Jun 09 01:44:15 PM PDT 24
Finished Jun 09 01:44:25 PM PDT 24
Peak memory 216740 kb
Host smart-39db47fc-2cc0-44fe-b69d-482f9a79c45d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3514414436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3514414436
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1902893711
Short name T333
Test name
Test status
Simulation time 2899347977 ps
CPU time 22.9 seconds
Started Jun 09 01:44:18 PM PDT 24
Finished Jun 09 01:44:42 PM PDT 24
Peak memory 200508 kb
Host smart-75bb4fc1-43fe-428d-80c6-0b441e1a5a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902893711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1902893711
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3852805467
Short name T480
Test name
Test status
Simulation time 16807829469 ps
CPU time 1031.34 seconds
Started Jun 09 01:44:18 PM PDT 24
Finished Jun 09 02:01:30 PM PDT 24
Peak memory 734980 kb
Host smart-c56019ec-72af-4927-b4b1-8f2f8d1db2a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3852805467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3852805467
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.2998648580
Short name T422
Test name
Test status
Simulation time 116585223 ps
CPU time 3.31 seconds
Started Jun 09 01:44:15 PM PDT 24
Finished Jun 09 01:44:18 PM PDT 24
Peak memory 200364 kb
Host smart-4532b18d-7541-4737-a45d-043284390351
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998648580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2998648580
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2254982370
Short name T506
Test name
Test status
Simulation time 18174021479 ps
CPU time 90.95 seconds
Started Jun 09 01:44:12 PM PDT 24
Finished Jun 09 01:45:43 PM PDT 24
Peak memory 200500 kb
Host smart-c4ce6a8d-4e24-4149-bafc-56afe61b3ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254982370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2254982370
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3446555844
Short name T423
Test name
Test status
Simulation time 330765414 ps
CPU time 4.77 seconds
Started Jun 09 01:44:11 PM PDT 24
Finished Jun 09 01:44:16 PM PDT 24
Peak memory 200408 kb
Host smart-c24d0e30-8837-4654-bcca-d4584b1f0297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446555844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3446555844
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3266741138
Short name T55
Test name
Test status
Simulation time 377830437960 ps
CPU time 3714.85 seconds
Started Jun 09 01:44:16 PM PDT 24
Finished Jun 09 02:46:12 PM PDT 24
Peak memory 804104 kb
Host smart-8d62ed3e-ffbe-4f6d-b87f-a26a159ea18f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266741138 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3266741138
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.4291198388
Short name T48
Test name
Test status
Simulation time 70945386 ps
CPU time 1.36 seconds
Started Jun 09 01:44:16 PM PDT 24
Finished Jun 09 01:44:17 PM PDT 24
Peak memory 200408 kb
Host smart-2f229a83-68af-443a-837e-25c12ff96424
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291198388 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.4291198388
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.1203093545
Short name T340
Test name
Test status
Simulation time 58368955257 ps
CPU time 456.29 seconds
Started Jun 09 01:44:17 PM PDT 24
Finished Jun 09 01:51:53 PM PDT 24
Peak memory 200456 kb
Host smart-30837044-36d3-4f65-8bcb-c79c74442f5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203093545 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.1203093545
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3350272181
Short name T122
Test name
Test status
Simulation time 12351549054 ps
CPU time 81.92 seconds
Started Jun 09 01:44:18 PM PDT 24
Finished Jun 09 01:45:40 PM PDT 24
Peak memory 200504 kb
Host smart-d8377967-875a-4d93-9197-97cf7d91e79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350272181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3350272181
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1967456045
Short name T367
Test name
Test status
Simulation time 11622804 ps
CPU time 0.58 seconds
Started Jun 09 01:44:21 PM PDT 24
Finished Jun 09 01:44:22 PM PDT 24
Peak memory 195356 kb
Host smart-d52e0faa-4f5a-4058-9b77-8d4e77b4f5b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967456045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1967456045
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.3938502424
Short name T363
Test name
Test status
Simulation time 505254014 ps
CPU time 12.68 seconds
Started Jun 09 01:44:18 PM PDT 24
Finished Jun 09 01:44:31 PM PDT 24
Peak memory 214628 kb
Host smart-648585db-5f45-4b75-bde4-87969587ebaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3938502424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.3938502424
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.2015554329
Short name T561
Test name
Test status
Simulation time 4421042443 ps
CPU time 41.68 seconds
Started Jun 09 01:44:18 PM PDT 24
Finished Jun 09 01:45:00 PM PDT 24
Peak memory 200504 kb
Host smart-4fc4e267-9e5b-4c85-abe8-09847d92331d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015554329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2015554329
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2311567566
Short name T471
Test name
Test status
Simulation time 3669449202 ps
CPU time 478.4 seconds
Started Jun 09 01:44:20 PM PDT 24
Finished Jun 09 01:52:19 PM PDT 24
Peak memory 696856 kb
Host smart-ceb39117-58d0-40b3-b40f-e7252d949689
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2311567566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2311567566
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.4292310098
Short name T243
Test name
Test status
Simulation time 18491989831 ps
CPU time 122.26 seconds
Started Jun 09 01:44:20 PM PDT 24
Finished Jun 09 01:46:23 PM PDT 24
Peak memory 200432 kb
Host smart-a1cf7284-ed46-4117-8913-655e9a14f649
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292310098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.4292310098
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1436843898
Short name T183
Test name
Test status
Simulation time 3402633644 ps
CPU time 93.98 seconds
Started Jun 09 01:44:18 PM PDT 24
Finished Jun 09 01:45:53 PM PDT 24
Peak memory 200536 kb
Host smart-efc9372a-b5aa-4241-8f97-9bf573a87897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436843898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1436843898
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2174132432
Short name T207
Test name
Test status
Simulation time 714392699 ps
CPU time 5.97 seconds
Started Jun 09 01:44:16 PM PDT 24
Finished Jun 09 01:44:22 PM PDT 24
Peak memory 200484 kb
Host smart-0ddd79f2-9f0b-42fa-8c87-01ff282f6756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174132432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2174132432
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.648471275
Short name T410
Test name
Test status
Simulation time 1923900039 ps
CPU time 80.59 seconds
Started Jun 09 01:44:23 PM PDT 24
Finished Jun 09 01:45:43 PM PDT 24
Peak memory 200480 kb
Host smart-8dd5fdae-e834-402f-9df1-ab9c5440c624
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648471275 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.648471275
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.1303039678
Short name T544
Test name
Test status
Simulation time 87923836 ps
CPU time 1.09 seconds
Started Jun 09 01:44:15 PM PDT 24
Finished Jun 09 01:44:16 PM PDT 24
Peak memory 200264 kb
Host smart-c3fa3cea-3bf6-4fa9-907a-2a297b4b7d76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303039678 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.1303039678
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.1773239962
Short name T62
Test name
Test status
Simulation time 45109430862 ps
CPU time 442.52 seconds
Started Jun 09 01:44:17 PM PDT 24
Finished Jun 09 01:51:39 PM PDT 24
Peak memory 200472 kb
Host smart-108a9d24-e57b-45d7-8797-d190186e422b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773239962 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.1773239962
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2364656673
Short name T334
Test name
Test status
Simulation time 2154354213 ps
CPU time 98.72 seconds
Started Jun 09 01:44:17 PM PDT 24
Finished Jun 09 01:45:56 PM PDT 24
Peak memory 200528 kb
Host smart-3632b6c3-f140-410c-87e4-894af522d24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364656673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2364656673
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/185.hmac_stress_all_with_rand_reset.796105494
Short name T12
Test name
Test status
Simulation time 7286329862 ps
CPU time 310.94 seconds
Started Jun 09 01:47:50 PM PDT 24
Finished Jun 09 01:53:02 PM PDT 24
Peak memory 375576 kb
Host smart-7bc93c26-83de-479d-bf2d-46eeb0b92718
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=796105494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.hmac_stress_all_with_rand_reset.796105494
Directory /workspace/185.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1879785220
Short name T545
Test name
Test status
Simulation time 43053850 ps
CPU time 0.6 seconds
Started Jun 09 01:44:22 PM PDT 24
Finished Jun 09 01:44:23 PM PDT 24
Peak memory 196116 kb
Host smart-1ac72c37-bfce-4909-90fa-dc7b89c90526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879785220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1879785220
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3559833488
Short name T191
Test name
Test status
Simulation time 2591869099 ps
CPU time 27.34 seconds
Started Jun 09 01:44:21 PM PDT 24
Finished Jun 09 01:44:48 PM PDT 24
Peak memory 200456 kb
Host smart-b3918b33-a64e-4ea4-8240-3a640aa2f56b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3559833488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3559833488
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1442945818
Short name T49
Test name
Test status
Simulation time 11779774618 ps
CPU time 48.07 seconds
Started Jun 09 01:44:21 PM PDT 24
Finished Jun 09 01:45:09 PM PDT 24
Peak memory 200480 kb
Host smart-d1150fbb-ca12-45ce-a6e8-782d1b839f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442945818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1442945818
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_error.3160285640
Short name T246
Test name
Test status
Simulation time 184820156753 ps
CPU time 210.84 seconds
Started Jun 09 01:44:23 PM PDT 24
Finished Jun 09 01:47:54 PM PDT 24
Peak memory 200500 kb
Host smart-3f11b580-54c3-4c19-a910-c8ddd6fe8ea4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160285640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3160285640
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1021982695
Short name T214
Test name
Test status
Simulation time 2975577758 ps
CPU time 24.64 seconds
Started Jun 09 01:44:20 PM PDT 24
Finished Jun 09 01:44:45 PM PDT 24
Peak memory 200556 kb
Host smart-169f4db9-e163-49a3-a826-4d0ad4146467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021982695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1021982695
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.4196553745
Short name T365
Test name
Test status
Simulation time 1228731612 ps
CPU time 8.03 seconds
Started Jun 09 01:44:21 PM PDT 24
Finished Jun 09 01:44:29 PM PDT 24
Peak memory 200444 kb
Host smart-b038d2ed-cdae-475c-8829-429248a1623d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196553745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.4196553745
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1062995445
Short name T474
Test name
Test status
Simulation time 90040314581 ps
CPU time 2505.64 seconds
Started Jun 09 01:44:19 PM PDT 24
Finished Jun 09 02:26:05 PM PDT 24
Peak memory 773868 kb
Host smart-1faddbe6-80d3-467f-a5b4-52a3d6b1bf3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062995445 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1062995445
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.3680792871
Short name T403
Test name
Test status
Simulation time 30099303 ps
CPU time 1.1 seconds
Started Jun 09 01:44:21 PM PDT 24
Finished Jun 09 01:44:22 PM PDT 24
Peak memory 200436 kb
Host smart-ecb9b623-3b68-486d-a054-88707b05f773
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680792871 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.3680792871
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.2580511656
Short name T498
Test name
Test status
Simulation time 169207196412 ps
CPU time 464.96 seconds
Started Jun 09 01:44:22 PM PDT 24
Finished Jun 09 01:52:07 PM PDT 24
Peak memory 200432 kb
Host smart-a35b98c0-04e9-4203-b259-b2958ec01c70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580511656 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.2580511656
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.4288867834
Short name T154
Test name
Test status
Simulation time 10657273330 ps
CPU time 48.57 seconds
Started Jun 09 01:44:22 PM PDT 24
Finished Jun 09 01:45:11 PM PDT 24
Peak memory 200436 kb
Host smart-2e2d58d7-91a2-4375-917e-781fd8176739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288867834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.4288867834
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.4128616212
Short name T174
Test name
Test status
Simulation time 13022211 ps
CPU time 0.6 seconds
Started Jun 09 01:43:49 PM PDT 24
Finished Jun 09 01:43:50 PM PDT 24
Peak memory 196412 kb
Host smart-f07cb894-b319-4ef1-b7ce-0212b06111fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128616212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.4128616212
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.956185774
Short name T344
Test name
Test status
Simulation time 315566594 ps
CPU time 15.27 seconds
Started Jun 09 01:43:41 PM PDT 24
Finished Jun 09 01:43:57 PM PDT 24
Peak memory 216440 kb
Host smart-6a39580e-7d97-4539-a37c-8906e955c06a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=956185774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.956185774
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.869748212
Short name T238
Test name
Test status
Simulation time 818634507 ps
CPU time 3.38 seconds
Started Jun 09 01:43:41 PM PDT 24
Finished Jun 09 01:43:45 PM PDT 24
Peak memory 200448 kb
Host smart-eeaffedb-58cc-4f04-ba4b-e2b5b16a427c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869748212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.869748212
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1794180183
Short name T194
Test name
Test status
Simulation time 3066478662 ps
CPU time 677.89 seconds
Started Jun 09 01:43:43 PM PDT 24
Finished Jun 09 01:55:01 PM PDT 24
Peak memory 659408 kb
Host smart-d4e54464-2aa0-44eb-84d9-7a0f8f6a0ad6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1794180183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1794180183
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2219293559
Short name T448
Test name
Test status
Simulation time 9985603292 ps
CPU time 84.24 seconds
Started Jun 09 01:43:40 PM PDT 24
Finished Jun 09 01:45:04 PM PDT 24
Peak memory 200520 kb
Host smart-502c553e-52dc-4095-b982-c510c712d8e3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219293559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2219293559
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.5716890
Short name T184
Test name
Test status
Simulation time 22791731890 ps
CPU time 116.53 seconds
Started Jun 09 01:43:40 PM PDT 24
Finished Jun 09 01:45:37 PM PDT 24
Peak memory 200504 kb
Host smart-c08d7c9f-bf98-4ee8-95c6-af2dbfdd6a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5716890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.5716890
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_smoke.1546551691
Short name T397
Test name
Test status
Simulation time 405871493 ps
CPU time 4.88 seconds
Started Jun 09 01:43:42 PM PDT 24
Finished Jun 09 01:43:47 PM PDT 24
Peak memory 200456 kb
Host smart-423b7236-9a57-4601-9c3b-6fbadc765b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546551691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1546551691
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2776457627
Short name T250
Test name
Test status
Simulation time 66060000401 ps
CPU time 1881.28 seconds
Started Jun 09 01:43:48 PM PDT 24
Finished Jun 09 02:15:10 PM PDT 24
Peak memory 700184 kb
Host smart-74f5b5ea-d1dd-4901-8d2e-6a3fc95b117f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776457627 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2776457627
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.3136528363
Short name T590
Test name
Test status
Simulation time 37765765 ps
CPU time 1.26 seconds
Started Jun 09 01:43:50 PM PDT 24
Finished Jun 09 01:43:52 PM PDT 24
Peak memory 200436 kb
Host smart-fce2d80d-9b74-4cb3-86b4-464d88783127
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136528363 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.3136528363
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.355503484
Short name T475
Test name
Test status
Simulation time 132231569681 ps
CPU time 489.96 seconds
Started Jun 09 01:43:41 PM PDT 24
Finished Jun 09 01:51:52 PM PDT 24
Peak memory 200432 kb
Host smart-25de4f26-c234-410c-960b-47718de7c650
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355503484 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.355503484
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2290684401
Short name T149
Test name
Test status
Simulation time 1465750249 ps
CPU time 7.21 seconds
Started Jun 09 01:43:38 PM PDT 24
Finished Jun 09 01:43:46 PM PDT 24
Peak memory 200492 kb
Host smart-0cb607bd-db6c-4141-a8dc-cfb1a425c0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290684401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2290684401
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1622188609
Short name T23
Test name
Test status
Simulation time 18310946 ps
CPU time 0.57 seconds
Started Jun 09 01:44:25 PM PDT 24
Finished Jun 09 01:44:26 PM PDT 24
Peak memory 196088 kb
Host smart-5d107baa-3a51-42e4-b659-1113863094bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622188609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1622188609
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1275743608
Short name T358
Test name
Test status
Simulation time 92243840 ps
CPU time 1.64 seconds
Started Jun 09 01:44:25 PM PDT 24
Finished Jun 09 01:44:27 PM PDT 24
Peak memory 200220 kb
Host smart-d446015e-61d1-4a0e-a3b4-4dd6fea132b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1275743608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1275743608
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.908429480
Short name T532
Test name
Test status
Simulation time 9988224376 ps
CPU time 34.96 seconds
Started Jun 09 01:44:28 PM PDT 24
Finished Jun 09 01:45:03 PM PDT 24
Peak memory 200440 kb
Host smart-4f9dcce7-636b-4fa3-96aa-5999eb7e3762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908429480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.908429480
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1993167873
Short name T233
Test name
Test status
Simulation time 7273386775 ps
CPU time 907.44 seconds
Started Jun 09 01:44:26 PM PDT 24
Finished Jun 09 01:59:34 PM PDT 24
Peak memory 730048 kb
Host smart-318160a1-2fc3-4d27-a811-87c22d867ba1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1993167873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1993167873
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.4264593196
Short name T141
Test name
Test status
Simulation time 9920279672 ps
CPU time 127.76 seconds
Started Jun 09 01:44:30 PM PDT 24
Finished Jun 09 01:46:38 PM PDT 24
Peak memory 200548 kb
Host smart-2f2a5ce9-1a22-4957-baeb-7dd515d7109b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264593196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.4264593196
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.353201001
Short name T566
Test name
Test status
Simulation time 16505507570 ps
CPU time 22.48 seconds
Started Jun 09 01:44:27 PM PDT 24
Finished Jun 09 01:44:49 PM PDT 24
Peak memory 200416 kb
Host smart-e9a7657c-efaf-4410-bea1-10ce5a300f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353201001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.353201001
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3447432426
Short name T213
Test name
Test status
Simulation time 21090489 ps
CPU time 0.78 seconds
Started Jun 09 01:44:22 PM PDT 24
Finished Jun 09 01:44:23 PM PDT 24
Peak memory 198428 kb
Host smart-155d645e-687b-4ee5-9731-0cb9bfabb23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447432426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3447432426
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2790896267
Short name T350
Test name
Test status
Simulation time 1578854608 ps
CPU time 22.9 seconds
Started Jun 09 01:44:27 PM PDT 24
Finished Jun 09 01:44:50 PM PDT 24
Peak memory 200488 kb
Host smart-81d13320-56fd-46d0-9aaf-97c007049aae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790896267 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2790896267
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.3352545814
Short name T485
Test name
Test status
Simulation time 129026451 ps
CPU time 1.29 seconds
Started Jun 09 01:44:26 PM PDT 24
Finished Jun 09 01:44:28 PM PDT 24
Peak memory 200468 kb
Host smart-a01fbb26-469d-4c7c-8bdc-c794ddf69973
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352545814 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.3352545814
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.3998399040
Short name T98
Test name
Test status
Simulation time 30815751577 ps
CPU time 434.02 seconds
Started Jun 09 01:44:27 PM PDT 24
Finished Jun 09 01:51:41 PM PDT 24
Peak memory 200620 kb
Host smart-29dc8fb0-de0b-4ff0-a1bf-d24f1c9fea99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998399040 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.3998399040
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1557715613
Short name T118
Test name
Test status
Simulation time 44505994618 ps
CPU time 114.1 seconds
Started Jun 09 01:44:27 PM PDT 24
Finished Jun 09 01:46:21 PM PDT 24
Peak memory 200556 kb
Host smart-bef4caac-2586-4e86-aed9-138856bc1ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557715613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1557715613
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1677003655
Short name T22
Test name
Test status
Simulation time 24487790 ps
CPU time 0.57 seconds
Started Jun 09 01:44:32 PM PDT 24
Finished Jun 09 01:44:33 PM PDT 24
Peak memory 195380 kb
Host smart-ae773dde-92a1-490a-84ac-3cb6c581db76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677003655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1677003655
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3747918749
Short name T568
Test name
Test status
Simulation time 2177819930 ps
CPU time 45.95 seconds
Started Jun 09 01:44:24 PM PDT 24
Finished Jun 09 01:45:11 PM PDT 24
Peak memory 242460 kb
Host smart-91b5754a-d7af-4cfa-bd69-a750ae89c278
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3747918749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3747918749
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1642954555
Short name T406
Test name
Test status
Simulation time 4299540687 ps
CPU time 45.52 seconds
Started Jun 09 01:44:26 PM PDT 24
Finished Jun 09 01:45:12 PM PDT 24
Peak memory 200572 kb
Host smart-8bd68298-8417-406c-8dff-3b3d2f976d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642954555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1642954555
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.706056011
Short name T427
Test name
Test status
Simulation time 3572775567 ps
CPU time 787.26 seconds
Started Jun 09 01:44:26 PM PDT 24
Finished Jun 09 01:57:34 PM PDT 24
Peak memory 716224 kb
Host smart-c1723bb2-7292-4166-81f1-1f7a297eb64e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=706056011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.706056011
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.955378261
Short name T523
Test name
Test status
Simulation time 652713493 ps
CPU time 9.88 seconds
Started Jun 09 01:44:30 PM PDT 24
Finished Jun 09 01:44:40 PM PDT 24
Peak memory 200236 kb
Host smart-cbdc2e93-72ab-42dd-9b4c-ad0e0adf88cb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955378261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.955378261
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2661380638
Short name T279
Test name
Test status
Simulation time 13458934829 ps
CPU time 45.4 seconds
Started Jun 09 01:44:28 PM PDT 24
Finished Jun 09 01:45:13 PM PDT 24
Peak memory 200492 kb
Host smart-b3784d9e-5b25-44d8-b6eb-07f638c1393c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661380638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2661380638
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2296163604
Short name T114
Test name
Test status
Simulation time 448301852 ps
CPU time 5.21 seconds
Started Jun 09 01:44:27 PM PDT 24
Finished Jun 09 01:44:32 PM PDT 24
Peak memory 200456 kb
Host smart-63d2005c-7a8a-4377-ba1f-5911600782e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296163604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2296163604
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1152300294
Short name T58
Test name
Test status
Simulation time 77548645280 ps
CPU time 1515.76 seconds
Started Jun 09 01:44:30 PM PDT 24
Finished Jun 09 02:09:46 PM PDT 24
Peak memory 714532 kb
Host smart-23230b20-e282-418b-a09c-9ce151d3ec2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152300294 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1152300294
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.3601719891
Short name T136
Test name
Test status
Simulation time 28360728 ps
CPU time 1.03 seconds
Started Jun 09 01:44:29 PM PDT 24
Finished Jun 09 01:44:30 PM PDT 24
Peak memory 200240 kb
Host smart-dce415bf-ea12-4310-92ff-1d98739b1356
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601719891 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.3601719891
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.3217826357
Short name T234
Test name
Test status
Simulation time 26676720111 ps
CPU time 487.91 seconds
Started Jun 09 01:44:27 PM PDT 24
Finished Jun 09 01:52:35 PM PDT 24
Peak memory 200484 kb
Host smart-068e07d3-9b8d-4621-9497-e4a193967f5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217826357 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.3217826357
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1583372598
Short name T443
Test name
Test status
Simulation time 1710409787 ps
CPU time 24.63 seconds
Started Jun 09 01:44:29 PM PDT 24
Finished Jun 09 01:44:54 PM PDT 24
Peak memory 200492 kb
Host smart-30176429-6e54-453e-87fc-740b93e8bae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583372598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1583372598
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3832554321
Short name T549
Test name
Test status
Simulation time 48257361 ps
CPU time 0.64 seconds
Started Jun 09 01:44:33 PM PDT 24
Finished Jun 09 01:44:34 PM PDT 24
Peak memory 196444 kb
Host smart-8c36bbfe-f932-48d2-b0a4-4f2034527efa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832554321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3832554321
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.1617823287
Short name T256
Test name
Test status
Simulation time 9690082581 ps
CPU time 63.8 seconds
Started Jun 09 01:44:30 PM PDT 24
Finished Jun 09 01:45:34 PM PDT 24
Peak memory 233272 kb
Host smart-054e0593-76b7-4031-a848-d1b89c7ccd0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1617823287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1617823287
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1677230316
Short name T274
Test name
Test status
Simulation time 852172578 ps
CPU time 45.93 seconds
Started Jun 09 01:44:32 PM PDT 24
Finished Jun 09 01:45:18 PM PDT 24
Peak memory 200480 kb
Host smart-5d97b20f-4efb-4d03-8ebf-ed162719fcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677230316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1677230316
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2532585113
Short name T345
Test name
Test status
Simulation time 12013725470 ps
CPU time 477.12 seconds
Started Jun 09 01:44:32 PM PDT 24
Finished Jun 09 01:52:30 PM PDT 24
Peak memory 652084 kb
Host smart-ef2c4afb-52e6-4070-a0b4-c0ec9f912576
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2532585113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2532585113
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.3761455520
Short name T18
Test name
Test status
Simulation time 26483184811 ps
CPU time 116.55 seconds
Started Jun 09 01:44:32 PM PDT 24
Finished Jun 09 01:46:29 PM PDT 24
Peak memory 200512 kb
Host smart-fa3b08a7-6ac9-4a82-b720-bcaa02ba2b8f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761455520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3761455520
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.378177556
Short name T127
Test name
Test status
Simulation time 14207202230 ps
CPU time 145.92 seconds
Started Jun 09 01:44:31 PM PDT 24
Finished Jun 09 01:46:58 PM PDT 24
Peak memory 200556 kb
Host smart-1f37b2aa-21b6-4c9a-b8ec-795e18ca2945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378177556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.378177556
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3751898443
Short name T291
Test name
Test status
Simulation time 830452183 ps
CPU time 7.32 seconds
Started Jun 09 01:44:30 PM PDT 24
Finished Jun 09 01:44:38 PM PDT 24
Peak memory 200464 kb
Host smart-96622cca-3447-4804-988a-cc40fd8c15e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751898443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3751898443
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2387549450
Short name T56
Test name
Test status
Simulation time 157184191015 ps
CPU time 4168.11 seconds
Started Jun 09 01:44:32 PM PDT 24
Finished Jun 09 02:54:00 PM PDT 24
Peak memory 876808 kb
Host smart-fd2279e3-8f9b-417a-8324-1d1c95c4f256
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387549450 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2387549450
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.1580618887
Short name T228
Test name
Test status
Simulation time 175704789 ps
CPU time 1.27 seconds
Started Jun 09 01:44:32 PM PDT 24
Finished Jun 09 01:44:33 PM PDT 24
Peak memory 200396 kb
Host smart-8646fb38-3c98-4cc4-95d6-7b968b77813b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580618887 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.1580618887
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.2080442496
Short name T99
Test name
Test status
Simulation time 26245769501 ps
CPU time 496.91 seconds
Started Jun 09 01:44:31 PM PDT 24
Finished Jun 09 01:52:49 PM PDT 24
Peak memory 200436 kb
Host smart-63e6c120-73e9-4bb3-9582-4a9af2f687dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080442496 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.2080442496
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.4014932751
Short name T384
Test name
Test status
Simulation time 749815748 ps
CPU time 11.06 seconds
Started Jun 09 01:44:32 PM PDT 24
Finished Jun 09 01:44:43 PM PDT 24
Peak memory 200376 kb
Host smart-bc58c62c-e3bf-41bb-a436-4ed3bd32995c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014932751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.4014932751
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3593457978
Short name T21
Test name
Test status
Simulation time 21177411 ps
CPU time 0.61 seconds
Started Jun 09 01:44:38 PM PDT 24
Finished Jun 09 01:44:39 PM PDT 24
Peak memory 195412 kb
Host smart-c6486100-ce5a-41cd-b17d-53a9fcf4a295
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593457978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3593457978
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1523195625
Short name T430
Test name
Test status
Simulation time 1548759746 ps
CPU time 36.51 seconds
Started Jun 09 01:44:33 PM PDT 24
Finished Jun 09 01:45:10 PM PDT 24
Peak memory 228984 kb
Host smart-d71ccbd6-f193-4eac-81b8-064c4c47cf6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1523195625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1523195625
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.149787420
Short name T312
Test name
Test status
Simulation time 9427389855 ps
CPU time 51.24 seconds
Started Jun 09 01:44:31 PM PDT 24
Finished Jun 09 01:45:23 PM PDT 24
Peak memory 200532 kb
Host smart-7d4904f6-cffb-4780-956a-2652a069cbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149787420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.149787420
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.3636175761
Short name T446
Test name
Test status
Simulation time 3011410540 ps
CPU time 710.19 seconds
Started Jun 09 01:44:31 PM PDT 24
Finished Jun 09 01:56:22 PM PDT 24
Peak memory 695560 kb
Host smart-52360422-f9cc-4fe2-bfc1-73f62f02990a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3636175761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.3636175761
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.418876411
Short name T269
Test name
Test status
Simulation time 12099089999 ps
CPU time 40.14 seconds
Started Jun 09 01:44:35 PM PDT 24
Finished Jun 09 01:45:15 PM PDT 24
Peak memory 200484 kb
Host smart-b015c916-ea68-45ce-ad31-4b5290b4a62b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418876411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.418876411
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.4062636751
Short name T378
Test name
Test status
Simulation time 4968733746 ps
CPU time 97.52 seconds
Started Jun 09 01:44:32 PM PDT 24
Finished Jun 09 01:46:10 PM PDT 24
Peak memory 200496 kb
Host smart-eaf16d0f-7a4d-4239-8c9a-4aba9ae299cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062636751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.4062636751
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1188528618
Short name T317
Test name
Test status
Simulation time 1334968261 ps
CPU time 11 seconds
Started Jun 09 01:44:32 PM PDT 24
Finished Jun 09 01:44:44 PM PDT 24
Peak memory 200508 kb
Host smart-b0846c04-c009-497f-bc04-a021351b4e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188528618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1188528618
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.544944403
Short name T330
Test name
Test status
Simulation time 395990496494 ps
CPU time 2584.67 seconds
Started Jun 09 01:44:34 PM PDT 24
Finished Jun 09 02:27:39 PM PDT 24
Peak memory 720628 kb
Host smart-319517be-997d-40c0-8bf5-669e9f964415
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544944403 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.544944403
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.1569943230
Short name T235
Test name
Test status
Simulation time 111659907 ps
CPU time 1.12 seconds
Started Jun 09 01:44:38 PM PDT 24
Finished Jun 09 01:44:39 PM PDT 24
Peak memory 200492 kb
Host smart-651ad378-ff6b-421b-802d-906fd6b1632f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569943230 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.1569943230
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.4048327493
Short name T158
Test name
Test status
Simulation time 8003784096 ps
CPU time 424.36 seconds
Started Jun 09 01:44:38 PM PDT 24
Finished Jun 09 01:51:42 PM PDT 24
Peak memory 200480 kb
Host smart-5d429d55-5af5-42fa-aa64-817f702e9a3a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048327493 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.4048327493
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3686730642
Short name T496
Test name
Test status
Simulation time 1332130493 ps
CPU time 54.68 seconds
Started Jun 09 01:44:36 PM PDT 24
Finished Jun 09 01:45:31 PM PDT 24
Peak memory 200428 kb
Host smart-6ee518b0-1d7b-4ff5-9d1a-af55dc3cd0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686730642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3686730642
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2803400066
Short name T479
Test name
Test status
Simulation time 12208825 ps
CPU time 0.59 seconds
Started Jun 09 01:44:40 PM PDT 24
Finished Jun 09 01:44:41 PM PDT 24
Peak memory 196416 kb
Host smart-be1c8e86-87b1-4b0a-8dcd-bb498cd537a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803400066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2803400066
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3695332648
Short name T10
Test name
Test status
Simulation time 1094109765 ps
CPU time 6.11 seconds
Started Jun 09 01:44:36 PM PDT 24
Finished Jun 09 01:44:42 PM PDT 24
Peak memory 202444 kb
Host smart-76e5e20f-3f2d-42a3-aaa6-08f58b8916dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3695332648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3695332648
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2449957669
Short name T275
Test name
Test status
Simulation time 9300594377 ps
CPU time 66.44 seconds
Started Jun 09 01:44:39 PM PDT 24
Finished Jun 09 01:45:45 PM PDT 24
Peak memory 200448 kb
Host smart-844fc612-d168-4f0a-8d75-d3caff763f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449957669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2449957669
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.792372824
Short name T529
Test name
Test status
Simulation time 2850493088 ps
CPU time 721.77 seconds
Started Jun 09 01:44:35 PM PDT 24
Finished Jun 09 01:56:37 PM PDT 24
Peak memory 695584 kb
Host smart-0856c0af-27c1-4497-a786-dc4c03f6750f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=792372824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.792372824
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2867408457
Short name T315
Test name
Test status
Simulation time 10044414554 ps
CPU time 63.14 seconds
Started Jun 09 01:44:41 PM PDT 24
Finished Jun 09 01:45:44 PM PDT 24
Peak memory 200496 kb
Host smart-491b07c1-135b-4535-9909-b1e43e18e7dc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867408457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2867408457
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2809709963
Short name T67
Test name
Test status
Simulation time 18155888445 ps
CPU time 61.46 seconds
Started Jun 09 01:44:39 PM PDT 24
Finished Jun 09 01:45:40 PM PDT 24
Peak memory 200572 kb
Host smart-007f9f5e-e3d4-4828-9077-5ee5c53a0eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809709963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2809709963
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1458219560
Short name T121
Test name
Test status
Simulation time 127652673 ps
CPU time 4.79 seconds
Started Jun 09 01:44:36 PM PDT 24
Finished Jun 09 01:44:41 PM PDT 24
Peak memory 200508 kb
Host smart-8cd5dbdc-0ab9-49cc-9428-851d1622fb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458219560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1458219560
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3691962474
Short name T170
Test name
Test status
Simulation time 79882336756 ps
CPU time 499.42 seconds
Started Jun 09 01:44:41 PM PDT 24
Finished Jun 09 01:53:01 PM PDT 24
Peak memory 627248 kb
Host smart-0c3ac931-2fca-46ec-8945-bd62f98f13e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691962474 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3691962474
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.2424076885
Short name T251
Test name
Test status
Simulation time 62879922 ps
CPU time 1.44 seconds
Started Jun 09 01:44:39 PM PDT 24
Finished Jun 09 01:44:41 PM PDT 24
Peak memory 200408 kb
Host smart-5f8dc9dc-68b9-4bfe-9af6-ce8188796698
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424076885 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.2424076885
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.1957338242
Short name T208
Test name
Test status
Simulation time 81214326510 ps
CPU time 550.4 seconds
Started Jun 09 01:44:40 PM PDT 24
Finished Jun 09 01:53:51 PM PDT 24
Peak memory 200412 kb
Host smart-c8bde4d8-9def-437b-91ab-d919aef2e0f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957338242 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.1957338242
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.698430249
Short name T28
Test name
Test status
Simulation time 2270093657 ps
CPU time 31.49 seconds
Started Jun 09 01:44:36 PM PDT 24
Finished Jun 09 01:45:07 PM PDT 24
Peak memory 200552 kb
Host smart-96c894ac-5a0e-4240-aa67-824515a39c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698430249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.698430249
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3257347024
Short name T66
Test name
Test status
Simulation time 15175137 ps
CPU time 0.6 seconds
Started Jun 09 01:44:42 PM PDT 24
Finished Jun 09 01:44:43 PM PDT 24
Peak memory 196400 kb
Host smart-d6af370c-80ef-4d41-8653-be88a8a00a81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257347024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3257347024
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1386430755
Short name T492
Test name
Test status
Simulation time 2584511928 ps
CPU time 32.13 seconds
Started Jun 09 01:44:43 PM PDT 24
Finished Jun 09 01:45:15 PM PDT 24
Peak memory 225100 kb
Host smart-9af7b872-89cc-4d9c-84d5-4e5c591d9624
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1386430755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1386430755
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.504723077
Short name T231
Test name
Test status
Simulation time 2744356280 ps
CPU time 41.43 seconds
Started Jun 09 01:44:43 PM PDT 24
Finished Jun 09 01:45:24 PM PDT 24
Peak memory 200512 kb
Host smart-d10c9e5c-de5d-40ee-8589-05f03b282609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504723077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.504723077
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3835307637
Short name T280
Test name
Test status
Simulation time 9725190659 ps
CPU time 638.11 seconds
Started Jun 09 01:44:42 PM PDT 24
Finished Jun 09 01:55:20 PM PDT 24
Peak memory 660244 kb
Host smart-844a05a1-e861-42c9-86bd-0e47aa8d64cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3835307637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3835307637
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3014304963
Short name T393
Test name
Test status
Simulation time 816657916 ps
CPU time 11.57 seconds
Started Jun 09 01:44:43 PM PDT 24
Finished Jun 09 01:44:55 PM PDT 24
Peak memory 200412 kb
Host smart-b41c3679-f1d9-4635-ae5f-0a6345516747
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014304963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3014304963
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1108702776
Short name T101
Test name
Test status
Simulation time 468536806 ps
CPU time 7.04 seconds
Started Jun 09 01:44:44 PM PDT 24
Finished Jun 09 01:44:51 PM PDT 24
Peak memory 200464 kb
Host smart-d6631583-0183-4762-b0a6-2702d2423a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108702776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1108702776
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1904671889
Short name T65
Test name
Test status
Simulation time 333652550 ps
CPU time 2.01 seconds
Started Jun 09 01:44:41 PM PDT 24
Finished Jun 09 01:44:43 PM PDT 24
Peak memory 200444 kb
Host smart-a9c902f2-a826-4854-8de3-8db0a0d29aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904671889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1904671889
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.293909300
Short name T93
Test name
Test status
Simulation time 44832374082 ps
CPU time 2068.48 seconds
Started Jun 09 01:44:44 PM PDT 24
Finished Jun 09 02:19:12 PM PDT 24
Peak memory 728144 kb
Host smart-0edd5651-08f4-4cc0-90f0-fa8b1adaf764
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293909300 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.293909300
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.327738898
Short name T202
Test name
Test status
Simulation time 87020464 ps
CPU time 1.1 seconds
Started Jun 09 01:44:39 PM PDT 24
Finished Jun 09 01:44:41 PM PDT 24
Peak memory 200152 kb
Host smart-79f7c4c0-a829-42df-8998-cb8011e251c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327738898 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.hmac_test_hmac_vectors.327738898
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.2780797959
Short name T420
Test name
Test status
Simulation time 84698987835 ps
CPU time 576.25 seconds
Started Jun 09 01:44:39 PM PDT 24
Finished Jun 09 01:54:15 PM PDT 24
Peak memory 200412 kb
Host smart-5eaf2164-6e57-418c-9479-0df556ceda35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780797959 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.2780797959
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3600308748
Short name T459
Test name
Test status
Simulation time 14901260580 ps
CPU time 14.22 seconds
Started Jun 09 01:44:43 PM PDT 24
Finished Jun 09 01:44:57 PM PDT 24
Peak memory 200508 kb
Host smart-81076cb9-d111-40cd-b4b0-62430d284690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600308748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3600308748
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.907335092
Short name T557
Test name
Test status
Simulation time 86392767 ps
CPU time 0.58 seconds
Started Jun 09 01:44:46 PM PDT 24
Finished Jun 09 01:44:47 PM PDT 24
Peak memory 196392 kb
Host smart-7fb5f533-40d7-44c3-8975-3faf8a92d367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907335092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.907335092
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2776928494
Short name T113
Test name
Test status
Simulation time 34915408 ps
CPU time 2.31 seconds
Started Jun 09 01:44:41 PM PDT 24
Finished Jun 09 01:44:43 PM PDT 24
Peak memory 216376 kb
Host smart-f9e60556-0b41-42bf-b72e-108663d31f5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2776928494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2776928494
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.3435382015
Short name T328
Test name
Test status
Simulation time 967411632 ps
CPU time 50.46 seconds
Started Jun 09 01:44:46 PM PDT 24
Finished Jun 09 01:45:37 PM PDT 24
Peak memory 200444 kb
Host smart-de05735d-566b-4b3a-9aae-c10cf149f640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435382015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3435382015
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.532783050
Short name T439
Test name
Test status
Simulation time 3713946484 ps
CPU time 188.49 seconds
Started Jun 09 01:44:40 PM PDT 24
Finished Jun 09 01:47:49 PM PDT 24
Peak memory 608824 kb
Host smart-af8a6d49-9b84-49d7-9909-89e17d4014c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=532783050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.532783050
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3920317063
Short name T226
Test name
Test status
Simulation time 3195328330 ps
CPU time 41.62 seconds
Started Jun 09 01:44:46 PM PDT 24
Finished Jun 09 01:45:28 PM PDT 24
Peak memory 200500 kb
Host smart-9885743c-7df2-4cf0-b8f4-3af593bb966c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920317063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3920317063
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3777004871
Short name T336
Test name
Test status
Simulation time 4979272003 ps
CPU time 51.02 seconds
Started Jun 09 01:44:41 PM PDT 24
Finished Jun 09 01:45:32 PM PDT 24
Peak memory 200488 kb
Host smart-e76a60f4-cc0a-4c04-90af-2dd187a79903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777004871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3777004871
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.4247978001
Short name T47
Test name
Test status
Simulation time 334582213 ps
CPU time 5.37 seconds
Started Jun 09 01:44:41 PM PDT 24
Finished Jun 09 01:44:47 PM PDT 24
Peak memory 200416 kb
Host smart-8b0e3a47-f318-4976-abe0-ffedb9f57dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247978001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.4247978001
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.1277064051
Short name T51
Test name
Test status
Simulation time 53776663813 ps
CPU time 485.13 seconds
Started Jun 09 01:44:46 PM PDT 24
Finished Jun 09 01:52:51 PM PDT 24
Peak memory 200480 kb
Host smart-6809e620-45c1-48c8-86c3-9e3afdc53e0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277064051 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1277064051
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.2423736142
Short name T255
Test name
Test status
Simulation time 162211642 ps
CPU time 1.3 seconds
Started Jun 09 01:44:47 PM PDT 24
Finished Jun 09 01:44:48 PM PDT 24
Peak memory 200456 kb
Host smart-87175c8c-d464-4d51-bfce-cac55f175d8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423736142 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.2423736142
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.1429849392
Short name T361
Test name
Test status
Simulation time 8832376856 ps
CPU time 459.76 seconds
Started Jun 09 01:44:46 PM PDT 24
Finished Jun 09 01:52:26 PM PDT 24
Peak memory 200436 kb
Host smart-c9bf9c7a-c70f-436a-9ad4-5e7179a0c893
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429849392 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.1429849392
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1037644303
Short name T594
Test name
Test status
Simulation time 5678625176 ps
CPU time 24.28 seconds
Started Jun 09 01:44:47 PM PDT 24
Finished Jun 09 01:45:11 PM PDT 24
Peak memory 200496 kb
Host smart-1e6aa110-9635-4ab8-a07b-d40a3f16f77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037644303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1037644303
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2842680855
Short name T115
Test name
Test status
Simulation time 20317479 ps
CPU time 0.58 seconds
Started Jun 09 01:44:49 PM PDT 24
Finished Jun 09 01:44:50 PM PDT 24
Peak memory 195396 kb
Host smart-55365164-4204-4a88-9347-6a651312238c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842680855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2842680855
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1404220852
Short name T192
Test name
Test status
Simulation time 4497312039 ps
CPU time 59.99 seconds
Started Jun 09 01:44:46 PM PDT 24
Finished Jun 09 01:45:47 PM PDT 24
Peak memory 233364 kb
Host smart-51eba4f8-fa0c-4201-8136-228b008d202e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1404220852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1404220852
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.815131425
Short name T370
Test name
Test status
Simulation time 2996111480 ps
CPU time 36.45 seconds
Started Jun 09 01:44:51 PM PDT 24
Finished Jun 09 01:45:28 PM PDT 24
Peak memory 200476 kb
Host smart-efa924c8-674c-49a1-8596-0deebb4c77f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815131425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.815131425
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1481914605
Short name T432
Test name
Test status
Simulation time 6763654667 ps
CPU time 885.51 seconds
Started Jun 09 01:44:50 PM PDT 24
Finished Jun 09 01:59:35 PM PDT 24
Peak memory 762828 kb
Host smart-fc472828-f2f9-43d9-944e-29561fd71ac8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1481914605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1481914605
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.205212879
Short name T463
Test name
Test status
Simulation time 6109540197 ps
CPU time 83.11 seconds
Started Jun 09 01:44:51 PM PDT 24
Finished Jun 09 01:46:14 PM PDT 24
Peak memory 200456 kb
Host smart-3f85c3cd-a64f-4e88-8e18-17653e31e384
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205212879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.205212879
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3473969441
Short name T288
Test name
Test status
Simulation time 6379882548 ps
CPU time 74.18 seconds
Started Jun 09 01:44:51 PM PDT 24
Finished Jun 09 01:46:06 PM PDT 24
Peak memory 200540 kb
Host smart-a0d44d7a-3436-4891-ba5c-65af515263ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473969441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3473969441
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1312814969
Short name T241
Test name
Test status
Simulation time 48042377 ps
CPU time 1.51 seconds
Started Jun 09 01:44:46 PM PDT 24
Finished Jun 09 01:44:47 PM PDT 24
Peak memory 200188 kb
Host smart-5f4bd119-9ace-45fe-800d-28622e78969c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312814969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1312814969
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.1942463770
Short name T503
Test name
Test status
Simulation time 48877605532 ps
CPU time 1842.11 seconds
Started Jun 09 01:44:51 PM PDT 24
Finished Jun 09 02:15:33 PM PDT 24
Peak memory 632292 kb
Host smart-71a84198-991c-4bcb-babf-68303edc557f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942463770 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1942463770
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.3200343747
Short name T287
Test name
Test status
Simulation time 64648666 ps
CPU time 1.37 seconds
Started Jun 09 01:44:51 PM PDT 24
Finished Jun 09 01:44:52 PM PDT 24
Peak memory 200448 kb
Host smart-a1b64d57-4252-4d4a-a53c-0d9914e9cac5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200343747 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.3200343747
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.177190580
Short name T206
Test name
Test status
Simulation time 106707966300 ps
CPU time 498 seconds
Started Jun 09 01:44:50 PM PDT 24
Finished Jun 09 01:53:08 PM PDT 24
Peak memory 200436 kb
Host smart-f525afcd-cd19-41b2-8e6b-a00629c8fb49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177190580 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.177190580
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3919428305
Short name T167
Test name
Test status
Simulation time 7916943605 ps
CPU time 93.48 seconds
Started Jun 09 01:44:52 PM PDT 24
Finished Jun 09 01:46:25 PM PDT 24
Peak memory 200504 kb
Host smart-28eaca3d-a765-4875-9158-b86792602cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919428305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3919428305
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.864331836
Short name T586
Test name
Test status
Simulation time 20139687 ps
CPU time 0.56 seconds
Started Jun 09 01:44:56 PM PDT 24
Finished Jun 09 01:44:57 PM PDT 24
Peak memory 196444 kb
Host smart-4948d303-ef7e-48a7-bb1e-3bf63886c1ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864331836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.864331836
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.209707713
Short name T573
Test name
Test status
Simulation time 294753827 ps
CPU time 17 seconds
Started Jun 09 01:44:50 PM PDT 24
Finished Jun 09 01:45:07 PM PDT 24
Peak memory 216984 kb
Host smart-50c14b73-fa50-460f-86ce-c971aeb33723
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=209707713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.209707713
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.4171321474
Short name T313
Test name
Test status
Simulation time 156866636 ps
CPU time 8.4 seconds
Started Jun 09 01:44:52 PM PDT 24
Finished Jun 09 01:45:00 PM PDT 24
Peak memory 200360 kb
Host smart-809b7ee5-7907-43cd-8a6f-c2794637dd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171321474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.4171321474
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2077495461
Short name T5
Test name
Test status
Simulation time 2479989692 ps
CPU time 160.32 seconds
Started Jun 09 01:44:51 PM PDT 24
Finished Jun 09 01:47:32 PM PDT 24
Peak memory 445112 kb
Host smart-a4996c54-5c1b-4857-9bac-63a99f2b70ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2077495461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2077495461
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.2248237853
Short name T457
Test name
Test status
Simulation time 18539800532 ps
CPU time 20.44 seconds
Started Jun 09 01:44:49 PM PDT 24
Finished Jun 09 01:45:10 PM PDT 24
Peak memory 200496 kb
Host smart-1815dc57-9cd8-4fec-87b5-7fc969c9e9c5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248237853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2248237853
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.4120535466
Short name T412
Test name
Test status
Simulation time 12267067347 ps
CPU time 74.7 seconds
Started Jun 09 01:44:51 PM PDT 24
Finished Jun 09 01:46:06 PM PDT 24
Peak memory 200452 kb
Host smart-f1ff5965-d6f7-4a2e-8fb6-e0b557e47e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120535466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.4120535466
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1422106904
Short name T89
Test name
Test status
Simulation time 27156751 ps
CPU time 0.73 seconds
Started Jun 09 01:44:52 PM PDT 24
Finished Jun 09 01:44:53 PM PDT 24
Peak memory 198408 kb
Host smart-9de4891a-0005-43f3-a969-b981e570662d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422106904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1422106904
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2909527849
Short name T577
Test name
Test status
Simulation time 27916490981 ps
CPU time 111.73 seconds
Started Jun 09 01:44:55 PM PDT 24
Finished Jun 09 01:46:47 PM PDT 24
Peak memory 216224 kb
Host smart-625c730a-094c-41d9-a27b-1ede99b1fc05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909527849 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2909527849
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.2557527959
Short name T321
Test name
Test status
Simulation time 186180607 ps
CPU time 1.12 seconds
Started Jun 09 01:44:57 PM PDT 24
Finished Jun 09 01:44:58 PM PDT 24
Peak memory 200256 kb
Host smart-ec964933-b9e9-420d-b8a0-d12f654602d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557527959 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.2557527959
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.1173826927
Short name T221
Test name
Test status
Simulation time 26378441649 ps
CPU time 479.41 seconds
Started Jun 09 01:44:57 PM PDT 24
Finished Jun 09 01:52:57 PM PDT 24
Peak memory 200484 kb
Host smart-b970a62b-88ae-433b-8184-a58cfef4fd44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173826927 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.1173826927
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2331863555
Short name T216
Test name
Test status
Simulation time 4279978623 ps
CPU time 40.89 seconds
Started Jun 09 01:44:52 PM PDT 24
Finished Jun 09 01:45:33 PM PDT 24
Peak memory 200480 kb
Host smart-bd8d3c7a-6cba-4ff2-ba3b-46e379b3ac61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331863555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2331863555
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.777637805
Short name T157
Test name
Test status
Simulation time 11689834 ps
CPU time 0.6 seconds
Started Jun 09 01:45:01 PM PDT 24
Finished Jun 09 01:45:02 PM PDT 24
Peak memory 195396 kb
Host smart-dee235ee-5506-4f06-b8ed-1584acc0d713
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777637805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.777637805
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2706168170
Short name T284
Test name
Test status
Simulation time 1495249532 ps
CPU time 21.01 seconds
Started Jun 09 01:44:57 PM PDT 24
Finished Jun 09 01:45:18 PM PDT 24
Peak memory 216712 kb
Host smart-d9160392-2e24-4ea9-86a9-3456bbd9e0c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2706168170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2706168170
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2901240979
Short name T539
Test name
Test status
Simulation time 17168142774 ps
CPU time 57.11 seconds
Started Jun 09 01:44:56 PM PDT 24
Finished Jun 09 01:45:54 PM PDT 24
Peak memory 200528 kb
Host smart-0857cb59-16c2-4ea0-bbf7-c854e0055674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901240979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2901240979
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.2767018561
Short name T592
Test name
Test status
Simulation time 1163480222 ps
CPU time 39.17 seconds
Started Jun 09 01:44:56 PM PDT 24
Finished Jun 09 01:45:36 PM PDT 24
Peak memory 328768 kb
Host smart-b8abc685-4b8f-417d-9cdd-315700ed95b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2767018561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2767018561
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1590613959
Short name T4
Test name
Test status
Simulation time 11538123335 ps
CPU time 169.85 seconds
Started Jun 09 01:44:57 PM PDT 24
Finished Jun 09 01:47:47 PM PDT 24
Peak memory 200516 kb
Host smart-5142fda7-dbd6-4b4f-b6fd-503fd79d31cd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590613959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1590613959
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3124988636
Short name T455
Test name
Test status
Simulation time 9715867961 ps
CPU time 55.11 seconds
Started Jun 09 01:44:58 PM PDT 24
Finished Jun 09 01:45:53 PM PDT 24
Peak memory 200464 kb
Host smart-61b29ea7-de40-4fb0-b3ae-bb14e5feec7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124988636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3124988636
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.4020019111
Short name T225
Test name
Test status
Simulation time 519097998 ps
CPU time 4.91 seconds
Started Jun 09 01:44:56 PM PDT 24
Finished Jun 09 01:45:02 PM PDT 24
Peak memory 200408 kb
Host smart-da2a96a3-cb29-4c92-97ae-9216172541c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020019111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.4020019111
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.1783509247
Short name T541
Test name
Test status
Simulation time 36739713447 ps
CPU time 327.43 seconds
Started Jun 09 01:45:01 PM PDT 24
Finished Jun 09 01:50:29 PM PDT 24
Peak memory 200496 kb
Host smart-596f04df-476d-4938-8977-3b6e5a91a844
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783509247 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1783509247
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.4199938089
Short name T489
Test name
Test status
Simulation time 138559889 ps
CPU time 1.33 seconds
Started Jun 09 01:45:01 PM PDT 24
Finished Jun 09 01:45:02 PM PDT 24
Peak memory 200496 kb
Host smart-46877197-8bb6-4856-ab73-5a22c47bbb32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199938089 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.4199938089
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.386131978
Short name T519
Test name
Test status
Simulation time 158295051437 ps
CPU time 519.51 seconds
Started Jun 09 01:44:56 PM PDT 24
Finished Jun 09 01:53:36 PM PDT 24
Peak memory 200504 kb
Host smart-13c83e09-36c3-4611-abd4-946c4e73eb50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386131978 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.386131978
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1989170985
Short name T128
Test name
Test status
Simulation time 6428161138 ps
CPU time 88.95 seconds
Started Jun 09 01:44:56 PM PDT 24
Finished Jun 09 01:46:25 PM PDT 24
Peak memory 200484 kb
Host smart-64a1ebdc-81f4-40d4-bcf5-fe13e62e7fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989170985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1989170985
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.4038354253
Short name T351
Test name
Test status
Simulation time 39822221 ps
CPU time 0.64 seconds
Started Jun 09 01:43:46 PM PDT 24
Finished Jun 09 01:43:47 PM PDT 24
Peak memory 197148 kb
Host smart-a3ec060b-a67d-4161-b1c7-cc1e196a9406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038354253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.4038354253
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.4037895365
Short name T34
Test name
Test status
Simulation time 4503088803 ps
CPU time 27.9 seconds
Started Jun 09 01:43:47 PM PDT 24
Finished Jun 09 01:44:16 PM PDT 24
Peak memory 224668 kb
Host smart-e70bf1e9-3670-4c84-9591-2ead0a2b9bd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4037895365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.4037895365
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1536466960
Short name T306
Test name
Test status
Simulation time 992866780 ps
CPU time 4.43 seconds
Started Jun 09 01:43:48 PM PDT 24
Finished Jun 09 01:43:53 PM PDT 24
Peak memory 200404 kb
Host smart-8b866758-b912-4355-937f-ba2d8d7483e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536466960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1536466960
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2398285918
Short name T442
Test name
Test status
Simulation time 10086367003 ps
CPU time 718.55 seconds
Started Jun 09 01:43:47 PM PDT 24
Finished Jun 09 01:55:47 PM PDT 24
Peak memory 669312 kb
Host smart-35f25496-f3e0-49d1-9e73-686b27ec65b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2398285918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2398285918
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1690159021
Short name T484
Test name
Test status
Simulation time 1083076070 ps
CPU time 6.54 seconds
Started Jun 09 01:43:46 PM PDT 24
Finished Jun 09 01:43:53 PM PDT 24
Peak memory 200340 kb
Host smart-05ca1423-6dc0-42fa-916b-a4c060fb3241
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690159021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1690159021
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2055327762
Short name T366
Test name
Test status
Simulation time 4332092768 ps
CPU time 83.86 seconds
Started Jun 09 01:43:48 PM PDT 24
Finished Jun 09 01:45:13 PM PDT 24
Peak memory 200488 kb
Host smart-491653a9-c881-481c-873c-4494f0e2e077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055327762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2055327762
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1232650655
Short name T30
Test name
Test status
Simulation time 142941739 ps
CPU time 0.82 seconds
Started Jun 09 01:43:47 PM PDT 24
Finished Jun 09 01:43:48 PM PDT 24
Peak memory 218776 kb
Host smart-1053b479-7aef-40ee-9260-a1795eda7b3e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232650655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1232650655
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.579661663
Short name T276
Test name
Test status
Simulation time 807024847 ps
CPU time 8.01 seconds
Started Jun 09 01:43:48 PM PDT 24
Finished Jun 09 01:43:57 PM PDT 24
Peak memory 200440 kb
Host smart-d64a2246-497f-4074-bb4f-fbfb45f75cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579661663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.579661663
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.4132459124
Short name T142
Test name
Test status
Simulation time 6717959558 ps
CPU time 92.99 seconds
Started Jun 09 01:43:53 PM PDT 24
Finished Jun 09 01:45:27 PM PDT 24
Peak memory 200496 kb
Host smart-4983bbf7-dc6d-486f-bdb0-3c2e80c426fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132459124 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.4132459124
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.941928256
Short name T190
Test name
Test status
Simulation time 237940110 ps
CPU time 1.37 seconds
Started Jun 09 01:43:48 PM PDT 24
Finished Jun 09 01:43:50 PM PDT 24
Peak memory 200452 kb
Host smart-120a9e4e-c4cf-474a-bf05-f4e224004a8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941928256 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_hmac_vectors.941928256
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.438518316
Short name T591
Test name
Test status
Simulation time 97726671554 ps
CPU time 525.55 seconds
Started Jun 09 01:43:49 PM PDT 24
Finished Jun 09 01:52:36 PM PDT 24
Peak memory 200464 kb
Host smart-884c1987-451b-4d13-89ac-087db2933cf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438518316 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.438518316
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.4174938555
Short name T262
Test name
Test status
Simulation time 364119397 ps
CPU time 19.37 seconds
Started Jun 09 01:43:47 PM PDT 24
Finished Jun 09 01:44:07 PM PDT 24
Peak memory 200436 kb
Host smart-07d1cb17-e2f1-4d14-9f7f-b6c7cf2f3325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174938555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.4174938555
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1325612151
Short name T258
Test name
Test status
Simulation time 19271170 ps
CPU time 0.63 seconds
Started Jun 09 01:45:05 PM PDT 24
Finished Jun 09 01:45:06 PM PDT 24
Peak memory 195364 kb
Host smart-5d668af2-d7b5-469e-8d9c-17ef7148d5d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325612151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1325612151
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.315886681
Short name T331
Test name
Test status
Simulation time 293316359 ps
CPU time 7.06 seconds
Started Jun 09 01:44:59 PM PDT 24
Finished Jun 09 01:45:06 PM PDT 24
Peak memory 208640 kb
Host smart-506c9b1f-f7c2-442b-a0f6-c0c237080829
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=315886681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.315886681
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3442109707
Short name T249
Test name
Test status
Simulation time 5701085342 ps
CPU time 28.13 seconds
Started Jun 09 01:45:00 PM PDT 24
Finished Jun 09 01:45:29 PM PDT 24
Peak memory 200452 kb
Host smart-9d212640-2a1b-4c58-9279-871b2cf84fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442109707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3442109707
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1010472492
Short name T416
Test name
Test status
Simulation time 2032657073 ps
CPU time 506.68 seconds
Started Jun 09 01:45:02 PM PDT 24
Finished Jun 09 01:53:29 PM PDT 24
Peak memory 707228 kb
Host smart-42c0f476-a3ae-4477-b7d6-e5e7e62cc5a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1010472492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1010472492
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.2344965816
Short name T595
Test name
Test status
Simulation time 1295156155 ps
CPU time 24.21 seconds
Started Jun 09 01:44:59 PM PDT 24
Finished Jun 09 01:45:23 PM PDT 24
Peak memory 200412 kb
Host smart-16b6c082-4f22-467c-b62b-2f44c781aaed
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344965816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2344965816
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1098096735
Short name T137
Test name
Test status
Simulation time 874886583 ps
CPU time 8.09 seconds
Started Jun 09 01:45:02 PM PDT 24
Finished Jun 09 01:45:10 PM PDT 24
Peak memory 200408 kb
Host smart-263ff8ae-9f50-4ea0-86eb-c1c55a69dbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098096735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1098096735
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.947007349
Short name T559
Test name
Test status
Simulation time 115200478 ps
CPU time 4 seconds
Started Jun 09 01:45:02 PM PDT 24
Finished Jun 09 01:45:07 PM PDT 24
Peak memory 200416 kb
Host smart-42a00355-89bc-4b03-aa6b-96be7f3516b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947007349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.947007349
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.1334546844
Short name T325
Test name
Test status
Simulation time 73841853 ps
CPU time 1.16 seconds
Started Jun 09 01:45:09 PM PDT 24
Finished Jun 09 01:45:11 PM PDT 24
Peak memory 200428 kb
Host smart-b96b4932-a621-435a-8458-1b18e5fd0bf6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334546844 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.1334546844
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.760201441
Short name T19
Test name
Test status
Simulation time 7351301514 ps
CPU time 425.89 seconds
Started Jun 09 01:45:05 PM PDT 24
Finished Jun 09 01:52:11 PM PDT 24
Peak memory 200432 kb
Host smart-73869cbf-2b87-4a4f-b542-7bd0e6f677f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760201441 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.760201441
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.588520362
Short name T426
Test name
Test status
Simulation time 2272190990 ps
CPU time 40.89 seconds
Started Jun 09 01:45:08 PM PDT 24
Finished Jun 09 01:45:49 PM PDT 24
Peak memory 200504 kb
Host smart-31abd68f-a93f-48d8-90d1-b87e9e2d784d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588520362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.588520362
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1920195462
Short name T145
Test name
Test status
Simulation time 15014811 ps
CPU time 0.61 seconds
Started Jun 09 01:45:11 PM PDT 24
Finished Jun 09 01:45:12 PM PDT 24
Peak memory 197140 kb
Host smart-2c740f84-0f17-43db-95d2-1b819c429e8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920195462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1920195462
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.890863814
Short name T272
Test name
Test status
Simulation time 511407326 ps
CPU time 7.75 seconds
Started Jun 09 01:45:05 PM PDT 24
Finished Jun 09 01:45:13 PM PDT 24
Peak memory 208556 kb
Host smart-bde09a71-9c24-4db5-9fe3-892b46297a3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=890863814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.890863814
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1537157794
Short name T431
Test name
Test status
Simulation time 7495817105 ps
CPU time 38.94 seconds
Started Jun 09 01:45:08 PM PDT 24
Finished Jun 09 01:45:47 PM PDT 24
Peak memory 200512 kb
Host smart-86bff3fc-3580-4f51-bf5f-f9687916de75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537157794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1537157794
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.25778269
Short name T268
Test name
Test status
Simulation time 1356245275 ps
CPU time 389.59 seconds
Started Jun 09 01:45:05 PM PDT 24
Finished Jun 09 01:51:35 PM PDT 24
Peak memory 690480 kb
Host smart-6cc66d7e-94df-48e4-84bd-743790facc98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=25778269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.25778269
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.2461471171
Short name T481
Test name
Test status
Simulation time 2533125136 ps
CPU time 145.21 seconds
Started Jun 09 01:45:06 PM PDT 24
Finished Jun 09 01:47:32 PM PDT 24
Peak memory 200568 kb
Host smart-f1ce5df2-e740-41c9-80bf-75b7229ec62d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461471171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2461471171
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.642484058
Short name T402
Test name
Test status
Simulation time 21278131313 ps
CPU time 117.77 seconds
Started Jun 09 01:45:07 PM PDT 24
Finished Jun 09 01:47:05 PM PDT 24
Peak memory 200528 kb
Host smart-86031c27-3953-4e95-9f1a-b2b172c5ee25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642484058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.642484058
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1822371164
Short name T178
Test name
Test status
Simulation time 597721489 ps
CPU time 5.56 seconds
Started Jun 09 01:45:07 PM PDT 24
Finished Jun 09 01:45:12 PM PDT 24
Peak memory 200492 kb
Host smart-28a1947e-f133-498c-97b5-522daba4588e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822371164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1822371164
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1483635291
Short name T96
Test name
Test status
Simulation time 43096563964 ps
CPU time 1244.81 seconds
Started Jun 09 01:45:11 PM PDT 24
Finished Jun 09 02:05:56 PM PDT 24
Peak memory 245664 kb
Host smart-51c86938-bd84-4005-8bcf-da46927f570b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483635291 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1483635291
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.2191543371
Short name T562
Test name
Test status
Simulation time 28734223 ps
CPU time 1.07 seconds
Started Jun 09 01:45:11 PM PDT 24
Finished Jun 09 01:45:12 PM PDT 24
Peak memory 200272 kb
Host smart-3a79be85-7fd6-43c8-aa4d-39e44883f27a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191543371 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.2191543371
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.923803977
Short name T156
Test name
Test status
Simulation time 26074325642 ps
CPU time 486.07 seconds
Started Jun 09 01:45:10 PM PDT 24
Finished Jun 09 01:53:16 PM PDT 24
Peak memory 200436 kb
Host smart-43fb0da7-3560-4257-9524-e0e2c19c489c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923803977 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.923803977
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.3997616200
Short name T500
Test name
Test status
Simulation time 4264534407 ps
CPU time 77.56 seconds
Started Jun 09 01:45:10 PM PDT 24
Finished Jun 09 01:46:28 PM PDT 24
Peak memory 200508 kb
Host smart-f7641f65-7032-4298-9289-2461a6c4a2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997616200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3997616200
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2194633830
Short name T189
Test name
Test status
Simulation time 19559300 ps
CPU time 0.56 seconds
Started Jun 09 01:45:16 PM PDT 24
Finished Jun 09 01:45:16 PM PDT 24
Peak memory 195232 kb
Host smart-7ba7ff33-4e8c-4aed-a37f-adc6030f8c8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194633830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2194633830
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2876304072
Short name T445
Test name
Test status
Simulation time 1597625292 ps
CPU time 17.49 seconds
Started Jun 09 01:45:16 PM PDT 24
Finished Jun 09 01:45:34 PM PDT 24
Peak memory 208640 kb
Host smart-59aa9ea3-9b46-4adc-8561-bae4af3de256
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2876304072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2876304072
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1186431428
Short name T295
Test name
Test status
Simulation time 4454304702 ps
CPU time 56.84 seconds
Started Jun 09 01:45:14 PM PDT 24
Finished Jun 09 01:46:11 PM PDT 24
Peak memory 200544 kb
Host smart-a6ab0d51-97dd-4941-bd93-828ad95cc5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186431428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1186431428
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.687806959
Short name T508
Test name
Test status
Simulation time 51896178736 ps
CPU time 880.44 seconds
Started Jun 09 01:45:24 PM PDT 24
Finished Jun 09 02:00:05 PM PDT 24
Peak memory 742312 kb
Host smart-cc43ed12-c852-4aa0-89e4-008190d82498
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=687806959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.687806959
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.1044826300
Short name T198
Test name
Test status
Simulation time 35440475546 ps
CPU time 99.95 seconds
Started Jun 09 01:45:16 PM PDT 24
Finished Jun 09 01:46:56 PM PDT 24
Peak memory 200520 kb
Host smart-82e666ac-1f42-4939-8756-ab0d899b34a0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044826300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1044826300
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.341290291
Short name T72
Test name
Test status
Simulation time 4763935597 ps
CPU time 80.7 seconds
Started Jun 09 01:45:16 PM PDT 24
Finished Jun 09 01:46:37 PM PDT 24
Peak memory 200536 kb
Host smart-076b3eca-4111-448b-a006-0531ebb92882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341290291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.341290291
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.812969483
Short name T124
Test name
Test status
Simulation time 308313617 ps
CPU time 2.27 seconds
Started Jun 09 01:45:10 PM PDT 24
Finished Jun 09 01:45:13 PM PDT 24
Peak memory 200488 kb
Host smart-aada4174-f683-462b-a96f-e3e585612e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812969483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.812969483
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2456250037
Short name T123
Test name
Test status
Simulation time 256591418524 ps
CPU time 1966.87 seconds
Started Jun 09 01:45:14 PM PDT 24
Finished Jun 09 02:18:01 PM PDT 24
Peak memory 709756 kb
Host smart-ba524bd7-9768-4e22-8d26-c7c9fcbcb5bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456250037 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2456250037
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.2315424746
Short name T232
Test name
Test status
Simulation time 216025252 ps
CPU time 1.45 seconds
Started Jun 09 01:45:19 PM PDT 24
Finished Jun 09 01:45:20 PM PDT 24
Peak memory 200480 kb
Host smart-610a258f-06d4-4577-bbe2-915b0bd089c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315424746 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.2315424746
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.1349275950
Short name T466
Test name
Test status
Simulation time 83001291723 ps
CPU time 572.76 seconds
Started Jun 09 01:45:24 PM PDT 24
Finished Jun 09 01:54:57 PM PDT 24
Peak memory 200428 kb
Host smart-119ca1fa-a170-4135-ad46-347d661babf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349275950 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.1349275950
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.751872946
Short name T133
Test name
Test status
Simulation time 2111710030 ps
CPU time 29.13 seconds
Started Jun 09 01:45:16 PM PDT 24
Finished Jun 09 01:45:45 PM PDT 24
Peak memory 200432 kb
Host smart-e7011e17-70f0-42ec-bc34-e9c7dc5b8dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751872946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.751872946
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.856244827
Short name T543
Test name
Test status
Simulation time 11907543 ps
CPU time 0.6 seconds
Started Jun 09 01:45:22 PM PDT 24
Finished Jun 09 01:45:23 PM PDT 24
Peak memory 197140 kb
Host smart-fe822a70-6913-43ec-ab5f-e039c61fe51e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856244827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.856244827
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.1231868764
Short name T565
Test name
Test status
Simulation time 736772252 ps
CPU time 38.23 seconds
Started Jun 09 01:45:16 PM PDT 24
Finished Jun 09 01:45:54 PM PDT 24
Peak memory 208624 kb
Host smart-5f35f59e-ce1e-4e96-95e2-6a4168f20dd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1231868764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1231868764
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.4124089078
Short name T26
Test name
Test status
Simulation time 534037063 ps
CPU time 27.46 seconds
Started Jun 09 01:45:16 PM PDT 24
Finished Jun 09 01:45:44 PM PDT 24
Peak memory 200436 kb
Host smart-56dc4d1f-9a6d-463a-bf71-06e8daf2d1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124089078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.4124089078
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3319159224
Short name T388
Test name
Test status
Simulation time 11130039937 ps
CPU time 1455.25 seconds
Started Jun 09 01:45:16 PM PDT 24
Finished Jun 09 02:09:32 PM PDT 24
Peak memory 755848 kb
Host smart-7c68cd5c-5892-403a-a96d-6448a301f3f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3319159224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3319159224
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.4188363946
Short name T376
Test name
Test status
Simulation time 1863180610 ps
CPU time 23.32 seconds
Started Jun 09 01:45:20 PM PDT 24
Finished Jun 09 01:45:44 PM PDT 24
Peak memory 200428 kb
Host smart-afce532d-a295-456e-b79e-f7eb536d85ef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188363946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.4188363946
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2235412915
Short name T296
Test name
Test status
Simulation time 9052511661 ps
CPU time 29.71 seconds
Started Jun 09 01:45:16 PM PDT 24
Finished Jun 09 01:45:46 PM PDT 24
Peak memory 200528 kb
Host smart-a6b13e45-0664-41e9-afc0-776d6cffe7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235412915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2235412915
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3481163727
Short name T52
Test name
Test status
Simulation time 100147130 ps
CPU time 0.74 seconds
Started Jun 09 01:45:24 PM PDT 24
Finished Jun 09 01:45:25 PM PDT 24
Peak memory 198396 kb
Host smart-29ee79f1-0122-414b-8915-9f7de048999c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481163727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3481163727
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.4005740416
Short name T95
Test name
Test status
Simulation time 34899505268 ps
CPU time 1468.32 seconds
Started Jun 09 01:45:22 PM PDT 24
Finished Jun 09 02:09:51 PM PDT 24
Peak memory 788128 kb
Host smart-5f05462e-0651-4894-b84d-87cc1addce35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005740416 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.4005740416
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.2865984302
Short name T286
Test name
Test status
Simulation time 57315961 ps
CPU time 1.1 seconds
Started Jun 09 01:45:16 PM PDT 24
Finished Jun 09 01:45:18 PM PDT 24
Peak memory 200276 kb
Host smart-7b73a268-861c-428a-af6c-921cfa597753
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865984302 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.2865984302
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.3244693438
Short name T188
Test name
Test status
Simulation time 39883967302 ps
CPU time 513.23 seconds
Started Jun 09 01:45:20 PM PDT 24
Finished Jun 09 01:53:54 PM PDT 24
Peak memory 200428 kb
Host smart-ec75506b-5681-4f90-96ee-9bff43909471
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244693438 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.3244693438
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3416789860
Short name T203
Test name
Test status
Simulation time 709062472 ps
CPU time 5.94 seconds
Started Jun 09 01:45:16 PM PDT 24
Finished Jun 09 01:45:22 PM PDT 24
Peak memory 200240 kb
Host smart-92dd2aac-2457-404b-a4b9-d4ee4146c481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416789860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3416789860
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.141631536
Short name T180
Test name
Test status
Simulation time 78590556 ps
CPU time 0.59 seconds
Started Jun 09 01:45:22 PM PDT 24
Finished Jun 09 01:45:23 PM PDT 24
Peak memory 196008 kb
Host smart-17949341-cde2-4fb1-a737-f5b3463c91bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141631536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.141631536
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2205197258
Short name T273
Test name
Test status
Simulation time 1245775409 ps
CPU time 30.05 seconds
Started Jun 09 01:45:21 PM PDT 24
Finished Jun 09 01:45:51 PM PDT 24
Peak memory 208648 kb
Host smart-821509d6-5752-408e-a573-568ea07bf1d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2205197258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2205197258
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1857126745
Short name T297
Test name
Test status
Simulation time 2425292946 ps
CPU time 45.98 seconds
Started Jun 09 01:45:21 PM PDT 24
Finished Jun 09 01:46:07 PM PDT 24
Peak memory 200528 kb
Host smart-3d7e2fa1-0640-426a-b432-244f8e74cbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857126745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1857126745
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3912070028
Short name T323
Test name
Test status
Simulation time 45003996212 ps
CPU time 1554.25 seconds
Started Jun 09 01:45:22 PM PDT 24
Finished Jun 09 02:11:17 PM PDT 24
Peak memory 800248 kb
Host smart-9303c287-3b82-4964-a933-7382e88bf779
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3912070028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3912070028
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3223199724
Short name T223
Test name
Test status
Simulation time 2447895651 ps
CPU time 47.28 seconds
Started Jun 09 01:45:21 PM PDT 24
Finished Jun 09 01:46:08 PM PDT 24
Peak memory 200492 kb
Host smart-4997272c-4848-4af0-a7ad-7f805762dd87
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223199724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3223199724
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3304786669
Short name T467
Test name
Test status
Simulation time 17989494251 ps
CPU time 135.41 seconds
Started Jun 09 01:45:21 PM PDT 24
Finished Jun 09 01:47:37 PM PDT 24
Peak memory 200556 kb
Host smart-10d395d5-341a-4d7f-b900-db913e02560f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304786669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3304786669
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2938319286
Short name T210
Test name
Test status
Simulation time 370373442 ps
CPU time 4.29 seconds
Started Jun 09 01:45:20 PM PDT 24
Finished Jun 09 01:45:25 PM PDT 24
Peak memory 200664 kb
Host smart-4ce73f69-ea05-4b79-bd26-c80d6d05bd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938319286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2938319286
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3808110760
Short name T63
Test name
Test status
Simulation time 5029458711 ps
CPU time 68.93 seconds
Started Jun 09 01:45:22 PM PDT 24
Finished Jun 09 01:46:31 PM PDT 24
Peak memory 200540 kb
Host smart-cd54d674-447e-4511-90d2-de7f0c6b1feb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808110760 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3808110760
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.4161807753
Short name T584
Test name
Test status
Simulation time 76706617 ps
CPU time 1.4 seconds
Started Jun 09 01:45:20 PM PDT 24
Finished Jun 09 01:45:22 PM PDT 24
Peak memory 200448 kb
Host smart-d30d8d1f-074d-4ee1-a804-2377dfd0cdf4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161807753 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.4161807753
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.4011528314
Short name T477
Test name
Test status
Simulation time 46963296539 ps
CPU time 480.55 seconds
Started Jun 09 01:45:25 PM PDT 24
Finished Jun 09 01:53:26 PM PDT 24
Peak memory 200420 kb
Host smart-20bdb8a2-def7-4756-b84c-2ab511e94f62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011528314 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.4011528314
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1486581908
Short name T385
Test name
Test status
Simulation time 4215066537 ps
CPU time 14.88 seconds
Started Jun 09 01:45:21 PM PDT 24
Finished Jun 09 01:45:36 PM PDT 24
Peak memory 200524 kb
Host smart-91e75892-78b5-45fb-af53-32718ece7260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486581908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1486581908
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.4148365829
Short name T453
Test name
Test status
Simulation time 17351154 ps
CPU time 0.61 seconds
Started Jun 09 01:45:31 PM PDT 24
Finished Jun 09 01:45:32 PM PDT 24
Peak memory 196036 kb
Host smart-17920304-3d21-4b48-825d-19c5fdefbd57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148365829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.4148365829
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1228227536
Short name T436
Test name
Test status
Simulation time 505033904 ps
CPU time 22.26 seconds
Started Jun 09 01:45:22 PM PDT 24
Finished Jun 09 01:45:44 PM PDT 24
Peak memory 233172 kb
Host smart-8d6f99dc-1155-4dcd-b6cc-01dc4f325c74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1228227536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1228227536
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2351055695
Short name T266
Test name
Test status
Simulation time 2341246434 ps
CPU time 42.22 seconds
Started Jun 09 01:45:26 PM PDT 24
Finished Jun 09 01:46:08 PM PDT 24
Peak memory 200512 kb
Host smart-09bf2a4e-5ba7-4d2a-a88f-556f92ca1162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351055695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2351055695
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.36976468
Short name T377
Test name
Test status
Simulation time 2557808461 ps
CPU time 254.38 seconds
Started Jun 09 01:45:26 PM PDT 24
Finished Jun 09 01:49:40 PM PDT 24
Peak memory 470152 kb
Host smart-59e4ec48-4167-40a6-ab02-0042492d0376
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=36976468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.36976468
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.897128049
Short name T462
Test name
Test status
Simulation time 1329442345 ps
CPU time 71.38 seconds
Started Jun 09 01:45:24 PM PDT 24
Finished Jun 09 01:46:35 PM PDT 24
Peak memory 200444 kb
Host smart-e4822cd2-1cc8-41dd-8006-2b8179ee1c95
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897128049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.897128049
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1759563669
Short name T117
Test name
Test status
Simulation time 41868522689 ps
CPU time 134.6 seconds
Started Jun 09 01:45:23 PM PDT 24
Finished Jun 09 01:47:38 PM PDT 24
Peak memory 200496 kb
Host smart-dca78e95-5921-40dc-adcd-4828add91c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759563669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1759563669
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3533934459
Short name T168
Test name
Test status
Simulation time 31034628 ps
CPU time 1.29 seconds
Started Jun 09 01:45:19 PM PDT 24
Finished Jun 09 01:45:21 PM PDT 24
Peak memory 200392 kb
Host smart-46bfb563-1681-41fd-8276-7e5e4dcbb025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533934459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3533934459
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1109114978
Short name T59
Test name
Test status
Simulation time 63147467136 ps
CPU time 2895.66 seconds
Started Jun 09 01:45:26 PM PDT 24
Finished Jun 09 02:33:42 PM PDT 24
Peak memory 811664 kb
Host smart-1aa8ed12-af4c-4335-a8ea-7bc5ca228b93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109114978 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1109114978
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.3802251123
Short name T264
Test name
Test status
Simulation time 223007667 ps
CPU time 1.28 seconds
Started Jun 09 01:45:26 PM PDT 24
Finished Jun 09 01:45:28 PM PDT 24
Peak memory 200448 kb
Host smart-276edccc-4a25-41e5-b949-63c1be628b80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802251123 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.3802251123
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.4159678156
Short name T283
Test name
Test status
Simulation time 34518175324 ps
CPU time 525.48 seconds
Started Jun 09 01:45:27 PM PDT 24
Finished Jun 09 01:54:13 PM PDT 24
Peak memory 200468 kb
Host smart-34100621-a92e-4773-8266-27461cb5d14b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159678156 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.4159678156
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1084979093
Short name T560
Test name
Test status
Simulation time 241353330 ps
CPU time 5.04 seconds
Started Jun 09 01:45:26 PM PDT 24
Finished Jun 09 01:45:32 PM PDT 24
Peak memory 200460 kb
Host smart-bad57487-5b75-4cea-b1c7-5255effce0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084979093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1084979093
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1411113186
Short name T160
Test name
Test status
Simulation time 142054219 ps
CPU time 0.6 seconds
Started Jun 09 01:45:31 PM PDT 24
Finished Jun 09 01:45:32 PM PDT 24
Peak memory 195532 kb
Host smart-954653cf-044a-4318-a60f-add0ec52ea91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411113186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1411113186
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1781170601
Short name T348
Test name
Test status
Simulation time 1405839323 ps
CPU time 35.79 seconds
Started Jun 09 01:45:27 PM PDT 24
Finished Jun 09 01:46:03 PM PDT 24
Peak memory 225044 kb
Host smart-88409172-3551-450b-8dd0-f1e005319977
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1781170601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1781170601
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1263842272
Short name T152
Test name
Test status
Simulation time 4037797471 ps
CPU time 56.28 seconds
Started Jun 09 01:45:30 PM PDT 24
Finished Jun 09 01:46:26 PM PDT 24
Peak memory 200484 kb
Host smart-c824f0b7-00c4-4d13-8bcd-9767fab659f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263842272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1263842272
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3254150120
Short name T259
Test name
Test status
Simulation time 7070242580 ps
CPU time 458.73 seconds
Started Jun 09 01:45:25 PM PDT 24
Finished Jun 09 01:53:04 PM PDT 24
Peak memory 470036 kb
Host smart-e34a73df-a85c-42a6-886a-23da0995d46a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3254150120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3254150120
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1107734705
Short name T526
Test name
Test status
Simulation time 13068218454 ps
CPU time 169.34 seconds
Started Jun 09 01:45:24 PM PDT 24
Finished Jun 09 01:48:14 PM PDT 24
Peak memory 200464 kb
Host smart-118781f9-3360-4206-a7d5-a4c1f3ee50ad
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107734705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1107734705
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.4142295135
Short name T175
Test name
Test status
Simulation time 8637175341 ps
CPU time 80.67 seconds
Started Jun 09 01:45:26 PM PDT 24
Finished Jun 09 01:46:46 PM PDT 24
Peak memory 200540 kb
Host smart-51d704bc-4d94-4db1-9014-56e2d7f86833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142295135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.4142295135
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.3530705310
Short name T531
Test name
Test status
Simulation time 571273845 ps
CPU time 6.67 seconds
Started Jun 09 01:45:24 PM PDT 24
Finished Jun 09 01:45:31 PM PDT 24
Peak memory 200504 kb
Host smart-ec704261-e305-447b-b0ee-ebbc63e64dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530705310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3530705310
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.258402825
Short name T278
Test name
Test status
Simulation time 155636798279 ps
CPU time 3539.8 seconds
Started Jun 09 01:45:30 PM PDT 24
Finished Jun 09 02:44:30 PM PDT 24
Peak memory 788384 kb
Host smart-d11c081a-836a-482a-ac2b-193568d0f018
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258402825 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.258402825
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.1054417056
Short name T409
Test name
Test status
Simulation time 62974650 ps
CPU time 1.39 seconds
Started Jun 09 01:45:30 PM PDT 24
Finished Jun 09 01:45:32 PM PDT 24
Peak memory 200448 kb
Host smart-5c6c6a3f-b7ae-4337-a544-d95e5401bf6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054417056 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.1054417056
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.2363832424
Short name T289
Test name
Test status
Simulation time 133240795426 ps
CPU time 449.6 seconds
Started Jun 09 01:45:31 PM PDT 24
Finished Jun 09 01:53:01 PM PDT 24
Peak memory 200396 kb
Host smart-699c94c8-e065-4410-8f8a-84c1414ff69a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363832424 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.2363832424
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.989294863
Short name T337
Test name
Test status
Simulation time 2193307285 ps
CPU time 18.02 seconds
Started Jun 09 01:45:30 PM PDT 24
Finished Jun 09 01:45:48 PM PDT 24
Peak memory 200492 kb
Host smart-6f320716-ed94-4e67-90cf-2c2a4c6b2aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989294863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.989294863
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.4215148158
Short name T173
Test name
Test status
Simulation time 15365513 ps
CPU time 0.62 seconds
Started Jun 09 01:45:34 PM PDT 24
Finished Jun 09 01:45:35 PM PDT 24
Peak memory 196408 kb
Host smart-4fce202f-140b-4798-b3b9-4a7254ffcb05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215148158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.4215148158
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3572753503
Short name T212
Test name
Test status
Simulation time 68994005 ps
CPU time 3.69 seconds
Started Jun 09 01:45:31 PM PDT 24
Finished Jun 09 01:45:35 PM PDT 24
Peak memory 200488 kb
Host smart-0802c491-607a-4aad-a94d-480909055bcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3572753503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3572753503
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3556267682
Short name T88
Test name
Test status
Simulation time 1966549013 ps
CPU time 34.03 seconds
Started Jun 09 01:45:30 PM PDT 24
Finished Jun 09 01:46:04 PM PDT 24
Peak memory 200448 kb
Host smart-82254940-d4b6-4e61-801f-5f95251f7d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556267682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3556267682
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.616489641
Short name T227
Test name
Test status
Simulation time 1025048499 ps
CPU time 106.75 seconds
Started Jun 09 01:45:31 PM PDT 24
Finished Jun 09 01:47:18 PM PDT 24
Peak memory 469020 kb
Host smart-c2577a4e-e6e6-4644-b355-18fe9d437a72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=616489641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.616489641
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2791789844
Short name T414
Test name
Test status
Simulation time 2383259056 ps
CPU time 128.15 seconds
Started Jun 09 01:45:29 PM PDT 24
Finished Jun 09 01:47:38 PM PDT 24
Peak memory 200516 kb
Host smart-e2fdabb9-a20e-450e-b4a6-ddc4c57303b4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791789844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2791789844
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3402710834
Short name T588
Test name
Test status
Simulation time 14463992699 ps
CPU time 75.1 seconds
Started Jun 09 01:45:32 PM PDT 24
Finished Jun 09 01:46:47 PM PDT 24
Peak memory 200492 kb
Host smart-6fdd024d-0c89-4727-be30-2ba3caf24ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402710834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3402710834
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3381322174
Short name T50
Test name
Test status
Simulation time 50228779 ps
CPU time 2.01 seconds
Started Jun 09 01:45:31 PM PDT 24
Finished Jun 09 01:45:33 PM PDT 24
Peak memory 200440 kb
Host smart-341bff6e-cd2e-44b3-8b2f-6c730c219078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381322174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3381322174
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.140685239
Short name T493
Test name
Test status
Simulation time 113911878013 ps
CPU time 3071.76 seconds
Started Jun 09 01:45:35 PM PDT 24
Finished Jun 09 02:36:47 PM PDT 24
Peak memory 794712 kb
Host smart-fe4d1511-593e-467d-8026-19dc00f73687
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140685239 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.140685239
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.559220549
Short name T495
Test name
Test status
Simulation time 118668100 ps
CPU time 1.35 seconds
Started Jun 09 01:45:30 PM PDT 24
Finished Jun 09 01:45:32 PM PDT 24
Peak memory 200452 kb
Host smart-13220d01-e1c0-495c-9798-f6fa47d3cacc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559220549 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_hmac_vectors.559220549
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.1543199803
Short name T220
Test name
Test status
Simulation time 306663990326 ps
CPU time 577.87 seconds
Started Jun 09 01:45:31 PM PDT 24
Finished Jun 09 01:55:09 PM PDT 24
Peak memory 200460 kb
Host smart-ac76eef5-debf-454e-919d-360376a25ea8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543199803 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.1543199803
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2456710759
Short name T204
Test name
Test status
Simulation time 11369166950 ps
CPU time 56.82 seconds
Started Jun 09 01:45:31 PM PDT 24
Finished Jun 09 01:46:28 PM PDT 24
Peak memory 200468 kb
Host smart-f5561434-91e6-484e-8ad4-860b9e8e3c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456710759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2456710759
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.4213036386
Short name T319
Test name
Test status
Simulation time 68422607 ps
CPU time 0.59 seconds
Started Jun 09 01:45:41 PM PDT 24
Finished Jun 09 01:45:42 PM PDT 24
Peak memory 196416 kb
Host smart-a8a527e9-13f2-4963-a092-25790cf566ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213036386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.4213036386
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.506545205
Short name T311
Test name
Test status
Simulation time 372912115 ps
CPU time 13.44 seconds
Started Jun 09 01:45:34 PM PDT 24
Finished Jun 09 01:45:48 PM PDT 24
Peak memory 219064 kb
Host smart-cf986c42-ced0-4085-84e4-e009e9b6e5c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=506545205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.506545205
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.4036696578
Short name T320
Test name
Test status
Simulation time 18443974834 ps
CPU time 60.08 seconds
Started Jun 09 01:45:35 PM PDT 24
Finished Jun 09 01:46:36 PM PDT 24
Peak memory 200524 kb
Host smart-cf5c1aa0-649e-4543-b014-63a53f5aa418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036696578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.4036696578
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3260376459
Short name T387
Test name
Test status
Simulation time 1744838644 ps
CPU time 391.25 seconds
Started Jun 09 01:45:34 PM PDT 24
Finished Jun 09 01:52:06 PM PDT 24
Peak memory 502748 kb
Host smart-bdf5c033-45e0-4eb1-a4d4-58e2d79b7216
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3260376459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3260376459
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2235814206
Short name T447
Test name
Test status
Simulation time 8197602383 ps
CPU time 115.23 seconds
Started Jun 09 01:45:34 PM PDT 24
Finished Jun 09 01:47:29 PM PDT 24
Peak memory 200500 kb
Host smart-ce21293e-2e04-4e9b-ba59-ed2337c1aa91
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235814206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2235814206
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3566888402
Short name T205
Test name
Test status
Simulation time 277000455 ps
CPU time 17.14 seconds
Started Jun 09 01:45:35 PM PDT 24
Finished Jun 09 01:45:52 PM PDT 24
Peak memory 200424 kb
Host smart-dcf568c9-e3d9-409d-a471-027291b49887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566888402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3566888402
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.921447811
Short name T521
Test name
Test status
Simulation time 25429323 ps
CPU time 1.05 seconds
Started Jun 09 01:45:35 PM PDT 24
Finished Jun 09 01:45:36 PM PDT 24
Peak memory 200232 kb
Host smart-c7beb139-b219-4c9f-b579-49e62a5613f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921447811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.921447811
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.628611625
Short name T153
Test name
Test status
Simulation time 117594570 ps
CPU time 1.34 seconds
Started Jun 09 01:45:39 PM PDT 24
Finished Jun 09 01:45:41 PM PDT 24
Peak memory 200416 kb
Host smart-9f4b0aa4-f279-4f42-96e8-87caadf4e674
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628611625 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_hmac_vectors.628611625
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.1560193294
Short name T418
Test name
Test status
Simulation time 7225885493 ps
CPU time 411.22 seconds
Started Jun 09 01:45:42 PM PDT 24
Finished Jun 09 01:52:33 PM PDT 24
Peak memory 200436 kb
Host smart-7543f69b-5201-4060-9af4-c729cdbef595
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560193294 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.1560193294
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.3403066084
Short name T159
Test name
Test status
Simulation time 1028045174 ps
CPU time 15.24 seconds
Started Jun 09 01:45:41 PM PDT 24
Finished Jun 09 01:45:57 PM PDT 24
Peak memory 200440 kb
Host smart-ea88cd41-b0ab-42a9-a31a-c75449d598ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403066084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.3403066084
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3367078822
Short name T538
Test name
Test status
Simulation time 37189156 ps
CPU time 0.62 seconds
Started Jun 09 01:45:48 PM PDT 24
Finished Jun 09 01:45:48 PM PDT 24
Peak memory 195384 kb
Host smart-ee964381-91c4-420f-a84c-f202540592f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367078822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3367078822
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3105569514
Short name T35
Test name
Test status
Simulation time 694897845 ps
CPU time 36.24 seconds
Started Jun 09 01:45:39 PM PDT 24
Finished Jun 09 01:46:16 PM PDT 24
Peak memory 221896 kb
Host smart-2091a065-9a89-4a9e-a6ab-7535e2bb3b48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3105569514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3105569514
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.2557419495
Short name T428
Test name
Test status
Simulation time 9584435429 ps
CPU time 48.21 seconds
Started Jun 09 01:45:41 PM PDT 24
Finished Jun 09 01:46:30 PM PDT 24
Peak memory 200540 kb
Host smart-b6aa02e2-0721-4b91-8625-57a3905f321a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557419495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2557419495
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3204478806
Short name T219
Test name
Test status
Simulation time 15336833759 ps
CPU time 901.02 seconds
Started Jun 09 01:45:40 PM PDT 24
Finished Jun 09 02:00:42 PM PDT 24
Peak memory 692292 kb
Host smart-1731ac07-b51e-4456-904f-62e6f1c1e298
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3204478806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3204478806
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1103063268
Short name T419
Test name
Test status
Simulation time 2896221321 ps
CPU time 53.26 seconds
Started Jun 09 01:45:46 PM PDT 24
Finished Jun 09 01:46:39 PM PDT 24
Peak memory 200568 kb
Host smart-2306c709-21df-4fdd-9550-440a4843ba9e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103063268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1103063268
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1281746284
Short name T525
Test name
Test status
Simulation time 22338957310 ps
CPU time 108.39 seconds
Started Jun 09 01:45:40 PM PDT 24
Finished Jun 09 01:47:29 PM PDT 24
Peak memory 200464 kb
Host smart-9e22b1d2-d6c9-4103-b60e-b799ccfde269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281746284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1281746284
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3219894749
Short name T314
Test name
Test status
Simulation time 904486302 ps
CPU time 8.14 seconds
Started Jun 09 01:45:42 PM PDT 24
Finished Jun 09 01:45:51 PM PDT 24
Peak memory 200440 kb
Host smart-8a248684-3868-4e33-a055-070d2bacd756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219894749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3219894749
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.648127114
Short name T551
Test name
Test status
Simulation time 38679709978 ps
CPU time 2265.92 seconds
Started Jun 09 01:45:45 PM PDT 24
Finished Jun 09 02:23:32 PM PDT 24
Peak memory 825024 kb
Host smart-055bbf09-db5b-40ec-b38f-8823dbcf8d7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648127114 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.648127114
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.3526480420
Short name T461
Test name
Test status
Simulation time 202020383 ps
CPU time 1.12 seconds
Started Jun 09 01:45:45 PM PDT 24
Finished Jun 09 01:45:46 PM PDT 24
Peak memory 199952 kb
Host smart-49ea7d93-cb38-4f60-920c-87ece73262e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526480420 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.3526480420
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.1971766211
Short name T270
Test name
Test status
Simulation time 25850227539 ps
CPU time 487.14 seconds
Started Jun 09 01:45:51 PM PDT 24
Finished Jun 09 01:53:58 PM PDT 24
Peak memory 200372 kb
Host smart-3f38aa06-4290-4bac-a1ce-a8be703ea44a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971766211 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.1971766211
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.1847556119
Short name T298
Test name
Test status
Simulation time 4178422421 ps
CPU time 62.66 seconds
Started Jun 09 01:45:46 PM PDT 24
Finished Jun 09 01:46:49 PM PDT 24
Peak memory 200480 kb
Host smart-7212276f-36f5-40ad-a855-85d3c29d9e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847556119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1847556119
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.780081929
Short name T147
Test name
Test status
Simulation time 34146980 ps
CPU time 0.6 seconds
Started Jun 09 01:43:49 PM PDT 24
Finished Jun 09 01:43:50 PM PDT 24
Peak memory 195572 kb
Host smart-7b903205-7a30-4e98-b147-0dc4d3c91f07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780081929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.780081929
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3076688539
Short name T593
Test name
Test status
Simulation time 5546304326 ps
CPU time 72.79 seconds
Started Jun 09 01:43:53 PM PDT 24
Finished Jun 09 01:45:06 PM PDT 24
Peak memory 237380 kb
Host smart-f790884d-7a01-4f26-ab97-827fd302069b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3076688539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3076688539
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2343186877
Short name T373
Test name
Test status
Simulation time 4540683507 ps
CPU time 58.88 seconds
Started Jun 09 01:43:47 PM PDT 24
Finished Jun 09 01:44:46 PM PDT 24
Peak memory 200500 kb
Host smart-110a9589-7562-4511-ac93-28c170e791d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343186877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2343186877
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1582705231
Short name T527
Test name
Test status
Simulation time 5032984107 ps
CPU time 1330.64 seconds
Started Jun 09 01:43:47 PM PDT 24
Finished Jun 09 02:05:58 PM PDT 24
Peak memory 774120 kb
Host smart-d4ee3d86-fb4b-41aa-bb62-b36139717055
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1582705231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1582705231
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.439228846
Short name T146
Test name
Test status
Simulation time 17385014658 ps
CPU time 64.96 seconds
Started Jun 09 01:43:48 PM PDT 24
Finished Jun 09 01:44:53 PM PDT 24
Peak memory 200424 kb
Host smart-5bb3b67e-d959-4030-9b92-bf79b1d02c69
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439228846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.439228846
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1319399291
Short name T355
Test name
Test status
Simulation time 6818021769 ps
CPU time 126.25 seconds
Started Jun 09 01:43:49 PM PDT 24
Finished Jun 09 01:45:56 PM PDT 24
Peak memory 200488 kb
Host smart-f3bc7f45-a518-4eec-bf33-71c8b0378070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319399291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1319399291
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2470265429
Short name T29
Test name
Test status
Simulation time 166606943 ps
CPU time 0.91 seconds
Started Jun 09 01:43:46 PM PDT 24
Finished Jun 09 01:43:47 PM PDT 24
Peak memory 218860 kb
Host smart-dd9a7cbb-505e-499e-a501-11b32d8b34ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470265429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2470265429
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.3539587047
Short name T550
Test name
Test status
Simulation time 168965121 ps
CPU time 6.1 seconds
Started Jun 09 01:43:48 PM PDT 24
Finished Jun 09 01:43:55 PM PDT 24
Peak memory 200440 kb
Host smart-7042c3e3-7fde-4738-95db-396aa7bc6c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539587047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3539587047
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2410534343
Short name T401
Test name
Test status
Simulation time 63802778173 ps
CPU time 1142.09 seconds
Started Jun 09 01:43:47 PM PDT 24
Finished Jun 09 02:02:50 PM PDT 24
Peak memory 684744 kb
Host smart-22793d63-1c82-47e2-ba20-c6a2f86a254f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410534343 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2410534343
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.2454185536
Short name T263
Test name
Test status
Simulation time 70905550 ps
CPU time 1.29 seconds
Started Jun 09 01:43:47 PM PDT 24
Finished Jun 09 01:43:48 PM PDT 24
Peak memory 200444 kb
Host smart-a2b9eb9d-2101-44b0-a285-d688b8cbfa74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454185536 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.2454185536
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.2889914978
Short name T490
Test name
Test status
Simulation time 43306822688 ps
CPU time 591.42 seconds
Started Jun 09 01:43:48 PM PDT 24
Finished Jun 09 01:53:40 PM PDT 24
Peak memory 200500 kb
Host smart-38d25eca-6885-4992-99bf-443b6402b7f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889914978 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.2889914978
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2564380661
Short name T501
Test name
Test status
Simulation time 1983918723 ps
CPU time 36.14 seconds
Started Jun 09 01:43:48 PM PDT 24
Finished Jun 09 01:44:25 PM PDT 24
Peak memory 200492 kb
Host smart-a6ff8ab7-5f59-4789-b199-4645bd035686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564380661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2564380661
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.340573510
Short name T511
Test name
Test status
Simulation time 16405098 ps
CPU time 0.62 seconds
Started Jun 09 01:45:46 PM PDT 24
Finished Jun 09 01:45:47 PM PDT 24
Peak memory 196392 kb
Host smart-0a939d6f-bca0-48d4-941f-c606255ec222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340573510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.340573510
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.3692505191
Short name T2
Test name
Test status
Simulation time 4405934882 ps
CPU time 52.4 seconds
Started Jun 09 01:45:49 PM PDT 24
Finished Jun 09 01:46:42 PM PDT 24
Peak memory 225108 kb
Host smart-d1467b74-5104-4cb4-9f39-c805af96eda5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3692505191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3692505191
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3631203412
Short name T112
Test name
Test status
Simulation time 969354804 ps
CPU time 15.98 seconds
Started Jun 09 01:45:47 PM PDT 24
Finished Jun 09 01:46:03 PM PDT 24
Peak memory 200384 kb
Host smart-70e7e628-4084-46e6-9c96-486b3db7b5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631203412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3631203412
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2728601220
Short name T139
Test name
Test status
Simulation time 4068252794 ps
CPU time 1229.24 seconds
Started Jun 09 01:45:45 PM PDT 24
Finished Jun 09 02:06:14 PM PDT 24
Peak memory 710220 kb
Host smart-f7a788de-33eb-49d6-8826-9b5e853e4ab0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2728601220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2728601220
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.1964530682
Short name T470
Test name
Test status
Simulation time 15330985829 ps
CPU time 205.76 seconds
Started Jun 09 01:45:51 PM PDT 24
Finished Jun 09 01:49:17 PM PDT 24
Peak memory 200456 kb
Host smart-432b56f7-b240-43db-b089-27271e64cf3f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964530682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1964530682
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.496075913
Short name T399
Test name
Test status
Simulation time 2064728422 ps
CPU time 39.8 seconds
Started Jun 09 01:45:46 PM PDT 24
Finished Jun 09 01:46:26 PM PDT 24
Peak memory 200468 kb
Host smart-5671286a-75cb-43b5-9012-3dde360d5d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496075913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.496075913
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.374447713
Short name T144
Test name
Test status
Simulation time 165288001 ps
CPU time 1.62 seconds
Started Jun 09 01:45:51 PM PDT 24
Finished Jun 09 01:45:53 PM PDT 24
Peak memory 200472 kb
Host smart-2fd35070-a4de-42c3-b83e-d38cfcdda2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374447713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.374447713
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2809771457
Short name T60
Test name
Test status
Simulation time 740735460612 ps
CPU time 1097.44 seconds
Started Jun 09 01:45:49 PM PDT 24
Finished Jun 09 02:04:07 PM PDT 24
Peak memory 236848 kb
Host smart-e7c221aa-03af-4ec9-b6b0-878fa61ed3a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809771457 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2809771457
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.794500069
Short name T126
Test name
Test status
Simulation time 208853682 ps
CPU time 1.06 seconds
Started Jun 09 01:45:48 PM PDT 24
Finished Jun 09 01:45:49 PM PDT 24
Peak memory 200412 kb
Host smart-07e7fd2f-5421-4538-b4a4-9e7040da4349
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794500069 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_hmac_vectors.794500069
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.1926269826
Short name T69
Test name
Test status
Simulation time 35023508552 ps
CPU time 482.68 seconds
Started Jun 09 01:45:45 PM PDT 24
Finished Jun 09 01:53:48 PM PDT 24
Peak memory 200440 kb
Host smart-295b7a97-1ebd-404f-a32b-0198d36c0e17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926269826 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.1926269826
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.791570675
Short name T507
Test name
Test status
Simulation time 2076916032 ps
CPU time 70.64 seconds
Started Jun 09 01:45:48 PM PDT 24
Finished Jun 09 01:46:59 PM PDT 24
Peak memory 200448 kb
Host smart-e37ff11c-a2fb-4714-9b57-cdbf65bcc28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791570675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.791570675
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3837497431
Short name T125
Test name
Test status
Simulation time 12024482 ps
CPU time 0.57 seconds
Started Jun 09 01:45:56 PM PDT 24
Finished Jun 09 01:45:57 PM PDT 24
Peak memory 196120 kb
Host smart-02c23e8d-0858-4d9a-8782-59f564fa2868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837497431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3837497431
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.3160708021
Short name T1
Test name
Test status
Simulation time 2197598755 ps
CPU time 38.4 seconds
Started Jun 09 01:45:50 PM PDT 24
Finished Jun 09 01:46:28 PM PDT 24
Peak memory 216588 kb
Host smart-1635adba-d3c6-4407-8ed4-9ccf1b7e2b0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3160708021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3160708021
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2438917390
Short name T181
Test name
Test status
Simulation time 15592754965 ps
CPU time 80.52 seconds
Started Jun 09 01:45:49 PM PDT 24
Finished Jun 09 01:47:09 PM PDT 24
Peak memory 200496 kb
Host smart-171523ab-2466-43be-a739-2b2655ee8f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438917390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2438917390
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.3756259958
Short name T254
Test name
Test status
Simulation time 442114111 ps
CPU time 77.73 seconds
Started Jun 09 01:45:51 PM PDT 24
Finished Jun 09 01:47:09 PM PDT 24
Peak memory 412740 kb
Host smart-858a4e1e-2435-443e-ab02-2eb5163fb891
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3756259958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3756259958
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.774216147
Short name T434
Test name
Test status
Simulation time 22953509950 ps
CPU time 141.64 seconds
Started Jun 09 01:45:51 PM PDT 24
Finished Jun 09 01:48:13 PM PDT 24
Peak memory 200548 kb
Host smart-2b4ee93a-cc8a-444d-a1bb-e617237bd6ba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774216147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.774216147
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3171858140
Short name T465
Test name
Test status
Simulation time 13403661603 ps
CPU time 32.03 seconds
Started Jun 09 01:45:51 PM PDT 24
Finished Jun 09 01:46:24 PM PDT 24
Peak memory 200520 kb
Host smart-22c34ded-9a3f-419e-821a-be2bbc7022fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171858140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3171858140
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1455792590
Short name T130
Test name
Test status
Simulation time 4032442459 ps
CPU time 14.62 seconds
Started Jun 09 01:45:46 PM PDT 24
Finished Jun 09 01:46:01 PM PDT 24
Peak memory 200548 kb
Host smart-b24e21ea-263f-4ded-b016-60e24ca925af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455792590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1455792590
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3391531270
Short name T307
Test name
Test status
Simulation time 409153949784 ps
CPU time 944.6 seconds
Started Jun 09 01:45:49 PM PDT 24
Finished Jun 09 02:01:34 PM PDT 24
Peak memory 200696 kb
Host smart-146fe6b2-d153-4f66-9f18-651baae125bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391531270 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3391531270
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.4118753789
Short name T335
Test name
Test status
Simulation time 32357010 ps
CPU time 1.29 seconds
Started Jun 09 01:45:50 PM PDT 24
Finished Jun 09 01:45:51 PM PDT 24
Peak memory 200444 kb
Host smart-f5ec18d2-f7d6-4474-8f65-cf1c9a815617
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118753789 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.4118753789
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.1707590010
Short name T267
Test name
Test status
Simulation time 71857577848 ps
CPU time 468.61 seconds
Started Jun 09 01:45:51 PM PDT 24
Finished Jun 09 01:53:40 PM PDT 24
Peak memory 200484 kb
Host smart-10ae41d2-a9e1-41f7-aacc-df74da058c02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707590010 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.1707590010
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1925948720
Short name T176
Test name
Test status
Simulation time 1876605661 ps
CPU time 21.73 seconds
Started Jun 09 01:45:50 PM PDT 24
Finished Jun 09 01:46:12 PM PDT 24
Peak memory 200448 kb
Host smart-f8f4fc19-ba1f-4de8-b401-d6e4cce4a289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925948720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1925948720
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3090441191
Short name T362
Test name
Test status
Simulation time 47188269 ps
CPU time 0.6 seconds
Started Jun 09 01:45:57 PM PDT 24
Finished Jun 09 01:45:58 PM PDT 24
Peak memory 196392 kb
Host smart-25fb1a38-d039-4ece-9e02-45547e2f4100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090441191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3090441191
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.225871709
Short name T32
Test name
Test status
Simulation time 813289124 ps
CPU time 44.17 seconds
Started Jun 09 01:45:58 PM PDT 24
Finished Jun 09 01:46:42 PM PDT 24
Peak memory 236356 kb
Host smart-2ee1c5ba-9bf5-406c-a814-a0e199415ba0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=225871709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.225871709
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.81614428
Short name T215
Test name
Test status
Simulation time 18215786543 ps
CPU time 55.97 seconds
Started Jun 09 01:45:56 PM PDT 24
Finished Jun 09 01:46:52 PM PDT 24
Peak memory 200536 kb
Host smart-4e07d269-ffaa-469b-b512-f697e1d0c0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81614428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.81614428
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.62985946
Short name T383
Test name
Test status
Simulation time 2526972253 ps
CPU time 712.33 seconds
Started Jun 09 01:45:57 PM PDT 24
Finished Jun 09 01:57:50 PM PDT 24
Peak memory 714416 kb
Host smart-83aa6b01-6c2b-4d12-acd8-234727490891
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=62985946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.62985946
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.1011628513
Short name T395
Test name
Test status
Simulation time 1593335139 ps
CPU time 7.47 seconds
Started Jun 09 01:45:57 PM PDT 24
Finished Jun 09 01:46:05 PM PDT 24
Peak memory 200236 kb
Host smart-664d946a-89a0-4486-9326-d23c840260bc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011628513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1011628513
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3054741520
Short name T535
Test name
Test status
Simulation time 6100943348 ps
CPU time 84.76 seconds
Started Jun 09 01:45:55 PM PDT 24
Finished Jun 09 01:47:20 PM PDT 24
Peak memory 200560 kb
Host smart-8513e23d-a4fc-44da-98aa-28a636f037a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054741520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3054741520
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3949212514
Short name T487
Test name
Test status
Simulation time 3705679836 ps
CPU time 11.83 seconds
Started Jun 09 01:45:55 PM PDT 24
Finished Jun 09 01:46:07 PM PDT 24
Peak memory 200500 kb
Host smart-88a5e106-6634-4e0f-a94e-c68fc7a2624a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949212514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3949212514
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.84083783
Short name T552
Test name
Test status
Simulation time 76445437029 ps
CPU time 1372.5 seconds
Started Jun 09 01:45:55 PM PDT 24
Finished Jun 09 02:08:48 PM PDT 24
Peak memory 200464 kb
Host smart-14b8d836-6159-487c-932b-dfcd1467b41f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84083783 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.84083783
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.1233053041
Short name T407
Test name
Test status
Simulation time 233472589 ps
CPU time 1.45 seconds
Started Jun 09 01:45:56 PM PDT 24
Finished Jun 09 01:45:58 PM PDT 24
Peak memory 200364 kb
Host smart-b29e98b0-1e0b-477e-8943-7c93575677f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233053041 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.1233053041
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.621866013
Short name T502
Test name
Test status
Simulation time 56465852992 ps
CPU time 455.62 seconds
Started Jun 09 01:45:59 PM PDT 24
Finished Jun 09 01:53:35 PM PDT 24
Peak memory 200428 kb
Host smart-d9763874-d54a-4ff5-bb2c-dc75e5f009fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621866013 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.621866013
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2160351932
Short name T261
Test name
Test status
Simulation time 10115433195 ps
CPU time 30.11 seconds
Started Jun 09 01:45:56 PM PDT 24
Finished Jun 09 01:46:26 PM PDT 24
Peak memory 200456 kb
Host smart-5a789eec-9fb3-4b4c-8ab6-7bcb9d768bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160351932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2160351932
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1727927858
Short name T394
Test name
Test status
Simulation time 21611600 ps
CPU time 0.61 seconds
Started Jun 09 01:46:07 PM PDT 24
Finished Jun 09 01:46:08 PM PDT 24
Peak memory 195376 kb
Host smart-9d549f49-ccff-486d-b228-c62fb9fac938
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727927858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1727927858
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1359952747
Short name T177
Test name
Test status
Simulation time 947631189 ps
CPU time 67.94 seconds
Started Jun 09 01:46:01 PM PDT 24
Finished Jun 09 01:47:09 PM PDT 24
Peak memory 249832 kb
Host smart-a6ddc54c-f26b-485e-9b10-94e9b36ac933
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1359952747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1359952747
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2095866308
Short name T163
Test name
Test status
Simulation time 15937595772 ps
CPU time 60.72 seconds
Started Jun 09 01:46:02 PM PDT 24
Finished Jun 09 01:47:03 PM PDT 24
Peak memory 200560 kb
Host smart-5e77886e-532f-4bc7-bc93-99f07d76d8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095866308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2095866308
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.809534381
Short name T571
Test name
Test status
Simulation time 463913081 ps
CPU time 13.24 seconds
Started Jun 09 01:46:01 PM PDT 24
Finished Jun 09 01:46:15 PM PDT 24
Peak memory 229836 kb
Host smart-5742f40d-3080-40ae-87b3-a44335e39500
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=809534381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.809534381
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3633409758
Short name T364
Test name
Test status
Simulation time 2786094783 ps
CPU time 9.88 seconds
Started Jun 09 01:46:03 PM PDT 24
Finished Jun 09 01:46:13 PM PDT 24
Peak memory 200248 kb
Host smart-777ff2cd-bd6b-430e-a576-ba5d5a6302dc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633409758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3633409758
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1596763542
Short name T301
Test name
Test status
Simulation time 34032040218 ps
CPU time 124.22 seconds
Started Jun 09 01:46:02 PM PDT 24
Finished Jun 09 01:48:06 PM PDT 24
Peak memory 200492 kb
Host smart-f5567d9f-3580-4cb8-9a06-c205cd2b99ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596763542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1596763542
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.4039133179
Short name T134
Test name
Test status
Simulation time 103543116 ps
CPU time 1.59 seconds
Started Jun 09 01:46:01 PM PDT 24
Finished Jun 09 01:46:03 PM PDT 24
Peak memory 200440 kb
Host smart-e302ee3e-56e2-4131-8180-3b279ba45c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039133179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.4039133179
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.2018436199
Short name T187
Test name
Test status
Simulation time 385153297 ps
CPU time 1.35 seconds
Started Jun 09 01:46:09 PM PDT 24
Finished Jun 09 01:46:11 PM PDT 24
Peak memory 200428 kb
Host smart-2e1ba612-ee9f-482e-818a-307df1321946
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018436199 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.2018436199
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.1280183676
Short name T356
Test name
Test status
Simulation time 24429234674 ps
CPU time 464.01 seconds
Started Jun 09 01:46:07 PM PDT 24
Finished Jun 09 01:53:51 PM PDT 24
Peak memory 200412 kb
Host smart-dfb0eefa-ca9d-47ea-be5d-c9edb8e4c80a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280183676 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.1280183676
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1314776407
Short name T488
Test name
Test status
Simulation time 17825947951 ps
CPU time 71.58 seconds
Started Jun 09 01:46:01 PM PDT 24
Finished Jun 09 01:47:13 PM PDT 24
Peak memory 200536 kb
Host smart-f3d4ab54-9233-4ec8-9d83-ade45076b929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314776407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1314776407
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3394182187
Short name T138
Test name
Test status
Simulation time 19310578 ps
CPU time 0.55 seconds
Started Jun 09 01:46:10 PM PDT 24
Finished Jun 09 01:46:11 PM PDT 24
Peak memory 195360 kb
Host smart-81b30719-e563-49ba-a607-aac26b880fd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394182187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3394182187
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3837589343
Short name T179
Test name
Test status
Simulation time 1662633073 ps
CPU time 45.4 seconds
Started Jun 09 01:46:06 PM PDT 24
Finished Jun 09 01:46:51 PM PDT 24
Peak memory 247520 kb
Host smart-1d260f5c-e013-4170-a399-a843a84a88f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3837589343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3837589343
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2455426782
Short name T494
Test name
Test status
Simulation time 404624135 ps
CPU time 21.99 seconds
Started Jun 09 01:46:08 PM PDT 24
Finished Jun 09 01:46:30 PM PDT 24
Peak memory 200480 kb
Host smart-ba4f6e12-8db5-4b55-bc2d-717185db063e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455426782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2455426782
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1617996699
Short name T164
Test name
Test status
Simulation time 1438495107 ps
CPU time 45.85 seconds
Started Jun 09 01:46:08 PM PDT 24
Finished Jun 09 01:46:54 PM PDT 24
Peak memory 251780 kb
Host smart-740f504c-2a66-425e-b2f3-ec60a7383b23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1617996699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1617996699
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.377450979
Short name T522
Test name
Test status
Simulation time 28100560108 ps
CPU time 76.99 seconds
Started Jun 09 01:46:06 PM PDT 24
Finished Jun 09 01:47:23 PM PDT 24
Peak memory 200584 kb
Host smart-661c621a-b763-4bb9-b923-088923dcb9d7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377450979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.377450979
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.3203654158
Short name T324
Test name
Test status
Simulation time 5222507591 ps
CPU time 64.52 seconds
Started Jun 09 01:46:09 PM PDT 24
Finished Jun 09 01:47:14 PM PDT 24
Peak memory 200476 kb
Host smart-03c569f8-db51-4415-b484-d69a32757684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203654158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3203654158
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.4270894791
Short name T589
Test name
Test status
Simulation time 551169368 ps
CPU time 3.68 seconds
Started Jun 09 01:46:09 PM PDT 24
Finished Jun 09 01:46:13 PM PDT 24
Peak memory 200440 kb
Host smart-38317e79-c35e-4f7c-8aab-ee653d4d90e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270894791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.4270894791
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.3306977168
Short name T230
Test name
Test status
Simulation time 147166290 ps
CPU time 1.34 seconds
Started Jun 09 01:46:07 PM PDT 24
Finished Jun 09 01:46:08 PM PDT 24
Peak memory 200404 kb
Host smart-10c2d7e8-b5ea-4206-bef0-8219b96457a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306977168 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.3306977168
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.1866149881
Short name T338
Test name
Test status
Simulation time 8380315087 ps
CPU time 465.07 seconds
Started Jun 09 01:46:08 PM PDT 24
Finished Jun 09 01:53:53 PM PDT 24
Peak memory 200412 kb
Host smart-0f57e334-c1f6-45be-b90f-eae66371ebe4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866149881 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.1866149881
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.15512473
Short name T574
Test name
Test status
Simulation time 2015717097 ps
CPU time 30.27 seconds
Started Jun 09 01:46:07 PM PDT 24
Finished Jun 09 01:46:37 PM PDT 24
Peak memory 200508 kb
Host smart-b294fccd-41a8-431b-91aa-2890fd79f248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15512473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.15512473
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.778426203
Short name T567
Test name
Test status
Simulation time 46642993 ps
CPU time 0.62 seconds
Started Jun 09 01:46:12 PM PDT 24
Finished Jun 09 01:46:12 PM PDT 24
Peak memory 196388 kb
Host smart-bac39192-d9a5-49b6-9afe-d05c64606747
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778426203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.778426203
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.2608664846
Short name T390
Test name
Test status
Simulation time 289233771 ps
CPU time 14.79 seconds
Started Jun 09 01:46:12 PM PDT 24
Finished Jun 09 01:46:27 PM PDT 24
Peak memory 229216 kb
Host smart-8d006430-5056-4133-b5ad-001d34494ef1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2608664846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2608664846
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.1561843476
Short name T292
Test name
Test status
Simulation time 48523386083 ps
CPU time 60.93 seconds
Started Jun 09 01:46:11 PM PDT 24
Finished Jun 09 01:47:12 PM PDT 24
Peak memory 200524 kb
Host smart-2fba67b4-c269-423a-a566-ffcaf02fb509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561843476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1561843476
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1240569830
Short name T533
Test name
Test status
Simulation time 6470134055 ps
CPU time 752.71 seconds
Started Jun 09 01:46:13 PM PDT 24
Finished Jun 09 01:58:46 PM PDT 24
Peak memory 702672 kb
Host smart-a83e80dd-a415-4089-9e03-adfffc90e810
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1240569830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1240569830
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.3012358694
Short name T229
Test name
Test status
Simulation time 4121418890 ps
CPU time 74.99 seconds
Started Jun 09 01:46:12 PM PDT 24
Finished Jun 09 01:47:28 PM PDT 24
Peak memory 200488 kb
Host smart-21569afb-eb57-4a64-9658-4f48061c7215
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012358694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.3012358694
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3891176818
Short name T587
Test name
Test status
Simulation time 1820666930 ps
CPU time 33.83 seconds
Started Jun 09 01:46:07 PM PDT 24
Finished Jun 09 01:46:41 PM PDT 24
Peak memory 200624 kb
Host smart-afd96048-e6c4-4d85-874b-1f7274d9517f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891176818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3891176818
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3269773963
Short name T132
Test name
Test status
Simulation time 137477073 ps
CPU time 4.68 seconds
Started Jun 09 01:46:06 PM PDT 24
Finished Jun 09 01:46:10 PM PDT 24
Peak memory 200416 kb
Host smart-cc6ec2fc-8f20-49c5-b918-91ce869fa550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269773963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3269773963
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.3053773265
Short name T548
Test name
Test status
Simulation time 28298138073 ps
CPU time 407.43 seconds
Started Jun 09 01:46:13 PM PDT 24
Finished Jun 09 01:53:01 PM PDT 24
Peak memory 448104 kb
Host smart-a0048417-e220-41de-bf7f-b03d57ed06cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053773265 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3053773265
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.1949537957
Short name T252
Test name
Test status
Simulation time 143036903 ps
CPU time 1.4 seconds
Started Jun 09 01:46:13 PM PDT 24
Finished Jun 09 01:46:15 PM PDT 24
Peak memory 200472 kb
Host smart-ccb62a4a-e2e5-4d5d-b46e-b83fd322c9da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949537957 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.1949537957
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.3536174692
Short name T195
Test name
Test status
Simulation time 27715725129 ps
CPU time 440.8 seconds
Started Jun 09 01:46:11 PM PDT 24
Finished Jun 09 01:53:32 PM PDT 24
Peak memory 200488 kb
Host smart-20ce2cf0-2627-433c-ac16-65e37b0277d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536174692 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.3536174692
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_alert_test.2117868397
Short name T172
Test name
Test status
Simulation time 15045167 ps
CPU time 0.58 seconds
Started Jun 09 01:46:24 PM PDT 24
Finished Jun 09 01:46:25 PM PDT 24
Peak memory 196388 kb
Host smart-9f000b34-9484-4af5-897d-7253f1b66adb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117868397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2117868397
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3729607763
Short name T239
Test name
Test status
Simulation time 2647189198 ps
CPU time 33.34 seconds
Started Jun 09 01:46:17 PM PDT 24
Finished Jun 09 01:46:51 PM PDT 24
Peak memory 210860 kb
Host smart-877db8a1-f321-4a2b-a851-4f5aa5f59e58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3729607763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3729607763
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.908394345
Short name T349
Test name
Test status
Simulation time 343422063 ps
CPU time 5.68 seconds
Started Jun 09 01:46:15 PM PDT 24
Finished Jun 09 01:46:21 PM PDT 24
Peak memory 200456 kb
Host smart-94551b87-d90c-4235-9343-23635de11f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908394345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.908394345
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2546209068
Short name T119
Test name
Test status
Simulation time 8841504585 ps
CPU time 619.28 seconds
Started Jun 09 01:46:19 PM PDT 24
Finished Jun 09 01:56:38 PM PDT 24
Peak memory 746228 kb
Host smart-f4dbc3b3-b83b-4c47-aeea-fc93acfd3ae1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2546209068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2546209068
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.105353151
Short name T197
Test name
Test status
Simulation time 55196379757 ps
CPU time 62.82 seconds
Started Jun 09 01:46:16 PM PDT 24
Finished Jun 09 01:47:19 PM PDT 24
Peak memory 200528 kb
Host smart-42f789d3-8a64-4b21-9a7b-2797654f15c1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105353151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.105353151
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1451219588
Short name T581
Test name
Test status
Simulation time 4081974625 ps
CPU time 63.34 seconds
Started Jun 09 01:46:16 PM PDT 24
Finished Jun 09 01:47:20 PM PDT 24
Peak memory 200484 kb
Host smart-6af9e8f2-c577-40b1-b71b-7cd6c17ee8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451219588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1451219588
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.2770890058
Short name T8
Test name
Test status
Simulation time 2993571589 ps
CPU time 16.4 seconds
Started Jun 09 01:46:11 PM PDT 24
Finished Jun 09 01:46:27 PM PDT 24
Peak memory 200508 kb
Host smart-c25c34f2-cca9-4433-9eae-d28ca0268917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770890058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2770890058
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3445375862
Short name T40
Test name
Test status
Simulation time 227507048017 ps
CPU time 5862.87 seconds
Started Jun 09 01:46:16 PM PDT 24
Finished Jun 09 03:24:00 PM PDT 24
Peak memory 898664 kb
Host smart-6b8b7021-1f81-4b60-bd5f-1a6a01282f78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445375862 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3445375862
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.1907781025
Short name T528
Test name
Test status
Simulation time 110095724 ps
CPU time 1.36 seconds
Started Jun 09 01:46:19 PM PDT 24
Finished Jun 09 01:46:21 PM PDT 24
Peak memory 200408 kb
Host smart-28d78a8c-d7fc-427a-8eb8-8cf3ec5cf443
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907781025 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.1907781025
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.2681121055
Short name T64
Test name
Test status
Simulation time 59238755157 ps
CPU time 455.1 seconds
Started Jun 09 01:46:19 PM PDT 24
Finished Jun 09 01:53:55 PM PDT 24
Peak memory 200500 kb
Host smart-9c71a287-ff04-4254-a590-3ec67943cb5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681121055 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.2681121055
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.3191953884
Short name T499
Test name
Test status
Simulation time 2941503181 ps
CPU time 14.51 seconds
Started Jun 09 01:46:17 PM PDT 24
Finished Jun 09 01:46:32 PM PDT 24
Peak memory 200732 kb
Host smart-0e6dfbd3-2b5e-4852-bfdb-d688210fc1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191953884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.3191953884
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1536829181
Short name T129
Test name
Test status
Simulation time 28315709 ps
CPU time 0.57 seconds
Started Jun 09 01:46:25 PM PDT 24
Finished Jun 09 01:46:25 PM PDT 24
Peak memory 195376 kb
Host smart-0be0c021-461e-4175-a664-301ded7ea659
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536829181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1536829181
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.126458812
Short name T444
Test name
Test status
Simulation time 839111409 ps
CPU time 47.51 seconds
Started Jun 09 01:46:24 PM PDT 24
Finished Jun 09 01:47:12 PM PDT 24
Peak memory 227748 kb
Host smart-b7bdef99-6f77-492b-9fa1-96e87b120dbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=126458812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.126458812
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3101858532
Short name T504
Test name
Test status
Simulation time 3242556841 ps
CPU time 14.61 seconds
Started Jun 09 01:46:21 PM PDT 24
Finished Jun 09 01:46:36 PM PDT 24
Peak memory 200576 kb
Host smart-6d1b9026-1a10-45ac-a901-e390c999169d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101858532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3101858532
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3210838137
Short name T342
Test name
Test status
Simulation time 25646258348 ps
CPU time 1241.88 seconds
Started Jun 09 01:46:32 PM PDT 24
Finished Jun 09 02:07:14 PM PDT 24
Peak memory 755004 kb
Host smart-fa9e1494-0a6b-4b14-abaa-d1eb531e6aca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3210838137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3210838137
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2445502338
Short name T217
Test name
Test status
Simulation time 4463682649 ps
CPU time 62.45 seconds
Started Jun 09 01:46:22 PM PDT 24
Finished Jun 09 01:47:25 PM PDT 24
Peak memory 200424 kb
Host smart-afeddf2d-1a69-4235-9575-b8c3fb3622f3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445502338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2445502338
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.4235040806
Short name T209
Test name
Test status
Simulation time 3009507224 ps
CPU time 43.68 seconds
Started Jun 09 01:46:28 PM PDT 24
Finished Jun 09 01:47:12 PM PDT 24
Peak memory 200492 kb
Host smart-b6ddc1e4-f037-42d3-8cac-61337f52d588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235040806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.4235040806
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1104451896
Short name T424
Test name
Test status
Simulation time 11315919466 ps
CPU time 34.7 seconds
Started Jun 09 01:46:21 PM PDT 24
Finished Jun 09 01:46:56 PM PDT 24
Peak memory 200680 kb
Host smart-e0ff58e1-972a-4bd1-9ef5-2578d7c33bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104451896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1104451896
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.4055150737
Short name T510
Test name
Test status
Simulation time 165319875628 ps
CPU time 2273.8 seconds
Started Jun 09 01:46:22 PM PDT 24
Finished Jun 09 02:24:16 PM PDT 24
Peak memory 200496 kb
Host smart-d16210bd-32ce-4fa7-b1d4-1d114eb23726
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055150737 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.4055150737
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.1008673997
Short name T576
Test name
Test status
Simulation time 56481084 ps
CPU time 1.15 seconds
Started Jun 09 01:46:27 PM PDT 24
Finished Jun 09 01:46:29 PM PDT 24
Peak memory 200248 kb
Host smart-b7534e62-976d-412f-b758-111e77c88d57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008673997 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.1008673997
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.1465142579
Short name T518
Test name
Test status
Simulation time 7606030595 ps
CPU time 451.8 seconds
Started Jun 09 01:46:33 PM PDT 24
Finished Jun 09 01:54:05 PM PDT 24
Peak memory 200456 kb
Host smart-91e7f6b5-856d-47ea-86f9-5f04347507d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465142579 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.1465142579
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3246171923
Short name T277
Test name
Test status
Simulation time 29565408 ps
CPU time 0.98 seconds
Started Jun 09 01:46:28 PM PDT 24
Finished Jun 09 01:46:29 PM PDT 24
Peak memory 198288 kb
Host smart-01312bc5-0250-44ce-b576-ee35b8ee784c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246171923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3246171923
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.55983479
Short name T299
Test name
Test status
Simulation time 17247182 ps
CPU time 0.6 seconds
Started Jun 09 01:46:34 PM PDT 24
Finished Jun 09 01:46:35 PM PDT 24
Peak memory 196420 kb
Host smart-38eae8a7-f38c-402d-832d-1e714ad14dc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55983479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.55983479
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.4256023872
Short name T516
Test name
Test status
Simulation time 839975595 ps
CPU time 49.75 seconds
Started Jun 09 01:46:24 PM PDT 24
Finished Jun 09 01:47:14 PM PDT 24
Peak memory 222936 kb
Host smart-1a3193f5-7935-4bf2-b183-24105b6dacb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4256023872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.4256023872
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2183071398
Short name T316
Test name
Test status
Simulation time 1237756085 ps
CPU time 19.36 seconds
Started Jun 09 01:46:27 PM PDT 24
Finished Jun 09 01:46:47 PM PDT 24
Peak memory 200428 kb
Host smart-ccb762e5-7466-4498-843e-eb7a7a6e0443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183071398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2183071398
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1935516033
Short name T70
Test name
Test status
Simulation time 3764021573 ps
CPU time 73.09 seconds
Started Jun 09 01:46:30 PM PDT 24
Finished Jun 09 01:47:43 PM PDT 24
Peak memory 336328 kb
Host smart-cd1d72c5-9e52-48da-a3df-cae9eb15d76f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1935516033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1935516033
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.736052907
Short name T148
Test name
Test status
Simulation time 35270606504 ps
CPU time 109.74 seconds
Started Jun 09 01:46:26 PM PDT 24
Finished Jun 09 01:48:16 PM PDT 24
Peak memory 200500 kb
Host smart-68d2f06d-0827-4e3d-80fc-8c57f2130b50
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736052907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.736052907
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1846503109
Short name T339
Test name
Test status
Simulation time 779089020 ps
CPU time 46.19 seconds
Started Jun 09 01:46:22 PM PDT 24
Finished Jun 09 01:47:09 PM PDT 24
Peak memory 200436 kb
Host smart-08cdc818-b969-44b8-961d-2bf36616701f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846503109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1846503109
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3359489431
Short name T53
Test name
Test status
Simulation time 236956464 ps
CPU time 2.11 seconds
Started Jun 09 01:46:20 PM PDT 24
Finished Jun 09 01:46:22 PM PDT 24
Peak memory 200444 kb
Host smart-7835b394-1c2d-4447-8526-fb54c717be67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359489431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3359489431
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2177505155
Short name T391
Test name
Test status
Simulation time 180097402476 ps
CPU time 1775.07 seconds
Started Jun 09 01:46:28 PM PDT 24
Finished Jun 09 02:16:04 PM PDT 24
Peak memory 820812 kb
Host smart-36b48bcd-74f3-44f9-88f9-f5e8429e6387
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177505155 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2177505155
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.1492891315
Short name T253
Test name
Test status
Simulation time 61469302 ps
CPU time 1.43 seconds
Started Jun 09 01:46:27 PM PDT 24
Finished Jun 09 01:46:29 PM PDT 24
Peak memory 200448 kb
Host smart-0a28b596-666c-4ca2-907c-6f375521aa21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492891315 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.1492891315
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.2183653155
Short name T374
Test name
Test status
Simulation time 27312531470 ps
CPU time 385.56 seconds
Started Jun 09 01:46:29 PM PDT 24
Finished Jun 09 01:52:55 PM PDT 24
Peak memory 200424 kb
Host smart-5d29d94a-080b-4b13-a4aa-16a29c9d2283
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183653155 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.2183653155
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3267944606
Short name T440
Test name
Test status
Simulation time 7374136305 ps
CPU time 72.57 seconds
Started Jun 09 01:46:25 PM PDT 24
Finished Jun 09 01:47:38 PM PDT 24
Peak memory 200496 kb
Host smart-32da9815-5317-40eb-819f-d83cd2d16532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267944606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3267944606
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.4199763255
Short name T473
Test name
Test status
Simulation time 25174563 ps
CPU time 0.59 seconds
Started Jun 09 01:46:31 PM PDT 24
Finished Jun 09 01:46:32 PM PDT 24
Peak memory 196408 kb
Host smart-28da7637-306f-4f88-a4cf-a6e92d117d21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199763255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.4199763255
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.704521035
Short name T302
Test name
Test status
Simulation time 93206538 ps
CPU time 2.88 seconds
Started Jun 09 01:46:30 PM PDT 24
Finished Jun 09 01:46:33 PM PDT 24
Peak memory 200312 kb
Host smart-abcfb5d6-2f15-4ccf-bf28-7c4a34098485
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=704521035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.704521035
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2518625210
Short name T497
Test name
Test status
Simulation time 1238524461 ps
CPU time 13.67 seconds
Started Jun 09 01:46:29 PM PDT 24
Finished Jun 09 01:46:43 PM PDT 24
Peak memory 200420 kb
Host smart-19dbe0fc-426e-47c7-a1b3-4d2ef73b7d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518625210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2518625210
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1517112382
Short name T382
Test name
Test status
Simulation time 1375771904 ps
CPU time 335.08 seconds
Started Jun 09 01:46:25 PM PDT 24
Finished Jun 09 01:52:00 PM PDT 24
Peak memory 654136 kb
Host smart-3d94c523-a9cb-47e1-af0f-1fa7541d32ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1517112382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1517112382
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.754171421
Short name T162
Test name
Test status
Simulation time 2000564070 ps
CPU time 30.16 seconds
Started Jun 09 01:46:34 PM PDT 24
Finished Jun 09 01:47:04 PM PDT 24
Peak memory 200392 kb
Host smart-2be8f9cb-d25e-411b-92a9-f15a846eddc7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754171421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.754171421
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3107453294
Short name T534
Test name
Test status
Simulation time 1149535847 ps
CPU time 22.2 seconds
Started Jun 09 01:46:30 PM PDT 24
Finished Jun 09 01:46:52 PM PDT 24
Peak memory 200404 kb
Host smart-ab43d236-0311-400f-9f60-dea02295aa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107453294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3107453294
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1734430486
Short name T200
Test name
Test status
Simulation time 389855897 ps
CPU time 4.75 seconds
Started Jun 09 01:46:28 PM PDT 24
Finished Jun 09 01:46:34 PM PDT 24
Peak memory 200404 kb
Host smart-6903978c-652e-4e47-9dea-d86761b70db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734430486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1734430486
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2676906803
Short name T408
Test name
Test status
Simulation time 72753623204 ps
CPU time 2588.78 seconds
Started Jun 09 01:46:31 PM PDT 24
Finished Jun 09 02:29:41 PM PDT 24
Peak memory 767292 kb
Host smart-5feffaf8-ea0d-4738-9e6d-7817d61045e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676906803 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2676906803
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_stress_all_with_rand_reset.3125563088
Short name T16
Test name
Test status
Simulation time 55999457551 ps
CPU time 954.8 seconds
Started Jun 09 01:46:30 PM PDT 24
Finished Jun 09 02:02:26 PM PDT 24
Peak memory 660352 kb
Host smart-c343d3d8-845d-49f0-b5de-9fdbc62a1b7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3125563088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all_with_rand_reset.3125563088
Directory /workspace/49.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.365404730
Short name T326
Test name
Test status
Simulation time 31276887 ps
CPU time 1.02 seconds
Started Jun 09 01:46:32 PM PDT 24
Finished Jun 09 01:46:33 PM PDT 24
Peak memory 200212 kb
Host smart-21d27ee0-b342-4533-a62a-4153cf803559
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365404730 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_hmac_vectors.365404730
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.2209139945
Short name T572
Test name
Test status
Simulation time 80356885853 ps
CPU time 507.54 seconds
Started Jun 09 01:46:32 PM PDT 24
Finished Jun 09 01:55:00 PM PDT 24
Peak memory 200480 kb
Host smart-15e0ae00-080f-479e-bd99-bd9bfc17047a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209139945 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.2209139945
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1660909531
Short name T546
Test name
Test status
Simulation time 16394151487 ps
CPU time 76.99 seconds
Started Jun 09 01:46:33 PM PDT 24
Finished Jun 09 01:47:50 PM PDT 24
Peak memory 200476 kb
Host smart-14294a2d-2c3f-4dac-84df-7e685493de72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660909531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1660909531
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.118408036
Short name T347
Test name
Test status
Simulation time 18118314 ps
CPU time 0.6 seconds
Started Jun 09 01:43:51 PM PDT 24
Finished Jun 09 01:43:52 PM PDT 24
Peak memory 197136 kb
Host smart-fffe143d-1ce4-4303-949d-2abfa192927e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118408036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.118408036
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2945189429
Short name T433
Test name
Test status
Simulation time 4129388256 ps
CPU time 54.14 seconds
Started Jun 09 01:43:46 PM PDT 24
Finished Jun 09 01:44:41 PM PDT 24
Peak memory 233016 kb
Host smart-a6709e34-22aa-4949-ada3-06c1cef31c23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2945189429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2945189429
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2722452858
Short name T578
Test name
Test status
Simulation time 348781112 ps
CPU time 8.66 seconds
Started Jun 09 01:43:46 PM PDT 24
Finished Jun 09 01:43:56 PM PDT 24
Peak memory 200444 kb
Host smart-c546f450-aef4-45a1-8643-b8c57a5cdbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722452858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2722452858
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1378894604
Short name T392
Test name
Test status
Simulation time 7449426526 ps
CPU time 922.3 seconds
Started Jun 09 01:43:48 PM PDT 24
Finished Jun 09 01:59:12 PM PDT 24
Peak memory 718856 kb
Host smart-aa8bdaf1-26ff-481f-ab82-119e1c407cd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1378894604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1378894604
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3832694580
Short name T454
Test name
Test status
Simulation time 8875065499 ps
CPU time 116.39 seconds
Started Jun 09 01:43:48 PM PDT 24
Finished Jun 09 01:45:45 PM PDT 24
Peak memory 200484 kb
Host smart-d8de5c73-e993-440d-af02-e4f879e60d1d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832694580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3832694580
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.885124833
Short name T381
Test name
Test status
Simulation time 6295520552 ps
CPU time 90.32 seconds
Started Jun 09 01:43:50 PM PDT 24
Finished Jun 09 01:45:20 PM PDT 24
Peak memory 200516 kb
Host smart-81835933-493c-40fb-9cb3-d6af242900f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885124833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.885124833
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.384277942
Short name T469
Test name
Test status
Simulation time 682924922 ps
CPU time 6.5 seconds
Started Jun 09 01:43:47 PM PDT 24
Finished Jun 09 01:43:55 PM PDT 24
Peak memory 200464 kb
Host smart-e72e9335-8f13-455c-9384-c76d0b061665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384277942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.384277942
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3384104478
Short name T468
Test name
Test status
Simulation time 28287652293 ps
CPU time 2342.34 seconds
Started Jun 09 01:44:01 PM PDT 24
Finished Jun 09 02:23:04 PM PDT 24
Peak memory 813376 kb
Host smart-942ac326-6a26-4e60-becb-20bcbeef6d57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384104478 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3384104478
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.2691113160
Short name T555
Test name
Test status
Simulation time 301609991 ps
CPU time 1.28 seconds
Started Jun 09 01:43:52 PM PDT 24
Finished Jun 09 01:43:54 PM PDT 24
Peak memory 200372 kb
Host smart-308098e0-9078-4f33-a9f8-ee973fad9883
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691113160 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.2691113160
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.2307976861
Short name T199
Test name
Test status
Simulation time 29085114696 ps
CPU time 552.57 seconds
Started Jun 09 01:43:51 PM PDT 24
Finished Jun 09 01:53:04 PM PDT 24
Peak memory 200416 kb
Host smart-302d52f1-0965-4607-8c08-de8f53a680ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307976861 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.2307976861
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.684075681
Short name T242
Test name
Test status
Simulation time 18334030516 ps
CPU time 89.6 seconds
Started Jun 09 01:43:53 PM PDT 24
Finished Jun 09 01:45:22 PM PDT 24
Peak memory 200492 kb
Host smart-4c726bfa-8c8f-4e0f-93dc-8854a45729de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684075681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.684075681
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2100634970
Short name T281
Test name
Test status
Simulation time 12062468 ps
CPU time 0.6 seconds
Started Jun 09 01:43:56 PM PDT 24
Finished Jun 09 01:43:56 PM PDT 24
Peak memory 196428 kb
Host smart-49fcf840-87b3-48ff-b37f-992c1ce3095f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100634970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2100634970
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.511811460
Short name T460
Test name
Test status
Simulation time 721864370 ps
CPU time 19.31 seconds
Started Jun 09 01:43:53 PM PDT 24
Finished Jun 09 01:44:13 PM PDT 24
Peak memory 218888 kb
Host smart-c283f5cf-08c9-4bfe-90ab-7ce6fca0585f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=511811460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.511811460
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.2757001189
Short name T309
Test name
Test status
Simulation time 7277196120 ps
CPU time 46.38 seconds
Started Jun 09 01:43:52 PM PDT 24
Finished Jun 09 01:44:39 PM PDT 24
Peak memory 200488 kb
Host smart-08d4d6e3-225d-4a01-9bf7-c1e505f59d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757001189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2757001189
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.4188908586
Short name T71
Test name
Test status
Simulation time 4764762705 ps
CPU time 552.14 seconds
Started Jun 09 01:43:52 PM PDT 24
Finished Jun 09 01:53:04 PM PDT 24
Peak memory 666296 kb
Host smart-44bce0d0-3e76-4d7c-afb2-a7c9ed909d19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4188908586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.4188908586
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1958972470
Short name T346
Test name
Test status
Simulation time 2200583014 ps
CPU time 60.66 seconds
Started Jun 09 01:43:54 PM PDT 24
Finished Jun 09 01:44:55 PM PDT 24
Peak memory 200436 kb
Host smart-5c03ef62-e2d7-42f3-89c1-756211bf87f9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958972470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1958972470
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.767535853
Short name T248
Test name
Test status
Simulation time 10844733091 ps
CPU time 57.24 seconds
Started Jun 09 01:43:52 PM PDT 24
Finished Jun 09 01:44:50 PM PDT 24
Peak memory 200524 kb
Host smart-de160a5a-0dc4-4e66-8770-12ac92f70b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767535853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.767535853
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.134234127
Short name T540
Test name
Test status
Simulation time 1085998112 ps
CPU time 6.1 seconds
Started Jun 09 01:43:55 PM PDT 24
Finished Jun 09 01:44:01 PM PDT 24
Peak memory 200416 kb
Host smart-19115477-7e91-469b-9482-c96500743b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134234127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.134234127
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.743576824
Short name T421
Test name
Test status
Simulation time 4143042023 ps
CPU time 38.34 seconds
Started Jun 09 01:43:50 PM PDT 24
Finished Jun 09 01:44:29 PM PDT 24
Peak memory 200552 kb
Host smart-d493de0b-b12b-4f6a-b22e-3811f739afad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743576824 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.743576824
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.3459786880
Short name T341
Test name
Test status
Simulation time 70174710 ps
CPU time 1.31 seconds
Started Jun 09 01:43:51 PM PDT 24
Finished Jun 09 01:43:53 PM PDT 24
Peak memory 200512 kb
Host smart-4d45eb8e-ce48-4c84-bbc0-866bc5993bee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459786880 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.3459786880
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.1163983405
Short name T415
Test name
Test status
Simulation time 53936440540 ps
CPU time 487.6 seconds
Started Jun 09 01:43:52 PM PDT 24
Finished Jun 09 01:52:00 PM PDT 24
Peak memory 200484 kb
Host smart-79de857b-dc5b-4324-b176-8d29dc8a529f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163983405 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.1163983405
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1911187859
Short name T371
Test name
Test status
Simulation time 7217101670 ps
CPU time 37.96 seconds
Started Jun 09 01:43:53 PM PDT 24
Finished Jun 09 01:44:32 PM PDT 24
Peak memory 200488 kb
Host smart-ee1a0502-0447-4180-ba07-04b20a045ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911187859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1911187859
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2621500522
Short name T135
Test name
Test status
Simulation time 16975641 ps
CPU time 0.62 seconds
Started Jun 09 01:43:58 PM PDT 24
Finished Jun 09 01:43:59 PM PDT 24
Peak memory 196400 kb
Host smart-e026cde5-3e2d-4730-b2c3-956d618803c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621500522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2621500522
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.824376223
Short name T368
Test name
Test status
Simulation time 5313524715 ps
CPU time 59.83 seconds
Started Jun 09 01:43:55 PM PDT 24
Finished Jun 09 01:44:55 PM PDT 24
Peak memory 225100 kb
Host smart-52390c8e-140c-44c0-b675-ddf6053eb272
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=824376223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.824376223
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1358094148
Short name T512
Test name
Test status
Simulation time 1046794799 ps
CPU time 15.43 seconds
Started Jun 09 01:43:52 PM PDT 24
Finished Jun 09 01:44:08 PM PDT 24
Peak memory 200396 kb
Host smart-2cd17617-2094-43d3-a554-1d1e038378de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358094148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1358094148
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1470491376
Short name T290
Test name
Test status
Simulation time 2605212082 ps
CPU time 595.96 seconds
Started Jun 09 01:43:52 PM PDT 24
Finished Jun 09 01:53:48 PM PDT 24
Peak memory 700036 kb
Host smart-846f8e2c-628b-4683-a241-577ca53c1d48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1470491376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1470491376
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.4139398073
Short name T563
Test name
Test status
Simulation time 20735763948 ps
CPU time 140.8 seconds
Started Jun 09 01:43:53 PM PDT 24
Finished Jun 09 01:46:14 PM PDT 24
Peak memory 200464 kb
Host smart-25e016a9-9db9-4a47-badb-bc8d8a73ceb1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139398073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.4139398073
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.850472318
Short name T537
Test name
Test status
Simulation time 1096814201 ps
CPU time 64.61 seconds
Started Jun 09 01:43:52 PM PDT 24
Finished Jun 09 01:44:57 PM PDT 24
Peak memory 200440 kb
Host smart-db5d04d4-6d78-4cf7-8ee2-7e4719265ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850472318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.850472318
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1894503899
Short name T155
Test name
Test status
Simulation time 1281712521 ps
CPU time 5.1 seconds
Started Jun 09 01:43:51 PM PDT 24
Finished Jun 09 01:43:56 PM PDT 24
Peak memory 200436 kb
Host smart-461ecf5c-6645-4f53-8aad-a0a85f144368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894503899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1894503899
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1359446791
Short name T33
Test name
Test status
Simulation time 14251982731 ps
CPU time 706.48 seconds
Started Jun 09 01:43:55 PM PDT 24
Finished Jun 09 01:55:41 PM PDT 24
Peak memory 227088 kb
Host smart-ce7767a7-9024-4d65-a8dc-248a67568a42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359446791 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1359446791
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.1467442395
Short name T305
Test name
Test status
Simulation time 61436128 ps
CPU time 1.42 seconds
Started Jun 09 01:43:50 PM PDT 24
Finished Jun 09 01:43:52 PM PDT 24
Peak memory 200496 kb
Host smart-a9e4caa6-5735-4549-acad-cc58dbca7f0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467442395 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.1467442395
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.3276175641
Short name T458
Test name
Test status
Simulation time 432651555327 ps
CPU time 534.14 seconds
Started Jun 09 01:43:52 PM PDT 24
Finished Jun 09 01:52:47 PM PDT 24
Peak memory 200452 kb
Host smart-188f6c7b-2ab5-419d-b9f2-c689a2c2ddcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276175641 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.3276175641
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.82873800
Short name T379
Test name
Test status
Simulation time 1513001323 ps
CPU time 30.28 seconds
Started Jun 09 01:43:54 PM PDT 24
Finished Jun 09 01:44:24 PM PDT 24
Peak memory 200448 kb
Host smart-5718c0ad-19b3-4330-92f6-b1e11fc3ce0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82873800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.82873800
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/75.hmac_stress_all_with_rand_reset.2960666099
Short name T17
Test name
Test status
Simulation time 23900457924 ps
CPU time 358.04 seconds
Started Jun 09 01:46:44 PM PDT 24
Finished Jun 09 01:52:43 PM PDT 24
Peak memory 216096 kb
Host smart-c0253bff-18c1-4cc6-9a47-00dbc388013d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2960666099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.hmac_stress_all_with_rand_reset.2960666099
Directory /workspace/75.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.hmac_stress_all_with_rand_reset.2115160725
Short name T46
Test name
Test status
Simulation time 57223374028 ps
CPU time 2344.59 seconds
Started Jun 09 01:46:48 PM PDT 24
Finished Jun 09 02:25:53 PM PDT 24
Peak memory 831992 kb
Host smart-441f5cc7-f97d-4b37-90eb-760b086fd588
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2115160725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.hmac_stress_all_with_rand_reset.2115160725
Directory /workspace/79.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2422886678
Short name T517
Test name
Test status
Simulation time 40630761 ps
CPU time 0.6 seconds
Started Jun 09 01:43:59 PM PDT 24
Finished Jun 09 01:44:00 PM PDT 24
Peak memory 195380 kb
Host smart-4b2c8224-826a-4bf9-88af-aee12acad9ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422886678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2422886678
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.875657949
Short name T357
Test name
Test status
Simulation time 621829711 ps
CPU time 31.91 seconds
Started Jun 09 01:43:56 PM PDT 24
Finished Jun 09 01:44:29 PM PDT 24
Peak memory 208560 kb
Host smart-ecc117b6-31bb-4681-a505-70805ddaa125
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=875657949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.875657949
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2731906048
Short name T520
Test name
Test status
Simulation time 830484617 ps
CPU time 9.44 seconds
Started Jun 09 01:43:56 PM PDT 24
Finished Jun 09 01:44:06 PM PDT 24
Peak memory 200464 kb
Host smart-77264c99-11a7-4340-8572-f0db4985e322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731906048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2731906048
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.932570666
Short name T237
Test name
Test status
Simulation time 4758759552 ps
CPU time 1219.94 seconds
Started Jun 09 01:43:55 PM PDT 24
Finished Jun 09 02:04:16 PM PDT 24
Peak memory 765332 kb
Host smart-e2330532-0465-4c44-9d42-2f626d6f5337
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=932570666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.932570666
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3473655122
Short name T171
Test name
Test status
Simulation time 90336179688 ps
CPU time 166.71 seconds
Started Jun 09 01:44:01 PM PDT 24
Finished Jun 09 01:46:48 PM PDT 24
Peak memory 200428 kb
Host smart-92d71c23-0f9c-4540-9522-3996aaaa30d9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473655122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3473655122
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.2490970685
Short name T265
Test name
Test status
Simulation time 3338396185 ps
CPU time 47.43 seconds
Started Jun 09 01:43:56 PM PDT 24
Finished Jun 09 01:44:43 PM PDT 24
Peak memory 200476 kb
Host smart-7c40f354-44f3-49cf-8ca4-f281ad274617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490970685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2490970685
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3816967395
Short name T405
Test name
Test status
Simulation time 1634320028 ps
CPU time 11.34 seconds
Started Jun 09 01:43:54 PM PDT 24
Finished Jun 09 01:44:06 PM PDT 24
Peak memory 200436 kb
Host smart-a19b2bbc-ef10-4524-b0e9-3c7ad07c3a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816967395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3816967395
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2698581164
Short name T73
Test name
Test status
Simulation time 36127182747 ps
CPU time 130.71 seconds
Started Jun 09 01:43:57 PM PDT 24
Finished Jun 09 01:46:08 PM PDT 24
Peak memory 200500 kb
Host smart-734644ea-c635-485b-a2f0-d43ecd750c40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698581164 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2698581164
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.1231629069
Short name T257
Test name
Test status
Simulation time 238540873 ps
CPU time 1.42 seconds
Started Jun 09 01:43:57 PM PDT 24
Finished Jun 09 01:43:59 PM PDT 24
Peak memory 200404 kb
Host smart-41fd5255-047d-4831-82fd-4ce996ca95d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231629069 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.1231629069
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.350594609
Short name T530
Test name
Test status
Simulation time 12336714169 ps
CPU time 435.09 seconds
Started Jun 09 01:43:57 PM PDT 24
Finished Jun 09 01:51:12 PM PDT 24
Peak memory 200392 kb
Host smart-48f78e4a-8736-478d-af16-19087676df06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350594609 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.350594609
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.3231154729
Short name T327
Test name
Test status
Simulation time 5623789998 ps
CPU time 45.11 seconds
Started Jun 09 01:43:58 PM PDT 24
Finished Jun 09 01:44:43 PM PDT 24
Peak memory 200480 kb
Host smart-9b0e709e-3600-4320-b5c3-ce1b2a2635d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231154729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3231154729
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.4066236504
Short name T582
Test name
Test status
Simulation time 32364244 ps
CPU time 0.57 seconds
Started Jun 09 01:43:58 PM PDT 24
Finished Jun 09 01:43:59 PM PDT 24
Peak memory 196096 kb
Host smart-7fb9c104-57da-45fe-933e-e083d65784c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066236504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.4066236504
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.800361481
Short name T575
Test name
Test status
Simulation time 175172743 ps
CPU time 4.35 seconds
Started Jun 09 01:43:58 PM PDT 24
Finished Jun 09 01:44:03 PM PDT 24
Peak memory 200412 kb
Host smart-f99d52f8-0e9d-4a3c-bb90-8d9960b6bd50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=800361481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.800361481
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.4280077555
Short name T166
Test name
Test status
Simulation time 7971661065 ps
CPU time 24.04 seconds
Started Jun 09 01:43:56 PM PDT 24
Finished Jun 09 01:44:20 PM PDT 24
Peak memory 200504 kb
Host smart-ca7ee369-cdc3-4c79-a207-f64bf374e995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280077555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.4280077555
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2098530683
Short name T196
Test name
Test status
Simulation time 393754265 ps
CPU time 113.59 seconds
Started Jun 09 01:43:58 PM PDT 24
Finished Jun 09 01:45:51 PM PDT 24
Peak memory 618684 kb
Host smart-f9ae54dc-09cf-4c45-90f6-df7fcaf12e92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2098530683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2098530683
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3212561524
Short name T240
Test name
Test status
Simulation time 22791520887 ps
CPU time 23.81 seconds
Started Jun 09 01:44:03 PM PDT 24
Finished Jun 09 01:44:27 PM PDT 24
Peak memory 200448 kb
Host smart-9c9c8a53-95b3-4689-a0a2-5966a48305bb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212561524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3212561524
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3510149167
Short name T476
Test name
Test status
Simulation time 1486279854 ps
CPU time 21.96 seconds
Started Jun 09 01:44:00 PM PDT 24
Finished Jun 09 01:44:22 PM PDT 24
Peak memory 200476 kb
Host smart-0413ba34-07aa-4379-926c-aefec48099fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510149167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3510149167
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1899728766
Short name T354
Test name
Test status
Simulation time 105686263 ps
CPU time 3.77 seconds
Started Jun 09 01:43:59 PM PDT 24
Finished Jun 09 01:44:03 PM PDT 24
Peak memory 200440 kb
Host smart-6ef0e9e6-a935-4dc5-959f-298a3e074b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899728766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1899728766
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1572796998
Short name T36
Test name
Test status
Simulation time 33066928279 ps
CPU time 2205.66 seconds
Started Jun 09 01:44:02 PM PDT 24
Finished Jun 09 02:20:48 PM PDT 24
Peak memory 828060 kb
Host smart-7d5a577a-e1bb-4e59-ac45-c3efc2023196
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572796998 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1572796998
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.2640920780
Short name T509
Test name
Test status
Simulation time 98120084 ps
CPU time 1.18 seconds
Started Jun 09 01:43:59 PM PDT 24
Finished Jun 09 01:44:00 PM PDT 24
Peak memory 200472 kb
Host smart-962ee72a-d57e-42be-ac57-efc3e032aa68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640920780 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.2640920780
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.205205016
Short name T185
Test name
Test status
Simulation time 121009470192 ps
CPU time 491.06 seconds
Started Jun 09 01:43:54 PM PDT 24
Finished Jun 09 01:52:06 PM PDT 24
Peak memory 200436 kb
Host smart-9466a0ad-fbb0-4e69-8561-870b44d20b06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205205016 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.205205016
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2643856374
Short name T411
Test name
Test status
Simulation time 22027810450 ps
CPU time 84.11 seconds
Started Jun 09 01:43:59 PM PDT 24
Finished Jun 09 01:45:23 PM PDT 24
Peak memory 200568 kb
Host smart-311e7e4c-8f98-4efe-a8b8-3b4d9c67563d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643856374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2643856374
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/97.hmac_stress_all_with_rand_reset.2799777350
Short name T15
Test name
Test status
Simulation time 52205677120 ps
CPU time 3694.71 seconds
Started Jun 09 01:47:04 PM PDT 24
Finished Jun 09 02:48:39 PM PDT 24
Peak memory 810220 kb
Host smart-2ef09679-bc28-4ac4-869a-4462f8df3f04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2799777350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.hmac_stress_all_with_rand_reset.2799777350
Directory /workspace/97.hmac_stress_all_with_rand_reset/latest
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