Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	12934506	1			T1	25248		T2	12568		T3	286522
all_values[1]	12934506	1			T1	25248		T2	12568		T3	286522
all_values[2]	12934506	1			T1	25248		T2	12568		T3	286522

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

175608

1

T3

2838

T11

2

T21

305

auto[1]

38627910

1

T1

75744

T2

37704

T3

856728

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32307137

1

T1

67560

T2

33524

T3

716578

auto[1]

6496381

1

T1

8184

T2

4180

T3

142988

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	60040	1			T3	2810		T15	2		T34	3
all_values[0]	auto[0]	auto[1]	365	1			T3	8		T15	5		T35	2
all_values[0]	auto[1]	auto[0]	12840864	1			T1	25212		T2	12558		T3	283098
all_values[0]	auto[1]	auto[1]	33237	1			T1	36		T2	10		T3	606
all_values[1]	auto[0]	auto[0]	60989	1			T3	3		T11	2		T10	6
all_values[1]	auto[0]	auto[1]	162	1			T3	1		T15	4		T10	5
all_values[1]	auto[1]	auto[0]	12873074	1			T1	25248		T2	12568		T3	286516
all_values[1]	auto[1]	auto[1]	281	1			T3	2		T15	3		T10	6
all_values[2]	auto[0]	auto[0]	28333	1			T3	16		T15	2		T35	3
all_values[2]	auto[0]	auto[1]	25719	1			T21	305		T15	4		T10	10
all_values[2]	auto[1]	auto[0]	6443837	1			T1	17100		T2	8398		T3	144135
all_values[2]	auto[1]	auto[1]	6436617	1			T1	8148		T2	4170		T3	142371