Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5984439

1

T1

6708

T2

4652

T3

132125

auto[1]

2319573

1

T1

17853

T2

7638

T3

47324

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2317047

1

T1

7192

T2

8082

T3

53869

auto[1]

5986965

1

T1

17369

T2

4208

T3

125580

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5069481

1

T3

86145

T4

4832

T5

22

auto[1]

3234531

1

T1

24561

T2

12290

T3

93304

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6661937	1			T1	16719		T2	8945		T3	173558
fifo_depth[1]	275126	1			T1	727		T2	286		T3	3555
fifo_depth[2]	216393	1			T1	727		T2	310		T3	1535
fifo_depth[3]	167356	1			T1	771		T2	301		T3	533
fifo_depth[4]	138331	1			T1	806		T2	285		T3	184
fifo_depth[5]	115388	1			T1	812		T2	340		T3	46
fifo_depth[6]	107747	1			T1	756		T2	331		T3	22
fifo_depth[7]	93083	1			T1	734		T2	292		T3	7

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1642075

1

T1

7842

T2

3345

T3

5891

auto[1]

6661937

1

T1

16719

T2

8945

T3

173558

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8293309

1

T1

24561

T2

12290

T3

179449

auto[1]

10703

1

T4

4

T5

3

T11

2

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

85011

1

T3

25

T4

414

T5

6

auto[0]

auto[0]

auto[0]

auto[1]

95938

1

T3

205

T4

321

T5

5

auto[0]

auto[0]

auto[1]

auto[0]

717588

1

T3

2088

T4

149

T5

4

auto[0]

auto[0]

auto[1]

auto[1]

101149

1

T3

136

T4

525

T5

1

auto[0]

auto[1]

auto[0]

auto[0]

164941

1

T1

361

T2

562

T3

691

auto[0]

auto[1]

auto[0]

auto[1]

160582

1

T1

1420

T2

1971

T3

905

auto[0]

auto[1]

auto[1]

auto[0]

169019

1

T1

1595

T2

495

T3

1330

auto[0]

auto[1]

auto[1]

auto[1]

147847

1

T1

4466

T2

317

T3

511

auto[1]

auto[0]

auto[0]

auto[0]

275385

1

T3

1671

T4

849

T5

3

auto[1]

auto[0]

auto[0]

auto[1]

273443

1

T3

5908

T4

689

T5

1

auto[1]

auto[0]

auto[1]

auto[0]

3266934

1

T3

73147

T4

115

T6

495

auto[1]

auto[0]

auto[1]

auto[1]

254033

1

T3

2965

T4

1770

T5

2

auto[1]

auto[1]

auto[0]

auto[0]

648248

1

T1

202

T2

649

T3

23989

auto[1]

auto[1]

auto[0]

auto[1]

613499

1

T1

5209

T2

4900

T3

20475

auto[1]

auto[1]

auto[1]

auto[0]

657313

1

T1

4550

T2

2946

T3

29184

auto[1]

auto[1]

auto[1]

auto[1]

673082

1

T1

6758

T2

450

T3

16219

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

359608

1

T3

1696

T4

1263

T5

8

auto[0]

auto[0]

auto[0]

auto[1]

367978

1

T3

6113

T4

1008

T5

5

auto[0]

auto[0]

auto[1]

auto[0]

3983384

1

T3

75235

T4

264

T5

4

auto[0]

auto[0]

auto[1]

auto[1]

351673

1

T3

3101

T4

2294

T5

3

auto[0]

auto[1]

auto[0]

auto[0]

812743

1

T1

563

T2

1211

T3

24680

auto[0]

auto[1]

auto[0]

auto[1]

772845

1

T1

6629

T2

6871

T3

21380

auto[0]

auto[1]

auto[1]

auto[0]

824763

1

T1

6145

T2

3441

T3

30514

auto[0]

auto[1]

auto[1]

auto[1]

820315

1

T1

11224

T2

767

T3

16730

auto[1]

auto[0]

auto[0]

auto[0]

788

1

T5

1

T35

1

T31

1

auto[1]

auto[0]

auto[0]

auto[1]

1403

1

T4

2

T5

1

T76

6

auto[1]

auto[0]

auto[1]

auto[0]

1138

1

T35

1

T31

1

T76

7

auto[1]

auto[0]

auto[1]

auto[1]

3509

1

T4

1

T76

75

T7

1

auto[1]

auto[1]

auto[0]

auto[0]

446

1

T11

1

T7

1

T89

5

auto[1]

auto[1]

auto[0]

auto[1]

1236

1

T4

1

T35

1

T104

1

auto[1]

auto[1]

auto[1]

auto[0]

1569

1

T31

1

T76

197

T7

2

auto[1]

auto[1]

auto[1]

auto[1]

614

1

T5

1

T11

1

T76

2

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	275385	1			T3	1671		T4	849		T5	3
fifo_depth[0]	auto[0]	auto[0]	auto[1]	273443	1			T3	5908		T4	689		T5	1
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3266934	1			T3	73147		T4	115		T6	495
fifo_depth[0]	auto[0]	auto[1]	auto[1]	254033	1			T3	2965		T4	1770		T5	2
fifo_depth[0]	auto[1]	auto[0]	auto[0]	648248	1			T1	202		T2	649		T3	23989
fifo_depth[0]	auto[1]	auto[0]	auto[1]	613499	1			T1	5209		T2	4900		T3	20475
fifo_depth[0]	auto[1]	auto[1]	auto[0]	657313	1			T1	4550		T2	2946		T3	29184
fifo_depth[0]	auto[1]	auto[1]	auto[1]	673082	1			T1	6758		T2	450		T3	16219
fifo_depth[1]	auto[0]	auto[0]	auto[0]	8767	1			T3	10		T4	45		T6	10
fifo_depth[1]	auto[0]	auto[0]	auto[1]	8791	1			T3	132		T4	42		T6	17
fifo_depth[1]	auto[0]	auto[1]	auto[0]	177966	1			T3	1546		T4	12		T6	27
fifo_depth[1]	auto[0]	auto[1]	auto[1]	8561	1			T3	62		T4	72		T6	107
fifo_depth[1]	auto[1]	auto[0]	auto[0]	18039	1			T1	34		T2	44		T3	353
fifo_depth[1]	auto[1]	auto[0]	auto[1]	17569	1			T1	113		T2	173		T3	475
fifo_depth[1]	auto[1]	auto[1]	auto[0]	18557	1			T1	144		T2	44		T3	710
fifo_depth[1]	auto[1]	auto[1]	auto[1]	16876	1			T1	436		T2	25		T3	267
fifo_depth[2]	auto[0]	auto[0]	auto[0]	7418	1			T3	10		T4	36		T6	9
fifo_depth[2]	auto[0]	auto[0]	auto[1]	7881	1			T3	44		T4	29		T6	7
fifo_depth[2]	auto[0]	auto[1]	auto[0]	129291	1			T3	400		T4	16		T6	12
fifo_depth[2]	auto[0]	auto[1]	auto[1]	7914	1			T3	40		T4	63		T6	86
fifo_depth[2]	auto[1]	auto[0]	auto[0]	16471	1			T1	36		T2	53		T3	214
fifo_depth[2]	auto[1]	auto[0]	auto[1]	16147	1			T1	129		T2	192		T3	283
fifo_depth[2]	auto[1]	auto[1]	auto[0]	16604	1			T1	173		T2	36		T3	396
fifo_depth[2]	auto[1]	auto[1]	auto[1]	14667	1			T1	389		T2	29		T3	148
fifo_depth[3]	auto[0]	auto[0]	auto[0]	5499	1			T3	4		T4	51		T6	3
fifo_depth[3]	auto[0]	auto[0]	auto[1]	6049	1			T3	20		T4	31		T6	5
fifo_depth[3]	auto[0]	auto[1]	auto[0]	95537	1			T3	105		T4	15		T6	12
fifo_depth[3]	auto[0]	auto[1]	auto[1]	6025	1			T3	11		T4	74		T6	61
fifo_depth[3]	auto[1]	auto[0]	auto[0]	14226	1			T1	36		T2	49		T3	75
fifo_depth[3]	auto[1]	auto[0]	auto[1]	13819	1			T1	117		T2	179		T3	91
fifo_depth[3]	auto[1]	auto[1]	auto[0]	13820	1			T1	174		T2	46		T3	163
fifo_depth[3]	auto[1]	auto[1]	auto[1]	12381	1			T1	444		T2	27		T3	64
fifo_depth[4]	auto[0]	auto[0]	auto[0]	5252	1			T3	1		T4	39		T21	1
fifo_depth[4]	auto[0]	auto[0]	auto[1]	6325	1			T3	7		T4	40		T21	95
fifo_depth[4]	auto[0]	auto[1]	auto[0]	69313	1			T3	29		T4	12		T6	4
fifo_depth[4]	auto[0]	auto[1]	auto[1]	6198	1			T3	8		T4	59		T6	25
fifo_depth[4]	auto[1]	auto[0]	auto[0]	13490	1			T1	45		T2	45		T3	31
fifo_depth[4]	auto[1]	auto[0]	auto[1]	12954	1			T1	138		T2	170		T3	43
fifo_depth[4]	auto[1]	auto[1]	auto[0]	12894	1			T1	198		T2	49		T3	46
fifo_depth[4]	auto[1]	auto[1]	auto[1]	11905	1			T1	425		T2	21		T3	19
fifo_depth[5]	auto[0]	auto[0]	auto[0]	4156	1			T4	42		T6	1		T21	2
fifo_depth[5]	auto[0]	auto[0]	auto[1]	4720	1			T3	1		T4	33		T21	105
fifo_depth[5]	auto[0]	auto[1]	auto[0]	54986	1			T3	7		T4	19		T6	1
fifo_depth[5]	auto[0]	auto[1]	auto[1]	4718	1			T3	7		T4	45		T6	13
fifo_depth[5]	auto[1]	auto[0]	auto[0]	12443	1			T1	42		T2	68		T3	6
fifo_depth[5]	auto[1]	auto[0]	auto[1]	12035	1			T1	146		T2	187		T3	8
fifo_depth[5]	auto[1]	auto[1]	auto[0]	11630	1			T1	191		T2	50		T3	9
fifo_depth[5]	auto[1]	auto[1]	auto[1]	10700	1			T1	433		T2	35		T3	8
fifo_depth[6]	auto[0]	auto[0]	auto[0]	4040	1			T4	43		T21	1		T10	4
fifo_depth[6]	auto[0]	auto[0]	auto[1]	5093	1			T4	28		T21	80		T10	8
fifo_depth[6]	auto[0]	auto[1]	auto[0]	47391	1			T4	14		T21	14		T10	3
fifo_depth[6]	auto[0]	auto[1]	auto[1]	5028	1			T3	3		T4	44		T6	3
fifo_depth[6]	auto[1]	auto[0]	auto[0]	12617	1			T1	34		T2	61		T3	9
fifo_depth[6]	auto[1]	auto[0]	auto[1]	11666	1			T1	124		T2	186		T3	4
fifo_depth[6]	auto[1]	auto[1]	auto[0]	11315	1			T1	159		T2	54		T3	4
fifo_depth[6]	auto[1]	auto[1]	auto[1]	10597	1			T1	439		T2	30		T3	2
fifo_depth[7]	auto[0]	auto[0]	auto[0]	3667	1			T4	38		T31	106		T17	2
fifo_depth[7]	auto[0]	auto[0]	auto[1]	4269	1			T4	36		T21	89		T31	153
fifo_depth[7]	auto[0]	auto[1]	auto[0]	37221	1			T3	1		T4	15		T21	12
fifo_depth[7]	auto[0]	auto[1]	auto[1]	4513	1			T3	2		T4	37		T6	4
fifo_depth[7]	auto[1]	auto[0]	auto[0]	11905	1			T1	35		T2	53		T4	9
fifo_depth[7]	auto[1]	auto[0]	auto[1]	11158	1			T1	122		T2	166		T3	1
fifo_depth[7]	auto[1]	auto[1]	auto[0]	10785	1			T1	156		T2	46		T3	1
fifo_depth[7]	auto[1]	auto[1]	auto[1]	9565	1			T1	421		T2	27		T3	2