Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	12934506	1			T1	25248		T2	12568		T3	286522
all_pins[1]	12934506	1			T1	25248		T2	12568		T3	286522
all_pins[2]	12934506	1			T1	25248		T2	12568		T3	286522

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	32332838	1			T1	67556		T2	33521		T3	716578
values[0x1]	6470680	1			T1	8188		T2	4183		T3	142988
transitions[0x0=>0x1]	6470519	1			T1	8188		T2	4183		T3	142986
transitions[0x1=>0x0]	6470531	1			T1	8188		T2	4183		T3	142986

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	12900738	1			T1	25208		T2	12555		T3	285907
all_pins[0]	values[0x1]	33768	1			T1	40		T2	13		T3	615
all_pins[0]	transitions[0x0=>0x1]	33684	1			T1	40		T2	13		T3	614
all_pins[0]	transitions[0x1=>0x0]	6436545	1			T1	8148		T2	4170		T3	142370
all_pins[1]	values[0x0]	12934211	1			T1	25248		T2	12568		T3	286520
all_pins[1]	values[0x1]	295	1			T3	2		T15	3		T10	6
all_pins[1]	transitions[0x0=>0x1]	262	1			T3	2		T15	2		T10	5
all_pins[1]	transitions[0x1=>0x0]	33735	1			T1	40		T2	13		T3	615
all_pins[2]	values[0x0]	6497889	1			T1	17100		T2	8398		T3	144151
all_pins[2]	values[0x1]	6436617	1			T1	8148		T2	4170		T3	142371
all_pins[2]	transitions[0x0=>0x1]	6436573	1			T1	8148		T2	4170		T3	142370
all_pins[2]	transitions[0x1=>0x0]	251	1			T3	1		T15	1		T10	5