Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 776 1 T3 10 T15 10 T10 27
all_values[1] 776 1 T3 10 T15 10 T10 27
all_values[2] 776 1 T3 10 T15 10 T10 27


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1178 1 T3 15 T15 16 T10 41
auto[1] 1150 1 T3 15 T15 14 T10 40


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 836 1 T3 15 T15 5 T10 23
auto[1] 1492 1 T3 15 T15 25 T10 58


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1310 1 T3 19 T15 11 T10 42
auto[1] 1018 1 T3 11 T15 19 T10 39


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 159 1 T3 4 T15 1 T10 2
all_values[0] auto[0] auto[0] auto[1] 65 1 T3 1 T15 1 T10 2
all_values[0] auto[0] auto[1] auto[0] 123 1 T3 1 T10 3 T91 6
all_values[0] auto[0] auto[1] auto[1] 90 1 T15 2 T10 6 T94 1
all_values[0] auto[1] auto[0] auto[1] 193 1 T3 3 T15 4 T10 8
all_values[0] auto[1] auto[1] auto[1] 146 1 T3 1 T15 2 T10 6
all_values[1] auto[0] auto[0] auto[0] 113 1 T10 5 T91 2 T95 5
all_values[1] auto[0] auto[0] auto[1] 96 1 T3 1 T10 3 T91 1
all_values[1] auto[0] auto[1] auto[0] 131 1 T3 4 T15 2 T10 6
all_values[1] auto[0] auto[1] auto[1] 95 1 T3 2 T15 1 T10 2
all_values[1] auto[1] auto[0] auto[1] 160 1 T3 1 T15 3 T10 5
all_values[1] auto[1] auto[1] auto[1] 181 1 T3 2 T15 4 T10 6
all_values[2] auto[0] auto[0] auto[0] 166 1 T3 3 T15 2 T10 5
all_values[2] auto[0] auto[0] auto[1] 71 1 T15 1 T10 4 T95 1
all_values[2] auto[0] auto[1] auto[0] 144 1 T3 3 T10 2 T7 3
all_values[2] auto[0] auto[1] auto[1] 57 1 T15 1 T10 2 T91 3
all_values[2] auto[1] auto[0] auto[1] 155 1 T3 2 T15 4 T10 7
all_values[2] auto[1] auto[1] auto[1] 183 1 T3 2 T15 2 T10 7


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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