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 LINE       63
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T19,T9
11CoveredT1,T2,T3

 LINE       75
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT16,T22,T23
10CoveredT39,T40,T41

 LINE       82
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT16,T22,T23
010CoveredT39,T40,T41
100CoveredT16,T22,T23

 LINE       130
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[4096:8191]}) ? 1'b0 : 1'b1)
             ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       168
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT39,T40,T41
010CoveredT7,T19,T9
100CoveredT7,T19,T9

 LINE       1946
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_INTR_STATE_OFFSET)
            -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1947
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET)
            -------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1948
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_INTR_TEST_OFFSET)
            ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T15,T10

 LINE       1949
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET)
            -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T13,T14

 LINE       1950
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_CFG_OFFSET)
            ---------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1951
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_CMD_OFFSET)
            ---------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1952
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_STATUS_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1953
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_ERR_CODE_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1954
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET)
            -------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T20

 LINE       1955
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_0_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1956
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_1_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1957
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_2_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1958
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_3_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1959
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_4_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1960
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_5_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1961
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_6_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1962
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_7_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1963
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_8_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1964
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_9_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1965
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_10_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1966
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_11_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1967
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_12_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1968
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_13_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1969
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_14_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1970
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_15_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1971
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_16_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1972
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_17_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1973
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_18_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1974
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_19_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1975
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_20_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1976
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_21_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1977
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_22_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1978
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_23_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1979
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_24_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1980
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_25_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1981
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_26_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1982
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_27_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1983
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_28_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1984
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_29_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1985
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_30_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1986
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_31_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1987
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_0_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1988
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_1_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1989
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_2_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1990
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_3_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1991
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_4_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1992
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_5_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1993
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_6_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1994
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_7_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1995
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_8_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1996
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_9_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1997
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_10_OFFSET)
            ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1998
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_11_OFFSET)
            ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1999
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_12_OFFSET)
            ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2000
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_13_OFFSET)
            ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2001
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_14_OFFSET)
            ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2002
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_15_OFFSET)
            ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2003
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2004
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2007
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2007
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       2011
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[37] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[40] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[42] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[43] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[44] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[45] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[46] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[47] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[48] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[49] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[50] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[51] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[52] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[53] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[54] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[55] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[56] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[57] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[58] & ((|(4'b1111 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT7,T19,T9

 LINE       2011
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | 
     36  (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | 
     37  (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | 
     38  (addr_hit[37] & ((|(4'b1111 & (~reg_be))))) | 
     39  (addr_hit[38] & ((|(4'b1111 & (~reg_be))))) | 
     40  (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) | 
     41  (addr_hit[40] & ((|(4'b1111 & (~reg_be))))) | 
     42  (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) | 
     43  (addr_hit[42] & ((|(4'b1111 & (~reg_be))))) | 
     44  (addr_hit[43] & ((|(4'b1111 & (~reg_be))))) | 
     45  (addr_hit[44] & ((|(4'b1111 & (~reg_be))))) | 
     46  (addr_hit[45] & ((|(4'b1111 & (~reg_be))))) | 
     47  (addr_hit[46] & ((|(4'b1111 & (~reg_be))))) | 
     48  (addr_hit[47] & ((|(4'b1111 & (~reg_be))))) | 
     49  (addr_hit[48] & ((|(4'b1111 & (~reg_be))))) | 
     50  (addr_hit[49] & ((|(4'b1111 & (~reg_be))))) | 
     51  (addr_hit[50] & ((|(4'b1111 & (~reg_be))))) | 
     52  (addr_hit[51] & ((|(4'b1111 & (~reg_be))))) | 
     53  (addr_hit[52] & ((|(4'b1111 & (~reg_be))))) | 
     54  (addr_hit[53] & ((|(4'b1111 & (~reg_be))))) | 
     55  (addr_hit[54] & ((|(4'b1111 & (~reg_be))))) | 
     56  (addr_hit[55] & ((|(4'b1111 & (~reg_be))))) | 
     57  (addr_hit[56] & ((|(4'b1111 & (~reg_be))))) | 
     58  (addr_hit[57] & ((|(4'b1111 & (~reg_be))))) | 
     59  (addr_hit[58] & ((|(4'b1111 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT1,T2,T3
59 (addr_hit[58] & ((|(4'...CoveredT1,T2,T3
58 (addr_hit[57] & ((|(4'...CoveredT1,T2,T3
57 (addr_hit[56] & ((|(4'...CoveredT1,T2,T3
56 (addr_hit[55] & ((|(4'...CoveredT1,T2,T3
55 (addr_hit[54] & ((|(4'...CoveredT1,T2,T3
54 (addr_hit[53] & ((|(4'...CoveredT1,T2,T3
53 (addr_hit[52] & ((|(4'...CoveredT1,T2,T3
52 (addr_hit[51] & ((|(4'...CoveredT1,T2,T3
51 (addr_hit[50] & ((|(4'...CoveredT1,T2,T3
50 (addr_hit[49] & ((|(4'...CoveredT1,T2,T3
49 (addr_hit[48] & ((|(4'...CoveredT1,T2,T3
48 (addr_hit[47] & ((|(4'...CoveredT1,T2,T3
47 (addr_hit[46] & ((|(4'...CoveredT1,T2,T3
46 (addr_hit[45] & ((|(4'...CoveredT1,T2,T3
45 (addr_hit[44] & ((|(4'...CoveredT1,T2,T3
44 (addr_hit[43] & ((|(4'...CoveredT1,T2,T3
43 (addr_hit[42] & ((|(4'...CoveredT1,T2,T3
42 (addr_hit[41] & ((|(4'...CoveredT1,T2,T3
41 (addr_hit[40] & ((|(4'...CoveredT17,T18,T42
40 (addr_hit[39] & ((|(4'...CoveredT17,T18,T42
39 (addr_hit[38] & ((|(4'...CoveredT17,T18,T42
38 (addr_hit[37] & ((|(4'...CoveredT17,T18,T42
37 (addr_hit[36] & ((|(4'...CoveredT17,T18,T42
36 (addr_hit[35] & ((|(4'...CoveredT17,T18,T42
35 (addr_hit[34] & ((|(4'...CoveredT16,T17,T18
34 (addr_hit[33] & ((|(4'...CoveredT17,T18,T42
33 (addr_hit[32] & ((|(4'...CoveredT17,T18,T42
32 (addr_hit[31] & ((|(4'...CoveredT17,T18,T42
31 (addr_hit[30] & ((|(4'...CoveredT17,T18,T42
30 (addr_hit[29] & ((|(4'...CoveredT17,T18,T42
29 (addr_hit[28] & ((|(4'...CoveredT17,T18,T42
28 (addr_hit[27] & ((|(4'...CoveredT17,T18,T42
27 (addr_hit[26] & ((|(4'...CoveredT17,T18,T42
26 (addr_hit[25] & ((|(4'...CoveredT17,T18,T42
25 (addr_hit[24] & ((|(4'...CoveredT17,T18,T42
24 (addr_hit[23] & ((|(4'...CoveredT17,T18,T42
23 (addr_hit[22] & ((|(4'...CoveredT17,T18,T42
22 (addr_hit[21] & ((|(4'...CoveredT17,T18,T42
21 (addr_hit[20] & ((|(4'...CoveredT17,T18,T42
20 (addr_hit[19] & ((|(4'...CoveredT17,T18,T42
19 (addr_hit[18] & ((|(4'...CoveredT17,T18,T42
18 (addr_hit[17] & ((|(4'...CoveredT17,T18,T42
17 (addr_hit[16] & ((|(4'...CoveredT17,T18,T42
16 (addr_hit[15] & ((|(4'...CoveredT17,T18,T42
15 (addr_hit[14] & ((|(4'...CoveredT17,T18,T42
14 (addr_hit[13] & ((|(4'...CoveredT17,T18,T42
13 (addr_hit[12] & ((|(4'...CoveredT17,T18,T42
12 (addr_hit[11] & ((|(4'...CoveredT17,T18,T42
11 (addr_hit[10] & ((|(4'...CoveredT17,T18,T42
10 (addr_hit[9] & ((|(4'b...CoveredT17,T18,T42
9 (addr_hit[8] & ((|(4'b...CoveredT17,T18,T42
8 (addr_hit[7] & ((|(4'b...CoveredT1,T2,T3
7 (addr_hit[6] & ((|(4'b...CoveredT1,T2,T3
6 (addr_hit[5] & ((|(4'b...CoveredT17,T18,T42
5 (addr_hit[4] & ((|(4'b...CoveredT1,T2,T3
4 (addr_hit[3] & ((|(4'b...CoveredT17,T18,T42
3 (addr_hit[2] & ((|(4'b...CoveredT3,T15,T10
2 (addr_hit[1] & ((|(4'b...CoveredT3,T15,T10
1 (addr_hit[0] & ((|(4'b...CoveredT1,T2,T3

 LINE       2011
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2011
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T15,T10

 LINE       2011
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T15,T10
11CoveredT3,T15,T10

 LINE       2011
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT12,T13,T14
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2011
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2011
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2011
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T20
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT16,T17,T18

 LINE       2011
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T18,T42

 LINE       2011
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2011
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2011
 SUB-EXPRESSION (addr_hit[43] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2011
 SUB-EXPRESSION (addr_hit[44] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2011
 SUB-EXPRESSION (addr_hit[45] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2011
 SUB-EXPRESSION (addr_hit[46] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2011
 SUB-EXPRESSION (addr_hit[47] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2011
 SUB-EXPRESSION (addr_hit[48] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2011
 SUB-EXPRESSION (addr_hit[49] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2011
 SUB-EXPRESSION (addr_hit[50] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2011
 SUB-EXPRESSION (addr_hit[51] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2011
 SUB-EXPRESSION (addr_hit[52] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2011
 SUB-EXPRESSION (addr_hit[53] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2011
 SUB-EXPRESSION (addr_hit[54] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2011
 SUB-EXPRESSION (addr_hit[55] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2011
 SUB-EXPRESSION (addr_hit[56] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2011
 SUB-EXPRESSION (addr_hit[57] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2011
 SUB-EXPRESSION (addr_hit[58] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2074
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT7,T19,T9
111CoveredT1,T2,T3

 LINE       2079
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT7,T19,T9
111CoveredT1,T2,T3

 LINE       2086
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T15,T10
110CoveredT7,T19,T9
111CoveredT3,T15,T10

 LINE       2093
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT12,T13,T14
110CoveredT7,T19,T9
111CoveredT12,T13,T14

 LINE       2096
 EXPRESSION (addr_hit[4] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       2097
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT7,T19,T9
111CoveredT1,T2,T3

 LINE       2112
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT7,T19,T9
111CoveredT1,T2,T3

 LINE       2121
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       2122
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T4,T20
110CoveredT7,T19,T9
111CoveredT3,T4,T20

 LINE       2125
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT7,T19,T9
111CoveredT1,T2,T3
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%