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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.26 94.84 92.14 100.00 76.92 89.38 99.49 72.04


Total test records in report: 725
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T534 /workspace/coverage/default/44.hmac_burst_wr.2079369257 Jun 10 05:43:29 PM PDT 24 Jun 10 05:43:39 PM PDT 24 694584837 ps
T535 /workspace/coverage/default/48.hmac_wipe_secret.942947254 Jun 10 05:43:41 PM PDT 24 Jun 10 05:43:46 PM PDT 24 1257805500 ps
T536 /workspace/coverage/default/21.hmac_alert_test.489835048 Jun 10 05:42:23 PM PDT 24 Jun 10 05:42:24 PM PDT 24 19528032 ps
T537 /workspace/coverage/default/5.hmac_error.3091183754 Jun 10 05:41:46 PM PDT 24 Jun 10 05:42:20 PM PDT 24 1823807496 ps
T538 /workspace/coverage/default/8.hmac_smoke.4049854136 Jun 10 05:41:53 PM PDT 24 Jun 10 05:41:59 PM PDT 24 1049706949 ps
T539 /workspace/coverage/default/34.hmac_stress_all.1084911761 Jun 10 05:42:57 PM PDT 24 Jun 10 05:57:21 PM PDT 24 16787482356 ps
T540 /workspace/coverage/default/23.hmac_long_msg.2535333160 Jun 10 05:42:32 PM PDT 24 Jun 10 05:43:00 PM PDT 24 3524417323 ps
T541 /workspace/coverage/default/1.hmac_long_msg.3174439581 Jun 10 05:41:48 PM PDT 24 Jun 10 05:43:27 PM PDT 24 5015963073 ps
T542 /workspace/coverage/default/2.hmac_burst_wr.3296771354 Jun 10 05:41:44 PM PDT 24 Jun 10 05:42:34 PM PDT 24 3454279057 ps
T543 /workspace/coverage/default/43.hmac_wipe_secret.3860979300 Jun 10 05:43:28 PM PDT 24 Jun 10 05:43:54 PM PDT 24 2595286907 ps
T544 /workspace/coverage/default/23.hmac_back_pressure.2603484166 Jun 10 05:42:25 PM PDT 24 Jun 10 05:43:20 PM PDT 24 4379529981 ps
T545 /workspace/coverage/default/25.hmac_stress_all.420271755 Jun 10 05:42:32 PM PDT 24 Jun 10 05:51:32 PM PDT 24 40578294610 ps
T546 /workspace/coverage/default/6.hmac_test_sha_vectors.3418277932 Jun 10 05:41:53 PM PDT 24 Jun 10 05:50:36 PM PDT 24 36286197136 ps
T547 /workspace/coverage/default/33.hmac_datapath_stress.815435771 Jun 10 05:42:49 PM PDT 24 Jun 10 05:51:32 PM PDT 24 22666089163 ps
T548 /workspace/coverage/default/0.hmac_smoke.1874265193 Jun 10 05:41:55 PM PDT 24 Jun 10 05:41:59 PM PDT 24 264265367 ps
T549 /workspace/coverage/default/6.hmac_burst_wr.3008651106 Jun 10 05:41:46 PM PDT 24 Jun 10 05:42:37 PM PDT 24 2555653484 ps
T550 /workspace/coverage/default/6.hmac_test_hmac_vectors.3889650526 Jun 10 05:42:02 PM PDT 24 Jun 10 05:42:04 PM PDT 24 112755630 ps
T551 /workspace/coverage/default/33.hmac_smoke.1570829524 Jun 10 05:42:51 PM PDT 24 Jun 10 05:43:00 PM PDT 24 1612324520 ps
T552 /workspace/coverage/default/28.hmac_long_msg.4090114378 Jun 10 05:42:48 PM PDT 24 Jun 10 05:44:04 PM PDT 24 20643067901 ps
T553 /workspace/coverage/default/46.hmac_wipe_secret.109417098 Jun 10 05:43:36 PM PDT 24 Jun 10 05:45:00 PM PDT 24 4520602584 ps
T554 /workspace/coverage/default/22.hmac_burst_wr.1982174118 Jun 10 05:42:18 PM PDT 24 Jun 10 05:43:07 PM PDT 24 4931678448 ps
T555 /workspace/coverage/default/42.hmac_stress_all.3793490574 Jun 10 05:43:20 PM PDT 24 Jun 10 06:02:00 PM PDT 24 50318550059 ps
T556 /workspace/coverage/default/16.hmac_long_msg.653493953 Jun 10 05:42:08 PM PDT 24 Jun 10 05:43:58 PM PDT 24 26866500573 ps
T557 /workspace/coverage/default/28.hmac_wipe_secret.2375835759 Jun 10 05:42:48 PM PDT 24 Jun 10 05:42:59 PM PDT 24 496476551 ps
T558 /workspace/coverage/default/27.hmac_burst_wr.2284933795 Jun 10 05:42:34 PM PDT 24 Jun 10 05:43:35 PM PDT 24 14182222904 ps
T559 /workspace/coverage/default/47.hmac_smoke.3721276408 Jun 10 05:43:35 PM PDT 24 Jun 10 05:43:37 PM PDT 24 145214130 ps
T560 /workspace/coverage/default/38.hmac_alert_test.1905794599 Jun 10 05:43:14 PM PDT 24 Jun 10 05:43:15 PM PDT 24 14316815 ps
T8 /workspace/coverage/default/70.hmac_stress_all_with_rand_reset.336510723 Jun 10 05:43:52 PM PDT 24 Jun 10 06:14:21 PM PDT 24 28625140737 ps
T561 /workspace/coverage/default/45.hmac_wipe_secret.3040209541 Jun 10 05:43:29 PM PDT 24 Jun 10 05:44:13 PM PDT 24 2249116808 ps
T562 /workspace/coverage/default/24.hmac_test_sha_vectors.1444190575 Jun 10 05:42:40 PM PDT 24 Jun 10 05:50:35 PM PDT 24 100869768390 ps
T563 /workspace/coverage/default/16.hmac_error.1176668219 Jun 10 05:42:13 PM PDT 24 Jun 10 05:43:57 PM PDT 24 33823143961 ps
T564 /workspace/coverage/default/30.hmac_smoke.3724859386 Jun 10 05:42:36 PM PDT 24 Jun 10 05:42:38 PM PDT 24 115620819 ps
T565 /workspace/coverage/default/18.hmac_alert_test.2717081811 Jun 10 05:42:30 PM PDT 24 Jun 10 05:42:31 PM PDT 24 13413033 ps
T566 /workspace/coverage/default/41.hmac_long_msg.106102948 Jun 10 05:43:16 PM PDT 24 Jun 10 05:44:49 PM PDT 24 25435215395 ps
T567 /workspace/coverage/default/11.hmac_long_msg.2136137354 Jun 10 05:41:56 PM PDT 24 Jun 10 05:42:10 PM PDT 24 2883573612 ps
T568 /workspace/coverage/default/24.hmac_back_pressure.2555042425 Jun 10 05:42:22 PM PDT 24 Jun 10 05:42:34 PM PDT 24 1230944454 ps
T569 /workspace/coverage/default/11.hmac_alert_test.3083830020 Jun 10 05:42:16 PM PDT 24 Jun 10 05:42:17 PM PDT 24 42071418 ps
T570 /workspace/coverage/default/29.hmac_test_hmac_vectors.2835189135 Jun 10 05:42:43 PM PDT 24 Jun 10 05:42:45 PM PDT 24 256115475 ps
T571 /workspace/coverage/default/32.hmac_smoke.2769547481 Jun 10 05:42:51 PM PDT 24 Jun 10 05:42:54 PM PDT 24 420234437 ps
T572 /workspace/coverage/default/48.hmac_error.1562584243 Jun 10 05:43:38 PM PDT 24 Jun 10 05:44:41 PM PDT 24 14094050269 ps
T573 /workspace/coverage/default/46.hmac_test_hmac_vectors.3489498167 Jun 10 05:43:33 PM PDT 24 Jun 10 05:43:35 PM PDT 24 138832843 ps
T574 /workspace/coverage/default/45.hmac_back_pressure.3888174504 Jun 10 05:43:30 PM PDT 24 Jun 10 05:43:58 PM PDT 24 543439723 ps
T575 /workspace/coverage/default/37.hmac_back_pressure.84055960 Jun 10 05:43:00 PM PDT 24 Jun 10 05:43:33 PM PDT 24 5356903365 ps
T576 /workspace/coverage/default/42.hmac_smoke.3732353829 Jun 10 05:43:17 PM PDT 24 Jun 10 05:43:21 PM PDT 24 330407817 ps
T577 /workspace/coverage/default/38.hmac_back_pressure.2233654555 Jun 10 05:43:10 PM PDT 24 Jun 10 05:44:17 PM PDT 24 2212495367 ps
T578 /workspace/coverage/default/30.hmac_long_msg.672610193 Jun 10 05:42:36 PM PDT 24 Jun 10 05:44:13 PM PDT 24 1748902072 ps
T579 /workspace/coverage/default/7.hmac_test_sha_vectors.2224232013 Jun 10 05:41:54 PM PDT 24 Jun 10 05:50:50 PM PDT 24 39780168429 ps
T580 /workspace/coverage/default/29.hmac_burst_wr.1176130256 Jun 10 05:42:38 PM PDT 24 Jun 10 05:43:01 PM PDT 24 2178389579 ps
T581 /workspace/coverage/default/23.hmac_wipe_secret.552618194 Jun 10 05:42:41 PM PDT 24 Jun 10 05:43:24 PM PDT 24 2259481333 ps
T582 /workspace/coverage/default/36.hmac_test_hmac_vectors.2059970673 Jun 10 05:43:00 PM PDT 24 Jun 10 05:43:01 PM PDT 24 234517903 ps
T583 /workspace/coverage/default/24.hmac_smoke.3415223433 Jun 10 05:42:22 PM PDT 24 Jun 10 05:42:28 PM PDT 24 659520265 ps
T584 /workspace/coverage/default/7.hmac_test_hmac_vectors.3001668207 Jun 10 05:41:56 PM PDT 24 Jun 10 05:41:58 PM PDT 24 1098712961 ps
T585 /workspace/coverage/default/32.hmac_wipe_secret.2173317763 Jun 10 05:42:51 PM PDT 24 Jun 10 05:43:36 PM PDT 24 2336418582 ps
T586 /workspace/coverage/default/41.hmac_test_sha_vectors.381772924 Jun 10 05:43:17 PM PDT 24 Jun 10 05:51:12 PM PDT 24 7933237706 ps
T587 /workspace/coverage/default/33.hmac_error.1871949945 Jun 10 05:42:53 PM PDT 24 Jun 10 05:45:24 PM PDT 24 14937405238 ps
T588 /workspace/coverage/default/27.hmac_alert_test.961070602 Jun 10 05:42:33 PM PDT 24 Jun 10 05:42:34 PM PDT 24 36291460 ps
T47 /workspace/coverage/default/30.hmac_stress_all_with_rand_reset.3797965818 Jun 10 05:42:40 PM PDT 24 Jun 10 06:36:37 PM PDT 24 58966271673 ps
T589 /workspace/coverage/default/20.hmac_back_pressure.2408944159 Jun 10 05:42:13 PM PDT 24 Jun 10 05:43:03 PM PDT 24 2340575869 ps
T590 /workspace/coverage/default/35.hmac_smoke.2019619373 Jun 10 05:42:55 PM PDT 24 Jun 10 05:43:01 PM PDT 24 1185333188 ps
T591 /workspace/coverage/default/32.hmac_test_sha_vectors.373236749 Jun 10 05:42:51 PM PDT 24 Jun 10 05:50:46 PM PDT 24 26888349595 ps
T43 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2488314753 Jun 10 05:34:20 PM PDT 24 Jun 10 05:34:21 PM PDT 24 24534105 ps
T44 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2156642471 Jun 10 05:34:23 PM PDT 24 Jun 10 05:34:24 PM PDT 24 35054709 ps
T48 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2646115764 Jun 10 05:34:18 PM PDT 24 Jun 10 05:34:22 PM PDT 24 155212240 ps
T45 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.267141209 Jun 10 05:34:26 PM PDT 24 Jun 10 05:34:29 PM PDT 24 47663514 ps
T66 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.78235982 Jun 10 05:33:43 PM PDT 24 Jun 10 05:33:53 PM PDT 24 213519042 ps
T49 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2994512523 Jun 10 05:34:21 PM PDT 24 Jun 10 05:34:24 PM PDT 24 105401780 ps
T46 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2619480492 Jun 10 05:34:02 PM PDT 24 Jun 10 05:34:06 PM PDT 24 239578660 ps
T67 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2787833474 Jun 10 05:33:40 PM PDT 24 Jun 10 05:33:41 PM PDT 24 51710684 ps
T39 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.4170681642 Jun 10 05:34:13 PM PDT 24 Jun 10 05:34:15 PM PDT 24 398403063 ps
T592 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2084392733 Jun 10 05:33:42 PM PDT 24 Jun 10 05:33:44 PM PDT 24 21715521 ps
T593 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3149011729 Jun 10 05:33:44 PM PDT 24 Jun 10 05:33:49 PM PDT 24 380167718 ps
T40 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2890976312 Jun 10 05:34:23 PM PDT 24 Jun 10 05:34:26 PM PDT 24 92070849 ps
T64 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1892987127 Jun 10 05:33:40 PM PDT 24 Jun 10 05:33:42 PM PDT 24 122378659 ps
T65 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.4062777108 Jun 10 05:34:27 PM PDT 24 Jun 10 05:34:30 PM PDT 24 390869216 ps
T62 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3012502658 Jun 10 05:34:29 PM PDT 24 Jun 10 05:34:32 PM PDT 24 440175114 ps
T63 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.71258146 Jun 10 05:34:19 PM PDT 24 Jun 10 05:34:20 PM PDT 24 52144426 ps
T594 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3304120287 Jun 10 05:34:39 PM PDT 24 Jun 10 05:34:40 PM PDT 24 57450765 ps
T41 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.4134134739 Jun 10 05:34:23 PM PDT 24 Jun 10 05:34:28 PM PDT 24 1692688402 ps
T96 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2658612986 Jun 10 05:33:50 PM PDT 24 Jun 10 05:33:54 PM PDT 24 138547315 ps
T595 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1256972069 Jun 10 05:33:44 PM PDT 24 Jun 10 05:33:47 PM PDT 24 94192220 ps
T68 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.976804413 Jun 10 05:33:52 PM PDT 24 Jun 10 05:33:53 PM PDT 24 68227031 ps
T596 /workspace/coverage/cover_reg_top/30.hmac_intr_test.2273804622 Jun 10 05:34:38 PM PDT 24 Jun 10 05:34:39 PM PDT 24 40165102 ps
T597 /workspace/coverage/cover_reg_top/15.hmac_intr_test.3544632761 Jun 10 05:34:23 PM PDT 24 Jun 10 05:34:24 PM PDT 24 23125813 ps
T598 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1540773187 Jun 10 05:33:54 PM PDT 24 Jun 10 05:34:00 PM PDT 24 110843442 ps
T599 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.718541287 Jun 10 05:33:54 PM PDT 24 Jun 10 05:33:56 PM PDT 24 90766975 ps
T600 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.273118996 Jun 10 05:34:05 PM PDT 24 Jun 10 05:34:09 PM PDT 24 895625762 ps
T69 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2705466529 Jun 10 05:33:55 PM PDT 24 Jun 10 05:34:01 PM PDT 24 1489210560 ps
T601 /workspace/coverage/cover_reg_top/20.hmac_intr_test.3512553574 Jun 10 05:34:31 PM PDT 24 Jun 10 05:34:31 PM PDT 24 59085136 ps
T70 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1658975403 Jun 10 05:34:22 PM PDT 24 Jun 10 05:34:23 PM PDT 24 19338360 ps
T71 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2762808798 Jun 10 05:33:48 PM PDT 24 Jun 10 05:33:49 PM PDT 24 71570140 ps
T602 /workspace/coverage/cover_reg_top/39.hmac_intr_test.625160328 Jun 10 05:34:34 PM PDT 24 Jun 10 05:34:35 PM PDT 24 36974725 ps
T603 /workspace/coverage/cover_reg_top/10.hmac_intr_test.495514186 Jun 10 05:34:15 PM PDT 24 Jun 10 05:34:16 PM PDT 24 16509424 ps
T72 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2728942560 Jun 10 05:34:04 PM PDT 24 Jun 10 05:34:15 PM PDT 24 861788709 ps
T97 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3963639643 Jun 10 05:34:26 PM PDT 24 Jun 10 05:34:29 PM PDT 24 1602439439 ps
T604 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.346060059 Jun 10 05:34:07 PM PDT 24 Jun 10 05:34:10 PM PDT 24 196138251 ps
T605 /workspace/coverage/cover_reg_top/32.hmac_intr_test.2452777731 Jun 10 05:34:36 PM PDT 24 Jun 10 05:34:37 PM PDT 24 76190593 ps
T98 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2159792115 Jun 10 05:34:28 PM PDT 24 Jun 10 05:34:33 PM PDT 24 458037289 ps
T606 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2622316700 Jun 10 05:33:46 PM PDT 24 Jun 10 05:33:47 PM PDT 24 31197840 ps
T607 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2375112935 Jun 10 05:34:02 PM PDT 24 Jun 10 05:34:04 PM PDT 24 289897368 ps
T608 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1713634973 Jun 10 05:33:44 PM PDT 24 Jun 10 05:33:45 PM PDT 24 47658289 ps
T609 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2169542499 Jun 10 05:34:20 PM PDT 24 Jun 10 05:34:22 PM PDT 24 52927739 ps
T99 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.4157229857 Jun 10 05:33:44 PM PDT 24 Jun 10 05:33:49 PM PDT 24 435622730 ps
T610 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1241030468 Jun 10 05:34:26 PM PDT 24 Jun 10 05:34:29 PM PDT 24 224407379 ps
T611 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1007014661 Jun 10 05:34:38 PM PDT 24 Jun 10 05:34:39 PM PDT 24 23951099 ps
T73 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3578459896 Jun 10 05:34:17 PM PDT 24 Jun 10 05:34:18 PM PDT 24 80469771 ps
T612 /workspace/coverage/cover_reg_top/28.hmac_intr_test.4218202696 Jun 10 05:34:31 PM PDT 24 Jun 10 05:34:32 PM PDT 24 16078510 ps
T613 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3899467514 Jun 10 05:34:38 PM PDT 24 Jun 10 05:34:39 PM PDT 24 79928354 ps
T614 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1685657091 Jun 10 05:34:22 PM PDT 24 Jun 10 05:34:24 PM PDT 24 60724435 ps
T615 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.960519022 Jun 10 05:34:11 PM PDT 24 Jun 10 05:34:12 PM PDT 24 25223606 ps
T74 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.391250665 Jun 10 05:33:44 PM PDT 24 Jun 10 05:33:48 PM PDT 24 59488046 ps
T616 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1975551523 Jun 10 05:34:33 PM PDT 24 Jun 10 05:34:34 PM PDT 24 48200440 ps
T617 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1970253706 Jun 10 05:34:22 PM PDT 24 Jun 10 05:34:23 PM PDT 24 30972867 ps
T618 /workspace/coverage/cover_reg_top/22.hmac_intr_test.2067449420 Jun 10 05:34:30 PM PDT 24 Jun 10 05:34:31 PM PDT 24 10786765 ps
T619 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.832753773 Jun 10 05:33:50 PM PDT 24 Jun 10 05:33:51 PM PDT 24 14801558 ps
T620 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3256979497 Jun 10 05:34:24 PM PDT 24 Jun 10 05:34:25 PM PDT 24 57096259 ps
T621 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.360596017 Jun 10 05:34:17 PM PDT 24 Jun 10 05:34:19 PM PDT 24 128387675 ps
T101 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3862782109 Jun 10 05:33:42 PM PDT 24 Jun 10 05:33:45 PM PDT 24 313584916 ps
T622 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2878243439 Jun 10 05:33:48 PM PDT 24 Jun 10 05:33:49 PM PDT 24 51242679 ps
T623 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3973405910 Jun 10 05:34:06 PM PDT 24 Jun 10 05:34:08 PM PDT 24 284730697 ps
T624 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2649307037 Jun 10 05:34:39 PM PDT 24 Jun 10 05:34:40 PM PDT 24 24077372 ps
T625 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3045509206 Jun 10 05:34:04 PM PDT 24 Jun 10 05:48:54 PM PDT 24 128847417998 ps
T626 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4085591994 Jun 10 05:34:23 PM PDT 24 Jun 10 05:34:26 PM PDT 24 159517921 ps
T627 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.842914732 Jun 10 05:33:59 PM PDT 24 Jun 10 05:34:00 PM PDT 24 19561671 ps
T75 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3802455324 Jun 10 05:33:59 PM PDT 24 Jun 10 05:34:00 PM PDT 24 71689227 ps
T628 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.342910953 Jun 10 05:34:14 PM PDT 24 Jun 10 05:34:15 PM PDT 24 76049681 ps
T629 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2182961545 Jun 10 05:34:31 PM PDT 24 Jun 10 05:34:32 PM PDT 24 23259679 ps
T630 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4078925882 Jun 10 05:33:56 PM PDT 24 Jun 10 05:33:57 PM PDT 24 79045806 ps
T631 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.951453533 Jun 10 05:34:28 PM PDT 24 Jun 10 05:39:33 PM PDT 24 87016598358 ps
T632 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.934444330 Jun 10 05:34:13 PM PDT 24 Jun 10 05:34:14 PM PDT 24 36059223 ps
T633 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2435361352 Jun 10 05:34:40 PM PDT 24 Jun 10 05:34:41 PM PDT 24 39752326 ps
T634 /workspace/coverage/cover_reg_top/25.hmac_intr_test.536475402 Jun 10 05:34:32 PM PDT 24 Jun 10 05:34:33 PM PDT 24 13319644 ps
T635 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2170183707 Jun 10 05:34:14 PM PDT 24 Jun 10 05:34:16 PM PDT 24 68150770 ps
T636 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1453752019 Jun 10 05:34:03 PM PDT 24 Jun 10 05:34:04 PM PDT 24 14195861 ps
T637 /workspace/coverage/cover_reg_top/26.hmac_intr_test.4047869942 Jun 10 05:34:29 PM PDT 24 Jun 10 05:34:30 PM PDT 24 49455822 ps
T638 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3929982769 Jun 10 05:34:35 PM PDT 24 Jun 10 05:34:36 PM PDT 24 86627041 ps
T639 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1082499016 Jun 10 05:33:52 PM PDT 24 Jun 10 05:33:55 PM PDT 24 129502734 ps
T640 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2503865056 Jun 10 05:34:05 PM PDT 24 Jun 10 05:34:06 PM PDT 24 41191654 ps
T641 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1092930050 Jun 10 05:34:22 PM PDT 24 Jun 10 05:34:25 PM PDT 24 45889885 ps
T642 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1338032865 Jun 10 05:33:47 PM PDT 24 Jun 10 05:33:52 PM PDT 24 872399721 ps
T643 /workspace/coverage/cover_reg_top/3.hmac_intr_test.4034845822 Jun 10 05:33:52 PM PDT 24 Jun 10 05:33:52 PM PDT 24 17985430 ps
T644 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1097890680 Jun 10 05:34:27 PM PDT 24 Jun 10 05:34:29 PM PDT 24 68576700 ps
T645 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1351711152 Jun 10 05:33:58 PM PDT 24 Jun 10 05:33:59 PM PDT 24 29438535 ps
T100 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2097097885 Jun 10 05:33:59 PM PDT 24 Jun 10 05:34:03 PM PDT 24 227436135 ps
T646 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.657358559 Jun 10 05:34:07 PM PDT 24 Jun 10 05:34:12 PM PDT 24 226885084 ps
T647 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2655879405 Jun 10 05:33:42 PM PDT 24 Jun 10 05:33:43 PM PDT 24 13225182 ps
T648 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3525386350 Jun 10 05:33:58 PM PDT 24 Jun 10 05:33:59 PM PDT 24 38646743 ps
T649 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3065565828 Jun 10 05:33:47 PM PDT 24 Jun 10 05:33:51 PM PDT 24 436444824 ps
T650 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.4142488212 Jun 10 05:34:21 PM PDT 24 Jun 10 05:34:24 PM PDT 24 64850419 ps
T651 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.940049250 Jun 10 05:34:26 PM PDT 24 Jun 10 05:34:31 PM PDT 24 1219947804 ps
T652 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1478914880 Jun 10 05:33:45 PM PDT 24 Jun 10 05:33:46 PM PDT 24 136931496 ps
T653 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.928381356 Jun 10 05:34:27 PM PDT 24 Jun 10 05:34:30 PM PDT 24 174391384 ps
T654 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2356232406 Jun 10 05:34:05 PM PDT 24 Jun 10 05:34:07 PM PDT 24 48335434 ps
T655 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1769567671 Jun 10 05:34:22 PM PDT 24 Jun 10 05:34:24 PM PDT 24 38328887 ps
T656 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1820272237 Jun 10 05:34:22 PM PDT 24 Jun 10 05:34:23 PM PDT 24 32653498 ps
T657 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1381244804 Jun 10 05:34:09 PM PDT 24 Jun 10 05:34:11 PM PDT 24 39633600 ps
T658 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.4176194454 Jun 10 05:34:04 PM PDT 24 Jun 10 05:34:05 PM PDT 24 67952758 ps
T659 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3315108105 Jun 10 05:33:58 PM PDT 24 Jun 10 05:34:01 PM PDT 24 339700487 ps
T660 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3338424884 Jun 10 05:33:58 PM PDT 24 Jun 10 05:34:00 PM PDT 24 23420454 ps
T661 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3792617307 Jun 10 05:34:26 PM PDT 24 Jun 10 05:34:28 PM PDT 24 112033018 ps
T662 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2335070423 Jun 10 05:34:05 PM PDT 24 Jun 10 05:34:06 PM PDT 24 37879406 ps
T663 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2174635369 Jun 10 05:34:22 PM PDT 24 Jun 10 05:34:24 PM PDT 24 36940513 ps
T664 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.867033543 Jun 10 05:34:14 PM PDT 24 Jun 10 05:34:17 PM PDT 24 451162645 ps
T665 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1104765083 Jun 10 05:34:31 PM PDT 24 Jun 10 05:34:35 PM PDT 24 65983446 ps
T666 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.773042327 Jun 10 05:34:23 PM PDT 24 Jun 10 05:34:26 PM PDT 24 51265517 ps
T667 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1515495068 Jun 10 05:34:30 PM PDT 24 Jun 10 05:34:32 PM PDT 24 127688704 ps
T668 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1273338149 Jun 10 05:34:36 PM PDT 24 Jun 10 05:34:37 PM PDT 24 18248366 ps
T669 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3724142336 Jun 10 05:33:45 PM PDT 24 Jun 10 05:33:46 PM PDT 24 52787390 ps
T670 /workspace/coverage/cover_reg_top/6.hmac_intr_test.4123201669 Jun 10 05:33:59 PM PDT 24 Jun 10 05:34:00 PM PDT 24 18984022 ps
T671 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1028470197 Jun 10 05:33:50 PM PDT 24 Jun 10 05:33:51 PM PDT 24 21153203 ps
T672 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1987888125 Jun 10 05:33:43 PM PDT 24 Jun 10 05:33:44 PM PDT 24 39876531 ps
T103 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.4234755245 Jun 10 05:34:02 PM PDT 24 Jun 10 05:34:04 PM PDT 24 96417342 ps
T673 /workspace/coverage/cover_reg_top/31.hmac_intr_test.517199051 Jun 10 05:34:36 PM PDT 24 Jun 10 05:34:37 PM PDT 24 79227280 ps
T674 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2394499038 Jun 10 05:34:38 PM PDT 24 Jun 10 05:34:39 PM PDT 24 11631905 ps
T675 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1285334910 Jun 10 05:34:16 PM PDT 24 Jun 10 05:34:19 PM PDT 24 49322227 ps
T676 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3356296950 Jun 10 05:34:14 PM PDT 24 Jun 10 05:34:16 PM PDT 24 83207442 ps
T677 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2940761046 Jun 10 05:34:21 PM PDT 24 Jun 10 05:34:26 PM PDT 24 3405117965 ps
T678 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2542407169 Jun 10 05:34:28 PM PDT 24 Jun 10 05:34:31 PM PDT 24 183352026 ps
T679 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1106310786 Jun 10 05:34:27 PM PDT 24 Jun 10 05:34:29 PM PDT 24 76236753 ps
T680 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1961773530 Jun 10 05:34:23 PM PDT 24 Jun 10 05:34:24 PM PDT 24 31156390 ps
T681 /workspace/coverage/cover_reg_top/9.hmac_intr_test.3288214547 Jun 10 05:34:08 PM PDT 24 Jun 10 05:34:09 PM PDT 24 44984948 ps
T682 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3340222683 Jun 10 05:34:37 PM PDT 24 Jun 10 05:34:38 PM PDT 24 34049996 ps
T683 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.4131357887 Jun 10 05:34:23 PM PDT 24 Jun 10 05:34:25 PM PDT 24 143433124 ps
T684 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4387799 Jun 10 05:33:50 PM PDT 24 Jun 10 05:33:58 PM PDT 24 154944493 ps
T685 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3630642354 Jun 10 05:34:04 PM PDT 24 Jun 10 05:34:09 PM PDT 24 209385750 ps
T686 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1387078726 Jun 10 05:33:43 PM PDT 24 Jun 10 05:33:46 PM PDT 24 397779172 ps
T687 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3160979557 Jun 10 05:34:09 PM PDT 24 Jun 10 05:34:11 PM PDT 24 157099230 ps
T688 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2465793900 Jun 10 05:34:06 PM PDT 24 Jun 10 05:34:07 PM PDT 24 51492136 ps
T689 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1043546125 Jun 10 05:34:26 PM PDT 24 Jun 10 05:34:28 PM PDT 24 12877059 ps
T690 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2443234251 Jun 10 05:34:09 PM PDT 24 Jun 10 05:34:10 PM PDT 24 117784942 ps
T691 /workspace/coverage/cover_reg_top/35.hmac_intr_test.2870401592 Jun 10 05:34:35 PM PDT 24 Jun 10 05:34:36 PM PDT 24 45329210 ps
T692 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.4186712765 Jun 10 05:34:06 PM PDT 24 Jun 10 05:34:08 PM PDT 24 376015946 ps
T693 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3281819862 Jun 10 05:34:01 PM PDT 24 Jun 10 05:34:04 PM PDT 24 52345512 ps
T694 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2792860752 Jun 10 05:33:40 PM PDT 24 Jun 10 05:33:48 PM PDT 24 1813571435 ps
T695 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2220927053 Jun 10 05:34:16 PM PDT 24 Jun 10 05:34:20 PM PDT 24 247572102 ps
T102 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.699116530 Jun 10 05:34:22 PM PDT 24 Jun 10 05:34:27 PM PDT 24 126034899 ps
T696 /workspace/coverage/cover_reg_top/8.hmac_intr_test.414040283 Jun 10 05:34:06 PM PDT 24 Jun 10 05:34:07 PM PDT 24 21234117 ps
T697 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.825751181 Jun 10 05:34:03 PM PDT 24 Jun 10 05:37:00 PM PDT 24 17059456781 ps
T698 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2755476708 Jun 10 05:34:04 PM PDT 24 Jun 10 05:34:07 PM PDT 24 108789874 ps
T699 /workspace/coverage/cover_reg_top/23.hmac_intr_test.862406810 Jun 10 05:34:31 PM PDT 24 Jun 10 05:34:32 PM PDT 24 11912678 ps
T700 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3327128080 Jun 10 05:33:59 PM PDT 24 Jun 10 05:34:01 PM PDT 24 88808395 ps
T701 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2596873239 Jun 10 05:34:06 PM PDT 24 Jun 10 05:34:09 PM PDT 24 559118961 ps
T702 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2377733911 Jun 10 05:34:30 PM PDT 24 Jun 10 05:34:32 PM PDT 24 44559775 ps
T703 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3815336521 Jun 10 05:34:23 PM PDT 24 Jun 10 05:34:26 PM PDT 24 213244237 ps
T704 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2605455838 Jun 10 05:34:36 PM PDT 24 Jun 10 05:34:37 PM PDT 24 13117795 ps
T705 /workspace/coverage/cover_reg_top/24.hmac_intr_test.3929686590 Jun 10 05:34:32 PM PDT 24 Jun 10 05:34:33 PM PDT 24 166145775 ps
T706 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1808275213 Jun 10 05:34:38 PM PDT 24 Jun 10 05:34:39 PM PDT 24 18762054 ps
T707 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.4018286346 Jun 10 05:34:23 PM PDT 24 Jun 10 05:34:27 PM PDT 24 93925073 ps
T708 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2686868983 Jun 10 05:34:05 PM PDT 24 Jun 10 05:34:07 PM PDT 24 929188050 ps
T709 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3563311344 Jun 10 05:34:34 PM PDT 24 Jun 10 05:34:35 PM PDT 24 110928264 ps
T710 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1748626247 Jun 10 05:34:25 PM PDT 24 Jun 10 05:34:27 PM PDT 24 25595643 ps
T711 /workspace/coverage/cover_reg_top/46.hmac_intr_test.71262239 Jun 10 05:34:37 PM PDT 24 Jun 10 05:34:38 PM PDT 24 21761710 ps
T712 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3902292742 Jun 10 05:34:21 PM PDT 24 Jun 10 05:34:27 PM PDT 24 910051245 ps
T713 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.4066737610 Jun 10 05:33:45 PM PDT 24 Jun 10 05:33:46 PM PDT 24 159701763 ps
T714 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2281999796 Jun 10 05:34:30 PM PDT 24 Jun 10 05:34:31 PM PDT 24 46627278 ps
T715 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2945441887 Jun 10 05:34:37 PM PDT 24 Jun 10 05:34:38 PM PDT 24 67014288 ps
T716 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1997229772 Jun 10 05:34:18 PM PDT 24 Jun 10 05:34:19 PM PDT 24 12571117 ps
T717 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1219165780 Jun 10 05:33:55 PM PDT 24 Jun 10 05:34:01 PM PDT 24 109969281 ps
T718 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.603932485 Jun 10 05:34:06 PM PDT 24 Jun 10 05:34:08 PM PDT 24 61446498 ps
T719 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2398975463 Jun 10 05:33:42 PM PDT 24 Jun 10 05:33:44 PM PDT 24 518458858 ps
T720 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1476685385 Jun 10 05:34:19 PM PDT 24 Jun 10 05:34:20 PM PDT 24 71683032 ps
T721 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2357374813 Jun 10 05:34:09 PM PDT 24 Jun 10 05:34:10 PM PDT 24 68199661 ps
T722 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1749787413 Jun 10 05:34:36 PM PDT 24 Jun 10 05:34:37 PM PDT 24 24120779 ps
T723 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1517378079 Jun 10 05:34:18 PM PDT 24 Jun 10 05:34:19 PM PDT 24 52301537 ps
T724 /workspace/coverage/cover_reg_top/48.hmac_intr_test.3666415195 Jun 10 05:34:39 PM PDT 24 Jun 10 05:34:40 PM PDT 24 13525375 ps
T725 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3457907826 Jun 10 05:34:26 PM PDT 24 Jun 10 05:34:28 PM PDT 24 39595365 ps

Test location /workspace/coverage/default/23.hmac_stress_all.2173333422
Short name T3
Test name
Test status
Simulation time 153516878897 ps
CPU time 4329.97 seconds
Started Jun 10 05:42:22 PM PDT 24
Finished Jun 10 06:54:33 PM PDT 24
Peak memory 811992 kb
Host smart-5df71013-a6b0-48aa-a48c-f38c234eaa7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173333422 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2173333422
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_stress_all_with_rand_reset.3492071871
Short name T7
Test name
Test status
Simulation time 33240222915 ps
CPU time 2026.54 seconds
Started Jun 10 05:43:47 PM PDT 24
Finished Jun 10 06:17:34 PM PDT 24
Peak memory 796100 kb
Host smart-996657e4-fbb6-4ebb-ba4c-655fad4c9228
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3492071871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all_with_rand_reset.3492071871
Directory /workspace/49.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1642629516
Short name T16
Test name
Test status
Simulation time 85890898 ps
CPU time 1.03 seconds
Started Jun 10 05:41:47 PM PDT 24
Finished Jun 10 05:41:48 PM PDT 24
Peak memory 220160 kb
Host smart-9705b56a-ec12-49c8-9f7d-093a0ca3ec27
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642629516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1642629516
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/163.hmac_stress_all_with_rand_reset.756605551
Short name T9
Test name
Test status
Simulation time 74394534345 ps
CPU time 1927.53 seconds
Started Jun 10 05:44:19 PM PDT 24
Finished Jun 10 06:16:27 PM PDT 24
Peak memory 808108 kb
Host smart-b22235a6-9c0d-4ad9-83f7-9a09b0ba3270
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=756605551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.hmac_stress_all_with_rand_reset.756605551
Directory /workspace/163.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2890976312
Short name T40
Test name
Test status
Simulation time 92070849 ps
CPU time 2.78 seconds
Started Jun 10 05:34:23 PM PDT 24
Finished Jun 10 05:34:26 PM PDT 24
Peak memory 199364 kb
Host smart-59d7621e-8add-4f62-97b1-358a8bd5f3a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890976312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2890976312
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3274200235
Short name T18
Test name
Test status
Simulation time 5710640387 ps
CPU time 58.77 seconds
Started Jun 10 05:43:27 PM PDT 24
Finished Jun 10 05:44:27 PM PDT 24
Peak memory 200456 kb
Host smart-0ebaf067-9be8-4bd6-ae01-2f63b8970cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274200235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3274200235
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/70.hmac_stress_all_with_rand_reset.336510723
Short name T8
Test name
Test status
Simulation time 28625140737 ps
CPU time 1829.07 seconds
Started Jun 10 05:43:52 PM PDT 24
Finished Jun 10 06:14:21 PM PDT 24
Peak memory 833472 kb
Host smart-92cb04cf-da7a-4c11-ac26-b41624d22a03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=336510723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.hmac_stress_all_with_rand_reset.336510723
Directory /workspace/70.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.71258146
Short name T63
Test name
Test status
Simulation time 52144426 ps
CPU time 0.94 seconds
Started Jun 10 05:34:19 PM PDT 24
Finished Jun 10 05:34:20 PM PDT 24
Peak memory 198804 kb
Host smart-ea2dd2e9-12eb-48be-a8cd-a0fde81dd4f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71258146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.71258146
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2020119266
Short name T10
Test name
Test status
Simulation time 82078143935 ps
CPU time 1691.7 seconds
Started Jun 10 05:43:21 PM PDT 24
Finished Jun 10 06:11:33 PM PDT 24
Peak memory 712372 kb
Host smart-1338bac9-bf72-451a-ae26-5494341b218d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020119266 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2020119266
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1888366180
Short name T81
Test name
Test status
Simulation time 32390700706 ps
CPU time 2384.91 seconds
Started Jun 10 05:42:04 PM PDT 24
Finished Jun 10 06:21:50 PM PDT 24
Peak memory 776852 kb
Host smart-aadbab1b-8de3-4dee-8551-2405590ca0e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888366180 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1888366180
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.4134134739
Short name T41
Test name
Test status
Simulation time 1692688402 ps
CPU time 4.59 seconds
Started Jun 10 05:34:23 PM PDT 24
Finished Jun 10 05:34:28 PM PDT 24
Peak memory 199364 kb
Host smart-991e5a54-161a-4bf8-b89b-529fad4a60b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134134739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.4134134739
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2102535602
Short name T79
Test name
Test status
Simulation time 737887454 ps
CPU time 149.71 seconds
Started Jun 10 05:43:37 PM PDT 24
Finished Jun 10 05:46:07 PM PDT 24
Peak memory 459660 kb
Host smart-2668bb45-d5f6-4841-8015-d0429131bcaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2102535602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2102535602
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3934476990
Short name T150
Test name
Test status
Simulation time 12073940 ps
CPU time 0.6 seconds
Started Jun 10 05:41:56 PM PDT 24
Finished Jun 10 05:41:57 PM PDT 24
Peak memory 195416 kb
Host smart-4703e791-1c1e-44fe-9f67-706f16cc0a2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934476990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3934476990
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2159792115
Short name T98
Test name
Test status
Simulation time 458037289 ps
CPU time 4.35 seconds
Started Jun 10 05:34:28 PM PDT 24
Finished Jun 10 05:34:33 PM PDT 24
Peak memory 199352 kb
Host smart-a5f7c03a-e11a-4c30-9251-69f11a2b6d5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159792115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2159792115
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3071306283
Short name T87
Test name
Test status
Simulation time 9708968986 ps
CPU time 48.09 seconds
Started Jun 10 05:42:01 PM PDT 24
Finished Jun 10 05:42:50 PM PDT 24
Peak memory 200568 kb
Host smart-5769715e-adfe-46ce-8a41-257101ba529d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071306283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3071306283
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1525089688
Short name T35
Test name
Test status
Simulation time 1700551995 ps
CPU time 39.83 seconds
Started Jun 10 05:42:39 PM PDT 24
Finished Jun 10 05:43:19 PM PDT 24
Peak memory 216872 kb
Host smart-ccddaa21-9314-4b6e-a248-0ad52924bac6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1525089688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1525089688
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3862782109
Short name T101
Test name
Test status
Simulation time 313584916 ps
CPU time 2.94 seconds
Started Jun 10 05:33:42 PM PDT 24
Finished Jun 10 05:33:45 PM PDT 24
Peak memory 199396 kb
Host smart-7b510934-77d0-455a-85f8-937e1705a6e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862782109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3862782109
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.4162163909
Short name T76
Test name
Test status
Simulation time 1667268072 ps
CPU time 22.22 seconds
Started Jun 10 05:41:52 PM PDT 24
Finished Jun 10 05:42:14 PM PDT 24
Peak memory 200468 kb
Host smart-3d413bee-aedd-4117-9618-b2b3b46a5b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162163909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.4162163909
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2147939860
Short name T85
Test name
Test status
Simulation time 3887436737 ps
CPU time 75.59 seconds
Started Jun 10 05:42:49 PM PDT 24
Finished Jun 10 05:44:05 PM PDT 24
Peak memory 200600 kb
Host smart-d37983a8-42cb-4a1e-bd39-91e155009dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147939860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2147939860
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1878651005
Short name T88
Test name
Test status
Simulation time 21894023162 ps
CPU time 68.56 seconds
Started Jun 10 05:41:49 PM PDT 24
Finished Jun 10 05:42:58 PM PDT 24
Peak memory 200636 kb
Host smart-9a9a13a8-761b-4a55-a6a4-4e89c53783ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878651005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1878651005
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2792860752
Short name T694
Test name
Test status
Simulation time 1813571435 ps
CPU time 8.31 seconds
Started Jun 10 05:33:40 PM PDT 24
Finished Jun 10 05:33:48 PM PDT 24
Peak memory 199328 kb
Host smart-dd27a483-e499-470a-8a02-334c2d44f7e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792860752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2792860752
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.78235982
Short name T66
Test name
Test status
Simulation time 213519042 ps
CPU time 9.57 seconds
Started Jun 10 05:33:43 PM PDT 24
Finished Jun 10 05:33:53 PM PDT 24
Peak memory 198428 kb
Host smart-dcb050eb-1abe-42f2-a8f1-c36f0107b119
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78235982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.78235982
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3724142336
Short name T669
Test name
Test status
Simulation time 52787390 ps
CPU time 0.74 seconds
Started Jun 10 05:33:45 PM PDT 24
Finished Jun 10 05:33:46 PM PDT 24
Peak memory 197272 kb
Host smart-3a19547e-55ac-45ff-8809-6e5adc32f5f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724142336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3724142336
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1387078726
Short name T686
Test name
Test status
Simulation time 397779172 ps
CPU time 2.62 seconds
Started Jun 10 05:33:43 PM PDT 24
Finished Jun 10 05:33:46 PM PDT 24
Peak memory 199456 kb
Host smart-aefc0d8b-d466-4ef1-9937-4d264e1dc3ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387078726 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1387078726
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2787833474
Short name T67
Test name
Test status
Simulation time 51710684 ps
CPU time 0.92 seconds
Started Jun 10 05:33:40 PM PDT 24
Finished Jun 10 05:33:41 PM PDT 24
Peak memory 199072 kb
Host smart-83cbf7ac-d80f-4bfe-8f54-57a06ebe4551
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787833474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2787833474
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1987888125
Short name T672
Test name
Test status
Simulation time 39876531 ps
CPU time 0.62 seconds
Started Jun 10 05:33:43 PM PDT 24
Finished Jun 10 05:33:44 PM PDT 24
Peak memory 194256 kb
Host smart-1dbc57b6-9b68-4085-9663-7732b727f1c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987888125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1987888125
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2398975463
Short name T719
Test name
Test status
Simulation time 518458858 ps
CPU time 1.5 seconds
Started Jun 10 05:33:42 PM PDT 24
Finished Jun 10 05:33:44 PM PDT 24
Peak memory 199200 kb
Host smart-ca4b1e5c-17a9-4c9d-91b1-4dd49073fc30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398975463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2398975463
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1892987127
Short name T64
Test name
Test status
Simulation time 122378659 ps
CPU time 1.76 seconds
Started Jun 10 05:33:40 PM PDT 24
Finished Jun 10 05:33:42 PM PDT 24
Peak memory 199380 kb
Host smart-e3b80acd-d6f2-4e66-951d-bf4a2ab2ea34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892987127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1892987127
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.4157229857
Short name T99
Test name
Test status
Simulation time 435622730 ps
CPU time 4.49 seconds
Started Jun 10 05:33:44 PM PDT 24
Finished Jun 10 05:33:49 PM PDT 24
Peak memory 199384 kb
Host smart-97873f19-dc17-4307-af40-3ccc90cb1dee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157229857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.4157229857
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.391250665
Short name T74
Test name
Test status
Simulation time 59488046 ps
CPU time 3.21 seconds
Started Jun 10 05:33:44 PM PDT 24
Finished Jun 10 05:33:48 PM PDT 24
Peak memory 199456 kb
Host smart-f3b3007b-2786-4c5c-b36e-881984b7b3b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391250665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.391250665
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3149011729
Short name T593
Test name
Test status
Simulation time 380167718 ps
CPU time 5.43 seconds
Started Jun 10 05:33:44 PM PDT 24
Finished Jun 10 05:33:49 PM PDT 24
Peak memory 199228 kb
Host smart-42c91b0f-9ef4-4955-8fd6-241f91caf440
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149011729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3149011729
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1713634973
Short name T608
Test name
Test status
Simulation time 47658289 ps
CPU time 0.88 seconds
Started Jun 10 05:33:44 PM PDT 24
Finished Jun 10 05:33:45 PM PDT 24
Peak memory 198704 kb
Host smart-52ff1dbf-5b67-4cde-a481-9a083e3488b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713634973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1713634973
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.4066737610
Short name T713
Test name
Test status
Simulation time 159701763 ps
CPU time 1.27 seconds
Started Jun 10 05:33:45 PM PDT 24
Finished Jun 10 05:33:46 PM PDT 24
Peak memory 199200 kb
Host smart-6cb3c934-7d4a-4f5a-9f27-03195294d469
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066737610 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.4066737610
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1478914880
Short name T652
Test name
Test status
Simulation time 136931496 ps
CPU time 0.94 seconds
Started Jun 10 05:33:45 PM PDT 24
Finished Jun 10 05:33:46 PM PDT 24
Peak memory 198908 kb
Host smart-2bc3f7bc-467f-4625-aecd-75f7c353597d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478914880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1478914880
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2655879405
Short name T647
Test name
Test status
Simulation time 13225182 ps
CPU time 0.6 seconds
Started Jun 10 05:33:42 PM PDT 24
Finished Jun 10 05:33:43 PM PDT 24
Peak memory 194232 kb
Host smart-ff3cd062-06cb-4305-8071-c4869b31f125
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655879405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2655879405
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2084392733
Short name T592
Test name
Test status
Simulation time 21715521 ps
CPU time 1.07 seconds
Started Jun 10 05:33:42 PM PDT 24
Finished Jun 10 05:33:44 PM PDT 24
Peak memory 198036 kb
Host smart-e58ce845-13f4-41ac-8c31-6600168b5ec9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084392733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2084392733
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1256972069
Short name T595
Test name
Test status
Simulation time 94192220 ps
CPU time 2.62 seconds
Started Jun 10 05:33:44 PM PDT 24
Finished Jun 10 05:33:47 PM PDT 24
Peak memory 199532 kb
Host smart-c509619f-e6cb-431f-be46-683f167b1ad0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256972069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1256972069
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2170183707
Short name T635
Test name
Test status
Simulation time 68150770 ps
CPU time 1.17 seconds
Started Jun 10 05:34:14 PM PDT 24
Finished Jun 10 05:34:16 PM PDT 24
Peak memory 199204 kb
Host smart-88d070e1-6085-4ac9-ae2b-aaff1ed36f91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170183707 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2170183707
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.960519022
Short name T615
Test name
Test status
Simulation time 25223606 ps
CPU time 0.71 seconds
Started Jun 10 05:34:11 PM PDT 24
Finished Jun 10 05:34:12 PM PDT 24
Peak memory 197144 kb
Host smart-98d11157-835b-43bf-8fd0-df0f7b8f8074
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960519022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.960519022
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.495514186
Short name T603
Test name
Test status
Simulation time 16509424 ps
CPU time 0.64 seconds
Started Jun 10 05:34:15 PM PDT 24
Finished Jun 10 05:34:16 PM PDT 24
Peak memory 194232 kb
Host smart-249f68c9-e38a-4a21-a5e3-1e8277779898
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495514186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.495514186
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3356296950
Short name T676
Test name
Test status
Simulation time 83207442 ps
CPU time 1.11 seconds
Started Jun 10 05:34:14 PM PDT 24
Finished Jun 10 05:34:16 PM PDT 24
Peak memory 198052 kb
Host smart-047eebb3-e4eb-4eeb-bec2-455734fb8746
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356296950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3356296950
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.867033543
Short name T664
Test name
Test status
Simulation time 451162645 ps
CPU time 2.37 seconds
Started Jun 10 05:34:14 PM PDT 24
Finished Jun 10 05:34:17 PM PDT 24
Peak memory 199360 kb
Host smart-7bf06412-e84a-44b8-89c8-afa6b2444685
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867033543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.867033543
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.4170681642
Short name T39
Test name
Test status
Simulation time 398403063 ps
CPU time 1.89 seconds
Started Jun 10 05:34:13 PM PDT 24
Finished Jun 10 05:34:15 PM PDT 24
Peak memory 199316 kb
Host smart-5355d3f3-96e3-4253-bf17-fede3bd1286d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170681642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.4170681642
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.4142488212
Short name T650
Test name
Test status
Simulation time 64850419 ps
CPU time 2.11 seconds
Started Jun 10 05:34:21 PM PDT 24
Finished Jun 10 05:34:24 PM PDT 24
Peak memory 199324 kb
Host smart-3dd0e6fb-91da-4e93-9206-383581e04808
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142488212 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.4142488212
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1997229772
Short name T716
Test name
Test status
Simulation time 12571117 ps
CPU time 0.6 seconds
Started Jun 10 05:34:18 PM PDT 24
Finished Jun 10 05:34:19 PM PDT 24
Peak memory 194188 kb
Host smart-f62bc9f1-8de2-4ace-ae7d-0f99cdea91c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997229772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1997229772
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4085591994
Short name T626
Test name
Test status
Simulation time 159517921 ps
CPU time 2.16 seconds
Started Jun 10 05:34:23 PM PDT 24
Finished Jun 10 05:34:26 PM PDT 24
Peak memory 199496 kb
Host smart-d26eb460-d1c5-4587-8e7e-7d2f96fe97ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085591994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.4085591994
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1285334910
Short name T675
Test name
Test status
Simulation time 49322227 ps
CPU time 2.48 seconds
Started Jun 10 05:34:16 PM PDT 24
Finished Jun 10 05:34:19 PM PDT 24
Peak memory 199404 kb
Host smart-6948ab19-f842-46c7-8f73-117b3036afc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285334910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1285334910
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3902292742
Short name T712
Test name
Test status
Simulation time 910051245 ps
CPU time 4.51 seconds
Started Jun 10 05:34:21 PM PDT 24
Finished Jun 10 05:34:27 PM PDT 24
Peak memory 199304 kb
Host smart-9bf4673b-fe51-4261-b211-b1e94dc81792
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902292742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3902292742
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.360596017
Short name T621
Test name
Test status
Simulation time 128387675 ps
CPU time 1.12 seconds
Started Jun 10 05:34:17 PM PDT 24
Finished Jun 10 05:34:19 PM PDT 24
Peak memory 199216 kb
Host smart-066f6323-a780-448b-a96d-47af5b777137
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360596017 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.360596017
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3578459896
Short name T73
Test name
Test status
Simulation time 80469771 ps
CPU time 0.85 seconds
Started Jun 10 05:34:17 PM PDT 24
Finished Jun 10 05:34:18 PM PDT 24
Peak memory 198800 kb
Host smart-6130aae0-8078-4e1c-ab61-0fcc559e68dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578459896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3578459896
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1517378079
Short name T723
Test name
Test status
Simulation time 52301537 ps
CPU time 0.6 seconds
Started Jun 10 05:34:18 PM PDT 24
Finished Jun 10 05:34:19 PM PDT 24
Peak memory 194008 kb
Host smart-6f7e65a4-e675-4c92-a540-0f47be1ab9eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517378079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1517378079
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.342910953
Short name T628
Test name
Test status
Simulation time 76049681 ps
CPU time 1.02 seconds
Started Jun 10 05:34:14 PM PDT 24
Finished Jun 10 05:34:15 PM PDT 24
Peak memory 197972 kb
Host smart-436ceba4-2ed9-4442-b2f9-f88d6f7e6c34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342910953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.342910953
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2994512523
Short name T49
Test name
Test status
Simulation time 105401780 ps
CPU time 2.3 seconds
Started Jun 10 05:34:21 PM PDT 24
Finished Jun 10 05:34:24 PM PDT 24
Peak memory 199284 kb
Host smart-97508367-342b-4f9e-b8bc-fb27080360e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994512523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2994512523
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.699116530
Short name T102
Test name
Test status
Simulation time 126034899 ps
CPU time 4.15 seconds
Started Jun 10 05:34:22 PM PDT 24
Finished Jun 10 05:34:27 PM PDT 24
Peak memory 199520 kb
Host smart-c42ad7da-93df-446c-a12f-0f459301cf3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699116530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.699116530
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1769567671
Short name T655
Test name
Test status
Simulation time 38328887 ps
CPU time 1.38 seconds
Started Jun 10 05:34:22 PM PDT 24
Finished Jun 10 05:34:24 PM PDT 24
Peak memory 199208 kb
Host smart-c4b3be14-99bb-4de5-84b8-b5d8b34853a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769567671 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1769567671
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1476685385
Short name T720
Test name
Test status
Simulation time 71683032 ps
CPU time 0.73 seconds
Started Jun 10 05:34:19 PM PDT 24
Finished Jun 10 05:34:20 PM PDT 24
Peak memory 197140 kb
Host smart-d7151b94-e4a7-4f3c-93cc-8ceb0877ee5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476685385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1476685385
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1961773530
Short name T680
Test name
Test status
Simulation time 31156390 ps
CPU time 0.61 seconds
Started Jun 10 05:34:23 PM PDT 24
Finished Jun 10 05:34:24 PM PDT 24
Peak memory 194176 kb
Host smart-098414e8-74da-402f-9926-09352dbaecbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961773530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1961773530
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2488314753
Short name T43
Test name
Test status
Simulation time 24534105 ps
CPU time 1.13 seconds
Started Jun 10 05:34:20 PM PDT 24
Finished Jun 10 05:34:21 PM PDT 24
Peak memory 197788 kb
Host smart-781df9f6-e894-443e-8d52-aaf9118b2d78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488314753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2488314753
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2646115764
Short name T48
Test name
Test status
Simulation time 155212240 ps
CPU time 3.84 seconds
Started Jun 10 05:34:18 PM PDT 24
Finished Jun 10 05:34:22 PM PDT 24
Peak memory 199272 kb
Host smart-eadd4231-4b6f-4538-8dea-31ed3a2abe3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646115764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2646115764
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2220927053
Short name T695
Test name
Test status
Simulation time 247572102 ps
CPU time 3.97 seconds
Started Jun 10 05:34:16 PM PDT 24
Finished Jun 10 05:34:20 PM PDT 24
Peak memory 199340 kb
Host smart-c67f4fd1-8494-4255-a721-61ef444f0071
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220927053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2220927053
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2174635369
Short name T663
Test name
Test status
Simulation time 36940513 ps
CPU time 1.14 seconds
Started Jun 10 05:34:22 PM PDT 24
Finished Jun 10 05:34:24 PM PDT 24
Peak memory 199204 kb
Host smart-268e83de-5cda-4d25-b287-26ccd6166c8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174635369 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2174635369
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1658975403
Short name T70
Test name
Test status
Simulation time 19338360 ps
CPU time 0.72 seconds
Started Jun 10 05:34:22 PM PDT 24
Finished Jun 10 05:34:23 PM PDT 24
Peak memory 197520 kb
Host smart-fc9af88b-a5c7-4483-ac09-c600106d3f4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658975403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1658975403
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1043546125
Short name T689
Test name
Test status
Simulation time 12877059 ps
CPU time 0.6 seconds
Started Jun 10 05:34:26 PM PDT 24
Finished Jun 10 05:34:28 PM PDT 24
Peak memory 194184 kb
Host smart-badc158b-6268-40cd-b68f-1c867315dff5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043546125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1043546125
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2169542499
Short name T609
Test name
Test status
Simulation time 52927739 ps
CPU time 1.21 seconds
Started Jun 10 05:34:20 PM PDT 24
Finished Jun 10 05:34:22 PM PDT 24
Peak memory 199244 kb
Host smart-461f6c79-ae0e-409b-93a5-135c13a0f674
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169542499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2169542499
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1092930050
Short name T641
Test name
Test status
Simulation time 45889885 ps
CPU time 2.31 seconds
Started Jun 10 05:34:22 PM PDT 24
Finished Jun 10 05:34:25 PM PDT 24
Peak memory 199364 kb
Host smart-0d69f313-2089-4fdf-a611-223f169c6991
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092930050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1092930050
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.4131357887
Short name T683
Test name
Test status
Simulation time 143433124 ps
CPU time 1.3 seconds
Started Jun 10 05:34:23 PM PDT 24
Finished Jun 10 05:34:25 PM PDT 24
Peak memory 199404 kb
Host smart-f3bef2b8-3388-4a23-8c32-12f9101ff9fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131357887 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.4131357887
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1820272237
Short name T656
Test name
Test status
Simulation time 32653498 ps
CPU time 0.74 seconds
Started Jun 10 05:34:22 PM PDT 24
Finished Jun 10 05:34:23 PM PDT 24
Peak memory 197448 kb
Host smart-e86558e9-c14b-4c3e-9b43-1655a8a3f57c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820272237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1820272237
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3544632761
Short name T597
Test name
Test status
Simulation time 23125813 ps
CPU time 0.58 seconds
Started Jun 10 05:34:23 PM PDT 24
Finished Jun 10 05:34:24 PM PDT 24
Peak memory 194364 kb
Host smart-5c10b44f-e908-4269-8cf7-a0cfd9b0a363
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544632761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3544632761
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1685657091
Short name T614
Test name
Test status
Simulation time 60724435 ps
CPU time 1.2 seconds
Started Jun 10 05:34:22 PM PDT 24
Finished Jun 10 05:34:24 PM PDT 24
Peak memory 199072 kb
Host smart-0b8a5bb4-3f0a-4fe4-b2f7-69a3188793a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685657091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1685657091
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2940761046
Short name T677
Test name
Test status
Simulation time 3405117965 ps
CPU time 4.06 seconds
Started Jun 10 05:34:21 PM PDT 24
Finished Jun 10 05:34:26 PM PDT 24
Peak memory 199240 kb
Host smart-7767f968-863b-411e-b6f6-d264b9b029e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940761046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2940761046
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.951453533
Short name T631
Test name
Test status
Simulation time 87016598358 ps
CPU time 303.95 seconds
Started Jun 10 05:34:28 PM PDT 24
Finished Jun 10 05:39:33 PM PDT 24
Peak memory 215004 kb
Host smart-070fee7f-bb5c-46c0-aed5-4536d0814f26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951453533 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.951453533
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2156642471
Short name T44
Test name
Test status
Simulation time 35054709 ps
CPU time 0.92 seconds
Started Jun 10 05:34:23 PM PDT 24
Finished Jun 10 05:34:24 PM PDT 24
Peak memory 199080 kb
Host smart-f488aecb-c3cc-4cc6-887a-7d7032886764
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156642471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2156642471
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1970253706
Short name T617
Test name
Test status
Simulation time 30972867 ps
CPU time 0.58 seconds
Started Jun 10 05:34:22 PM PDT 24
Finished Jun 10 05:34:23 PM PDT 24
Peak memory 194160 kb
Host smart-1f7bc6e2-3e15-45c1-b81c-5aa2b2fefcc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970253706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1970253706
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3815336521
Short name T703
Test name
Test status
Simulation time 213244237 ps
CPU time 2.26 seconds
Started Jun 10 05:34:23 PM PDT 24
Finished Jun 10 05:34:26 PM PDT 24
Peak memory 199496 kb
Host smart-47a9dcb0-4c9d-4abc-9c33-648281b44ad7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815336521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3815336521
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.773042327
Short name T666
Test name
Test status
Simulation time 51265517 ps
CPU time 2.75 seconds
Started Jun 10 05:34:23 PM PDT 24
Finished Jun 10 05:34:26 PM PDT 24
Peak memory 199372 kb
Host smart-31531cc3-33b7-4f97-8ae9-b56c56f9ac36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773042327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.773042327
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.4018286346
Short name T707
Test name
Test status
Simulation time 93925073 ps
CPU time 2.97 seconds
Started Jun 10 05:34:23 PM PDT 24
Finished Jun 10 05:34:27 PM PDT 24
Peak memory 199484 kb
Host smart-d6f7b6d9-5259-48a6-87d0-361450c85763
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018286346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.4018286346
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.928381356
Short name T653
Test name
Test status
Simulation time 174391384 ps
CPU time 2.4 seconds
Started Jun 10 05:34:27 PM PDT 24
Finished Jun 10 05:34:30 PM PDT 24
Peak memory 199452 kb
Host smart-82f99b2a-1742-4e36-b0a1-f51a7a654977
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928381356 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.928381356
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1097890680
Short name T644
Test name
Test status
Simulation time 68576700 ps
CPU time 1 seconds
Started Jun 10 05:34:27 PM PDT 24
Finished Jun 10 05:34:29 PM PDT 24
Peak memory 199064 kb
Host smart-a1142b70-5806-45a1-b462-c00fed8cca25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097890680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1097890680
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1748626247
Short name T710
Test name
Test status
Simulation time 25595643 ps
CPU time 0.59 seconds
Started Jun 10 05:34:25 PM PDT 24
Finished Jun 10 05:34:27 PM PDT 24
Peak memory 194200 kb
Host smart-1b67324a-27b9-4b6f-bcdc-59b21e5fce7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748626247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1748626247
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3792617307
Short name T661
Test name
Test status
Simulation time 112033018 ps
CPU time 1.17 seconds
Started Jun 10 05:34:26 PM PDT 24
Finished Jun 10 05:34:28 PM PDT 24
Peak memory 199080 kb
Host smart-32db5ac9-0375-4fe9-9399-47573d2f9e9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792617307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3792617307
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.4062777108
Short name T65
Test name
Test status
Simulation time 390869216 ps
CPU time 2.27 seconds
Started Jun 10 05:34:27 PM PDT 24
Finished Jun 10 05:34:30 PM PDT 24
Peak memory 199392 kb
Host smart-fedbf6d1-5907-4537-aeac-3a8ae8ae0965
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062777108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.4062777108
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.267141209
Short name T45
Test name
Test status
Simulation time 47663514 ps
CPU time 1.75 seconds
Started Jun 10 05:34:26 PM PDT 24
Finished Jun 10 05:34:29 PM PDT 24
Peak memory 199408 kb
Host smart-23957629-8f76-48e1-b284-89b942e823af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267141209 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.267141209
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3256979497
Short name T620
Test name
Test status
Simulation time 57096259 ps
CPU time 0.7 seconds
Started Jun 10 05:34:24 PM PDT 24
Finished Jun 10 05:34:25 PM PDT 24
Peak memory 197088 kb
Host smart-d8b9adac-9410-4c70-bbf1-609674928a5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256979497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3256979497
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3457907826
Short name T725
Test name
Test status
Simulation time 39595365 ps
CPU time 0.62 seconds
Started Jun 10 05:34:26 PM PDT 24
Finished Jun 10 05:34:28 PM PDT 24
Peak memory 194252 kb
Host smart-ba4eb83d-d160-4900-a426-2b81b97d9c1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457907826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3457907826
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1515495068
Short name T667
Test name
Test status
Simulation time 127688704 ps
CPU time 1.68 seconds
Started Jun 10 05:34:30 PM PDT 24
Finished Jun 10 05:34:32 PM PDT 24
Peak memory 199324 kb
Host smart-b0016a7d-bed7-4e10-bdc7-31b18b614d86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515495068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1515495068
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1241030468
Short name T610
Test name
Test status
Simulation time 224407379 ps
CPU time 1.41 seconds
Started Jun 10 05:34:26 PM PDT 24
Finished Jun 10 05:34:29 PM PDT 24
Peak memory 199456 kb
Host smart-13f0819e-e02d-4caa-8217-b744470f791b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241030468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1241030468
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3963639643
Short name T97
Test name
Test status
Simulation time 1602439439 ps
CPU time 1.93 seconds
Started Jun 10 05:34:26 PM PDT 24
Finished Jun 10 05:34:29 PM PDT 24
Peak memory 199372 kb
Host smart-485e28fd-0616-40a2-8240-d2eda1534185
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963639643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3963639643
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3012502658
Short name T62
Test name
Test status
Simulation time 440175114 ps
CPU time 2.27 seconds
Started Jun 10 05:34:29 PM PDT 24
Finished Jun 10 05:34:32 PM PDT 24
Peak memory 199408 kb
Host smart-312d0a8e-06a0-457f-a913-f9464bbb2155
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012502658 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3012502658
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2182961545
Short name T629
Test name
Test status
Simulation time 23259679 ps
CPU time 0.89 seconds
Started Jun 10 05:34:31 PM PDT 24
Finished Jun 10 05:34:32 PM PDT 24
Peak memory 198572 kb
Host smart-58df3061-0792-46f6-8454-a410f5f944f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182961545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2182961545
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1106310786
Short name T679
Test name
Test status
Simulation time 76236753 ps
CPU time 0.61 seconds
Started Jun 10 05:34:27 PM PDT 24
Finished Jun 10 05:34:29 PM PDT 24
Peak memory 194192 kb
Host smart-2df9444e-c1e0-4b49-a0dd-f9223dfbea67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106310786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1106310786
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2377733911
Short name T702
Test name
Test status
Simulation time 44559775 ps
CPU time 2.03 seconds
Started Jun 10 05:34:30 PM PDT 24
Finished Jun 10 05:34:32 PM PDT 24
Peak memory 199332 kb
Host smart-89f83fc5-96cc-48fc-bb2a-ca2f2c5f1e4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377733911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.2377733911
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.940049250
Short name T651
Test name
Test status
Simulation time 1219947804 ps
CPU time 4 seconds
Started Jun 10 05:34:26 PM PDT 24
Finished Jun 10 05:34:31 PM PDT 24
Peak memory 199516 kb
Host smart-b0fd8221-09e6-44e7-a017-041c82af00fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940049250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.940049250
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2542407169
Short name T678
Test name
Test status
Simulation time 183352026 ps
CPU time 1.89 seconds
Started Jun 10 05:34:28 PM PDT 24
Finished Jun 10 05:34:31 PM PDT 24
Peak memory 199392 kb
Host smart-315cb0a6-e0fa-456e-bae6-c2d058bac4bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542407169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2542407169
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4387799
Short name T684
Test name
Test status
Simulation time 154944493 ps
CPU time 8.04 seconds
Started Jun 10 05:33:50 PM PDT 24
Finished Jun 10 05:33:58 PM PDT 24
Peak memory 199248 kb
Host smart-f093d54f-6497-49c6-9e48-9b5bc4d2ab66
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4387799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.4387799
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1219165780
Short name T717
Test name
Test status
Simulation time 109969281 ps
CPU time 5.33 seconds
Started Jun 10 05:33:55 PM PDT 24
Finished Jun 10 05:34:01 PM PDT 24
Peak memory 199336 kb
Host smart-2eb1c4a1-053c-40ae-b6e9-17d8f4682e42
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219165780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1219165780
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2762808798
Short name T71
Test name
Test status
Simulation time 71570140 ps
CPU time 1.01 seconds
Started Jun 10 05:33:48 PM PDT 24
Finished Jun 10 05:33:49 PM PDT 24
Peak memory 198800 kb
Host smart-e44aed01-5119-467f-a489-a82e357aad4d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762808798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2762808798
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1028470197
Short name T671
Test name
Test status
Simulation time 21153203 ps
CPU time 1.2 seconds
Started Jun 10 05:33:50 PM PDT 24
Finished Jun 10 05:33:51 PM PDT 24
Peak memory 199064 kb
Host smart-9acd5324-c95b-46f8-aff5-10a1bf64a94b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028470197 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1028470197
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2622316700
Short name T606
Test name
Test status
Simulation time 31197840 ps
CPU time 0.96 seconds
Started Jun 10 05:33:46 PM PDT 24
Finished Jun 10 05:33:47 PM PDT 24
Peak memory 199040 kb
Host smart-9955f8bb-7c59-46a7-8a53-0de8459e45d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622316700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2622316700
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2878243439
Short name T622
Test name
Test status
Simulation time 51242679 ps
CPU time 0.59 seconds
Started Jun 10 05:33:48 PM PDT 24
Finished Jun 10 05:33:49 PM PDT 24
Peak memory 194228 kb
Host smart-746ab661-4573-4c24-bb06-cd40a16a1268
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878243439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2878243439
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1082499016
Short name T639
Test name
Test status
Simulation time 129502734 ps
CPU time 2.22 seconds
Started Jun 10 05:33:52 PM PDT 24
Finished Jun 10 05:33:55 PM PDT 24
Peak memory 199404 kb
Host smart-97c90675-35ab-4ad1-a158-a33ed29b56cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082499016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1082499016
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1338032865
Short name T642
Test name
Test status
Simulation time 872399721 ps
CPU time 4.54 seconds
Started Jun 10 05:33:47 PM PDT 24
Finished Jun 10 05:33:52 PM PDT 24
Peak memory 199404 kb
Host smart-a3f44590-8188-4078-8ac9-ca21a91cb980
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338032865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1338032865
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3065565828
Short name T649
Test name
Test status
Simulation time 436444824 ps
CPU time 2.88 seconds
Started Jun 10 05:33:47 PM PDT 24
Finished Jun 10 05:33:51 PM PDT 24
Peak memory 199356 kb
Host smart-6233b464-b5a9-40a2-8048-8b7a763a3900
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065565828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3065565828
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3512553574
Short name T601
Test name
Test status
Simulation time 59085136 ps
CPU time 0.62 seconds
Started Jun 10 05:34:31 PM PDT 24
Finished Jun 10 05:34:31 PM PDT 24
Peak memory 194276 kb
Host smart-54c69f9a-2ff3-4ebc-8a44-6ac44369aa88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512553574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3512553574
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1007014661
Short name T611
Test name
Test status
Simulation time 23951099 ps
CPU time 0.61 seconds
Started Jun 10 05:34:38 PM PDT 24
Finished Jun 10 05:34:39 PM PDT 24
Peak memory 194192 kb
Host smart-db6dac6a-3cc3-4132-a690-e9c48717fad9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007014661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1007014661
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.2067449420
Short name T618
Test name
Test status
Simulation time 10786765 ps
CPU time 0.58 seconds
Started Jun 10 05:34:30 PM PDT 24
Finished Jun 10 05:34:31 PM PDT 24
Peak memory 194268 kb
Host smart-28fbaab3-8246-43e7-bb06-2632a142a687
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067449420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2067449420
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.862406810
Short name T699
Test name
Test status
Simulation time 11912678 ps
CPU time 0.62 seconds
Started Jun 10 05:34:31 PM PDT 24
Finished Jun 10 05:34:32 PM PDT 24
Peak memory 194352 kb
Host smart-5640f263-54a5-4a6c-b233-8ced0898d717
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862406810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.862406810
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3929686590
Short name T705
Test name
Test status
Simulation time 166145775 ps
CPU time 0.6 seconds
Started Jun 10 05:34:32 PM PDT 24
Finished Jun 10 05:34:33 PM PDT 24
Peak memory 194412 kb
Host smart-93d3bc14-c58b-4210-a5a8-723e4de76cd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929686590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3929686590
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.536475402
Short name T634
Test name
Test status
Simulation time 13319644 ps
CPU time 0.61 seconds
Started Jun 10 05:34:32 PM PDT 24
Finished Jun 10 05:34:33 PM PDT 24
Peak memory 194276 kb
Host smart-dbed437a-6b50-4565-a3e8-de430691be27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536475402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.536475402
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.4047869942
Short name T637
Test name
Test status
Simulation time 49455822 ps
CPU time 0.62 seconds
Started Jun 10 05:34:29 PM PDT 24
Finished Jun 10 05:34:30 PM PDT 24
Peak memory 194120 kb
Host smart-07eb22de-7988-4d20-bc7f-da9fc24a4d9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047869942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.4047869942
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2281999796
Short name T714
Test name
Test status
Simulation time 46627278 ps
CPU time 0.59 seconds
Started Jun 10 05:34:30 PM PDT 24
Finished Jun 10 05:34:31 PM PDT 24
Peak memory 194200 kb
Host smart-b068d8fe-894b-4241-b6f1-a416b0765d94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281999796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2281999796
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.4218202696
Short name T612
Test name
Test status
Simulation time 16078510 ps
CPU time 0.61 seconds
Started Jun 10 05:34:31 PM PDT 24
Finished Jun 10 05:34:32 PM PDT 24
Peak memory 194412 kb
Host smart-014de64a-9760-454d-a065-bbdfb80cd887
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218202696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.4218202696
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1975551523
Short name T616
Test name
Test status
Simulation time 48200440 ps
CPU time 0.62 seconds
Started Jun 10 05:34:33 PM PDT 24
Finished Jun 10 05:34:34 PM PDT 24
Peak memory 194176 kb
Host smart-5c6d0512-6d2a-4730-9d7c-d050856da122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975551523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1975551523
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2705466529
Short name T69
Test name
Test status
Simulation time 1489210560 ps
CPU time 5.95 seconds
Started Jun 10 05:33:55 PM PDT 24
Finished Jun 10 05:34:01 PM PDT 24
Peak memory 199316 kb
Host smart-78a2ca6f-5481-4fa0-b324-0fb313229ea4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705466529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2705466529
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1540773187
Short name T598
Test name
Test status
Simulation time 110843442 ps
CPU time 5.27 seconds
Started Jun 10 05:33:54 PM PDT 24
Finished Jun 10 05:34:00 PM PDT 24
Peak memory 199300 kb
Host smart-12e0e735-ac18-4560-b16e-2dfb2277b3d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540773187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1540773187
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.976804413
Short name T68
Test name
Test status
Simulation time 68227031 ps
CPU time 0.88 seconds
Started Jun 10 05:33:52 PM PDT 24
Finished Jun 10 05:33:53 PM PDT 24
Peak memory 198200 kb
Host smart-14eb2717-e917-464b-bf8d-eed48f173b6d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976804413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.976804413
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3338424884
Short name T660
Test name
Test status
Simulation time 23420454 ps
CPU time 1.34 seconds
Started Jun 10 05:33:58 PM PDT 24
Finished Jun 10 05:34:00 PM PDT 24
Peak memory 199408 kb
Host smart-43b3d99a-2e00-48c8-a01e-a7d23fa4be11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338424884 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.3338424884
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.832753773
Short name T619
Test name
Test status
Simulation time 14801558 ps
CPU time 0.82 seconds
Started Jun 10 05:33:50 PM PDT 24
Finished Jun 10 05:33:51 PM PDT 24
Peak memory 199044 kb
Host smart-1bdc2262-c193-462a-9581-96f4dc59c5a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832753773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.832753773
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.4034845822
Short name T643
Test name
Test status
Simulation time 17985430 ps
CPU time 0.64 seconds
Started Jun 10 05:33:52 PM PDT 24
Finished Jun 10 05:33:52 PM PDT 24
Peak memory 194236 kb
Host smart-65692e53-be87-446e-84ee-cde710b9501e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034845822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.4034845822
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4078925882
Short name T630
Test name
Test status
Simulation time 79045806 ps
CPU time 1.14 seconds
Started Jun 10 05:33:56 PM PDT 24
Finished Jun 10 05:33:57 PM PDT 24
Peak memory 197812 kb
Host smart-ac8e8c23-3255-44b3-9ddb-3d497e6e9d8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078925882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.4078925882
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.718541287
Short name T599
Test name
Test status
Simulation time 90766975 ps
CPU time 1.84 seconds
Started Jun 10 05:33:54 PM PDT 24
Finished Jun 10 05:33:56 PM PDT 24
Peak memory 199516 kb
Host smart-f42d214d-0384-45ac-83be-0d83fa692a65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718541287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.718541287
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2658612986
Short name T96
Test name
Test status
Simulation time 138547315 ps
CPU time 3.92 seconds
Started Jun 10 05:33:50 PM PDT 24
Finished Jun 10 05:33:54 PM PDT 24
Peak memory 199320 kb
Host smart-ea580159-451b-4651-88fa-f25f42438e09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658612986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2658612986
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2273804622
Short name T596
Test name
Test status
Simulation time 40165102 ps
CPU time 0.6 seconds
Started Jun 10 05:34:38 PM PDT 24
Finished Jun 10 05:34:39 PM PDT 24
Peak memory 194200 kb
Host smart-dab13a15-469b-4304-8fb2-a75074404423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273804622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2273804622
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.517199051
Short name T673
Test name
Test status
Simulation time 79227280 ps
CPU time 0.62 seconds
Started Jun 10 05:34:36 PM PDT 24
Finished Jun 10 05:34:37 PM PDT 24
Peak memory 194324 kb
Host smart-a340b94a-500f-4130-be14-89d3c2a0bfe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517199051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.517199051
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.2452777731
Short name T605
Test name
Test status
Simulation time 76190593 ps
CPU time 0.6 seconds
Started Jun 10 05:34:36 PM PDT 24
Finished Jun 10 05:34:37 PM PDT 24
Peak memory 194208 kb
Host smart-d8317d0c-fbcf-41a4-af72-50a7c89dab30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452777731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.2452777731
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2605455838
Short name T704
Test name
Test status
Simulation time 13117795 ps
CPU time 0.6 seconds
Started Jun 10 05:34:36 PM PDT 24
Finished Jun 10 05:34:37 PM PDT 24
Peak memory 194312 kb
Host smart-62766b07-58bf-47cb-986e-28e5682c8112
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605455838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2605455838
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3340222683
Short name T682
Test name
Test status
Simulation time 34049996 ps
CPU time 0.62 seconds
Started Jun 10 05:34:37 PM PDT 24
Finished Jun 10 05:34:38 PM PDT 24
Peak memory 194340 kb
Host smart-abd86d54-ee39-402a-a8c2-f98abff61bb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340222683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3340222683
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2870401592
Short name T691
Test name
Test status
Simulation time 45329210 ps
CPU time 0.64 seconds
Started Jun 10 05:34:35 PM PDT 24
Finished Jun 10 05:34:36 PM PDT 24
Peak memory 194280 kb
Host smart-78fdbd38-2484-493e-b48d-5a00cf747f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870401592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2870401592
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3899467514
Short name T613
Test name
Test status
Simulation time 79928354 ps
CPU time 0.57 seconds
Started Jun 10 05:34:38 PM PDT 24
Finished Jun 10 05:34:39 PM PDT 24
Peak memory 194236 kb
Host smart-d19e02d4-b46b-4386-8147-9761bda14a70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899467514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3899467514
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1749787413
Short name T722
Test name
Test status
Simulation time 24120779 ps
CPU time 0.59 seconds
Started Jun 10 05:34:36 PM PDT 24
Finished Jun 10 05:34:37 PM PDT 24
Peak memory 194100 kb
Host smart-60219bd0-b7de-4a9c-9f6c-71367c2eedd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749787413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1749787413
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2394499038
Short name T674
Test name
Test status
Simulation time 11631905 ps
CPU time 0.6 seconds
Started Jun 10 05:34:38 PM PDT 24
Finished Jun 10 05:34:39 PM PDT 24
Peak memory 194252 kb
Host smart-61cd4fa6-8273-4979-8df7-97429c935893
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394499038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2394499038
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.625160328
Short name T602
Test name
Test status
Simulation time 36974725 ps
CPU time 0.58 seconds
Started Jun 10 05:34:34 PM PDT 24
Finished Jun 10 05:34:35 PM PDT 24
Peak memory 194168 kb
Host smart-4f1a8fb2-e4ae-4813-a030-607d6f951de1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625160328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.625160328
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2619480492
Short name T46
Test name
Test status
Simulation time 239578660 ps
CPU time 3.08 seconds
Started Jun 10 05:34:02 PM PDT 24
Finished Jun 10 05:34:06 PM PDT 24
Peak memory 199268 kb
Host smart-dcee6b10-6847-40c3-ada3-7b7306dc7586
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619480492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2619480492
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2728942560
Short name T72
Test name
Test status
Simulation time 861788709 ps
CPU time 9.77 seconds
Started Jun 10 05:34:04 PM PDT 24
Finished Jun 10 05:34:15 PM PDT 24
Peak memory 199148 kb
Host smart-83fd761d-d90f-4475-bb50-8cba23cc2cad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728942560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2728942560
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1351711152
Short name T645
Test name
Test status
Simulation time 29438535 ps
CPU time 0.88 seconds
Started Jun 10 05:33:58 PM PDT 24
Finished Jun 10 05:33:59 PM PDT 24
Peak memory 198252 kb
Host smart-de667f0e-839a-4b86-bc17-62655b13b08e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351711152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1351711152
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3315108105
Short name T659
Test name
Test status
Simulation time 339700487 ps
CPU time 2.36 seconds
Started Jun 10 05:33:58 PM PDT 24
Finished Jun 10 05:34:01 PM PDT 24
Peak memory 199408 kb
Host smart-73d12425-2ab0-4f3d-9802-4574ea5bc76f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315108105 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3315108105
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.842914732
Short name T627
Test name
Test status
Simulation time 19561671 ps
CPU time 0.71 seconds
Started Jun 10 05:33:59 PM PDT 24
Finished Jun 10 05:34:00 PM PDT 24
Peak memory 197056 kb
Host smart-127b8fd0-2949-46a0-b8ec-7e8f3e2b0c07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842914732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.842914732
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3525386350
Short name T648
Test name
Test status
Simulation time 38646743 ps
CPU time 0.59 seconds
Started Jun 10 05:33:58 PM PDT 24
Finished Jun 10 05:33:59 PM PDT 24
Peak memory 194156 kb
Host smart-2f434c61-a025-451b-840e-89b30e37e1b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525386350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3525386350
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3327128080
Short name T700
Test name
Test status
Simulation time 88808395 ps
CPU time 2.09 seconds
Started Jun 10 05:33:59 PM PDT 24
Finished Jun 10 05:34:01 PM PDT 24
Peak memory 199376 kb
Host smart-5a32311f-0656-418e-960e-31b145fcffdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327128080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3327128080
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1104765083
Short name T665
Test name
Test status
Simulation time 65983446 ps
CPU time 3.53 seconds
Started Jun 10 05:34:31 PM PDT 24
Finished Jun 10 05:34:35 PM PDT 24
Peak memory 199376 kb
Host smart-1ec0a75e-fbee-4163-97cb-39c414717ad6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104765083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1104765083
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2097097885
Short name T100
Test name
Test status
Simulation time 227436135 ps
CPU time 4.51 seconds
Started Jun 10 05:33:59 PM PDT 24
Finished Jun 10 05:34:03 PM PDT 24
Peak memory 199360 kb
Host smart-9af6bab3-a996-477a-bacc-a164635ef245
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097097885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2097097885
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3929982769
Short name T638
Test name
Test status
Simulation time 86627041 ps
CPU time 0.62 seconds
Started Jun 10 05:34:35 PM PDT 24
Finished Jun 10 05:34:36 PM PDT 24
Peak memory 194340 kb
Host smart-84192db8-a82d-44b1-866a-71b414d35fce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929982769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3929982769
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2649307037
Short name T624
Test name
Test status
Simulation time 24077372 ps
CPU time 0.68 seconds
Started Jun 10 05:34:39 PM PDT 24
Finished Jun 10 05:34:40 PM PDT 24
Peak memory 194212 kb
Host smart-cc2e3b55-adda-4b3f-a9b8-4466cf19b798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649307037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2649307037
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2435361352
Short name T633
Test name
Test status
Simulation time 39752326 ps
CPU time 0.6 seconds
Started Jun 10 05:34:40 PM PDT 24
Finished Jun 10 05:34:41 PM PDT 24
Peak memory 194224 kb
Host smart-2b0b3900-795f-47ea-b905-9bdd6f47a7d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435361352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2435361352
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2945441887
Short name T715
Test name
Test status
Simulation time 67014288 ps
CPU time 0.59 seconds
Started Jun 10 05:34:37 PM PDT 24
Finished Jun 10 05:34:38 PM PDT 24
Peak memory 194204 kb
Host smart-cce078c5-5091-4a87-a030-f67fe9a3c7bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945441887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2945441887
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3563311344
Short name T709
Test name
Test status
Simulation time 110928264 ps
CPU time 0.61 seconds
Started Jun 10 05:34:34 PM PDT 24
Finished Jun 10 05:34:35 PM PDT 24
Peak memory 194188 kb
Host smart-cdd999fe-4844-43c9-a858-6e2a8b382845
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563311344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3563311344
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1273338149
Short name T668
Test name
Test status
Simulation time 18248366 ps
CPU time 0.57 seconds
Started Jun 10 05:34:36 PM PDT 24
Finished Jun 10 05:34:37 PM PDT 24
Peak memory 194208 kb
Host smart-0bd574d9-059c-4509-9302-a220d748e25d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273338149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1273338149
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.71262239
Short name T711
Test name
Test status
Simulation time 21761710 ps
CPU time 0.63 seconds
Started Jun 10 05:34:37 PM PDT 24
Finished Jun 10 05:34:38 PM PDT 24
Peak memory 194260 kb
Host smart-703e9e86-6ae1-49a6-a434-f8080e8313c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71262239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.71262239
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3304120287
Short name T594
Test name
Test status
Simulation time 57450765 ps
CPU time 0.6 seconds
Started Jun 10 05:34:39 PM PDT 24
Finished Jun 10 05:34:40 PM PDT 24
Peak memory 194252 kb
Host smart-c8a90012-6171-4f20-af36-13191e440571
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304120287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3304120287
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3666415195
Short name T724
Test name
Test status
Simulation time 13525375 ps
CPU time 0.58 seconds
Started Jun 10 05:34:39 PM PDT 24
Finished Jun 10 05:34:40 PM PDT 24
Peak memory 194180 kb
Host smart-5f57fcaa-0626-4c6a-a35c-fcad2f3c358a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666415195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3666415195
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1808275213
Short name T706
Test name
Test status
Simulation time 18762054 ps
CPU time 0.61 seconds
Started Jun 10 05:34:38 PM PDT 24
Finished Jun 10 05:34:39 PM PDT 24
Peak memory 194244 kb
Host smart-0a9fce20-9d02-4f8f-8f24-c94e1da1fbeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808275213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1808275213
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.825751181
Short name T697
Test name
Test status
Simulation time 17059456781 ps
CPU time 176.52 seconds
Started Jun 10 05:34:03 PM PDT 24
Finished Jun 10 05:37:00 PM PDT 24
Peak memory 215828 kb
Host smart-115a806d-323e-4317-bcb9-58106cd3cbb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825751181 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.825751181
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3802455324
Short name T75
Test name
Test status
Simulation time 71689227 ps
CPU time 0.74 seconds
Started Jun 10 05:33:59 PM PDT 24
Finished Jun 10 05:34:00 PM PDT 24
Peak memory 197180 kb
Host smart-566a5a12-f231-4f65-9403-321ebb6eae4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802455324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3802455324
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1453752019
Short name T636
Test name
Test status
Simulation time 14195861 ps
CPU time 0.59 seconds
Started Jun 10 05:34:03 PM PDT 24
Finished Jun 10 05:34:04 PM PDT 24
Peak memory 194204 kb
Host smart-b764644d-b36d-4bf2-b64b-e37de4a956d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453752019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1453752019
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2375112935
Short name T607
Test name
Test status
Simulation time 289897368 ps
CPU time 1.72 seconds
Started Jun 10 05:34:02 PM PDT 24
Finished Jun 10 05:34:04 PM PDT 24
Peak memory 199348 kb
Host smart-855b6d50-8c8e-491f-b9d3-78342608f2d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375112935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2375112935
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3281819862
Short name T693
Test name
Test status
Simulation time 52345512 ps
CPU time 2.83 seconds
Started Jun 10 05:34:01 PM PDT 24
Finished Jun 10 05:34:04 PM PDT 24
Peak memory 199400 kb
Host smart-2ddd20c6-ba0e-46e0-b92d-8321ab59376a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281819862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3281819862
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.4234755245
Short name T103
Test name
Test status
Simulation time 96417342 ps
CPU time 1.72 seconds
Started Jun 10 05:34:02 PM PDT 24
Finished Jun 10 05:34:04 PM PDT 24
Peak memory 199348 kb
Host smart-5a5ceda2-ba3e-47ab-b295-c5177a076ff0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234755245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.4234755245
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3973405910
Short name T623
Test name
Test status
Simulation time 284730697 ps
CPU time 1.89 seconds
Started Jun 10 05:34:06 PM PDT 24
Finished Jun 10 05:34:08 PM PDT 24
Peak memory 199408 kb
Host smart-01aba976-6a1c-404e-94e2-34a6e5d44161
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973405910 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3973405910
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2335070423
Short name T662
Test name
Test status
Simulation time 37879406 ps
CPU time 0.81 seconds
Started Jun 10 05:34:05 PM PDT 24
Finished Jun 10 05:34:06 PM PDT 24
Peak memory 198676 kb
Host smart-fa20199e-bebb-481a-b3ec-afb03e34cb0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335070423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2335070423
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.4123201669
Short name T670
Test name
Test status
Simulation time 18984022 ps
CPU time 0.57 seconds
Started Jun 10 05:33:59 PM PDT 24
Finished Jun 10 05:34:00 PM PDT 24
Peak memory 194224 kb
Host smart-dd0d3483-5a5b-4251-bc95-92d1625ca852
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123201669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.4123201669
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2755476708
Short name T698
Test name
Test status
Simulation time 108789874 ps
CPU time 2.32 seconds
Started Jun 10 05:34:04 PM PDT 24
Finished Jun 10 05:34:07 PM PDT 24
Peak memory 199336 kb
Host smart-f2ace71a-3dd8-4bfe-af8b-45866f06794c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755476708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2755476708
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3630642354
Short name T685
Test name
Test status
Simulation time 209385750 ps
CPU time 3.81 seconds
Started Jun 10 05:34:04 PM PDT 24
Finished Jun 10 05:34:09 PM PDT 24
Peak memory 199288 kb
Host smart-98e1b3b3-bb69-442a-917c-e88ce8f9d05a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630642354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3630642354
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2356232406
Short name T654
Test name
Test status
Simulation time 48335434 ps
CPU time 1.78 seconds
Started Jun 10 05:34:05 PM PDT 24
Finished Jun 10 05:34:07 PM PDT 24
Peak memory 199332 kb
Host smart-920ee15c-1c50-404f-9844-942ec540f19f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356232406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2356232406
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3045509206
Short name T625
Test name
Test status
Simulation time 128847417998 ps
CPU time 890.02 seconds
Started Jun 10 05:34:04 PM PDT 24
Finished Jun 10 05:48:54 PM PDT 24
Peak memory 224056 kb
Host smart-58ab5295-0ec6-4a8e-a741-f32a1a552171
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045509206 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3045509206
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2465793900
Short name T688
Test name
Test status
Simulation time 51492136 ps
CPU time 0.81 seconds
Started Jun 10 05:34:06 PM PDT 24
Finished Jun 10 05:34:07 PM PDT 24
Peak memory 198512 kb
Host smart-c96d9ddc-c76c-4b72-9016-9b63f8e0eb1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465793900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2465793900
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2503865056
Short name T640
Test name
Test status
Simulation time 41191654 ps
CPU time 0.62 seconds
Started Jun 10 05:34:05 PM PDT 24
Finished Jun 10 05:34:06 PM PDT 24
Peak memory 194220 kb
Host smart-92a78d15-3b0c-4548-abae-880e4dda2aa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503865056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2503865056
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2596873239
Short name T701
Test name
Test status
Simulation time 559118961 ps
CPU time 2.42 seconds
Started Jun 10 05:34:06 PM PDT 24
Finished Jun 10 05:34:09 PM PDT 24
Peak memory 199304 kb
Host smart-e2c16c87-821c-4850-b6cc-1b715dd578e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596873239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2596873239
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.603932485
Short name T718
Test name
Test status
Simulation time 61446498 ps
CPU time 1.43 seconds
Started Jun 10 05:34:06 PM PDT 24
Finished Jun 10 05:34:08 PM PDT 24
Peak memory 199380 kb
Host smart-d18fdec4-b3c7-41d9-8ed5-ee259daa630a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603932485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.603932485
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2686868983
Short name T708
Test name
Test status
Simulation time 929188050 ps
CPU time 1.96 seconds
Started Jun 10 05:34:05 PM PDT 24
Finished Jun 10 05:34:07 PM PDT 24
Peak memory 199312 kb
Host smart-7ef5dc02-aa2b-4dd0-9cc9-63b62f10b41e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686868983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2686868983
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1381244804
Short name T657
Test name
Test status
Simulation time 39633600 ps
CPU time 1.91 seconds
Started Jun 10 05:34:09 PM PDT 24
Finished Jun 10 05:34:11 PM PDT 24
Peak memory 199404 kb
Host smart-79474d99-c6c7-4cda-be3c-9520437057eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381244804 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.1381244804
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.4176194454
Short name T658
Test name
Test status
Simulation time 67952758 ps
CPU time 0.72 seconds
Started Jun 10 05:34:04 PM PDT 24
Finished Jun 10 05:34:05 PM PDT 24
Peak memory 197140 kb
Host smart-3494bc1a-e681-4586-be30-b24e26359b21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176194454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.4176194454
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.414040283
Short name T696
Test name
Test status
Simulation time 21234117 ps
CPU time 0.59 seconds
Started Jun 10 05:34:06 PM PDT 24
Finished Jun 10 05:34:07 PM PDT 24
Peak memory 194212 kb
Host smart-c4a5d1fe-f919-49d4-afec-c730f7e8e40a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414040283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.414040283
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3160979557
Short name T687
Test name
Test status
Simulation time 157099230 ps
CPU time 1.22 seconds
Started Jun 10 05:34:09 PM PDT 24
Finished Jun 10 05:34:11 PM PDT 24
Peak memory 197840 kb
Host smart-ddfdb1a8-6dad-4a45-bfaf-4a7cf65d8935
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160979557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3160979557
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.273118996
Short name T600
Test name
Test status
Simulation time 895625762 ps
CPU time 2.64 seconds
Started Jun 10 05:34:05 PM PDT 24
Finished Jun 10 05:34:09 PM PDT 24
Peak memory 199388 kb
Host smart-5560f8e4-b7c1-408c-8202-71005471e159
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273118996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.273118996
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.4186712765
Short name T692
Test name
Test status
Simulation time 376015946 ps
CPU time 1.97 seconds
Started Jun 10 05:34:06 PM PDT 24
Finished Jun 10 05:34:08 PM PDT 24
Peak memory 199400 kb
Host smart-f8cdf48b-9875-4bf0-af39-e3683a605620
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186712765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.4186712765
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.934444330
Short name T632
Test name
Test status
Simulation time 36059223 ps
CPU time 1.17 seconds
Started Jun 10 05:34:13 PM PDT 24
Finished Jun 10 05:34:14 PM PDT 24
Peak memory 199200 kb
Host smart-e54fa09e-dfe0-46cc-9162-5af5e28aed96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934444330 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.934444330
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2443234251
Short name T690
Test name
Test status
Simulation time 117784942 ps
CPU time 0.7 seconds
Started Jun 10 05:34:09 PM PDT 24
Finished Jun 10 05:34:10 PM PDT 24
Peak memory 196800 kb
Host smart-e8c03016-4ab0-4af8-846c-6b88d25e560b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443234251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2443234251
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.3288214547
Short name T681
Test name
Test status
Simulation time 44984948 ps
CPU time 0.59 seconds
Started Jun 10 05:34:08 PM PDT 24
Finished Jun 10 05:34:09 PM PDT 24
Peak memory 194252 kb
Host smart-a2cb0629-5ce6-4498-a90b-ef43d5c24ebb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288214547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3288214547
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2357374813
Short name T721
Test name
Test status
Simulation time 68199661 ps
CPU time 0.99 seconds
Started Jun 10 05:34:09 PM PDT 24
Finished Jun 10 05:34:10 PM PDT 24
Peak memory 197748 kb
Host smart-71ef3094-2153-448f-b548-37118d09f1e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357374813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2357374813
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.346060059
Short name T604
Test name
Test status
Simulation time 196138251 ps
CPU time 3.05 seconds
Started Jun 10 05:34:07 PM PDT 24
Finished Jun 10 05:34:10 PM PDT 24
Peak memory 199336 kb
Host smart-144a6c04-2edc-4e2c-b36f-4d07bd218388
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346060059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.346060059
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.657358559
Short name T646
Test name
Test status
Simulation time 226885084 ps
CPU time 4.53 seconds
Started Jun 10 05:34:07 PM PDT 24
Finished Jun 10 05:34:12 PM PDT 24
Peak memory 199252 kb
Host smart-dd1e65d6-6986-4dd4-ba0b-2443d1821989
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657358559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.657358559
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3142022209
Short name T245
Test name
Test status
Simulation time 45821917 ps
CPU time 0.61 seconds
Started Jun 10 05:41:53 PM PDT 24
Finished Jun 10 05:41:55 PM PDT 24
Peak memory 197120 kb
Host smart-706ff28d-91b5-4b8f-847e-831bf0de74e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142022209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3142022209
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2220389123
Short name T325
Test name
Test status
Simulation time 200332405 ps
CPU time 9.64 seconds
Started Jun 10 05:41:39 PM PDT 24
Finished Jun 10 05:41:49 PM PDT 24
Peak memory 208344 kb
Host smart-5d947122-ae61-463a-9941-a52307d28e1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2220389123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2220389123
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1399386127
Short name T508
Test name
Test status
Simulation time 16355774750 ps
CPU time 41.49 seconds
Started Jun 10 05:41:50 PM PDT 24
Finished Jun 10 05:42:32 PM PDT 24
Peak memory 200288 kb
Host smart-0f2d43b8-0728-4aa2-aa0e-0aceb54d49cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399386127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1399386127
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1809746656
Short name T125
Test name
Test status
Simulation time 673700918 ps
CPU time 46.19 seconds
Started Jun 10 05:41:38 PM PDT 24
Finished Jun 10 05:42:25 PM PDT 24
Peak memory 329188 kb
Host smart-c05dd7bd-8608-45d0-8232-e08620861f9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1809746656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1809746656
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.312301066
Short name T136
Test name
Test status
Simulation time 14829561441 ps
CPU time 47.33 seconds
Started Jun 10 05:41:38 PM PDT 24
Finished Jun 10 05:42:25 PM PDT 24
Peak memory 200648 kb
Host smart-b6383fa2-8e8e-4a65-ab48-6b1f73ac8978
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312301066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.312301066
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.2805530158
Short name T286
Test name
Test status
Simulation time 4361637194 ps
CPU time 89.08 seconds
Started Jun 10 05:41:57 PM PDT 24
Finished Jun 10 05:43:26 PM PDT 24
Peak memory 200408 kb
Host smart-fc1f35e3-7a90-4729-9d56-6700db373a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805530158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.2805530158
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2976397194
Short name T22
Test name
Test status
Simulation time 423480863 ps
CPU time 0.94 seconds
Started Jun 10 05:41:54 PM PDT 24
Finished Jun 10 05:41:56 PM PDT 24
Peak memory 219000 kb
Host smart-506922bb-5c03-4e97-8a32-ef9ff519bf7f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976397194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2976397194
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.1874265193
Short name T548
Test name
Test status
Simulation time 264265367 ps
CPU time 2.82 seconds
Started Jun 10 05:41:55 PM PDT 24
Finished Jun 10 05:41:59 PM PDT 24
Peak memory 200472 kb
Host smart-e338b14f-c2f1-463d-bc24-be4be2a25d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874265193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1874265193
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3846430131
Short name T121
Test name
Test status
Simulation time 191785702 ps
CPU time 10.18 seconds
Started Jun 10 05:41:41 PM PDT 24
Finished Jun 10 05:41:52 PM PDT 24
Peak memory 200332 kb
Host smart-18294efb-4c15-474c-abd0-d9464e90033e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846430131 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3846430131
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1714771407
Short name T107
Test name
Test status
Simulation time 367232407 ps
CPU time 1.4 seconds
Started Jun 10 05:41:50 PM PDT 24
Finished Jun 10 05:41:58 PM PDT 24
Peak memory 200356 kb
Host smart-6a6bfde5-e477-408e-a014-278e5877b532
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714771407 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.1714771407
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.612033622
Short name T398
Test name
Test status
Simulation time 33665047574 ps
CPU time 499.43 seconds
Started Jun 10 05:41:41 PM PDT 24
Finished Jun 10 05:50:01 PM PDT 24
Peak memory 200400 kb
Host smart-a9a2a208-c742-4eca-a5d2-e092076df92b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612033622 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.612033622
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3420841577
Short name T259
Test name
Test status
Simulation time 3870313965 ps
CPU time 73.12 seconds
Started Jun 10 05:41:39 PM PDT 24
Finished Jun 10 05:42:53 PM PDT 24
Peak memory 200484 kb
Host smart-57820a3a-677b-4929-b353-13070089248c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420841577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3420841577
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3097361001
Short name T180
Test name
Test status
Simulation time 43405645 ps
CPU time 0.61 seconds
Started Jun 10 05:41:52 PM PDT 24
Finished Jun 10 05:41:53 PM PDT 24
Peak memory 197072 kb
Host smart-f1177401-7c0d-449d-a9fb-80403f83aad5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097361001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3097361001
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.1454866324
Short name T301
Test name
Test status
Simulation time 316156579 ps
CPU time 21.13 seconds
Started Jun 10 05:41:52 PM PDT 24
Finished Jun 10 05:42:14 PM PDT 24
Peak memory 233080 kb
Host smart-e76a8170-c805-46e3-9672-a672595e5af9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1454866324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1454866324
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3259293603
Short name T408
Test name
Test status
Simulation time 683107031 ps
CPU time 169.29 seconds
Started Jun 10 05:41:40 PM PDT 24
Finished Jun 10 05:44:29 PM PDT 24
Peak memory 481628 kb
Host smart-a0253d4e-f76d-4739-b351-f46400cbc530
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3259293603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3259293603
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3859673318
Short name T222
Test name
Test status
Simulation time 47883245082 ps
CPU time 160.69 seconds
Started Jun 10 05:41:41 PM PDT 24
Finished Jun 10 05:44:23 PM PDT 24
Peak memory 200540 kb
Host smart-c63f597d-d164-4aab-b42b-9a60ec06c7d8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859673318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3859673318
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3174439581
Short name T541
Test name
Test status
Simulation time 5015963073 ps
CPU time 98.62 seconds
Started Jun 10 05:41:48 PM PDT 24
Finished Jun 10 05:43:27 PM PDT 24
Peak memory 200488 kb
Host smart-efc48b3c-afd0-4f1e-a318-1755e5f6e8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174439581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3174439581
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3767392128
Short name T23
Test name
Test status
Simulation time 375055123 ps
CPU time 1.02 seconds
Started Jun 10 05:41:54 PM PDT 24
Finished Jun 10 05:41:55 PM PDT 24
Peak memory 219936 kb
Host smart-36765833-eb79-4a4f-bf44-df61441a09f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767392128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3767392128
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3154307114
Short name T281
Test name
Test status
Simulation time 665694497 ps
CPU time 6.47 seconds
Started Jun 10 05:41:44 PM PDT 24
Finished Jun 10 05:41:51 PM PDT 24
Peak memory 200424 kb
Host smart-955b70be-d537-485c-a8c8-f7cd52c7bdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154307114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3154307114
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.635149856
Short name T461
Test name
Test status
Simulation time 286245031894 ps
CPU time 1570.74 seconds
Started Jun 10 05:41:40 PM PDT 24
Finished Jun 10 06:07:52 PM PDT 24
Peak memory 761988 kb
Host smart-a47ef83f-db70-4577-a2ee-5918ca99dace
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635149856 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.635149856
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.129241879
Short name T170
Test name
Test status
Simulation time 126363192 ps
CPU time 1.43 seconds
Started Jun 10 05:41:51 PM PDT 24
Finished Jun 10 05:41:53 PM PDT 24
Peak memory 200388 kb
Host smart-e2a0b76b-1b8e-4d6f-9663-7460944791b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129241879 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_hmac_vectors.129241879
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.3044550171
Short name T243
Test name
Test status
Simulation time 212669925350 ps
CPU time 612.31 seconds
Started Jun 10 05:41:41 PM PDT 24
Finished Jun 10 05:51:54 PM PDT 24
Peak memory 200440 kb
Host smart-e8c19ede-2fa5-414a-a443-a2bfbb959795
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044550171 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.3044550171
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3553430573
Short name T20
Test name
Test status
Simulation time 8496815903 ps
CPU time 59.1 seconds
Started Jun 10 05:41:42 PM PDT 24
Finished Jun 10 05:42:41 PM PDT 24
Peak memory 200544 kb
Host smart-88bf1fce-67fc-48c0-9739-d56e622d1c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553430573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3553430573
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.417467769
Short name T196
Test name
Test status
Simulation time 2563177898 ps
CPU time 59.63 seconds
Started Jun 10 05:41:58 PM PDT 24
Finished Jun 10 05:42:59 PM PDT 24
Peak memory 224928 kb
Host smart-6d8a4d7b-135b-4e73-936f-12ee913ddf5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=417467769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.417467769
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1622117694
Short name T375
Test name
Test status
Simulation time 6268753088 ps
CPU time 22.34 seconds
Started Jun 10 05:41:59 PM PDT 24
Finished Jun 10 05:42:22 PM PDT 24
Peak memory 200480 kb
Host smart-5e811679-4ef9-472b-ae80-26d5d861ebce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622117694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1622117694
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1186836551
Short name T510
Test name
Test status
Simulation time 3197539938 ps
CPU time 877.54 seconds
Started Jun 10 05:42:21 PM PDT 24
Finished Jun 10 05:56:59 PM PDT 24
Peak memory 720148 kb
Host smart-6b409d83-eb66-484f-9a65-8b85482c50d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1186836551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1186836551
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3583205496
Short name T42
Test name
Test status
Simulation time 9292018239 ps
CPU time 35.43 seconds
Started Jun 10 05:42:09 PM PDT 24
Finished Jun 10 05:42:45 PM PDT 24
Peak memory 200416 kb
Host smart-d9636a4d-deec-46ac-ae95-b7cd43b3dc18
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583205496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3583205496
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_smoke.2890772854
Short name T229
Test name
Test status
Simulation time 940606430 ps
CPU time 5.64 seconds
Started Jun 10 05:42:14 PM PDT 24
Finished Jun 10 05:42:20 PM PDT 24
Peak memory 200428 kb
Host smart-8568e406-4e60-4833-8c96-affbcc027e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890772854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.2890772854
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3513969001
Short name T450
Test name
Test status
Simulation time 8749001742 ps
CPU time 164.01 seconds
Started Jun 10 05:42:05 PM PDT 24
Finished Jun 10 05:44:49 PM PDT 24
Peak memory 200468 kb
Host smart-02bb177f-51e2-4137-b47a-e29cf7f4f4c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513969001 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3513969001
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.448917515
Short name T174
Test name
Test status
Simulation time 98608987 ps
CPU time 1.13 seconds
Started Jun 10 05:42:00 PM PDT 24
Finished Jun 10 05:42:02 PM PDT 24
Peak memory 200436 kb
Host smart-8990add6-7bed-4a2d-bc5c-f8e4db399621
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448917515 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_hmac_vectors.448917515
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.3452966307
Short name T453
Test name
Test status
Simulation time 158401020613 ps
CPU time 545.73 seconds
Started Jun 10 05:42:01 PM PDT 24
Finished Jun 10 05:51:07 PM PDT 24
Peak memory 200464 kb
Host smart-4097c072-af34-4697-988f-570b658da637
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452966307 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.3452966307
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.667542813
Short name T516
Test name
Test status
Simulation time 6398097826 ps
CPU time 83.41 seconds
Started Jun 10 05:41:59 PM PDT 24
Finished Jun 10 05:43:23 PM PDT 24
Peak memory 200380 kb
Host smart-942ff497-eda0-401d-8ed1-19d31f5861f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667542813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.667542813
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3083830020
Short name T569
Test name
Test status
Simulation time 42071418 ps
CPU time 0.59 seconds
Started Jun 10 05:42:16 PM PDT 24
Finished Jun 10 05:42:17 PM PDT 24
Peak memory 196928 kb
Host smart-ee548adb-3fad-4101-a80e-afd92527b892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083830020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3083830020
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.399338725
Short name T211
Test name
Test status
Simulation time 2457719081 ps
CPU time 34.5 seconds
Started Jun 10 05:42:00 PM PDT 24
Finished Jun 10 05:42:34 PM PDT 24
Peak memory 234832 kb
Host smart-eb049648-3fe8-49e9-9b63-4be85783e202
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=399338725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.399338725
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.4108407949
Short name T90
Test name
Test status
Simulation time 14869992482 ps
CPU time 21.7 seconds
Started Jun 10 05:42:21 PM PDT 24
Finished Jun 10 05:42:43 PM PDT 24
Peak memory 200416 kb
Host smart-b682ea2f-72be-48b6-947b-b5a774328500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108407949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.4108407949
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3342716498
Short name T190
Test name
Test status
Simulation time 1759949258 ps
CPU time 116.14 seconds
Started Jun 10 05:41:58 PM PDT 24
Finished Jun 10 05:43:55 PM PDT 24
Peak memory 587300 kb
Host smart-7dc774ec-4a20-472b-9f8f-a4fab0877d5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3342716498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3342716498
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.3378685407
Short name T417
Test name
Test status
Simulation time 37697545176 ps
CPU time 110.04 seconds
Started Jun 10 05:42:09 PM PDT 24
Finished Jun 10 05:44:00 PM PDT 24
Peak memory 200568 kb
Host smart-c37de4ba-f840-4b04-b578-9ce3c007399e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378685407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3378685407
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2136137354
Short name T567
Test name
Test status
Simulation time 2883573612 ps
CPU time 13.44 seconds
Started Jun 10 05:41:56 PM PDT 24
Finished Jun 10 05:42:10 PM PDT 24
Peak memory 200556 kb
Host smart-6fb2270c-1adb-463e-8b92-48f1b9110301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136137354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2136137354
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1786215236
Short name T358
Test name
Test status
Simulation time 5744249121 ps
CPU time 16.34 seconds
Started Jun 10 05:42:05 PM PDT 24
Finished Jun 10 05:42:22 PM PDT 24
Peak memory 200476 kb
Host smart-de0d61a1-c100-4764-a66f-bed803b56571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786215236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1786215236
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.1047822493
Short name T153
Test name
Test status
Simulation time 114317985 ps
CPU time 1.13 seconds
Started Jun 10 05:42:13 PM PDT 24
Finished Jun 10 05:42:14 PM PDT 24
Peak memory 200296 kb
Host smart-29f705a7-be99-45aa-ae70-0edc304cc465
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047822493 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.1047822493
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.1145170541
Short name T111
Test name
Test status
Simulation time 29394668911 ps
CPU time 420.93 seconds
Started Jun 10 05:41:58 PM PDT 24
Finished Jun 10 05:49:00 PM PDT 24
Peak memory 200436 kb
Host smart-b6abcd18-c5b1-4586-8fb7-907d79f74828
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145170541 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.1145170541
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.143520408
Short name T228
Test name
Test status
Simulation time 9837501161 ps
CPU time 78.97 seconds
Started Jun 10 05:42:02 PM PDT 24
Finished Jun 10 05:43:22 PM PDT 24
Peak memory 200504 kb
Host smart-983d8bfe-b669-4767-b4ad-4ffead0a47b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143520408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.143520408
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.272642327
Short name T402
Test name
Test status
Simulation time 12538202 ps
CPU time 0.57 seconds
Started Jun 10 05:42:09 PM PDT 24
Finished Jun 10 05:42:10 PM PDT 24
Peak memory 195248 kb
Host smart-f09e7f61-434a-4cda-824d-1d148ca4eeee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272642327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.272642327
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1744642652
Short name T157
Test name
Test status
Simulation time 3173030033 ps
CPU time 43.39 seconds
Started Jun 10 05:42:15 PM PDT 24
Finished Jun 10 05:42:58 PM PDT 24
Peak memory 220812 kb
Host smart-a63220df-7eba-4626-9157-c8cc0478022e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1744642652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1744642652
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.735792214
Short name T530
Test name
Test status
Simulation time 2925119606 ps
CPU time 12.09 seconds
Started Jun 10 05:42:24 PM PDT 24
Finished Jun 10 05:42:36 PM PDT 24
Peak memory 200484 kb
Host smart-c534c8db-9c52-4df8-ada5-dda94ac76e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735792214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.735792214
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.4228778289
Short name T389
Test name
Test status
Simulation time 865116413 ps
CPU time 152.82 seconds
Started Jun 10 05:42:17 PM PDT 24
Finished Jun 10 05:44:50 PM PDT 24
Peak memory 393652 kb
Host smart-9f52feb9-13b7-428b-a1ff-1368b6bb1eae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4228778289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.4228778289
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3710403464
Short name T338
Test name
Test status
Simulation time 12383404439 ps
CPU time 96.22 seconds
Started Jun 10 05:42:03 PM PDT 24
Finished Jun 10 05:43:40 PM PDT 24
Peak memory 200492 kb
Host smart-0aa297e4-d575-46c8-b92e-e9cc99d5282c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710403464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3710403464
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.4098461884
Short name T134
Test name
Test status
Simulation time 11295727857 ps
CPU time 53.32 seconds
Started Jun 10 05:42:11 PM PDT 24
Finished Jun 10 05:43:05 PM PDT 24
Peak memory 200504 kb
Host smart-107ca738-143e-499e-82c2-3f2e2a9674d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098461884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.4098461884
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.345620805
Short name T207
Test name
Test status
Simulation time 1244770098 ps
CPU time 7.6 seconds
Started Jun 10 05:42:03 PM PDT 24
Finished Jun 10 05:42:12 PM PDT 24
Peak memory 200432 kb
Host smart-fe2edef3-c6bf-416d-b72d-179cd64e8419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345620805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.345620805
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.235302174
Short name T371
Test name
Test status
Simulation time 4913457609 ps
CPU time 463.49 seconds
Started Jun 10 05:42:10 PM PDT 24
Finished Jun 10 05:49:54 PM PDT 24
Peak memory 470728 kb
Host smart-dd7a449b-c808-430d-88d2-c53f54a85f5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235302174 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.235302174
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.2177761303
Short name T434
Test name
Test status
Simulation time 59683336 ps
CPU time 1.25 seconds
Started Jun 10 05:42:01 PM PDT 24
Finished Jun 10 05:42:03 PM PDT 24
Peak memory 200440 kb
Host smart-9de5a881-f89b-470f-9436-890867dc11ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177761303 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.2177761303
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.3743239671
Short name T155
Test name
Test status
Simulation time 7114062153 ps
CPU time 412.32 seconds
Started Jun 10 05:42:01 PM PDT 24
Finished Jun 10 05:48:54 PM PDT 24
Peak memory 200460 kb
Host smart-c76942f6-5fb2-44a1-bd50-534b5abd3629
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743239671 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.3743239671
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.984812558
Short name T496
Test name
Test status
Simulation time 4189066806 ps
CPU time 50.5 seconds
Started Jun 10 05:42:09 PM PDT 24
Finished Jun 10 05:43:00 PM PDT 24
Peak memory 200572 kb
Host smart-f3b8aef8-54da-4fc7-a5f0-12a81a668000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984812558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.984812558
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2799318813
Short name T352
Test name
Test status
Simulation time 42844391 ps
CPU time 0.58 seconds
Started Jun 10 05:42:07 PM PDT 24
Finished Jun 10 05:42:07 PM PDT 24
Peak memory 195364 kb
Host smart-946548a4-c4dd-4163-ac99-3cb291f1c7e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799318813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2799318813
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.954400417
Short name T104
Test name
Test status
Simulation time 1456030810 ps
CPU time 30.1 seconds
Started Jun 10 05:42:09 PM PDT 24
Finished Jun 10 05:42:40 PM PDT 24
Peak memory 208536 kb
Host smart-ad5900b5-c67d-4e30-b509-181771e033f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=954400417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.954400417
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.707204852
Short name T293
Test name
Test status
Simulation time 10271403231 ps
CPU time 56.07 seconds
Started Jun 10 05:41:59 PM PDT 24
Finished Jun 10 05:42:56 PM PDT 24
Peak memory 200460 kb
Host smart-52a442e7-9904-46ef-9e14-b9b9e15eba55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707204852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.707204852
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2850110462
Short name T298
Test name
Test status
Simulation time 11805011972 ps
CPU time 837.92 seconds
Started Jun 10 05:42:09 PM PDT 24
Finished Jun 10 05:56:08 PM PDT 24
Peak memory 693548 kb
Host smart-5aada914-b3ac-40b2-a92d-7e900ad26a68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2850110462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2850110462
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2506217878
Short name T304
Test name
Test status
Simulation time 2959988727 ps
CPU time 39.78 seconds
Started Jun 10 05:42:12 PM PDT 24
Finished Jun 10 05:42:52 PM PDT 24
Peak memory 200464 kb
Host smart-60ebaa5f-50fc-4d87-9761-120c2a3b250e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506217878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2506217878
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.281575303
Short name T263
Test name
Test status
Simulation time 3772491889 ps
CPU time 45.44 seconds
Started Jun 10 05:42:12 PM PDT 24
Finished Jun 10 05:42:58 PM PDT 24
Peak memory 200480 kb
Host smart-7d8a203f-cd66-49fb-bebf-d3b45084ef87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281575303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.281575303
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3637665873
Short name T429
Test name
Test status
Simulation time 1683062997 ps
CPU time 9.33 seconds
Started Jun 10 05:42:14 PM PDT 24
Finished Jun 10 05:42:24 PM PDT 24
Peak memory 200468 kb
Host smart-943f9fa4-d19a-4aee-81e5-35fb1cacb296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637665873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3637665873
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.4209384990
Short name T60
Test name
Test status
Simulation time 922236105396 ps
CPU time 2678.48 seconds
Started Jun 10 05:42:16 PM PDT 24
Finished Jun 10 06:26:55 PM PDT 24
Peak memory 745196 kb
Host smart-67dbe920-8950-40f0-9b92-87d0780572bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209384990 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.4209384990
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.1397609604
Short name T377
Test name
Test status
Simulation time 31663455 ps
CPU time 1.27 seconds
Started Jun 10 05:42:03 PM PDT 24
Finished Jun 10 05:42:05 PM PDT 24
Peak memory 200516 kb
Host smart-88c69f97-fab1-4b42-b376-e5ec317134ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397609604 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.1397609604
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.3409708533
Short name T519
Test name
Test status
Simulation time 218488259681 ps
CPU time 535.16 seconds
Started Jun 10 05:42:04 PM PDT 24
Finished Jun 10 05:50:59 PM PDT 24
Peak memory 200520 kb
Host smart-e3d9a4a8-df40-487f-815b-c484ad51cad1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409708533 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.3409708533
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1248084671
Short name T524
Test name
Test status
Simulation time 2071318740 ps
CPU time 87.87 seconds
Started Jun 10 05:42:15 PM PDT 24
Finished Jun 10 05:43:43 PM PDT 24
Peak memory 200408 kb
Host smart-e92c0510-f9b8-4399-8f21-a175f119dcc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248084671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1248084671
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.973149941
Short name T240
Test name
Test status
Simulation time 15520305 ps
CPU time 0.62 seconds
Started Jun 10 05:42:05 PM PDT 24
Finished Jun 10 05:42:06 PM PDT 24
Peak memory 196456 kb
Host smart-6e117892-ddac-4904-8073-ca00eee500d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973149941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.973149941
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.284615570
Short name T11
Test name
Test status
Simulation time 3199991217 ps
CPU time 41.8 seconds
Started Jun 10 05:42:24 PM PDT 24
Finished Jun 10 05:43:06 PM PDT 24
Peak memory 208676 kb
Host smart-c59e489c-12c3-4bc7-a7b8-6716869496d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=284615570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.284615570
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.4095532965
Short name T482
Test name
Test status
Simulation time 1920389687 ps
CPU time 18.85 seconds
Started Jun 10 05:42:04 PM PDT 24
Finished Jun 10 05:42:24 PM PDT 24
Peak memory 200404 kb
Host smart-a07f83b5-7cc6-47fe-8e5b-1fb2d9b44356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095532965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.4095532965
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1988457525
Short name T193
Test name
Test status
Simulation time 4084168628 ps
CPU time 568.16 seconds
Started Jun 10 05:42:23 PM PDT 24
Finished Jun 10 05:51:52 PM PDT 24
Peak memory 731096 kb
Host smart-6d44b5fa-2944-4ef4-a808-309ad4046e28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1988457525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1988457525
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3016382776
Short name T348
Test name
Test status
Simulation time 27420752611 ps
CPU time 93.96 seconds
Started Jun 10 05:42:11 PM PDT 24
Finished Jun 10 05:43:46 PM PDT 24
Peak memory 200540 kb
Host smart-aad5a455-944a-414e-8835-68d80f459dbb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016382776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3016382776
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.3371550301
Short name T412
Test name
Test status
Simulation time 90229395 ps
CPU time 5.02 seconds
Started Jun 10 05:42:25 PM PDT 24
Finished Jun 10 05:42:30 PM PDT 24
Peak memory 200424 kb
Host smart-9226e123-9437-47bf-a10a-f3ede5fe445a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371550301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3371550301
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2203494641
Short name T260
Test name
Test status
Simulation time 1953228243 ps
CPU time 11.47 seconds
Started Jun 10 05:42:05 PM PDT 24
Finished Jun 10 05:42:17 PM PDT 24
Peak memory 200616 kb
Host smart-2455f4de-2bd4-4205-bd79-91eb5749bac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203494641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2203494641
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2072676865
Short name T86
Test name
Test status
Simulation time 55542893032 ps
CPU time 1317.47 seconds
Started Jun 10 05:42:23 PM PDT 24
Finished Jun 10 06:04:21 PM PDT 24
Peak memory 579064 kb
Host smart-ce2cb0f1-86c8-4da0-bee6-ceb4b821b039
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072676865 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2072676865
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.118913379
Short name T292
Test name
Test status
Simulation time 256255117 ps
CPU time 1.03 seconds
Started Jun 10 05:42:28 PM PDT 24
Finished Jun 10 05:42:30 PM PDT 24
Peak memory 200248 kb
Host smart-4b44bdfc-9642-4fe2-bc25-388920efe8ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118913379 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_hmac_vectors.118913379
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.3459733219
Short name T484
Test name
Test status
Simulation time 139731476879 ps
CPU time 473.91 seconds
Started Jun 10 05:42:17 PM PDT 24
Finished Jun 10 05:50:11 PM PDT 24
Peak memory 200476 kb
Host smart-06890fd8-68fb-4cff-8831-da84ab13bd2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459733219 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.3459733219
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.4044242151
Short name T172
Test name
Test status
Simulation time 133458164069 ps
CPU time 118.39 seconds
Started Jun 10 05:42:07 PM PDT 24
Finished Jun 10 05:44:06 PM PDT 24
Peak memory 200468 kb
Host smart-a8af278a-980d-4d78-ae10-eb71e3c9e883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044242151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.4044242151
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/145.hmac_stress_all_with_rand_reset.1135633169
Short name T19
Test name
Test status
Simulation time 34144958462 ps
CPU time 979.06 seconds
Started Jun 10 05:44:11 PM PDT 24
Finished Jun 10 06:00:30 PM PDT 24
Peak memory 216124 kb
Host smart-b7ffc446-8698-4146-adb7-0665d3242919
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1135633169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.hmac_stress_all_with_rand_reset.1135633169
Directory /workspace/145.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.101819540
Short name T233
Test name
Test status
Simulation time 55533294 ps
CPU time 0.61 seconds
Started Jun 10 05:42:11 PM PDT 24
Finished Jun 10 05:42:12 PM PDT 24
Peak memory 197116 kb
Host smart-21f59a06-89fe-4e09-a4e2-b4c704785342
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101819540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.101819540
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1957638975
Short name T320
Test name
Test status
Simulation time 24742599110 ps
CPU time 67.09 seconds
Started Jun 10 05:42:19 PM PDT 24
Finished Jun 10 05:43:27 PM PDT 24
Peak memory 224056 kb
Host smart-8c7c0eb6-3b28-41c7-8ef5-a37b2aaa39d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1957638975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1957638975
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2693996220
Short name T498
Test name
Test status
Simulation time 1204586231 ps
CPU time 24.51 seconds
Started Jun 10 05:42:09 PM PDT 24
Finished Jun 10 05:42:34 PM PDT 24
Peak memory 200420 kb
Host smart-666a2d66-f111-4921-88d0-23089adae162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693996220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2693996220
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3552371268
Short name T466
Test name
Test status
Simulation time 2777522521 ps
CPU time 690.46 seconds
Started Jun 10 05:42:22 PM PDT 24
Finished Jun 10 05:53:53 PM PDT 24
Peak memory 684556 kb
Host smart-6a93e88d-2a29-455b-835f-e199f3acffeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3552371268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3552371268
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2459248166
Short name T127
Test name
Test status
Simulation time 24013864033 ps
CPU time 116.12 seconds
Started Jun 10 05:42:06 PM PDT 24
Finished Jun 10 05:44:03 PM PDT 24
Peak memory 200456 kb
Host smart-cf4fb587-b9da-4500-8310-01bff612ae20
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459248166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2459248166
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1864944530
Short name T311
Test name
Test status
Simulation time 1247749781 ps
CPU time 18.84 seconds
Started Jun 10 05:42:25 PM PDT 24
Finished Jun 10 05:42:44 PM PDT 24
Peak memory 200424 kb
Host smart-f5cc973f-5cb5-42a5-b45c-c9619f0af519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864944530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1864944530
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.323021738
Short name T52
Test name
Test status
Simulation time 1139272512 ps
CPU time 5.52 seconds
Started Jun 10 05:42:28 PM PDT 24
Finished Jun 10 05:42:34 PM PDT 24
Peak memory 200428 kb
Host smart-81184021-3679-414f-aca0-15e8b5e87a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323021738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.323021738
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3289438147
Short name T4
Test name
Test status
Simulation time 7553364434 ps
CPU time 189.93 seconds
Started Jun 10 05:42:07 PM PDT 24
Finished Jun 10 05:45:17 PM PDT 24
Peak memory 233328 kb
Host smart-e9484c07-b11f-413f-844a-6acaf50bed4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289438147 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3289438147
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.3105969490
Short name T58
Test name
Test status
Simulation time 92208513 ps
CPU time 1.1 seconds
Started Jun 10 05:42:11 PM PDT 24
Finished Jun 10 05:42:13 PM PDT 24
Peak memory 200448 kb
Host smart-317ada35-3a13-4cd5-8d35-3f6116e927ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105969490 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.3105969490
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.1586184520
Short name T106
Test name
Test status
Simulation time 77016051324 ps
CPU time 489.99 seconds
Started Jun 10 05:42:07 PM PDT 24
Finished Jun 10 05:50:17 PM PDT 24
Peak memory 200456 kb
Host smart-73d33109-f9af-45b1-b6ca-fe3485dc1d5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586184520 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.1586184520
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1306091187
Short name T146
Test name
Test status
Simulation time 150168665 ps
CPU time 1.36 seconds
Started Jun 10 05:42:05 PM PDT 24
Finished Jun 10 05:42:06 PM PDT 24
Peak memory 200432 kb
Host smart-8870c3f7-39f1-4563-8beb-6ef9150e35f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306091187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1306091187
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.49312473
Short name T13
Test name
Test status
Simulation time 34993012 ps
CPU time 0.6 seconds
Started Jun 10 05:42:13 PM PDT 24
Finished Jun 10 05:42:14 PM PDT 24
Peak memory 196204 kb
Host smart-5f435e29-4e67-42be-8e0b-4d3b8495b110
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49312473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.49312473
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.4172744897
Short name T151
Test name
Test status
Simulation time 3172592890 ps
CPU time 41.86 seconds
Started Jun 10 05:42:13 PM PDT 24
Finished Jun 10 05:42:56 PM PDT 24
Peak memory 208648 kb
Host smart-8d61f692-cc24-482b-900c-225b7b888dc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4172744897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.4172744897
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1028309152
Short name T93
Test name
Test status
Simulation time 2552282195 ps
CPU time 67.91 seconds
Started Jun 10 05:42:30 PM PDT 24
Finished Jun 10 05:43:38 PM PDT 24
Peak memory 200464 kb
Host smart-18b466fb-4418-48e1-ab00-fce5c751606e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028309152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1028309152
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3375070511
Short name T154
Test name
Test status
Simulation time 2806416639 ps
CPU time 884.73 seconds
Started Jun 10 05:42:12 PM PDT 24
Finished Jun 10 05:56:57 PM PDT 24
Peak memory 724996 kb
Host smart-f29a4e9f-42ee-4c6b-afc5-7087c42b2ef7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3375070511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3375070511
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1176668219
Short name T563
Test name
Test status
Simulation time 33823143961 ps
CPU time 103.96 seconds
Started Jun 10 05:42:13 PM PDT 24
Finished Jun 10 05:43:57 PM PDT 24
Peak memory 200496 kb
Host smart-2cb9ee49-a5dc-4562-851d-22ee14d31eac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176668219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1176668219
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.653493953
Short name T556
Test name
Test status
Simulation time 26866500573 ps
CPU time 109.79 seconds
Started Jun 10 05:42:08 PM PDT 24
Finished Jun 10 05:43:58 PM PDT 24
Peak memory 200500 kb
Host smart-cab8562c-3f37-47ef-b969-b89b6d7b802f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653493953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.653493953
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.938169641
Short name T480
Test name
Test status
Simulation time 186375073 ps
CPU time 3.96 seconds
Started Jun 10 05:42:13 PM PDT 24
Finished Jun 10 05:42:18 PM PDT 24
Peak memory 200380 kb
Host smart-16c71e28-07e9-447d-b3f1-eefb18a4a9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938169641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.938169641
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.454711331
Short name T255
Test name
Test status
Simulation time 161718880363 ps
CPU time 1491.7 seconds
Started Jun 10 05:42:31 PM PDT 24
Finished Jun 10 06:07:23 PM PDT 24
Peak memory 229020 kb
Host smart-7ef7eaca-4bf7-42ed-917e-1f2dfbc4e1e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454711331 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.454711331
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.1550271810
Short name T234
Test name
Test status
Simulation time 68321407 ps
CPU time 1.17 seconds
Started Jun 10 05:42:24 PM PDT 24
Finished Jun 10 05:42:26 PM PDT 24
Peak memory 200384 kb
Host smart-73e5b6e3-339d-4438-aad4-aa4602a81c48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550271810 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.1550271810
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.2348491957
Short name T110
Test name
Test status
Simulation time 9906680020 ps
CPU time 426.08 seconds
Started Jun 10 05:42:33 PM PDT 24
Finished Jun 10 05:49:39 PM PDT 24
Peak memory 200424 kb
Host smart-8f586eb1-6d67-49b4-b760-097c02c52a4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348491957 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.2348491957
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1233709303
Short name T231
Test name
Test status
Simulation time 3472736490 ps
CPU time 39.45 seconds
Started Jun 10 05:42:14 PM PDT 24
Finished Jun 10 05:42:54 PM PDT 24
Peak memory 200524 kb
Host smart-949a23dc-4258-42d3-be8b-8634d302d405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233709303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1233709303
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.177686340
Short name T198
Test name
Test status
Simulation time 23038351 ps
CPU time 0.57 seconds
Started Jun 10 05:42:34 PM PDT 24
Finished Jun 10 05:42:35 PM PDT 24
Peak memory 196060 kb
Host smart-2232b2eb-fbaf-455d-bec1-73a11bd71613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177686340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.177686340
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3048782997
Short name T531
Test name
Test status
Simulation time 823288333 ps
CPU time 43.1 seconds
Started Jun 10 05:42:11 PM PDT 24
Finished Jun 10 05:42:54 PM PDT 24
Peak memory 225052 kb
Host smart-1e7f7e51-9246-47a6-99ee-c1deaeaf6642
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3048782997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3048782997
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2775548381
Short name T393
Test name
Test status
Simulation time 24887571844 ps
CPU time 33.5 seconds
Started Jun 10 05:42:32 PM PDT 24
Finished Jun 10 05:43:06 PM PDT 24
Peak memory 200512 kb
Host smart-01dc61ff-3e9f-4008-a75f-64f464071dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775548381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2775548381
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3860907105
Short name T380
Test name
Test status
Simulation time 12454915595 ps
CPU time 839.48 seconds
Started Jun 10 05:42:11 PM PDT 24
Finished Jun 10 05:56:11 PM PDT 24
Peak memory 736424 kb
Host smart-b8a9a23e-28d6-4d06-81c2-0d85fca155c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3860907105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3860907105
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1860800666
Short name T448
Test name
Test status
Simulation time 15439742010 ps
CPU time 76.46 seconds
Started Jun 10 05:42:10 PM PDT 24
Finished Jun 10 05:43:27 PM PDT 24
Peak memory 200460 kb
Host smart-2c8abd05-238e-4955-a6d2-2c713ee227c9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860800666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1860800666
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.844685507
Short name T160
Test name
Test status
Simulation time 3957073443 ps
CPU time 44.66 seconds
Started Jun 10 05:42:10 PM PDT 24
Finished Jun 10 05:42:55 PM PDT 24
Peak memory 200556 kb
Host smart-b89a64bd-d270-46da-b5da-0e27d22abcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844685507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.844685507
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3075750981
Short name T133
Test name
Test status
Simulation time 91191041 ps
CPU time 3.32 seconds
Started Jun 10 05:42:08 PM PDT 24
Finished Jun 10 05:42:12 PM PDT 24
Peak memory 200460 kb
Host smart-2a09613b-d566-40a8-be33-0175ee49c96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075750981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3075750981
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3834871201
Short name T94
Test name
Test status
Simulation time 81670047856 ps
CPU time 805.05 seconds
Started Jun 10 05:42:23 PM PDT 24
Finished Jun 10 05:55:49 PM PDT 24
Peak memory 200468 kb
Host smart-e46035dc-7e5e-46c9-b030-3e633fae071b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834871201 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3834871201
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.2378793356
Short name T405
Test name
Test status
Simulation time 63946170 ps
CPU time 1.38 seconds
Started Jun 10 05:42:18 PM PDT 24
Finished Jun 10 05:42:20 PM PDT 24
Peak memory 200400 kb
Host smart-90ab9915-496d-49bd-b08a-63f234b5ac25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378793356 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.2378793356
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.1187801457
Short name T360
Test name
Test status
Simulation time 7280831661 ps
CPU time 414.57 seconds
Started Jun 10 05:42:11 PM PDT 24
Finished Jun 10 05:49:06 PM PDT 24
Peak memory 200492 kb
Host smart-a46330c1-958a-4469-9f5f-e0d99d711dc4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187801457 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.1187801457
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1667233481
Short name T376
Test name
Test status
Simulation time 1398275721 ps
CPU time 35.4 seconds
Started Jun 10 05:42:31 PM PDT 24
Finished Jun 10 05:43:07 PM PDT 24
Peak memory 200200 kb
Host smart-b211d2dc-791c-4f56-98a0-3a81e0ae9ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667233481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1667233481
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2717081811
Short name T565
Test name
Test status
Simulation time 13413033 ps
CPU time 0.62 seconds
Started Jun 10 05:42:30 PM PDT 24
Finished Jun 10 05:42:31 PM PDT 24
Peak memory 196424 kb
Host smart-0e5297f5-c2df-4f50-ae13-e7e0381c8198
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717081811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2717081811
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.3900245683
Short name T37
Test name
Test status
Simulation time 2589719994 ps
CPU time 47.96 seconds
Started Jun 10 05:42:30 PM PDT 24
Finished Jun 10 05:43:19 PM PDT 24
Peak memory 224120 kb
Host smart-1f202775-a36c-4479-b31c-6f9cdaf53a0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3900245683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.3900245683
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3749451923
Short name T261
Test name
Test status
Simulation time 523295507 ps
CPU time 7.28 seconds
Started Jun 10 05:42:31 PM PDT 24
Finished Jun 10 05:42:39 PM PDT 24
Peak memory 200328 kb
Host smart-d3f79f48-f15c-4928-9c1e-0390ff49b119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749451923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3749451923
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2001850157
Short name T109
Test name
Test status
Simulation time 26154413788 ps
CPU time 420.03 seconds
Started Jun 10 05:42:37 PM PDT 24
Finished Jun 10 05:49:37 PM PDT 24
Peak memory 462100 kb
Host smart-de0cb5c8-5a0b-4d23-98da-d2af4c1b8d91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2001850157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2001850157
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.30275683
Short name T514
Test name
Test status
Simulation time 20893550965 ps
CPU time 67.75 seconds
Started Jun 10 05:42:17 PM PDT 24
Finished Jun 10 05:43:25 PM PDT 24
Peak memory 200340 kb
Host smart-4f3912ca-18e2-4416-b4a4-372f12de047f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30275683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.30275683
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1668000372
Short name T517
Test name
Test status
Simulation time 6157343608 ps
CPU time 107.21 seconds
Started Jun 10 05:42:31 PM PDT 24
Finished Jun 10 05:44:19 PM PDT 24
Peak memory 200520 kb
Host smart-caf070b8-b1a8-4cb7-ac1b-b35d8300a32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668000372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1668000372
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2330677891
Short name T460
Test name
Test status
Simulation time 223019769 ps
CPU time 4.05 seconds
Started Jun 10 05:42:31 PM PDT 24
Finished Jun 10 05:42:36 PM PDT 24
Peak memory 200460 kb
Host smart-85858e5c-4b5d-4783-aebe-f1414d5370db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330677891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2330677891
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2587366730
Short name T31
Test name
Test status
Simulation time 342069233311 ps
CPU time 1988.53 seconds
Started Jun 10 05:42:15 PM PDT 24
Finished Jun 10 06:15:24 PM PDT 24
Peak memory 695756 kb
Host smart-0702b918-a92e-4c33-a7d5-59aab6df76b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587366730 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2587366730
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.4246790752
Short name T221
Test name
Test status
Simulation time 60731727 ps
CPU time 1.19 seconds
Started Jun 10 05:42:30 PM PDT 24
Finished Jun 10 05:42:32 PM PDT 24
Peak memory 200452 kb
Host smart-8b9ff434-fafc-4176-a148-f39e3b04e75b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246790752 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.4246790752
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.3507003158
Short name T265
Test name
Test status
Simulation time 28907141842 ps
CPU time 412.42 seconds
Started Jun 10 05:42:23 PM PDT 24
Finished Jun 10 05:49:16 PM PDT 24
Peak memory 200432 kb
Host smart-63b1ff53-4fb3-4f0d-93a8-2351edc5faba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507003158 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.3507003158
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2898707252
Short name T392
Test name
Test status
Simulation time 1707590454 ps
CPU time 78.01 seconds
Started Jun 10 05:42:17 PM PDT 24
Finished Jun 10 05:43:35 PM PDT 24
Peak memory 200492 kb
Host smart-58cee769-7f9b-4dc8-ae92-4b9569386133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898707252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2898707252
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2540828646
Short name T282
Test name
Test status
Simulation time 120466454 ps
CPU time 0.6 seconds
Started Jun 10 05:42:30 PM PDT 24
Finished Jun 10 05:42:32 PM PDT 24
Peak memory 196176 kb
Host smart-02036139-685a-43a1-ab5d-7bdd50ab840a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540828646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2540828646
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3393142224
Short name T141
Test name
Test status
Simulation time 3648543856 ps
CPU time 50.82 seconds
Started Jun 10 05:42:41 PM PDT 24
Finished Jun 10 05:43:32 PM PDT 24
Peak memory 223036 kb
Host smart-24f0ff37-ccc1-446c-9079-c67f904be95e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3393142224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3393142224
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2322717540
Short name T78
Test name
Test status
Simulation time 41345761447 ps
CPU time 43.63 seconds
Started Jun 10 05:42:17 PM PDT 24
Finished Jun 10 05:43:01 PM PDT 24
Peak memory 200668 kb
Host smart-7054446c-7697-4fe8-9424-1f1b23e8d4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322717540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2322717540
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.596019658
Short name T300
Test name
Test status
Simulation time 2600555550 ps
CPU time 821.68 seconds
Started Jun 10 05:42:16 PM PDT 24
Finished Jun 10 05:55:58 PM PDT 24
Peak memory 681344 kb
Host smart-579cb20b-4d39-4bca-83c1-c1e3cda46a5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=596019658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.596019658
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.452022593
Short name T421
Test name
Test status
Simulation time 10883916423 ps
CPU time 34.65 seconds
Started Jun 10 05:42:16 PM PDT 24
Finished Jun 10 05:42:51 PM PDT 24
Peak memory 200380 kb
Host smart-67d9891d-281f-4dd5-9ee5-cd8d0a47157d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452022593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.452022593
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.3749833186
Short name T318
Test name
Test status
Simulation time 8088919850 ps
CPU time 68.53 seconds
Started Jun 10 05:42:15 PM PDT 24
Finished Jun 10 05:43:24 PM PDT 24
Peak memory 200484 kb
Host smart-55db98ab-00f4-4da2-925c-bcfe9af08b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749833186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3749833186
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.857563466
Short name T419
Test name
Test status
Simulation time 281229761 ps
CPU time 2.75 seconds
Started Jun 10 05:42:34 PM PDT 24
Finished Jun 10 05:42:37 PM PDT 24
Peak memory 200428 kb
Host smart-0594a791-5d3a-4fc4-adea-4143f361ab21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857563466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.857563466
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2107531777
Short name T91
Test name
Test status
Simulation time 76158024930 ps
CPU time 1351.63 seconds
Started Jun 10 05:42:16 PM PDT 24
Finished Jun 10 06:04:48 PM PDT 24
Peak memory 241420 kb
Host smart-78ac1790-3453-49d3-b7c4-efe4589a327e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107531777 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2107531777
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.45813601
Short name T384
Test name
Test status
Simulation time 63003933 ps
CPU time 1.22 seconds
Started Jun 10 05:42:41 PM PDT 24
Finished Jun 10 05:42:42 PM PDT 24
Peak memory 200420 kb
Host smart-6f73c844-0aaa-440d-b273-bd5616a62749
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45813601 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.hmac_test_hmac_vectors.45813601
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.208681371
Short name T149
Test name
Test status
Simulation time 44881357990 ps
CPU time 466.31 seconds
Started Jun 10 05:42:19 PM PDT 24
Finished Jun 10 05:50:06 PM PDT 24
Peak memory 200432 kb
Host smart-82666c5e-97ad-4794-bb59-e7d282502d88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208681371 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.208681371
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.692430315
Short name T387
Test name
Test status
Simulation time 635235138 ps
CPU time 30.64 seconds
Started Jun 10 05:42:13 PM PDT 24
Finished Jun 10 05:42:44 PM PDT 24
Peak memory 200436 kb
Host smart-5ddb19a4-1c3f-4e27-becf-ab61387419cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692430315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.692430315
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3797605338
Short name T14
Test name
Test status
Simulation time 13407840 ps
CPU time 0.59 seconds
Started Jun 10 05:41:52 PM PDT 24
Finished Jun 10 05:41:53 PM PDT 24
Peak memory 196432 kb
Host smart-8315d526-0c4f-47b4-a3a7-46c5b39fc806
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797605338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3797605338
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.471665344
Short name T529
Test name
Test status
Simulation time 116975502 ps
CPU time 5.65 seconds
Started Jun 10 05:41:40 PM PDT 24
Finished Jun 10 05:41:46 PM PDT 24
Peak memory 208568 kb
Host smart-9d1f972e-e56e-42f3-819a-767794973f99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=471665344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.471665344
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3296771354
Short name T542
Test name
Test status
Simulation time 3454279057 ps
CPU time 49.85 seconds
Started Jun 10 05:41:44 PM PDT 24
Finished Jun 10 05:42:34 PM PDT 24
Peak memory 200616 kb
Host smart-60606562-e1b7-495b-9a53-9776421b681f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296771354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3296771354
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.158753125
Short name T178
Test name
Test status
Simulation time 36288242725 ps
CPU time 775.18 seconds
Started Jun 10 05:41:39 PM PDT 24
Finished Jun 10 05:54:35 PM PDT 24
Peak memory 665224 kb
Host smart-0ac8f0fa-865d-4972-8ac7-633a86a636d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=158753125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.158753125
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.948252798
Short name T487
Test name
Test status
Simulation time 2077229702 ps
CPU time 28.97 seconds
Started Jun 10 05:41:49 PM PDT 24
Finished Jun 10 05:42:19 PM PDT 24
Peak memory 200440 kb
Host smart-c499604c-11f0-4f1a-b5b4-fb24634a916e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948252798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.948252798
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3021017142
Short name T416
Test name
Test status
Simulation time 5529681327 ps
CPU time 37.05 seconds
Started Jun 10 05:41:52 PM PDT 24
Finished Jun 10 05:42:30 PM PDT 24
Peak memory 200524 kb
Host smart-c962aa6b-aebc-422f-b216-fcfe4804c5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021017142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3021017142
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.770310818
Short name T24
Test name
Test status
Simulation time 477755114 ps
CPU time 1.03 seconds
Started Jun 10 05:41:58 PM PDT 24
Finished Jun 10 05:42:00 PM PDT 24
Peak memory 219908 kb
Host smart-5a7446d4-ba64-4a11-8da3-f7698d1f3d27
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770310818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.770310818
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.1156801828
Short name T271
Test name
Test status
Simulation time 747184949 ps
CPU time 7.35 seconds
Started Jun 10 05:41:54 PM PDT 24
Finished Jun 10 05:42:02 PM PDT 24
Peak memory 200464 kb
Host smart-c31ddc5b-215e-4df4-a523-cd6861d790b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156801828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1156801828
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3725754886
Short name T59
Test name
Test status
Simulation time 402048926423 ps
CPU time 1929.24 seconds
Started Jun 10 05:41:53 PM PDT 24
Finished Jun 10 06:14:03 PM PDT 24
Peak memory 694184 kb
Host smart-bb0f9bd9-15a1-4695-9ba3-90ed3dd0f052
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725754886 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3725754886
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.556781624
Short name T359
Test name
Test status
Simulation time 297945753 ps
CPU time 1.38 seconds
Started Jun 10 05:41:43 PM PDT 24
Finished Jun 10 05:41:44 PM PDT 24
Peak memory 200428 kb
Host smart-b9a902ff-7c2e-4b81-8a03-432e0d6b6f51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556781624 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_hmac_vectors.556781624
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.2837650179
Short name T439
Test name
Test status
Simulation time 27852810883 ps
CPU time 510.63 seconds
Started Jun 10 05:41:53 PM PDT 24
Finished Jun 10 05:50:24 PM PDT 24
Peak memory 200216 kb
Host smart-0d2b2411-a19a-4261-8388-7aff0d163849
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837650179 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.2837650179
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.636453127
Short name T356
Test name
Test status
Simulation time 2149565144 ps
CPU time 51.31 seconds
Started Jun 10 05:41:41 PM PDT 24
Finished Jun 10 05:42:33 PM PDT 24
Peak memory 200500 kb
Host smart-4996bcdf-82f4-438c-a228-964d5ee98650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636453127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.636453127
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2159908179
Short name T308
Test name
Test status
Simulation time 19383721 ps
CPU time 0.6 seconds
Started Jun 10 05:42:19 PM PDT 24
Finished Jun 10 05:42:21 PM PDT 24
Peak memory 196204 kb
Host smart-ec9f0a38-6943-4e04-be7e-5c95dad68a08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159908179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2159908179
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2408944159
Short name T589
Test name
Test status
Simulation time 2340575869 ps
CPU time 49.02 seconds
Started Jun 10 05:42:13 PM PDT 24
Finished Jun 10 05:43:03 PM PDT 24
Peak memory 216092 kb
Host smart-9359a9df-7d92-42a6-a088-8183cf7e88f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2408944159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2408944159
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1871907411
Short name T518
Test name
Test status
Simulation time 157022516 ps
CPU time 3.33 seconds
Started Jun 10 05:42:19 PM PDT 24
Finished Jun 10 05:42:23 PM PDT 24
Peak memory 200360 kb
Host smart-70a186ec-4544-4dee-8424-f9543a41a31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871907411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1871907411
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.515308353
Short name T28
Test name
Test status
Simulation time 10856488560 ps
CPU time 695.81 seconds
Started Jun 10 05:42:22 PM PDT 24
Finished Jun 10 05:53:59 PM PDT 24
Peak memory 699452 kb
Host smart-db99a4d0-d605-4222-94dc-c404cc8d3ed4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=515308353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.515308353
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1888460761
Short name T184
Test name
Test status
Simulation time 2517785309 ps
CPU time 139.21 seconds
Started Jun 10 05:42:42 PM PDT 24
Finished Jun 10 05:45:02 PM PDT 24
Peak memory 200516 kb
Host smart-c3494535-2c51-4342-baf6-028ae2826454
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888460761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1888460761
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1446781401
Short name T462
Test name
Test status
Simulation time 1778889421 ps
CPU time 112 seconds
Started Jun 10 05:42:18 PM PDT 24
Finished Jun 10 05:44:11 PM PDT 24
Peak memory 200428 kb
Host smart-0662f0b1-e333-491a-8190-9a5499259620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446781401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1446781401
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1569478173
Short name T444
Test name
Test status
Simulation time 491979926 ps
CPU time 7.42 seconds
Started Jun 10 05:42:17 PM PDT 24
Finished Jun 10 05:42:25 PM PDT 24
Peak memory 200544 kb
Host smart-d22f02b0-74ec-4b0c-b1c8-f8e0896913e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569478173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1569478173
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.3738011431
Short name T95
Test name
Test status
Simulation time 34703582316 ps
CPU time 609.67 seconds
Started Jun 10 05:42:18 PM PDT 24
Finished Jun 10 05:52:28 PM PDT 24
Peak memory 200516 kb
Host smart-3b1232f9-ab24-435b-ac85-ac46a32d7607
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738011431 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3738011431
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.2521055872
Short name T414
Test name
Test status
Simulation time 92593845 ps
CPU time 1.12 seconds
Started Jun 10 05:42:36 PM PDT 24
Finished Jun 10 05:42:37 PM PDT 24
Peak memory 200384 kb
Host smart-0f515edf-fb77-4b07-8178-430f57af3729
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521055872 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.2521055872
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.910854102
Short name T92
Test name
Test status
Simulation time 27656016099 ps
CPU time 487.6 seconds
Started Jun 10 05:42:18 PM PDT 24
Finished Jun 10 05:50:26 PM PDT 24
Peak memory 200444 kb
Host smart-2789fcfd-ad7a-4786-880e-8a88679b41ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910854102 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.910854102
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1847199717
Short name T470
Test name
Test status
Simulation time 12420462151 ps
CPU time 20.39 seconds
Started Jun 10 05:42:24 PM PDT 24
Finished Jun 10 05:42:45 PM PDT 24
Peak memory 200512 kb
Host smart-a3053ac7-f16c-4f0a-b9fc-f2faf5c1c6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847199717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1847199717
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.489835048
Short name T536
Test name
Test status
Simulation time 19528032 ps
CPU time 0.58 seconds
Started Jun 10 05:42:23 PM PDT 24
Finished Jun 10 05:42:24 PM PDT 24
Peak memory 195392 kb
Host smart-5e3dc10f-30f5-4873-8cce-c16444d27a55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489835048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.489835048
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.2118589777
Short name T433
Test name
Test status
Simulation time 966498956 ps
CPU time 47.32 seconds
Started Jun 10 05:42:31 PM PDT 24
Finished Jun 10 05:43:20 PM PDT 24
Peak memory 229376 kb
Host smart-3805f080-6281-4e63-a951-175f4ca78f2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2118589777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2118589777
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1925527625
Short name T247
Test name
Test status
Simulation time 2576806442 ps
CPU time 73.66 seconds
Started Jun 10 05:42:35 PM PDT 24
Finished Jun 10 05:43:49 PM PDT 24
Peak memory 200520 kb
Host smart-b12c1a12-d917-49da-bca5-1f8a44aa979d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925527625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1925527625
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3167112262
Short name T200
Test name
Test status
Simulation time 2407302489 ps
CPU time 773.55 seconds
Started Jun 10 05:42:19 PM PDT 24
Finished Jun 10 05:55:13 PM PDT 24
Peak memory 748668 kb
Host smart-54e935b2-b2e8-402d-9b9a-92a6d54e81bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3167112262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3167112262
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1814597736
Short name T312
Test name
Test status
Simulation time 8194676863 ps
CPU time 109.48 seconds
Started Jun 10 05:42:30 PM PDT 24
Finished Jun 10 05:44:21 PM PDT 24
Peak memory 200520 kb
Host smart-0ba53c8f-5137-433e-b7f5-cd2d4d854006
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814597736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1814597736
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2724041653
Short name T6
Test name
Test status
Simulation time 5870448167 ps
CPU time 63.34 seconds
Started Jun 10 05:42:20 PM PDT 24
Finished Jun 10 05:43:24 PM PDT 24
Peak memory 200532 kb
Host smart-9f5ec352-9c2c-43fd-ace8-041c1878f7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724041653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2724041653
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.487832213
Short name T350
Test name
Test status
Simulation time 59241987 ps
CPU time 1.99 seconds
Started Jun 10 05:42:23 PM PDT 24
Finished Jun 10 05:42:25 PM PDT 24
Peak memory 200508 kb
Host smart-412da088-be7f-4f9b-803c-4e59024953ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487832213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.487832213
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1931246450
Short name T216
Test name
Test status
Simulation time 39845610293 ps
CPU time 578.11 seconds
Started Jun 10 05:42:38 PM PDT 24
Finished Jun 10 05:52:17 PM PDT 24
Peak memory 200424 kb
Host smart-cea3079d-a1b0-4a64-ada7-47cd8b9fbf57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931246450 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1931246450
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.377797112
Short name T288
Test name
Test status
Simulation time 104526995 ps
CPU time 1.11 seconds
Started Jun 10 05:42:24 PM PDT 24
Finished Jun 10 05:42:25 PM PDT 24
Peak memory 200264 kb
Host smart-ce09b746-86af-487c-9b61-7666ae8fd7e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377797112 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_hmac_vectors.377797112
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.2645561010
Short name T147
Test name
Test status
Simulation time 96303036157 ps
CPU time 513.04 seconds
Started Jun 10 05:42:41 PM PDT 24
Finished Jun 10 05:51:15 PM PDT 24
Peak memory 200464 kb
Host smart-aae494bb-863b-4706-b633-454ba4efd13c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645561010 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.2645561010
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2755082421
Short name T403
Test name
Test status
Simulation time 7730343726 ps
CPU time 42.53 seconds
Started Jun 10 05:42:18 PM PDT 24
Finished Jun 10 05:43:01 PM PDT 24
Peak memory 200548 kb
Host smart-7b5bc31b-e642-4a99-908e-1bdc5fbd21c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755082421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2755082421
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.200060330
Short name T212
Test name
Test status
Simulation time 37848349 ps
CPU time 0.64 seconds
Started Jun 10 05:42:36 PM PDT 24
Finished Jun 10 05:42:37 PM PDT 24
Peak memory 196304 kb
Host smart-ab70f9d3-2926-450c-b55a-135428201fc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200060330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.200060330
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2977657121
Short name T117
Test name
Test status
Simulation time 3527155706 ps
CPU time 47.93 seconds
Started Jun 10 05:42:41 PM PDT 24
Finished Jun 10 05:43:30 PM PDT 24
Peak memory 229796 kb
Host smart-c233fe25-4ba7-43e6-bd5d-6bd9cc206a79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2977657121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2977657121
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1982174118
Short name T554
Test name
Test status
Simulation time 4931678448 ps
CPU time 48.44 seconds
Started Jun 10 05:42:18 PM PDT 24
Finished Jun 10 05:43:07 PM PDT 24
Peak memory 200536 kb
Host smart-20e4772c-15e6-4094-bdae-279bf9e154ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982174118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1982174118
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3874475933
Short name T77
Test name
Test status
Simulation time 5611063151 ps
CPU time 215.92 seconds
Started Jun 10 05:42:18 PM PDT 24
Finished Jun 10 05:45:55 PM PDT 24
Peak memory 436652 kb
Host smart-bbbce43f-753d-44bf-8e6c-940ae3c2caae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3874475933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3874475933
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.958921767
Short name T457
Test name
Test status
Simulation time 692182247 ps
CPU time 10.52 seconds
Started Jun 10 05:42:20 PM PDT 24
Finished Jun 10 05:42:31 PM PDT 24
Peak memory 200476 kb
Host smart-123980ab-b1cb-4eb1-bcef-3af2acdd86cd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958921767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.958921767
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3605203013
Short name T322
Test name
Test status
Simulation time 6703644555 ps
CPU time 104.88 seconds
Started Jun 10 05:42:36 PM PDT 24
Finished Jun 10 05:44:22 PM PDT 24
Peak memory 200436 kb
Host smart-b6f94663-d53c-4198-863d-622a78594012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605203013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3605203013
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1008257301
Short name T290
Test name
Test status
Simulation time 327298713 ps
CPU time 5.85 seconds
Started Jun 10 05:42:20 PM PDT 24
Finished Jun 10 05:42:26 PM PDT 24
Peak memory 200408 kb
Host smart-e0574b94-127c-4fc7-9670-d1fee484c0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008257301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1008257301
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.477273096
Short name T435
Test name
Test status
Simulation time 30821415458 ps
CPU time 667.55 seconds
Started Jun 10 05:42:44 PM PDT 24
Finished Jun 10 05:53:52 PM PDT 24
Peak memory 519556 kb
Host smart-6322f8b0-c5e0-4eb8-9659-5d08bea71a27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477273096 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.477273096
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.3765713016
Short name T438
Test name
Test status
Simulation time 219624442 ps
CPU time 1.19 seconds
Started Jun 10 05:42:38 PM PDT 24
Finished Jun 10 05:42:40 PM PDT 24
Peak memory 200440 kb
Host smart-71efe824-28c2-4cf3-bb43-b640f2cf722d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765713016 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.3765713016
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.307807617
Short name T532
Test name
Test status
Simulation time 207536027237 ps
CPU time 478.35 seconds
Started Jun 10 05:42:24 PM PDT 24
Finished Jun 10 05:50:23 PM PDT 24
Peak memory 200400 kb
Host smart-75889627-6daf-4b5e-b50d-2fcd7bdb5423
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307807617 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.307807617
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2499989783
Short name T295
Test name
Test status
Simulation time 5068037992 ps
CPU time 45.25 seconds
Started Jun 10 05:42:21 PM PDT 24
Finished Jun 10 05:43:07 PM PDT 24
Peak memory 200472 kb
Host smart-449e0cad-363f-4aef-bdc1-6c4cd3b6df35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499989783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2499989783
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2453686758
Short name T254
Test name
Test status
Simulation time 14571025 ps
CPU time 0.58 seconds
Started Jun 10 05:42:46 PM PDT 24
Finished Jun 10 05:42:47 PM PDT 24
Peak memory 197152 kb
Host smart-2adabc94-7304-4fd9-8adf-7c4b4da7ab03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453686758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2453686758
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2603484166
Short name T544
Test name
Test status
Simulation time 4379529981 ps
CPU time 55.3 seconds
Started Jun 10 05:42:25 PM PDT 24
Finished Jun 10 05:43:20 PM PDT 24
Peak memory 216208 kb
Host smart-2b69b916-7848-4bc5-bfb7-383678fc8d77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2603484166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2603484166
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3265592866
Short name T399
Test name
Test status
Simulation time 9642648568 ps
CPU time 47.87 seconds
Started Jun 10 05:42:22 PM PDT 24
Finished Jun 10 05:43:10 PM PDT 24
Peak memory 200436 kb
Host smart-9f27815b-aea1-49ac-94ea-7ce1146945a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265592866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3265592866
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.3194204631
Short name T173
Test name
Test status
Simulation time 5232365805 ps
CPU time 521.65 seconds
Started Jun 10 05:42:27 PM PDT 24
Finished Jun 10 05:51:09 PM PDT 24
Peak memory 668204 kb
Host smart-7525b6ba-5638-4d6e-b8be-01241144be16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3194204631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.3194204631
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.896901237
Short name T191
Test name
Test status
Simulation time 4235406743 ps
CPU time 49.45 seconds
Started Jun 10 05:42:31 PM PDT 24
Finished Jun 10 05:43:21 PM PDT 24
Peak memory 200512 kb
Host smart-6bfad70b-9304-48e3-8a23-5c3bf58f2d8a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896901237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.896901237
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2535333160
Short name T540
Test name
Test status
Simulation time 3524417323 ps
CPU time 27.47 seconds
Started Jun 10 05:42:32 PM PDT 24
Finished Jun 10 05:43:00 PM PDT 24
Peak memory 200484 kb
Host smart-cc1e873c-a8e0-4093-babd-f7bcf7cad056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535333160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2535333160
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1141144538
Short name T383
Test name
Test status
Simulation time 1643262301 ps
CPU time 10.49 seconds
Started Jun 10 05:42:37 PM PDT 24
Finished Jun 10 05:42:48 PM PDT 24
Peak memory 200240 kb
Host smart-f808154c-172d-4e3c-8f76-6dc165ce9d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141144538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1141144538
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.612482747
Short name T219
Test name
Test status
Simulation time 303060253 ps
CPU time 1.36 seconds
Started Jun 10 05:42:24 PM PDT 24
Finished Jun 10 05:42:25 PM PDT 24
Peak memory 200252 kb
Host smart-edd88c77-cd53-48ff-bd7d-0d056c628877
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612482747 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.612482747
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.3107484867
Short name T368
Test name
Test status
Simulation time 112204148419 ps
CPU time 519.5 seconds
Started Jun 10 05:42:23 PM PDT 24
Finished Jun 10 05:51:03 PM PDT 24
Peak memory 200504 kb
Host smart-64d9e3d1-0089-44a7-9184-3d1f5ad36eb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107484867 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.3107484867
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.552618194
Short name T581
Test name
Test status
Simulation time 2259481333 ps
CPU time 42.35 seconds
Started Jun 10 05:42:41 PM PDT 24
Finished Jun 10 05:43:24 PM PDT 24
Peak memory 200540 kb
Host smart-6d23acf1-8aef-4a5d-9492-194cfc028e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552618194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.552618194
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3106614613
Short name T388
Test name
Test status
Simulation time 29045838 ps
CPU time 0.57 seconds
Started Jun 10 05:42:31 PM PDT 24
Finished Jun 10 05:42:32 PM PDT 24
Peak memory 196032 kb
Host smart-178223cb-7a85-4370-8f3d-5a0186a3ea47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106614613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3106614613
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2555042425
Short name T568
Test name
Test status
Simulation time 1230944454 ps
CPU time 11.62 seconds
Started Jun 10 05:42:22 PM PDT 24
Finished Jun 10 05:42:34 PM PDT 24
Peak memory 215872 kb
Host smart-731359a6-a859-4d85-8c97-ad08de47cd4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2555042425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2555042425
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.480355925
Short name T499
Test name
Test status
Simulation time 199889384 ps
CPU time 9.72 seconds
Started Jun 10 05:42:24 PM PDT 24
Finished Jun 10 05:42:34 PM PDT 24
Peak memory 200520 kb
Host smart-c8373a2e-4f53-4461-9d09-818e6d4ce049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480355925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.480355925
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1944559250
Short name T330
Test name
Test status
Simulation time 2000029503 ps
CPU time 449 seconds
Started Jun 10 05:42:39 PM PDT 24
Finished Jun 10 05:50:09 PM PDT 24
Peak memory 654964 kb
Host smart-09e7a423-f7f4-4a00-acd8-18c22a0e6ec7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1944559250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1944559250
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3977888851
Short name T488
Test name
Test status
Simulation time 9936170553 ps
CPU time 135 seconds
Started Jun 10 05:42:30 PM PDT 24
Finished Jun 10 05:44:46 PM PDT 24
Peak memory 200628 kb
Host smart-cf869b9f-9b55-4cbd-b765-6ea11add3c2b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977888851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3977888851
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.631621832
Short name T129
Test name
Test status
Simulation time 9452022776 ps
CPU time 47.19 seconds
Started Jun 10 05:42:43 PM PDT 24
Finished Jun 10 05:43:30 PM PDT 24
Peak memory 200456 kb
Host smart-1c9d1740-e089-4bdb-baa6-95463f61f02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631621832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.631621832
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3415223433
Short name T583
Test name
Test status
Simulation time 659520265 ps
CPU time 6.31 seconds
Started Jun 10 05:42:22 PM PDT 24
Finished Jun 10 05:42:28 PM PDT 24
Peak memory 200408 kb
Host smart-186f2077-bf2a-4466-b71f-28d4ccb73d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415223433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3415223433
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3103438079
Short name T267
Test name
Test status
Simulation time 32349544606 ps
CPU time 562.71 seconds
Started Jun 10 05:42:31 PM PDT 24
Finished Jun 10 05:51:55 PM PDT 24
Peak memory 216932 kb
Host smart-41f4bd30-9e87-4c8b-bbcc-eb08dcdc3372
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103438079 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3103438079
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.1790523153
Short name T268
Test name
Test status
Simulation time 226233585 ps
CPU time 1.15 seconds
Started Jun 10 05:42:33 PM PDT 24
Finished Jun 10 05:42:34 PM PDT 24
Peak memory 200492 kb
Host smart-cb399175-4c6f-49af-9dd9-443cb3fa52a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790523153 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.1790523153
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.1444190575
Short name T562
Test name
Test status
Simulation time 100869768390 ps
CPU time 474.35 seconds
Started Jun 10 05:42:40 PM PDT 24
Finished Jun 10 05:50:35 PM PDT 24
Peak memory 200380 kb
Host smart-b18a00cd-ff70-4f44-b594-357b7cc5378c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444190575 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.1444190575
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2124429603
Short name T50
Test name
Test status
Simulation time 2174017766 ps
CPU time 91 seconds
Started Jun 10 05:42:27 PM PDT 24
Finished Jun 10 05:43:59 PM PDT 24
Peak memory 200460 kb
Host smart-84a766b5-3ffb-4c69-a0c8-074354b44fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124429603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2124429603
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.622167037
Short name T242
Test name
Test status
Simulation time 25663289 ps
CPU time 0.61 seconds
Started Jun 10 05:42:28 PM PDT 24
Finished Jun 10 05:42:29 PM PDT 24
Peak memory 196296 kb
Host smart-cb185f78-e5f6-4cc6-921e-8f471d44895e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622167037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.622167037
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.4038635
Short name T379
Test name
Test status
Simulation time 5731189188 ps
CPU time 24.52 seconds
Started Jun 10 05:42:31 PM PDT 24
Finished Jun 10 05:42:56 PM PDT 24
Peak memory 200480 kb
Host smart-3b477882-ad2a-4124-b776-0406f6f9c470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.4038635
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.4165057805
Short name T128
Test name
Test status
Simulation time 980106625 ps
CPU time 213.6 seconds
Started Jun 10 05:42:28 PM PDT 24
Finished Jun 10 05:46:02 PM PDT 24
Peak memory 635048 kb
Host smart-6fcec3f9-5b53-4497-9953-97fb7b376879
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4165057805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.4165057805
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.4015995028
Short name T415
Test name
Test status
Simulation time 6025732498 ps
CPU time 38.54 seconds
Started Jun 10 05:42:44 PM PDT 24
Finished Jun 10 05:43:23 PM PDT 24
Peak memory 200556 kb
Host smart-83af6ac7-a94a-4f2b-a270-0e5fb14868ea
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015995028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.4015995028
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1004031679
Short name T465
Test name
Test status
Simulation time 1124149977 ps
CPU time 62.02 seconds
Started Jun 10 05:42:43 PM PDT 24
Finished Jun 10 05:43:45 PM PDT 24
Peak memory 200424 kb
Host smart-d2d63cb7-38eb-438b-95fd-77f647b48f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004031679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1004031679
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3506093831
Short name T344
Test name
Test status
Simulation time 189256696 ps
CPU time 3.79 seconds
Started Jun 10 05:42:37 PM PDT 24
Finished Jun 10 05:42:41 PM PDT 24
Peak memory 200288 kb
Host smart-49cc58c0-ae81-4598-87e5-95489279a7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506093831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3506093831
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.420271755
Short name T545
Test name
Test status
Simulation time 40578294610 ps
CPU time 539.39 seconds
Started Jun 10 05:42:32 PM PDT 24
Finished Jun 10 05:51:32 PM PDT 24
Peak memory 233272 kb
Host smart-67c97c9c-250b-4b2a-8f8b-d061c7225466
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420271755 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.420271755
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.1686558973
Short name T209
Test name
Test status
Simulation time 61970916 ps
CPU time 1.18 seconds
Started Jun 10 05:42:32 PM PDT 24
Finished Jun 10 05:42:34 PM PDT 24
Peak memory 200220 kb
Host smart-f60cc3df-6cca-41ad-a900-d676a665794c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686558973 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.1686558973
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.4113302409
Short name T113
Test name
Test status
Simulation time 6841934509 ps
CPU time 379.48 seconds
Started Jun 10 05:42:43 PM PDT 24
Finished Jun 10 05:49:03 PM PDT 24
Peak memory 200448 kb
Host smart-d68a5600-38f0-4356-ac72-c422ae082c74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113302409 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.4113302409
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.971557600
Short name T481
Test name
Test status
Simulation time 1456186355 ps
CPU time 54.68 seconds
Started Jun 10 05:42:32 PM PDT 24
Finished Jun 10 05:43:27 PM PDT 24
Peak memory 200444 kb
Host smart-b5538d71-ebd8-4a4d-855b-cd96d886daa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971557600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.971557600
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.4093228599
Short name T473
Test name
Test status
Simulation time 12075529 ps
CPU time 0.57 seconds
Started Jun 10 05:42:33 PM PDT 24
Finished Jun 10 05:42:34 PM PDT 24
Peak memory 195248 kb
Host smart-6472f0b9-452e-4a5b-a19e-439884ae9a2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093228599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.4093228599
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2212084082
Short name T36
Test name
Test status
Simulation time 2316977542 ps
CPU time 21.92 seconds
Started Jun 10 05:42:33 PM PDT 24
Finished Jun 10 05:42:56 PM PDT 24
Peak memory 208660 kb
Host smart-5aa27691-497b-4956-91d8-5f1c2e70f6f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2212084082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2212084082
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1114745031
Short name T337
Test name
Test status
Simulation time 3787205765 ps
CPU time 50.13 seconds
Started Jun 10 05:42:30 PM PDT 24
Finished Jun 10 05:43:21 PM PDT 24
Peak memory 200620 kb
Host smart-da2fbc1d-b948-45a8-b52c-58a162a7e514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114745031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1114745031
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2736624244
Short name T302
Test name
Test status
Simulation time 1113539265 ps
CPU time 125.39 seconds
Started Jun 10 05:42:43 PM PDT 24
Finished Jun 10 05:44:49 PM PDT 24
Peak memory 449516 kb
Host smart-df57f73f-e9e4-47a9-b477-9b7263f86c45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2736624244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2736624244
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3227972889
Short name T521
Test name
Test status
Simulation time 11190876820 ps
CPU time 97.97 seconds
Started Jun 10 05:42:30 PM PDT 24
Finished Jun 10 05:44:09 PM PDT 24
Peak memory 200540 kb
Host smart-3f653ebe-a452-4419-9487-a8edd71d5ff2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227972889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3227972889
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1761940535
Short name T162
Test name
Test status
Simulation time 1628963892 ps
CPU time 97.45 seconds
Started Jun 10 05:42:43 PM PDT 24
Finished Jun 10 05:44:21 PM PDT 24
Peak memory 200496 kb
Host smart-d2d7e28f-3345-4bdf-a428-8576f6701217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761940535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1761940535
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3357204630
Short name T287
Test name
Test status
Simulation time 98898088 ps
CPU time 3.48 seconds
Started Jun 10 05:42:27 PM PDT 24
Finished Jun 10 05:42:31 PM PDT 24
Peak memory 200400 kb
Host smart-bb5db378-9e87-4dcf-8e48-cc7a3d44df81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357204630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3357204630
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.2020248949
Short name T285
Test name
Test status
Simulation time 16159466903 ps
CPU time 318.59 seconds
Started Jun 10 05:42:34 PM PDT 24
Finished Jun 10 05:47:53 PM PDT 24
Peak memory 200544 kb
Host smart-afe6af83-fecc-4b77-8faa-005c15c6dd39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020248949 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.2020248949
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.1019021031
Short name T331
Test name
Test status
Simulation time 35776113 ps
CPU time 1.42 seconds
Started Jun 10 05:42:48 PM PDT 24
Finished Jun 10 05:42:50 PM PDT 24
Peak memory 200400 kb
Host smart-0c99d4df-7782-4b0c-a93c-33d8e9890e6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019021031 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.1019021031
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.1579872734
Short name T353
Test name
Test status
Simulation time 59201822266 ps
CPU time 529.28 seconds
Started Jun 10 05:42:41 PM PDT 24
Finished Jun 10 05:51:31 PM PDT 24
Peak memory 200436 kb
Host smart-2d00d40c-fd89-4e45-9be8-5cc8aa0ecc0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579872734 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.1579872734
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3811377394
Short name T436
Test name
Test status
Simulation time 1950141323 ps
CPU time 37.84 seconds
Started Jun 10 05:42:41 PM PDT 24
Finished Jun 10 05:43:19 PM PDT 24
Peak memory 200396 kb
Host smart-168289fd-663b-4af4-8f34-7a18d93331ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811377394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3811377394
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.961070602
Short name T588
Test name
Test status
Simulation time 36291460 ps
CPU time 0.57 seconds
Started Jun 10 05:42:33 PM PDT 24
Finished Jun 10 05:42:34 PM PDT 24
Peak memory 196436 kb
Host smart-88acde3b-7bd8-442c-b095-2aa440e606bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961070602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.961070602
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2563465657
Short name T451
Test name
Test status
Simulation time 417893378 ps
CPU time 20.01 seconds
Started Jun 10 05:42:43 PM PDT 24
Finished Jun 10 05:43:04 PM PDT 24
Peak memory 219808 kb
Host smart-2e4e12f9-7da4-43b9-9d05-c6b6ee03d2ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2563465657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2563465657
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2284933795
Short name T558
Test name
Test status
Simulation time 14182222904 ps
CPU time 59.79 seconds
Started Jun 10 05:42:34 PM PDT 24
Finished Jun 10 05:43:35 PM PDT 24
Peak memory 200476 kb
Host smart-b1c75e5b-7fcb-4418-850b-27e6c501692c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284933795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2284933795
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1875165096
Short name T84
Test name
Test status
Simulation time 19639386388 ps
CPU time 1283.34 seconds
Started Jun 10 05:42:31 PM PDT 24
Finished Jun 10 06:03:55 PM PDT 24
Peak memory 777720 kb
Host smart-29112bc5-5ccc-4bc9-bb85-d72841f41f8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1875165096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1875165096
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3336698145
Short name T305
Test name
Test status
Simulation time 10007873346 ps
CPU time 187.98 seconds
Started Jun 10 05:42:45 PM PDT 24
Finished Jun 10 05:45:54 PM PDT 24
Peak memory 200508 kb
Host smart-0fda8b9c-7076-4ae7-95ca-9d62f3c99582
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336698145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3336698145
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.766643305
Short name T253
Test name
Test status
Simulation time 10305286208 ps
CPU time 35.43 seconds
Started Jun 10 05:42:45 PM PDT 24
Finished Jun 10 05:43:21 PM PDT 24
Peak memory 200496 kb
Host smart-c7ba281f-96b6-40d8-bcb3-f20e9a1869a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766643305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.766643305
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2600158283
Short name T220
Test name
Test status
Simulation time 144420313 ps
CPU time 3.81 seconds
Started Jun 10 05:42:41 PM PDT 24
Finished Jun 10 05:42:45 PM PDT 24
Peak memory 200452 kb
Host smart-a67c1f46-18d6-4ad6-8035-90ea666aa70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600158283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2600158283
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3239503726
Short name T61
Test name
Test status
Simulation time 44534848082 ps
CPU time 681.11 seconds
Started Jun 10 05:42:35 PM PDT 24
Finished Jun 10 05:53:56 PM PDT 24
Peak memory 240692 kb
Host smart-b877125c-3e7a-4cc2-abee-a11f5c9eab9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239503726 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3239503726
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.1245405186
Short name T425
Test name
Test status
Simulation time 214351347 ps
CPU time 1.13 seconds
Started Jun 10 05:42:43 PM PDT 24
Finished Jun 10 05:42:45 PM PDT 24
Peak memory 200080 kb
Host smart-5eb8fb8b-866d-4d0b-a468-a1e0bdea3c70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245405186 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.1245405186
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.276565121
Short name T122
Test name
Test status
Simulation time 69831981062 ps
CPU time 507.33 seconds
Started Jun 10 05:42:33 PM PDT 24
Finished Jun 10 05:51:01 PM PDT 24
Peak memory 200432 kb
Host smart-1643b2f5-e4e6-4622-9d8e-d68d866310e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276565121 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.276565121
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1864328809
Short name T276
Test name
Test status
Simulation time 7314794089 ps
CPU time 81.46 seconds
Started Jun 10 05:42:42 PM PDT 24
Finished Jun 10 05:44:04 PM PDT 24
Peak memory 200448 kb
Host smart-6fdb15c9-af15-4c8a-b0e8-d9eab2ed5013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864328809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1864328809
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.456825458
Short name T29
Test name
Test status
Simulation time 48262101 ps
CPU time 0.58 seconds
Started Jun 10 05:42:40 PM PDT 24
Finished Jun 10 05:42:41 PM PDT 24
Peak memory 195332 kb
Host smart-b09a7298-1f63-4d91-a5fc-c4baa106e8aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456825458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.456825458
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1558400514
Short name T280
Test name
Test status
Simulation time 2642420440 ps
CPU time 60.9 seconds
Started Jun 10 05:42:32 PM PDT 24
Finished Jun 10 05:43:34 PM PDT 24
Peak memory 226384 kb
Host smart-e39b6a26-6ff1-44ce-9ee3-253d27842923
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1558400514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1558400514
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.549778027
Short name T505
Test name
Test status
Simulation time 14790917480 ps
CPU time 59.72 seconds
Started Jun 10 05:42:34 PM PDT 24
Finished Jun 10 05:43:34 PM PDT 24
Peak memory 200532 kb
Host smart-9c6eb577-23c9-450b-b25d-c349cb10774f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549778027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.549778027
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.400309682
Short name T54
Test name
Test status
Simulation time 3464568695 ps
CPU time 863.93 seconds
Started Jun 10 05:42:31 PM PDT 24
Finished Jun 10 05:56:56 PM PDT 24
Peak memory 733856 kb
Host smart-4b26ae25-a20e-4e27-951e-272c3e2996df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=400309682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.400309682
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3304203408
Short name T314
Test name
Test status
Simulation time 943127651 ps
CPU time 53.06 seconds
Started Jun 10 05:42:37 PM PDT 24
Finished Jun 10 05:43:31 PM PDT 24
Peak memory 200428 kb
Host smart-67039b60-238f-4fd8-b7fa-91bbeac57279
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304203408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3304203408
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.4090114378
Short name T552
Test name
Test status
Simulation time 20643067901 ps
CPU time 75.49 seconds
Started Jun 10 05:42:48 PM PDT 24
Finished Jun 10 05:44:04 PM PDT 24
Peak memory 200444 kb
Host smart-38be43a2-4f4d-4267-a19a-c90203fa830a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090114378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.4090114378
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1512193931
Short name T303
Test name
Test status
Simulation time 956952419 ps
CPU time 5.81 seconds
Started Jun 10 05:42:51 PM PDT 24
Finished Jun 10 05:42:58 PM PDT 24
Peak memory 200364 kb
Host smart-bca569e5-de8b-4f33-a401-ddd6fa19dae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512193931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1512193931
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.8012448
Short name T289
Test name
Test status
Simulation time 228198985737 ps
CPU time 1554.29 seconds
Started Jun 10 05:42:43 PM PDT 24
Finished Jun 10 06:08:38 PM PDT 24
Peak memory 714852 kb
Host smart-df99fc20-dc64-4b72-8ac5-2a9bbeeff415
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8012448 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.8012448
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.274382750
Short name T490
Test name
Test status
Simulation time 32813835 ps
CPU time 1.26 seconds
Started Jun 10 05:42:45 PM PDT 24
Finished Jun 10 05:42:46 PM PDT 24
Peak memory 200400 kb
Host smart-48cc774a-b5b7-44c3-99fe-968eaf669800
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274382750 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_hmac_vectors.274382750
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.1935805615
Short name T279
Test name
Test status
Simulation time 12261459315 ps
CPU time 433.91 seconds
Started Jun 10 05:42:32 PM PDT 24
Finished Jun 10 05:49:47 PM PDT 24
Peak memory 200516 kb
Host smart-feb2f8b4-f36d-4ae4-9f38-f15d972e8b36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935805615 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.1935805615
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2375835759
Short name T557
Test name
Test status
Simulation time 496476551 ps
CPU time 10.94 seconds
Started Jun 10 05:42:48 PM PDT 24
Finished Jun 10 05:42:59 PM PDT 24
Peak memory 200392 kb
Host smart-c89f801a-2c88-4dd2-80b9-5f6ef5707309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375835759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2375835759
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1402743412
Short name T307
Test name
Test status
Simulation time 66248489 ps
CPU time 0.59 seconds
Started Jun 10 05:42:49 PM PDT 24
Finished Jun 10 05:42:50 PM PDT 24
Peak memory 196084 kb
Host smart-3da43377-9621-4112-a12e-86863f9d72c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402743412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1402743412
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1289708497
Short name T38
Test name
Test status
Simulation time 445981941 ps
CPU time 4.45 seconds
Started Jun 10 05:42:33 PM PDT 24
Finished Jun 10 05:42:38 PM PDT 24
Peak memory 200456 kb
Host smart-f236a4c5-3679-42a4-9f79-67ac3af49574
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1289708497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1289708497
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1176130256
Short name T580
Test name
Test status
Simulation time 2178389579 ps
CPU time 22.54 seconds
Started Jun 10 05:42:38 PM PDT 24
Finished Jun 10 05:43:01 PM PDT 24
Peak memory 200548 kb
Host smart-b2109297-561a-42a7-8dd4-881f5d9da8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176130256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1176130256
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.2352867483
Short name T118
Test name
Test status
Simulation time 720562288 ps
CPU time 167.62 seconds
Started Jun 10 05:42:47 PM PDT 24
Finished Jun 10 05:45:35 PM PDT 24
Peak memory 639576 kb
Host smart-f70f8add-2060-4216-b7ca-d479597b1092
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2352867483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2352867483
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1798454721
Short name T235
Test name
Test status
Simulation time 2243290684 ps
CPU time 24.31 seconds
Started Jun 10 05:42:36 PM PDT 24
Finished Jun 10 05:43:01 PM PDT 24
Peak memory 200532 kb
Host smart-04a0d001-e324-435d-8c4f-9dbe8e620622
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798454721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1798454721
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3582200425
Short name T449
Test name
Test status
Simulation time 8329642823 ps
CPU time 35.11 seconds
Started Jun 10 05:42:37 PM PDT 24
Finished Jun 10 05:43:13 PM PDT 24
Peak memory 200520 kb
Host smart-ade237d3-b94f-4d7c-a844-6ee3e934fe29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582200425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3582200425
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2458692587
Short name T355
Test name
Test status
Simulation time 979088031 ps
CPU time 8.69 seconds
Started Jun 10 05:42:36 PM PDT 24
Finished Jun 10 05:42:45 PM PDT 24
Peak memory 200420 kb
Host smart-2f1d2b3e-54b9-48ab-ad96-cfd0bc7539a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458692587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2458692587
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2871272082
Short name T139
Test name
Test status
Simulation time 47036343031 ps
CPU time 963.81 seconds
Started Jun 10 05:42:36 PM PDT 24
Finished Jun 10 05:58:40 PM PDT 24
Peak memory 611376 kb
Host smart-7fad0164-04dc-4d7a-aac2-17c804a7d4ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871272082 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2871272082
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.2835189135
Short name T570
Test name
Test status
Simulation time 256115475 ps
CPU time 1.46 seconds
Started Jun 10 05:42:43 PM PDT 24
Finished Jun 10 05:42:45 PM PDT 24
Peak memory 200388 kb
Host smart-abeca1b6-5028-469d-8b3d-1e6b8af0b999
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835189135 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.2835189135
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.186925914
Short name T329
Test name
Test status
Simulation time 23190557226 ps
CPU time 450.47 seconds
Started Jun 10 05:42:44 PM PDT 24
Finished Jun 10 05:50:15 PM PDT 24
Peak memory 200480 kb
Host smart-86730759-c3ff-4e34-975f-ffd568ad0b9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186925914 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.186925914
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2970145074
Short name T472
Test name
Test status
Simulation time 15805166529 ps
CPU time 61.13 seconds
Started Jun 10 05:42:45 PM PDT 24
Finished Jun 10 05:43:46 PM PDT 24
Peak memory 200436 kb
Host smart-ee91e6d0-f802-45c3-a43d-ca04cf3a6c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970145074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2970145074
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2799120769
Short name T404
Test name
Test status
Simulation time 17024098 ps
CPU time 0.59 seconds
Started Jun 10 05:41:51 PM PDT 24
Finished Jun 10 05:41:52 PM PDT 24
Peak memory 196384 kb
Host smart-d3006cdf-83ed-4879-868b-a9c066be8e1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799120769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2799120769
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.1260625112
Short name T477
Test name
Test status
Simulation time 1107468000 ps
CPU time 49.86 seconds
Started Jun 10 05:41:38 PM PDT 24
Finished Jun 10 05:42:28 PM PDT 24
Peak memory 219848 kb
Host smart-49c59d70-8b09-446c-9280-283ac17014c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1260625112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1260625112
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.41156132
Short name T345
Test name
Test status
Simulation time 6686601311 ps
CPU time 46.75 seconds
Started Jun 10 05:41:56 PM PDT 24
Finished Jun 10 05:42:43 PM PDT 24
Peak memory 200384 kb
Host smart-389fc0ca-9086-49a2-aecc-60ab5511b80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41156132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.41156132
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2290913963
Short name T34
Test name
Test status
Simulation time 9193858484 ps
CPU time 1141.81 seconds
Started Jun 10 05:41:44 PM PDT 24
Finished Jun 10 06:00:46 PM PDT 24
Peak memory 756644 kb
Host smart-d3e87c96-fadd-46f2-9f4f-a083af23d932
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2290913963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2290913963
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1169753463
Short name T148
Test name
Test status
Simulation time 7903397057 ps
CPU time 96.73 seconds
Started Jun 10 05:41:55 PM PDT 24
Finished Jun 10 05:43:33 PM PDT 24
Peak memory 200456 kb
Host smart-e9e2593b-1259-468d-b0bf-8cf7b798df2a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169753463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1169753463
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2060036865
Short name T323
Test name
Test status
Simulation time 76781530804 ps
CPU time 128.41 seconds
Started Jun 10 05:42:05 PM PDT 24
Finished Jun 10 05:44:14 PM PDT 24
Peak memory 200516 kb
Host smart-5cd53095-dcc3-416f-acb1-76e57477d392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060036865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2060036865
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_smoke.2654399426
Short name T297
Test name
Test status
Simulation time 190989035 ps
CPU time 1.38 seconds
Started Jun 10 05:41:53 PM PDT 24
Finished Jun 10 05:41:56 PM PDT 24
Peak memory 200376 kb
Host smart-62219e4e-ee34-4d0c-b357-dee7b1765c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654399426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2654399426
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3748839946
Short name T248
Test name
Test status
Simulation time 7193208848 ps
CPU time 315.77 seconds
Started Jun 10 05:41:56 PM PDT 24
Finished Jun 10 05:47:13 PM PDT 24
Peak memory 629448 kb
Host smart-20c8f4eb-029a-4d18-9b01-ae93f51f232d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748839946 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3748839946
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.1611371335
Short name T315
Test name
Test status
Simulation time 52690261 ps
CPU time 1.07 seconds
Started Jun 10 05:41:56 PM PDT 24
Finished Jun 10 05:41:58 PM PDT 24
Peak memory 200264 kb
Host smart-a244061a-7f4f-4510-9d20-7e63d95b5313
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611371335 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.1611371335
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.811576257
Short name T381
Test name
Test status
Simulation time 173116821432 ps
CPU time 558.57 seconds
Started Jun 10 05:41:55 PM PDT 24
Finished Jun 10 05:51:14 PM PDT 24
Peak memory 200448 kb
Host smart-2d64990f-2690-466b-91a6-d193852cc6d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811576257 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.811576257
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3304183790
Short name T57
Test name
Test status
Simulation time 1018597563 ps
CPU time 41.85 seconds
Started Jun 10 05:41:55 PM PDT 24
Finished Jun 10 05:42:38 PM PDT 24
Peak memory 200348 kb
Host smart-fd735fda-15b4-42bb-9779-3b742a9c1917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304183790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3304183790
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2031246418
Short name T347
Test name
Test status
Simulation time 44039586 ps
CPU time 0.6 seconds
Started Jun 10 05:42:42 PM PDT 24
Finished Jun 10 05:42:43 PM PDT 24
Peak memory 196432 kb
Host smart-9fd55ebc-34d1-4b55-99cc-0a0be2f6fb41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031246418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2031246418
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2840609538
Short name T145
Test name
Test status
Simulation time 1991749629 ps
CPU time 24.87 seconds
Started Jun 10 05:42:37 PM PDT 24
Finished Jun 10 05:43:02 PM PDT 24
Peak memory 216792 kb
Host smart-e27de8d6-0d4f-4a8d-8f9b-7bd5172e73c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2840609538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2840609538
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.2644892752
Short name T210
Test name
Test status
Simulation time 13778490769 ps
CPU time 44.11 seconds
Started Jun 10 05:42:46 PM PDT 24
Finished Jun 10 05:43:30 PM PDT 24
Peak memory 200484 kb
Host smart-a6863d2f-68bc-47e5-9a44-db1779254b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644892752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2644892752
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2159664326
Short name T409
Test name
Test status
Simulation time 803662541 ps
CPU time 189.42 seconds
Started Jun 10 05:42:36 PM PDT 24
Finished Jun 10 05:45:46 PM PDT 24
Peak memory 665496 kb
Host smart-65c45ebd-a2ab-4b51-a132-3159aadc83ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2159664326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2159664326
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.2101992078
Short name T218
Test name
Test status
Simulation time 1920555639 ps
CPU time 20.27 seconds
Started Jun 10 05:42:40 PM PDT 24
Finished Jun 10 05:43:00 PM PDT 24
Peak memory 200216 kb
Host smart-4fd9cd41-4df5-41f2-ae79-0ebb8308d32f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101992078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2101992078
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.672610193
Short name T578
Test name
Test status
Simulation time 1748902072 ps
CPU time 96.77 seconds
Started Jun 10 05:42:36 PM PDT 24
Finished Jun 10 05:44:13 PM PDT 24
Peak memory 200392 kb
Host smart-697ad714-de3e-4e69-9609-9d167ffa9aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672610193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.672610193
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3724859386
Short name T564
Test name
Test status
Simulation time 115620819 ps
CPU time 1.33 seconds
Started Jun 10 05:42:36 PM PDT 24
Finished Jun 10 05:42:38 PM PDT 24
Peak memory 200420 kb
Host smart-13ce761c-3dd1-43c8-80a9-6c0713235ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724859386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3724859386
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1300603873
Short name T528
Test name
Test status
Simulation time 130195329353 ps
CPU time 2754.96 seconds
Started Jun 10 05:42:43 PM PDT 24
Finished Jun 10 06:28:38 PM PDT 24
Peak memory 735708 kb
Host smart-e66a8817-0f84-4f7d-8b00-50a891c71404
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300603873 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1300603873
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_stress_all_with_rand_reset.3797965818
Short name T47
Test name
Test status
Simulation time 58966271673 ps
CPU time 3235.3 seconds
Started Jun 10 05:42:40 PM PDT 24
Finished Jun 10 06:36:37 PM PDT 24
Peak memory 258028 kb
Host smart-a0e8bd26-5dc9-4416-9f9c-a993c51ce05e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3797965818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all_with_rand_reset.3797965818
Directory /workspace/30.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.2600748009
Short name T171
Test name
Test status
Simulation time 231005381 ps
CPU time 1.34 seconds
Started Jun 10 05:42:45 PM PDT 24
Finished Jun 10 05:42:46 PM PDT 24
Peak memory 200452 kb
Host smart-8227a90b-75c3-445b-90c6-5f1d83298e17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600748009 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.2600748009
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.3564571391
Short name T411
Test name
Test status
Simulation time 25266340693 ps
CPU time 447.76 seconds
Started Jun 10 05:42:36 PM PDT 24
Finished Jun 10 05:50:05 PM PDT 24
Peak memory 200456 kb
Host smart-beaa45c8-a926-4ac4-82f1-c871d921e307
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564571391 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.3564571391
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.1941757130
Short name T186
Test name
Test status
Simulation time 11983189177 ps
CPU time 62.75 seconds
Started Jun 10 05:42:38 PM PDT 24
Finished Jun 10 05:43:41 PM PDT 24
Peak memory 200512 kb
Host smart-848f77d4-5a7c-4c50-9f5a-4dd415bc337a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941757130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1941757130
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.212277349
Short name T224
Test name
Test status
Simulation time 33171128 ps
CPU time 0.66 seconds
Started Jun 10 05:42:47 PM PDT 24
Finished Jun 10 05:42:48 PM PDT 24
Peak memory 197092 kb
Host smart-2fa9794b-3971-459e-a85c-f80d2892fbf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212277349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.212277349
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.777374169
Short name T441
Test name
Test status
Simulation time 205261396 ps
CPU time 11.72 seconds
Started Jun 10 05:42:44 PM PDT 24
Finished Jun 10 05:42:57 PM PDT 24
Peak memory 216816 kb
Host smart-a7860f6f-bb68-4775-bd4e-ca7d7aec8679
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=777374169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.777374169
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2833538090
Short name T506
Test name
Test status
Simulation time 2616574253 ps
CPU time 70.97 seconds
Started Jun 10 05:42:46 PM PDT 24
Finished Jun 10 05:43:57 PM PDT 24
Peak memory 200496 kb
Host smart-6f3a38ca-b5cf-45bd-92c7-c796c661e880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833538090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2833538090
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2057591579
Short name T423
Test name
Test status
Simulation time 17556489028 ps
CPU time 689.13 seconds
Started Jun 10 05:42:40 PM PDT 24
Finished Jun 10 05:54:10 PM PDT 24
Peak memory 727984 kb
Host smart-c6fa70ae-6ac8-44ce-8ff0-4489ba6d3cac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2057591579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2057591579
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3394208366
Short name T291
Test name
Test status
Simulation time 14154538769 ps
CPU time 168.03 seconds
Started Jun 10 05:42:52 PM PDT 24
Finished Jun 10 05:45:40 PM PDT 24
Peak memory 200496 kb
Host smart-d607fe7e-7ea0-4562-a692-0375f5434ac3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394208366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3394208366
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1653174626
Short name T214
Test name
Test status
Simulation time 44603531318 ps
CPU time 102.83 seconds
Started Jun 10 05:42:42 PM PDT 24
Finished Jun 10 05:44:25 PM PDT 24
Peak memory 200476 kb
Host smart-06081272-e01e-4577-8aec-862b8216f531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653174626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1653174626
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.4182088188
Short name T503
Test name
Test status
Simulation time 4949056947 ps
CPU time 17.09 seconds
Started Jun 10 05:42:46 PM PDT 24
Finished Jun 10 05:43:03 PM PDT 24
Peak memory 200536 kb
Host smart-ffaad1d7-ebd9-4143-9314-f9ed07b84564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182088188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.4182088188
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1430982787
Short name T206
Test name
Test status
Simulation time 3850770219 ps
CPU time 334.17 seconds
Started Jun 10 05:42:55 PM PDT 24
Finished Jun 10 05:48:30 PM PDT 24
Peak memory 690796 kb
Host smart-5af7e6b9-4f5b-4174-b2b3-044be8906c22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430982787 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1430982787
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.2142460604
Short name T437
Test name
Test status
Simulation time 33993798 ps
CPU time 1.25 seconds
Started Jun 10 05:42:48 PM PDT 24
Finished Jun 10 05:42:50 PM PDT 24
Peak memory 200360 kb
Host smart-3bcefec7-82b7-4278-adc8-cf541d1fab3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142460604 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.2142460604
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.4048770423
Short name T454
Test name
Test status
Simulation time 80652123334 ps
CPU time 525.18 seconds
Started Jun 10 05:42:55 PM PDT 24
Finished Jun 10 05:51:40 PM PDT 24
Peak memory 200452 kb
Host smart-e0c76fda-92d1-47f8-9d46-9a7091a24bf7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048770423 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.4048770423
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3057553275
Short name T397
Test name
Test status
Simulation time 16533641 ps
CPU time 0.67 seconds
Started Jun 10 05:42:50 PM PDT 24
Finished Jun 10 05:42:51 PM PDT 24
Peak memory 196384 kb
Host smart-9c79eac9-3442-4e01-833b-5eb65027106f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057553275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3057553275
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3770249524
Short name T226
Test name
Test status
Simulation time 194546287 ps
CPU time 7.52 seconds
Started Jun 10 05:42:49 PM PDT 24
Finished Jun 10 05:42:57 PM PDT 24
Peak memory 200336 kb
Host smart-0bf68659-936b-4148-984b-557dbd249f63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3770249524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3770249524
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3658770930
Short name T342
Test name
Test status
Simulation time 874208227 ps
CPU time 47.09 seconds
Started Jun 10 05:42:47 PM PDT 24
Finished Jun 10 05:43:34 PM PDT 24
Peak memory 200480 kb
Host smart-f42b547e-9139-46ce-ade9-99532b13f92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658770930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3658770930
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.4138069171
Short name T497
Test name
Test status
Simulation time 8440224414 ps
CPU time 611.48 seconds
Started Jun 10 05:42:49 PM PDT 24
Finished Jun 10 05:53:01 PM PDT 24
Peak memory 726680 kb
Host smart-d878c2cc-add0-4f31-a9b4-ae243719fee7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4138069171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.4138069171
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3153527810
Short name T413
Test name
Test status
Simulation time 704105526 ps
CPU time 38.29 seconds
Started Jun 10 05:42:51 PM PDT 24
Finished Jun 10 05:43:30 PM PDT 24
Peak memory 200324 kb
Host smart-df524541-1903-4ef4-b467-cec33e6f0c5b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153527810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3153527810
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.398725274
Short name T334
Test name
Test status
Simulation time 1556621946 ps
CPU time 20.89 seconds
Started Jun 10 05:42:50 PM PDT 24
Finished Jun 10 05:43:11 PM PDT 24
Peak memory 200432 kb
Host smart-9c42e1d5-37a1-4bf7-a9b4-b91fbf8dd83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398725274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.398725274
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2769547481
Short name T571
Test name
Test status
Simulation time 420234437 ps
CPU time 3.29 seconds
Started Jun 10 05:42:51 PM PDT 24
Finished Jun 10 05:42:54 PM PDT 24
Peak memory 200412 kb
Host smart-c2546941-1e49-439b-b5ba-0e5e7c48067d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769547481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2769547481
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.4260660823
Short name T164
Test name
Test status
Simulation time 19362954323 ps
CPU time 87.14 seconds
Started Jun 10 05:42:54 PM PDT 24
Finished Jun 10 05:44:22 PM PDT 24
Peak memory 200324 kb
Host smart-9b9ba9e8-d2d0-470d-8837-550fdacccd66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260660823 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.4260660823
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.4167087566
Short name T138
Test name
Test status
Simulation time 119690568 ps
CPU time 1.03 seconds
Started Jun 10 05:42:48 PM PDT 24
Finished Jun 10 05:42:50 PM PDT 24
Peak memory 200256 kb
Host smart-d5b1cf01-9215-46f2-92df-7d95ad85b9b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167087566 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.4167087566
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.373236749
Short name T591
Test name
Test status
Simulation time 26888349595 ps
CPU time 474.42 seconds
Started Jun 10 05:42:51 PM PDT 24
Finished Jun 10 05:50:46 PM PDT 24
Peak memory 200344 kb
Host smart-f90404e6-e510-4310-9d34-c1caa100c263
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373236749 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.373236749
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.2173317763
Short name T585
Test name
Test status
Simulation time 2336418582 ps
CPU time 44.99 seconds
Started Jun 10 05:42:51 PM PDT 24
Finished Jun 10 05:43:36 PM PDT 24
Peak memory 200496 kb
Host smart-c7d85329-a0fc-4c0a-8029-d09474f4d66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173317763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2173317763
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.4167841422
Short name T471
Test name
Test status
Simulation time 21122164 ps
CPU time 0.61 seconds
Started Jun 10 05:42:51 PM PDT 24
Finished Jun 10 05:42:52 PM PDT 24
Peak memory 195988 kb
Host smart-b3e5d4cf-b5c2-46ec-a5ef-b4a7bc0a38a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167841422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.4167841422
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3949008736
Short name T238
Test name
Test status
Simulation time 1926558869 ps
CPU time 50.24 seconds
Started Jun 10 05:42:51 PM PDT 24
Finished Jun 10 05:43:42 PM PDT 24
Peak memory 218844 kb
Host smart-e30f55a1-642b-4496-9340-09cf0b5da88b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3949008736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3949008736
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1611339521
Short name T491
Test name
Test status
Simulation time 7085753060 ps
CPU time 34.21 seconds
Started Jun 10 05:42:51 PM PDT 24
Finished Jun 10 05:43:26 PM PDT 24
Peak memory 200508 kb
Host smart-6215dcdf-7c50-40aa-b8c0-ef671230d056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611339521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1611339521
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.815435771
Short name T547
Test name
Test status
Simulation time 22666089163 ps
CPU time 522.89 seconds
Started Jun 10 05:42:49 PM PDT 24
Finished Jun 10 05:51:32 PM PDT 24
Peak memory 659376 kb
Host smart-77db5af7-ebfb-42b6-9813-8c0c7c9c607a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=815435771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.815435771
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1871949945
Short name T587
Test name
Test status
Simulation time 14937405238 ps
CPU time 150.73 seconds
Started Jun 10 05:42:53 PM PDT 24
Finished Jun 10 05:45:24 PM PDT 24
Peak memory 200468 kb
Host smart-2ab5126d-e7ab-4622-95f0-56eda01f92b8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871949945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1871949945
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.537647371
Short name T372
Test name
Test status
Simulation time 288103964 ps
CPU time 16.55 seconds
Started Jun 10 05:42:50 PM PDT 24
Finished Jun 10 05:43:07 PM PDT 24
Peak memory 200440 kb
Host smart-9aecbd0a-447f-406b-892d-ac2f40882fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537647371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.537647371
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1570829524
Short name T551
Test name
Test status
Simulation time 1612324520 ps
CPU time 8.84 seconds
Started Jun 10 05:42:51 PM PDT 24
Finished Jun 10 05:43:00 PM PDT 24
Peak memory 200384 kb
Host smart-25b1ab7a-748f-4c63-b0ce-ce35391da315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570829524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1570829524
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3897855678
Short name T32
Test name
Test status
Simulation time 73723948 ps
CPU time 1.11 seconds
Started Jun 10 05:42:50 PM PDT 24
Finished Jun 10 05:42:51 PM PDT 24
Peak memory 200444 kb
Host smart-fb5fd27b-fb0d-4201-9fa6-f3a241385b37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897855678 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3897855678
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.2875773224
Short name T363
Test name
Test status
Simulation time 66853243 ps
CPU time 1.4 seconds
Started Jun 10 05:42:50 PM PDT 24
Finished Jun 10 05:42:52 PM PDT 24
Peak memory 200468 kb
Host smart-091db49d-4dc7-44dc-bcb6-53696828151e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875773224 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.2875773224
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.2167275078
Short name T250
Test name
Test status
Simulation time 41853470077 ps
CPU time 561.55 seconds
Started Jun 10 05:42:51 PM PDT 24
Finished Jun 10 05:52:14 PM PDT 24
Peak memory 200392 kb
Host smart-679cf007-ebb5-4a91-87f2-ed5fb532b4f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167275078 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.2167275078
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1048748906
Short name T396
Test name
Test status
Simulation time 3300147278 ps
CPU time 60.25 seconds
Started Jun 10 05:42:49 PM PDT 24
Finished Jun 10 05:43:50 PM PDT 24
Peak memory 200536 kb
Host smart-b3d69de4-43d7-4265-8c54-ca8b91139dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048748906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1048748906
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2031602856
Short name T249
Test name
Test status
Simulation time 13528403 ps
CPU time 0.58 seconds
Started Jun 10 05:42:52 PM PDT 24
Finished Jun 10 05:42:53 PM PDT 24
Peak memory 197056 kb
Host smart-b9797c4e-0c46-4ddd-af5f-d1aa9dec55dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031602856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2031602856
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1069617195
Short name T256
Test name
Test status
Simulation time 1689494876 ps
CPU time 46.14 seconds
Started Jun 10 05:42:56 PM PDT 24
Finished Jun 10 05:43:42 PM PDT 24
Peak memory 230272 kb
Host smart-83e4a3f5-de3d-48f3-bbd6-f1b43bee475e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1069617195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1069617195
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.4063086165
Short name T257
Test name
Test status
Simulation time 446743307 ps
CPU time 10.85 seconds
Started Jun 10 05:42:51 PM PDT 24
Finished Jun 10 05:43:03 PM PDT 24
Peak memory 200448 kb
Host smart-506de339-13a3-4e83-bd2d-a246a7c986f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063086165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.4063086165
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3240957867
Short name T424
Test name
Test status
Simulation time 2792188527 ps
CPU time 779.14 seconds
Started Jun 10 05:42:58 PM PDT 24
Finished Jun 10 05:55:57 PM PDT 24
Peak memory 732076 kb
Host smart-919b8305-8aba-4d9e-8aa2-cf1007bef4db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3240957867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3240957867
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2753342654
Short name T483
Test name
Test status
Simulation time 3272375514 ps
CPU time 45.54 seconds
Started Jun 10 05:42:54 PM PDT 24
Finished Jun 10 05:43:40 PM PDT 24
Peak memory 200492 kb
Host smart-ebedeb03-b8cf-4e05-8659-7687b3b53bcc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753342654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2753342654
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.2148908817
Short name T310
Test name
Test status
Simulation time 1104869278 ps
CPU time 16.04 seconds
Started Jun 10 05:42:53 PM PDT 24
Finished Jun 10 05:43:10 PM PDT 24
Peak memory 200396 kb
Host smart-63d9a8bc-cb48-4048-9fb0-b22f810758a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148908817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.2148908817
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2794590915
Short name T53
Test name
Test status
Simulation time 1270542729 ps
CPU time 6.69 seconds
Started Jun 10 05:42:50 PM PDT 24
Finished Jun 10 05:42:57 PM PDT 24
Peak memory 200400 kb
Host smart-9cbb0a4f-d320-4e6e-8be5-827e21617a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794590915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2794590915
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1084911761
Short name T539
Test name
Test status
Simulation time 16787482356 ps
CPU time 863.5 seconds
Started Jun 10 05:42:57 PM PDT 24
Finished Jun 10 05:57:21 PM PDT 24
Peak memory 634496 kb
Host smart-5aa6b8b3-c399-499d-b2c2-24c4ad375ac6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084911761 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1084911761
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.1647783718
Short name T137
Test name
Test status
Simulation time 49935697 ps
CPU time 1.07 seconds
Started Jun 10 05:42:57 PM PDT 24
Finished Jun 10 05:42:59 PM PDT 24
Peak memory 200272 kb
Host smart-047c2b6f-60b9-44c4-a3fd-f54677046ccf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647783718 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.1647783718
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.902395849
Short name T317
Test name
Test status
Simulation time 46601072992 ps
CPU time 591.34 seconds
Started Jun 10 05:42:54 PM PDT 24
Finished Jun 10 05:52:46 PM PDT 24
Peak memory 200368 kb
Host smart-090815c4-4476-49a9-abc3-eb9421f89683
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902395849 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.902395849
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.4174299940
Short name T217
Test name
Test status
Simulation time 17503664997 ps
CPU time 30.41 seconds
Started Jun 10 05:42:55 PM PDT 24
Finished Jun 10 05:43:25 PM PDT 24
Peak memory 200528 kb
Host smart-b6a9a4a9-7b0b-4acf-be6d-f837cfee665f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174299940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.4174299940
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2317093545
Short name T513
Test name
Test status
Simulation time 18424266 ps
CPU time 0.62 seconds
Started Jun 10 05:43:00 PM PDT 24
Finished Jun 10 05:43:01 PM PDT 24
Peak memory 196392 kb
Host smart-a05a7f97-9845-42d4-96e5-e2e8c12596e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317093545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2317093545
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1407441218
Short name T27
Test name
Test status
Simulation time 1884681632 ps
CPU time 20.35 seconds
Started Jun 10 05:42:54 PM PDT 24
Finished Jun 10 05:43:15 PM PDT 24
Peak memory 208636 kb
Host smart-fe9a120a-991c-45ec-bcc8-1c42b97e92b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1407441218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1407441218
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1178917189
Short name T442
Test name
Test status
Simulation time 43201840327 ps
CPU time 52.13 seconds
Started Jun 10 05:42:58 PM PDT 24
Finished Jun 10 05:43:50 PM PDT 24
Peak memory 200504 kb
Host smart-533c6e5f-1a3b-4a2b-a0a4-44579f0203f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178917189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1178917189
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2904563854
Short name T362
Test name
Test status
Simulation time 15175815 ps
CPU time 0.73 seconds
Started Jun 10 05:42:55 PM PDT 24
Finished Jun 10 05:42:56 PM PDT 24
Peak memory 199404 kb
Host smart-8459dbb5-a8c6-4f2a-a17c-f3bad7d6a2f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2904563854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2904563854
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.424536821
Short name T140
Test name
Test status
Simulation time 31659755696 ps
CPU time 225.42 seconds
Started Jun 10 05:42:53 PM PDT 24
Finished Jun 10 05:46:38 PM PDT 24
Peak memory 200464 kb
Host smart-553fca0a-1221-4b3a-a826-4fe83a69e770
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424536821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.424536821
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.2281891517
Short name T343
Test name
Test status
Simulation time 3066372786 ps
CPU time 90.71 seconds
Started Jun 10 05:42:54 PM PDT 24
Finished Jun 10 05:44:25 PM PDT 24
Peak memory 200640 kb
Host smart-41bef585-3af3-46b6-957f-018d37d402b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281891517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2281891517
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2019619373
Short name T590
Test name
Test status
Simulation time 1185333188 ps
CPU time 5.55 seconds
Started Jun 10 05:42:55 PM PDT 24
Finished Jun 10 05:43:01 PM PDT 24
Peak memory 200264 kb
Host smart-9cbc7859-f1ad-4c23-984c-99ff3788566f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019619373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2019619373
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3238612462
Short name T456
Test name
Test status
Simulation time 63166523063 ps
CPU time 2860.88 seconds
Started Jun 10 05:42:59 PM PDT 24
Finished Jun 10 06:30:40 PM PDT 24
Peak memory 799588 kb
Host smart-aeac3ed0-062e-4691-87d2-90e70905a12b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238612462 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3238612462
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.221290812
Short name T428
Test name
Test status
Simulation time 64840298 ps
CPU time 1.22 seconds
Started Jun 10 05:42:58 PM PDT 24
Finished Jun 10 05:43:00 PM PDT 24
Peak memory 200448 kb
Host smart-2d3a92b8-9afc-4b3d-af7c-52dffe3013cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221290812 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_hmac_vectors.221290812
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.2671684273
Short name T270
Test name
Test status
Simulation time 41496038329 ps
CPU time 528.07 seconds
Started Jun 10 05:43:00 PM PDT 24
Finished Jun 10 05:51:48 PM PDT 24
Peak memory 200352 kb
Host smart-47ecb6a8-cb9b-43de-af8a-a46d8a720bbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671684273 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.2671684273
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.828568575
Short name T114
Test name
Test status
Simulation time 11015206684 ps
CPU time 51.52 seconds
Started Jun 10 05:43:02 PM PDT 24
Finished Jun 10 05:43:54 PM PDT 24
Peak memory 200372 kb
Host smart-2b6ac869-188e-448c-80e8-316f4f6acde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828568575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.828568575
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3046931616
Short name T410
Test name
Test status
Simulation time 42971786 ps
CPU time 0.6 seconds
Started Jun 10 05:43:03 PM PDT 24
Finished Jun 10 05:43:04 PM PDT 24
Peak memory 196080 kb
Host smart-8ee4d32b-8621-4b73-8808-e01577ed3ed5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046931616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3046931616
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.336081719
Short name T169
Test name
Test status
Simulation time 3579899758 ps
CPU time 58.39 seconds
Started Jun 10 05:42:57 PM PDT 24
Finished Jun 10 05:43:55 PM PDT 24
Peak memory 241472 kb
Host smart-d04d13c4-661a-47ea-bbea-2bb35b20b8d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=336081719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.336081719
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.964273090
Short name T89
Test name
Test status
Simulation time 554656833 ps
CPU time 28.32 seconds
Started Jun 10 05:43:01 PM PDT 24
Finished Jun 10 05:43:30 PM PDT 24
Peak memory 200484 kb
Host smart-a686bc4b-4957-46f0-ad48-9f5fa65bcf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964273090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.964273090
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1060133145
Short name T340
Test name
Test status
Simulation time 1864547231 ps
CPU time 532.35 seconds
Started Jun 10 05:43:00 PM PDT 24
Finished Jun 10 05:51:53 PM PDT 24
Peak memory 689268 kb
Host smart-b509b9e6-cc4c-42e1-a246-b5eba8b2fcc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1060133145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1060133145
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3312026310
Short name T237
Test name
Test status
Simulation time 2479878011 ps
CPU time 134.08 seconds
Started Jun 10 05:42:59 PM PDT 24
Finished Jun 10 05:45:13 PM PDT 24
Peak memory 200596 kb
Host smart-947ecdec-623e-4f17-8ecc-fc7c5cad74b3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312026310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3312026310
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2650784256
Short name T26
Test name
Test status
Simulation time 3470138930 ps
CPU time 36.35 seconds
Started Jun 10 05:42:57 PM PDT 24
Finished Jun 10 05:43:34 PM PDT 24
Peak memory 200504 kb
Host smart-0ec2526f-469e-472a-aa6a-e459a92763b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650784256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2650784256
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2060343953
Short name T278
Test name
Test status
Simulation time 403212701 ps
CPU time 7.16 seconds
Started Jun 10 05:42:59 PM PDT 24
Finished Jun 10 05:43:07 PM PDT 24
Peak memory 200400 kb
Host smart-9b9bbfa7-7da4-4e00-95de-051e3ee0e51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060343953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2060343953
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.4263843008
Short name T525
Test name
Test status
Simulation time 84841818956 ps
CPU time 3360.16 seconds
Started Jun 10 05:42:58 PM PDT 24
Finished Jun 10 06:38:59 PM PDT 24
Peak memory 831864 kb
Host smart-fe04f7bb-c4e5-4706-abc2-e2a38d064457
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263843008 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.4263843008
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.2059970673
Short name T582
Test name
Test status
Simulation time 234517903 ps
CPU time 1.26 seconds
Started Jun 10 05:43:00 PM PDT 24
Finished Jun 10 05:43:01 PM PDT 24
Peak memory 200412 kb
Host smart-fdc77df0-1da2-47dd-94a9-8b2a2e050de3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059970673 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.2059970673
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.1240004426
Short name T232
Test name
Test status
Simulation time 41222777815 ps
CPU time 541.75 seconds
Started Jun 10 05:42:59 PM PDT 24
Finished Jun 10 05:52:01 PM PDT 24
Peak memory 200436 kb
Host smart-2ad720ba-5317-40e8-8f43-bebaac2ad173
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240004426 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.1240004426
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2036062723
Short name T131
Test name
Test status
Simulation time 1325888680 ps
CPU time 33.06 seconds
Started Jun 10 05:43:01 PM PDT 24
Finished Jun 10 05:43:34 PM PDT 24
Peak memory 200352 kb
Host smart-56161941-0f5c-45cf-883b-66064cad920a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036062723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2036062723
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.1304420028
Short name T142
Test name
Test status
Simulation time 49397256 ps
CPU time 0.65 seconds
Started Jun 10 05:43:15 PM PDT 24
Finished Jun 10 05:43:16 PM PDT 24
Peak memory 196364 kb
Host smart-d11379f8-9359-4874-b3de-19f69781cbb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304420028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1304420028
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.84055960
Short name T575
Test name
Test status
Simulation time 5356903365 ps
CPU time 32.59 seconds
Started Jun 10 05:43:00 PM PDT 24
Finished Jun 10 05:43:33 PM PDT 24
Peak memory 230620 kb
Host smart-66dad88c-486e-48a1-8b3e-2598edec37f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=84055960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.84055960
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.4004516154
Short name T152
Test name
Test status
Simulation time 3025201522 ps
CPU time 38.72 seconds
Started Jun 10 05:43:03 PM PDT 24
Finished Jun 10 05:43:42 PM PDT 24
Peak memory 200484 kb
Host smart-5b815062-d8e3-4170-8998-e6db6bf58e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004516154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.4004516154
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2092222179
Short name T176
Test name
Test status
Simulation time 125544504 ps
CPU time 1.19 seconds
Started Jun 10 05:43:01 PM PDT 24
Finished Jun 10 05:43:02 PM PDT 24
Peak memory 200180 kb
Host smart-9118cba8-188e-4d03-a70b-70258efbe65d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2092222179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2092222179
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1140279306
Short name T326
Test name
Test status
Simulation time 10292248168 ps
CPU time 85.47 seconds
Started Jun 10 05:43:02 PM PDT 24
Finished Jun 10 05:44:28 PM PDT 24
Peak memory 200500 kb
Host smart-16ecd7c7-8c35-4319-8724-d59aa0a44882
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140279306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1140279306
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2792111778
Short name T306
Test name
Test status
Simulation time 10858488636 ps
CPU time 107.14 seconds
Started Jun 10 05:43:03 PM PDT 24
Finished Jun 10 05:44:51 PM PDT 24
Peak memory 200488 kb
Host smart-90c83e3f-a419-4090-a14f-8f74000f5fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792111778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2792111778
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2030082978
Short name T175
Test name
Test status
Simulation time 1561176732 ps
CPU time 9.18 seconds
Started Jun 10 05:43:09 PM PDT 24
Finished Jun 10 05:43:19 PM PDT 24
Peak memory 200376 kb
Host smart-55f10069-8531-4e42-915c-ec7470c389be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030082978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2030082978
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.300843422
Short name T447
Test name
Test status
Simulation time 7058680083 ps
CPU time 107.03 seconds
Started Jun 10 05:43:12 PM PDT 24
Finished Jun 10 05:44:59 PM PDT 24
Peak memory 208760 kb
Host smart-f380155c-9288-4d0a-af68-e0b6b8648e86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300843422 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.300843422
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.3094254268
Short name T341
Test name
Test status
Simulation time 65202942 ps
CPU time 1.45 seconds
Started Jun 10 05:43:10 PM PDT 24
Finished Jun 10 05:43:11 PM PDT 24
Peak memory 200252 kb
Host smart-3b06ea16-c7cc-4ba9-bcd3-312b4a5563d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094254268 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.3094254268
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.205764879
Short name T443
Test name
Test status
Simulation time 46256028188 ps
CPU time 476.42 seconds
Started Jun 10 05:43:02 PM PDT 24
Finished Jun 10 05:50:59 PM PDT 24
Peak memory 200240 kb
Host smart-0f78ab59-936f-49db-adfb-abdb0e1188d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205764879 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.205764879
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1879031761
Short name T126
Test name
Test status
Simulation time 521314347 ps
CPU time 25.58 seconds
Started Jun 10 05:43:04 PM PDT 24
Finished Jun 10 05:43:30 PM PDT 24
Peak memory 200504 kb
Host smart-54cd8e3a-4323-471b-82f1-014a6d6e867e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879031761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1879031761
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1905794599
Short name T560
Test name
Test status
Simulation time 14316815 ps
CPU time 0.61 seconds
Started Jun 10 05:43:14 PM PDT 24
Finished Jun 10 05:43:15 PM PDT 24
Peak memory 196404 kb
Host smart-1e76cd0b-ea1b-4f45-9082-ec9142120f82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905794599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1905794599
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2233654555
Short name T577
Test name
Test status
Simulation time 2212495367 ps
CPU time 65.64 seconds
Started Jun 10 05:43:10 PM PDT 24
Finished Jun 10 05:44:17 PM PDT 24
Peak memory 233188 kb
Host smart-26ecaa27-9e6e-4234-b70e-9150e4df5126
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2233654555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2233654555
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.2642977292
Short name T17
Test name
Test status
Simulation time 40757370129 ps
CPU time 67.07 seconds
Started Jun 10 05:43:04 PM PDT 24
Finished Jun 10 05:44:12 PM PDT 24
Peak memory 200440 kb
Host smart-a19bd066-cde4-4ffa-b23d-7b09cca39623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642977292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2642977292
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3664385221
Short name T83
Test name
Test status
Simulation time 6393200298 ps
CPU time 729.21 seconds
Started Jun 10 05:43:14 PM PDT 24
Finished Jun 10 05:55:23 PM PDT 24
Peak memory 699536 kb
Host smart-233015a1-65b1-485e-a635-aa6f4f25952c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3664385221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3664385221
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2417367996
Short name T215
Test name
Test status
Simulation time 12042446112 ps
CPU time 178.95 seconds
Started Jun 10 05:43:14 PM PDT 24
Finished Jun 10 05:46:13 PM PDT 24
Peak memory 200544 kb
Host smart-31105e6b-aee9-4c8d-ad3e-17facb83185c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417367996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2417367996
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.2304603544
Short name T354
Test name
Test status
Simulation time 845827549 ps
CPU time 49.94 seconds
Started Jun 10 05:43:08 PM PDT 24
Finished Jun 10 05:43:58 PM PDT 24
Peak memory 200460 kb
Host smart-fa8e4aec-89e8-4dfe-bf0d-c9f2db6131fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304603544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2304603544
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3495762829
Short name T188
Test name
Test status
Simulation time 1641607435 ps
CPU time 7.31 seconds
Started Jun 10 05:43:07 PM PDT 24
Finished Jun 10 05:43:15 PM PDT 24
Peak memory 200408 kb
Host smart-ef5f5027-bd6f-4efa-8d17-2e9a34385d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495762829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3495762829
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3146260355
Short name T183
Test name
Test status
Simulation time 2437057252 ps
CPU time 17.71 seconds
Started Jun 10 05:43:14 PM PDT 24
Finished Jun 10 05:43:32 PM PDT 24
Peak memory 200572 kb
Host smart-3dafec85-5bb3-4c08-a399-737aa6ecb7a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146260355 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3146260355
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.289254617
Short name T309
Test name
Test status
Simulation time 877888730 ps
CPU time 1.12 seconds
Started Jun 10 05:43:07 PM PDT 24
Finished Jun 10 05:43:08 PM PDT 24
Peak memory 200344 kb
Host smart-0865b171-0438-4340-987f-b3efde9ed777
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289254617 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_hmac_vectors.289254617
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.243917847
Short name T194
Test name
Test status
Simulation time 46259191697 ps
CPU time 484.32 seconds
Started Jun 10 05:43:14 PM PDT 24
Finished Jun 10 05:51:19 PM PDT 24
Peak memory 200504 kb
Host smart-7b953687-468c-40c1-b0a6-e4f3478b0a5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243917847 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.243917847
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.4079401594
Short name T115
Test name
Test status
Simulation time 1381182526 ps
CPU time 21.63 seconds
Started Jun 10 05:43:11 PM PDT 24
Finished Jun 10 05:43:33 PM PDT 24
Peak memory 200464 kb
Host smart-7ff7965e-562d-4372-be2d-99e6c52f91e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079401594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.4079401594
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1533338816
Short name T420
Test name
Test status
Simulation time 140702599 ps
CPU time 0.57 seconds
Started Jun 10 05:43:11 PM PDT 24
Finished Jun 10 05:43:12 PM PDT 24
Peak memory 196232 kb
Host smart-152aa99b-2c33-4dbc-8ebb-8e383ec4a09d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533338816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1533338816
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3213195558
Short name T324
Test name
Test status
Simulation time 430580704 ps
CPU time 21.48 seconds
Started Jun 10 05:43:13 PM PDT 24
Finished Jun 10 05:43:35 PM PDT 24
Peak memory 223252 kb
Host smart-4e5e3c00-0149-4d1a-896d-b73ad62ad981
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3213195558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3213195558
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.4011483238
Short name T313
Test name
Test status
Simulation time 556164290 ps
CPU time 11.22 seconds
Started Jun 10 05:43:14 PM PDT 24
Finished Jun 10 05:43:26 PM PDT 24
Peak memory 200428 kb
Host smart-0e02ba16-d1ab-427e-b2a3-eaec7bb29ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011483238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.4011483238
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2449616171
Short name T1
Test name
Test status
Simulation time 2776563331 ps
CPU time 615.89 seconds
Started Jun 10 05:43:15 PM PDT 24
Finished Jun 10 05:53:31 PM PDT 24
Peak memory 679188 kb
Host smart-177f909a-f8c4-4c47-96cb-b41a648951e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2449616171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2449616171
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3013533224
Short name T458
Test name
Test status
Simulation time 953768832 ps
CPU time 14.54 seconds
Started Jun 10 05:43:08 PM PDT 24
Finished Jun 10 05:43:22 PM PDT 24
Peak memory 200264 kb
Host smart-7becb9a2-57ef-4347-a678-c83c5f2f3ead
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013533224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3013533224
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3055713395
Short name T426
Test name
Test status
Simulation time 610948415 ps
CPU time 35.85 seconds
Started Jun 10 05:43:05 PM PDT 24
Finished Jun 10 05:43:41 PM PDT 24
Peak memory 200448 kb
Host smart-36075789-7f1d-409f-9930-4fae358efdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055713395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3055713395
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3873840973
Short name T367
Test name
Test status
Simulation time 127773084 ps
CPU time 4.52 seconds
Started Jun 10 05:43:15 PM PDT 24
Finished Jun 10 05:43:20 PM PDT 24
Peak memory 200440 kb
Host smart-4979e9c8-0fe1-483d-ba56-4cbebd2afbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873840973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3873840973
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3236074480
Short name T182
Test name
Test status
Simulation time 560972688818 ps
CPU time 4251.72 seconds
Started Jun 10 05:43:08 PM PDT 24
Finished Jun 10 06:54:00 PM PDT 24
Peak memory 814792 kb
Host smart-19f561cb-9702-469a-8b9b-3fcb53993a99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236074480 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3236074480
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.3860579257
Short name T165
Test name
Test status
Simulation time 35297217 ps
CPU time 1.29 seconds
Started Jun 10 05:43:09 PM PDT 24
Finished Jun 10 05:43:11 PM PDT 24
Peak memory 200496 kb
Host smart-4d9fc4ec-fa5c-4115-bc98-f7b50a5345ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860579257 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.3860579257
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.4003651364
Short name T166
Test name
Test status
Simulation time 30465403592 ps
CPU time 459.56 seconds
Started Jun 10 05:43:04 PM PDT 24
Finished Jun 10 05:50:44 PM PDT 24
Peak memory 200436 kb
Host smart-db9c7874-2b95-4d76-aa09-f7dcee2d48eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003651364 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.4003651364
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2426277363
Short name T294
Test name
Test status
Simulation time 10870253481 ps
CPU time 53.21 seconds
Started Jun 10 05:43:05 PM PDT 24
Finished Jun 10 05:43:58 PM PDT 24
Peak memory 200496 kb
Host smart-cf3ec761-d230-4d97-a2f9-aca9e7ea6870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426277363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2426277363
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2526423882
Short name T112
Test name
Test status
Simulation time 29625804 ps
CPU time 0.61 seconds
Started Jun 10 05:41:53 PM PDT 24
Finished Jun 10 05:41:55 PM PDT 24
Peak memory 195396 kb
Host smart-fae5e19e-8e94-43a2-b0a8-8099b19e90d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526423882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2526423882
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2693357343
Short name T467
Test name
Test status
Simulation time 1222689748 ps
CPU time 38.69 seconds
Started Jun 10 05:41:53 PM PDT 24
Finished Jun 10 05:42:33 PM PDT 24
Peak memory 226080 kb
Host smart-a5401483-64f8-4ece-8949-db585f6d850c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2693357343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2693357343
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.877383468
Short name T431
Test name
Test status
Simulation time 1819259876 ps
CPU time 25.64 seconds
Started Jun 10 05:41:53 PM PDT 24
Finished Jun 10 05:42:20 PM PDT 24
Peak memory 200380 kb
Host smart-157ec2f4-0e59-4f23-b133-69fe603035b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877383468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.877383468
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2739327376
Short name T335
Test name
Test status
Simulation time 5282115640 ps
CPU time 184.1 seconds
Started Jun 10 05:41:49 PM PDT 24
Finished Jun 10 05:44:53 PM PDT 24
Peak memory 598600 kb
Host smart-a6a0bbef-4b2e-4fd8-b0f9-34ad30fc72ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2739327376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2739327376
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2704454697
Short name T493
Test name
Test status
Simulation time 2006089028 ps
CPU time 53.38 seconds
Started Jun 10 05:42:04 PM PDT 24
Finished Jun 10 05:42:58 PM PDT 24
Peak memory 200516 kb
Host smart-76a31be2-9c77-486d-85cb-e834e2cd9c26
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704454697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2704454697
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3127680665
Short name T80
Test name
Test status
Simulation time 29032041315 ps
CPU time 101.21 seconds
Started Jun 10 05:41:55 PM PDT 24
Finished Jun 10 05:43:37 PM PDT 24
Peak memory 200368 kb
Host smart-b27d7ef8-eb48-4cba-8271-fd0e2ff282ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127680665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3127680665
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.4271954982
Short name T25
Test name
Test status
Simulation time 79902820 ps
CPU time 0.97 seconds
Started Jun 10 05:41:45 PM PDT 24
Finished Jun 10 05:41:46 PM PDT 24
Peak memory 219952 kb
Host smart-14cd01b0-4afa-4b37-b613-2b05c4286be4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271954982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.4271954982
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.2260540605
Short name T374
Test name
Test status
Simulation time 3913236827 ps
CPU time 13.26 seconds
Started Jun 10 05:41:47 PM PDT 24
Finished Jun 10 05:42:00 PM PDT 24
Peak memory 200488 kb
Host smart-0a157b08-6286-4ab7-bb58-d9a6ab9f3c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260540605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2260540605
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2068735419
Short name T382
Test name
Test status
Simulation time 252557521851 ps
CPU time 2948.77 seconds
Started Jun 10 05:41:56 PM PDT 24
Finished Jun 10 06:31:05 PM PDT 24
Peak memory 737340 kb
Host smart-51ab21fa-8130-4d66-b19b-668a49edb914
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068735419 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2068735419
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.2491880409
Short name T105
Test name
Test status
Simulation time 184551917 ps
CPU time 1.25 seconds
Started Jun 10 05:41:55 PM PDT 24
Finished Jun 10 05:41:57 PM PDT 24
Peak memory 200292 kb
Host smart-5bd17efb-a2f8-42e0-a3eb-4a7b714aedcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491880409 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.2491880409
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.2022252960
Short name T252
Test name
Test status
Simulation time 61980404568 ps
CPU time 420.77 seconds
Started Jun 10 05:41:46 PM PDT 24
Finished Jun 10 05:48:47 PM PDT 24
Peak memory 200400 kb
Host smart-d42c6930-9358-4784-8de8-b435918961d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022252960 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.2022252960
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1919589316
Short name T391
Test name
Test status
Simulation time 3159244513 ps
CPU time 74.97 seconds
Started Jun 10 05:41:43 PM PDT 24
Finished Jun 10 05:42:59 PM PDT 24
Peak memory 200652 kb
Host smart-af39f76f-1556-4bdd-94db-2c61857f7d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919589316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1919589316
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.4128458123
Short name T120
Test name
Test status
Simulation time 11425649 ps
CPU time 0.61 seconds
Started Jun 10 05:43:19 PM PDT 24
Finished Jun 10 05:43:20 PM PDT 24
Peak memory 195360 kb
Host smart-5ee4de1d-b3de-4ab6-82a8-186bdbdd48c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128458123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.4128458123
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.273516010
Short name T512
Test name
Test status
Simulation time 5937536961 ps
CPU time 24.84 seconds
Started Jun 10 05:43:10 PM PDT 24
Finished Jun 10 05:43:36 PM PDT 24
Peak memory 225892 kb
Host smart-0b71fd69-affa-4d19-ad8b-77a71e3a871a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=273516010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.273516010
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3424498075
Short name T394
Test name
Test status
Simulation time 1746131919 ps
CPU time 35.59 seconds
Started Jun 10 05:43:11 PM PDT 24
Finished Jun 10 05:43:47 PM PDT 24
Peak memory 200480 kb
Host smart-37d9e83c-0c0f-42d2-ae80-967f581da7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424498075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3424498075
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2830981831
Short name T395
Test name
Test status
Simulation time 1863271936 ps
CPU time 506.52 seconds
Started Jun 10 05:43:17 PM PDT 24
Finished Jun 10 05:51:44 PM PDT 24
Peak memory 728928 kb
Host smart-5d88efeb-4ee7-45aa-ae9d-a0a5874a4ef8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2830981831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2830981831
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.1995076277
Short name T213
Test name
Test status
Simulation time 6527844046 ps
CPU time 34.08 seconds
Started Jun 10 05:43:13 PM PDT 24
Finished Jun 10 05:43:48 PM PDT 24
Peak memory 200512 kb
Host smart-955fcb4d-fd80-400f-9f72-b14a828c8dac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995076277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1995076277
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.517569415
Short name T463
Test name
Test status
Simulation time 1772854219 ps
CPU time 51.87 seconds
Started Jun 10 05:43:11 PM PDT 24
Finished Jun 10 05:44:03 PM PDT 24
Peak memory 200424 kb
Host smart-cd022797-ea77-474a-ad8f-ab15b5b6acd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517569415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.517569415
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1034704861
Short name T156
Test name
Test status
Simulation time 488917330 ps
CPU time 5.27 seconds
Started Jun 10 05:43:16 PM PDT 24
Finished Jun 10 05:43:21 PM PDT 24
Peak memory 200404 kb
Host smart-a84cf256-c63e-4a22-977c-12891a1498aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034704861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1034704861
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2358075936
Short name T527
Test name
Test status
Simulation time 127283464513 ps
CPU time 585.09 seconds
Started Jun 10 05:43:11 PM PDT 24
Finished Jun 10 05:52:57 PM PDT 24
Peak memory 200560 kb
Host smart-19485ebc-75f1-42a2-9eaa-bd9ab3d32a32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358075936 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2358075936
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.2732559854
Short name T275
Test name
Test status
Simulation time 47163654 ps
CPU time 1.07 seconds
Started Jun 10 05:43:10 PM PDT 24
Finished Jun 10 05:43:11 PM PDT 24
Peak memory 200188 kb
Host smart-ad95d09c-a35b-46a0-9b7f-8af222dda791
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732559854 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.2732559854
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.960884356
Short name T523
Test name
Test status
Simulation time 96938532658 ps
CPU time 430.35 seconds
Started Jun 10 05:43:07 PM PDT 24
Finished Jun 10 05:50:18 PM PDT 24
Peak memory 200468 kb
Host smart-aded88c1-6f56-46f1-aa4f-9221697da492
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960884356 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.960884356
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.4074426502
Short name T346
Test name
Test status
Simulation time 7455636341 ps
CPU time 82.83 seconds
Started Jun 10 05:43:13 PM PDT 24
Finished Jun 10 05:44:36 PM PDT 24
Peak memory 200520 kb
Host smart-e794a0b6-7359-40c9-8b44-e392d1966c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074426502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.4074426502
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2956277784
Short name T476
Test name
Test status
Simulation time 30777013 ps
CPU time 0.57 seconds
Started Jun 10 05:43:21 PM PDT 24
Finished Jun 10 05:43:22 PM PDT 24
Peak memory 195308 kb
Host smart-f259148f-94fb-4a6a-bc4f-c5cf298f8a09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956277784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2956277784
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.663073690
Short name T327
Test name
Test status
Simulation time 1150693004 ps
CPU time 16.33 seconds
Started Jun 10 05:43:20 PM PDT 24
Finished Jun 10 05:43:36 PM PDT 24
Peak memory 210720 kb
Host smart-7421d5ed-1256-4295-b9cd-ea7602a75039
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=663073690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.663073690
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2900434810
Short name T446
Test name
Test status
Simulation time 950488257 ps
CPU time 47.04 seconds
Started Jun 10 05:43:20 PM PDT 24
Finished Jun 10 05:44:07 PM PDT 24
Peak memory 200396 kb
Host smart-3e9fc713-4277-4cec-aa7a-e8c351352db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900434810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2900434810
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1295609721
Short name T2
Test name
Test status
Simulation time 5098196966 ps
CPU time 275.9 seconds
Started Jun 10 05:43:20 PM PDT 24
Finished Jun 10 05:47:56 PM PDT 24
Peak memory 636616 kb
Host smart-67f4ede3-c680-4782-82b2-d60ad84d6bc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1295609721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1295609721
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3635157110
Short name T321
Test name
Test status
Simulation time 2949958632 ps
CPU time 166.22 seconds
Started Jun 10 05:43:21 PM PDT 24
Finished Jun 10 05:46:07 PM PDT 24
Peak memory 200540 kb
Host smart-ced1e768-2f60-4d45-8c56-4c856c6a920a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635157110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3635157110
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.106102948
Short name T566
Test name
Test status
Simulation time 25435215395 ps
CPU time 92.93 seconds
Started Jun 10 05:43:16 PM PDT 24
Finished Jun 10 05:44:49 PM PDT 24
Peak memory 200420 kb
Host smart-05841c41-fad9-41ab-8e8f-6ec61d34db61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106102948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.106102948
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.2059971329
Short name T159
Test name
Test status
Simulation time 394684166 ps
CPU time 2.15 seconds
Started Jun 10 05:43:26 PM PDT 24
Finished Jun 10 05:43:28 PM PDT 24
Peak memory 200480 kb
Host smart-46fe2f32-f22a-4ca3-b117-2d8fab1707b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059971329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2059971329
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.1997886683
Short name T400
Test name
Test status
Simulation time 88843419 ps
CPU time 1.11 seconds
Started Jun 10 05:43:20 PM PDT 24
Finished Jun 10 05:43:21 PM PDT 24
Peak memory 200220 kb
Host smart-b9e0dd53-0948-4b4b-8ed1-20e13d4cff07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997886683 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.1997886683
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.381772924
Short name T586
Test name
Test status
Simulation time 7933237706 ps
CPU time 475.23 seconds
Started Jun 10 05:43:17 PM PDT 24
Finished Jun 10 05:51:12 PM PDT 24
Peak memory 200440 kb
Host smart-913b7f77-154f-47b6-aa81-ab3f071ba1ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381772924 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.381772924
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.331828767
Short name T365
Test name
Test status
Simulation time 5233753707 ps
CPU time 38.16 seconds
Started Jun 10 05:43:16 PM PDT 24
Finished Jun 10 05:43:55 PM PDT 24
Peak memory 200444 kb
Host smart-b0916d85-1a4f-489e-b2fc-50d35d221d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331828767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.331828767
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1529943143
Short name T269
Test name
Test status
Simulation time 14813757 ps
CPU time 0.6 seconds
Started Jun 10 05:43:19 PM PDT 24
Finished Jun 10 05:43:20 PM PDT 24
Peak memory 196040 kb
Host smart-88533cee-536c-4f12-a47e-1c3e945d95ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529943143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1529943143
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1227506528
Short name T5
Test name
Test status
Simulation time 4289571153 ps
CPU time 54.92 seconds
Started Jun 10 05:43:23 PM PDT 24
Finished Jun 10 05:44:18 PM PDT 24
Peak memory 225064 kb
Host smart-1f6ec5e6-2b9b-44ce-826e-e0d89fbfa5f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1227506528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1227506528
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.753478079
Short name T108
Test name
Test status
Simulation time 684663810 ps
CPU time 10.95 seconds
Started Jun 10 05:43:22 PM PDT 24
Finished Jun 10 05:43:33 PM PDT 24
Peak memory 200220 kb
Host smart-80e9ac3e-c496-4df8-9ffd-e3bf37f7611b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753478079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.753478079
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.4198058750
Short name T130
Test name
Test status
Simulation time 10812055109 ps
CPU time 684.79 seconds
Started Jun 10 05:43:23 PM PDT 24
Finished Jun 10 05:54:48 PM PDT 24
Peak memory 742368 kb
Host smart-0c3b4ecf-eb44-446a-967a-5d58d2c9326d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4198058750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.4198058750
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3862593192
Short name T520
Test name
Test status
Simulation time 13114042447 ps
CPU time 56.11 seconds
Started Jun 10 05:43:19 PM PDT 24
Finished Jun 10 05:44:15 PM PDT 24
Peak memory 200552 kb
Host smart-5161409e-3e00-475a-9052-8fc8e7231c1f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862593192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3862593192
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3464715017
Short name T515
Test name
Test status
Simulation time 1746637302 ps
CPU time 5.77 seconds
Started Jun 10 05:43:25 PM PDT 24
Finished Jun 10 05:43:31 PM PDT 24
Peak memory 200396 kb
Host smart-0f373053-8180-47d7-833a-61f51519859d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464715017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3464715017
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3732353829
Short name T576
Test name
Test status
Simulation time 330407817 ps
CPU time 3.59 seconds
Started Jun 10 05:43:17 PM PDT 24
Finished Jun 10 05:43:21 PM PDT 24
Peak memory 200412 kb
Host smart-579d6523-006c-43e8-8988-6726eb975e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732353829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3732353829
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3793490574
Short name T555
Test name
Test status
Simulation time 50318550059 ps
CPU time 1118.81 seconds
Started Jun 10 05:43:20 PM PDT 24
Finished Jun 10 06:02:00 PM PDT 24
Peak memory 481840 kb
Host smart-e9eb58c6-e4df-4acb-87bc-fe408cf75b4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793490574 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3793490574
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.691542766
Short name T533
Test name
Test status
Simulation time 86917657 ps
CPU time 1.16 seconds
Started Jun 10 05:43:20 PM PDT 24
Finished Jun 10 05:43:21 PM PDT 24
Peak memory 200420 kb
Host smart-12a55925-36a9-4ddc-8961-7af053e9e9be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691542766 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_hmac_vectors.691542766
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.2799307539
Short name T236
Test name
Test status
Simulation time 25714976816 ps
CPU time 485.06 seconds
Started Jun 10 05:43:17 PM PDT 24
Finished Jun 10 05:51:22 PM PDT 24
Peak memory 200476 kb
Host smart-7f2bbed2-3322-4a8e-9acb-355447c9312a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799307539 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.2799307539
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.592782015
Short name T223
Test name
Test status
Simulation time 6924474669 ps
CPU time 32.25 seconds
Started Jun 10 05:43:21 PM PDT 24
Finished Jun 10 05:43:53 PM PDT 24
Peak memory 200544 kb
Host smart-3eeb9007-444d-42b4-ae51-3d2cccfd023a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592782015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.592782015
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3844080550
Short name T432
Test name
Test status
Simulation time 17956140 ps
CPU time 0.58 seconds
Started Jun 10 05:43:24 PM PDT 24
Finished Jun 10 05:43:25 PM PDT 24
Peak memory 195256 kb
Host smart-725f0b74-8f8e-4d49-9792-7790814d3fda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844080550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3844080550
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.4066138270
Short name T225
Test name
Test status
Simulation time 6472268268 ps
CPU time 59.11 seconds
Started Jun 10 05:43:21 PM PDT 24
Finished Jun 10 05:44:21 PM PDT 24
Peak memory 227480 kb
Host smart-951bb66d-5367-4b23-82b6-7bff3e5d37f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4066138270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.4066138270
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2413943852
Short name T203
Test name
Test status
Simulation time 359765254 ps
CPU time 2.35 seconds
Started Jun 10 05:43:23 PM PDT 24
Finished Jun 10 05:43:26 PM PDT 24
Peak memory 200344 kb
Host smart-02de72d5-a96a-46ca-904e-f84b87937488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413943852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2413943852
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2127206158
Short name T373
Test name
Test status
Simulation time 601282581 ps
CPU time 45.74 seconds
Started Jun 10 05:43:17 PM PDT 24
Finished Jun 10 05:44:03 PM PDT 24
Peak memory 314464 kb
Host smart-17e7b0f1-6efd-4847-8fea-3e257128e15c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2127206158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2127206158
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3964760131
Short name T208
Test name
Test status
Simulation time 2663412745 ps
CPU time 100.44 seconds
Started Jun 10 05:43:25 PM PDT 24
Finished Jun 10 05:45:05 PM PDT 24
Peak memory 200440 kb
Host smart-8de80519-9eb9-4c35-829c-f0bcfbf04584
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964760131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3964760131
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1820942944
Short name T485
Test name
Test status
Simulation time 1305429860 ps
CPU time 21.89 seconds
Started Jun 10 05:43:20 PM PDT 24
Finished Jun 10 05:43:42 PM PDT 24
Peak memory 200420 kb
Host smart-b92fd1e9-f679-4b19-aacd-60d0c731b9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820942944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1820942944
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3849896388
Short name T161
Test name
Test status
Simulation time 1160184259 ps
CPU time 5.66 seconds
Started Jun 10 05:43:21 PM PDT 24
Finished Jun 10 05:43:27 PM PDT 24
Peak memory 200420 kb
Host smart-66b22fd5-4fed-411b-875e-ab216540295e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849896388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3849896388
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2316000074
Short name T440
Test name
Test status
Simulation time 39644017463 ps
CPU time 1502.29 seconds
Started Jun 10 05:43:28 PM PDT 24
Finished Jun 10 06:08:31 PM PDT 24
Peak memory 766888 kb
Host smart-c16a55df-a080-4929-9847-92270a7f2020
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316000074 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2316000074
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.32014676
Short name T144
Test name
Test status
Simulation time 112656310 ps
CPU time 1.41 seconds
Started Jun 10 05:43:24 PM PDT 24
Finished Jun 10 05:43:26 PM PDT 24
Peak memory 200412 kb
Host smart-0e6be64e-28c4-4948-802d-52e1f4fad401
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32014676 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 43.hmac_test_hmac_vectors.32014676
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.1977896448
Short name T179
Test name
Test status
Simulation time 8265656471 ps
CPU time 447.79 seconds
Started Jun 10 05:43:24 PM PDT 24
Finished Jun 10 05:50:53 PM PDT 24
Peak memory 200436 kb
Host smart-5d798c25-e978-40dc-bc85-fab9b6c2d2e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977896448 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.1977896448
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.3860979300
Short name T543
Test name
Test status
Simulation time 2595286907 ps
CPU time 25.73 seconds
Started Jun 10 05:43:28 PM PDT 24
Finished Jun 10 05:43:54 PM PDT 24
Peak memory 200500 kb
Host smart-84117d73-2839-4c7e-a7f3-a997e6d5276d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860979300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3860979300
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.156754554
Short name T386
Test name
Test status
Simulation time 72560959 ps
CPU time 0.58 seconds
Started Jun 10 05:43:27 PM PDT 24
Finished Jun 10 05:43:28 PM PDT 24
Peak memory 196364 kb
Host smart-1d22e66e-cdee-469d-9fe8-2b6141e026aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156754554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.156754554
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.216670126
Short name T494
Test name
Test status
Simulation time 595092913 ps
CPU time 30.93 seconds
Started Jun 10 05:43:24 PM PDT 24
Finished Jun 10 05:43:55 PM PDT 24
Peak memory 216824 kb
Host smart-d077d9c1-495e-448c-8ccb-b5bdd1a1e488
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=216670126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.216670126
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2079369257
Short name T534
Test name
Test status
Simulation time 694584837 ps
CPU time 9.2 seconds
Started Jun 10 05:43:29 PM PDT 24
Finished Jun 10 05:43:39 PM PDT 24
Peak memory 200432 kb
Host smart-d67af9fa-86ca-41d6-b753-73666dd8e032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079369257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2079369257
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3130333249
Short name T55
Test name
Test status
Simulation time 1911543553 ps
CPU time 332.98 seconds
Started Jun 10 05:43:27 PM PDT 24
Finished Jun 10 05:49:01 PM PDT 24
Peak memory 459248 kb
Host smart-7a03388a-d21a-4f95-9881-233063e3e1e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3130333249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3130333249
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3897986482
Short name T500
Test name
Test status
Simulation time 2953456175 ps
CPU time 170.84 seconds
Started Jun 10 05:43:30 PM PDT 24
Finished Jun 10 05:46:21 PM PDT 24
Peak memory 200436 kb
Host smart-014b8d17-2aaf-4fa8-a09c-e44be9971b2a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897986482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3897986482
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1656549152
Short name T21
Test name
Test status
Simulation time 6741329913 ps
CPU time 33.29 seconds
Started Jun 10 05:43:23 PM PDT 24
Finished Jun 10 05:43:57 PM PDT 24
Peak memory 200460 kb
Host smart-f434bfc6-4e67-465e-8afa-0ec29b3df536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656549152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1656549152
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2444316812
Short name T502
Test name
Test status
Simulation time 171377129 ps
CPU time 3.26 seconds
Started Jun 10 05:43:24 PM PDT 24
Finished Jun 10 05:43:28 PM PDT 24
Peak memory 200396 kb
Host smart-47b7e411-e5a4-4b51-bf43-72cf331e8581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444316812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2444316812
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.4087710483
Short name T230
Test name
Test status
Simulation time 7730882603 ps
CPU time 759.62 seconds
Started Jun 10 05:43:28 PM PDT 24
Finished Jun 10 05:56:08 PM PDT 24
Peak memory 737272 kb
Host smart-65df8414-a45c-494f-9071-2ec7b3c19991
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087710483 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.4087710483
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.2857988518
Short name T277
Test name
Test status
Simulation time 254585307 ps
CPU time 1.18 seconds
Started Jun 10 05:43:30 PM PDT 24
Finished Jun 10 05:43:31 PM PDT 24
Peak memory 200420 kb
Host smart-6e2dd8da-fca9-4294-a252-a42d1682fe20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857988518 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.2857988518
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.224623900
Short name T264
Test name
Test status
Simulation time 27069298367 ps
CPU time 485.18 seconds
Started Jun 10 05:43:30 PM PDT 24
Finished Jun 10 05:51:35 PM PDT 24
Peak memory 200396 kb
Host smart-d24b9e18-4412-40ab-9dee-46b04429611c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224623900 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.224623900
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1967279169
Short name T507
Test name
Test status
Simulation time 4770730538 ps
CPU time 52.82 seconds
Started Jun 10 05:43:31 PM PDT 24
Finished Jun 10 05:44:24 PM PDT 24
Peak memory 200500 kb
Host smart-60bfaddc-5e2d-4f55-a737-5078794bee84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967279169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1967279169
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2508285835
Short name T56
Test name
Test status
Simulation time 41893377 ps
CPU time 0.61 seconds
Started Jun 10 05:43:36 PM PDT 24
Finished Jun 10 05:43:37 PM PDT 24
Peak memory 196152 kb
Host smart-0ce0725e-c33a-498b-806a-7dbb083b1e6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508285835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2508285835
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3888174504
Short name T574
Test name
Test status
Simulation time 543439723 ps
CPU time 28.05 seconds
Started Jun 10 05:43:30 PM PDT 24
Finished Jun 10 05:43:58 PM PDT 24
Peak memory 219828 kb
Host smart-79c2b11a-83cf-4f74-929e-704fa70c534f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3888174504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3888174504
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.800001617
Short name T82
Test name
Test status
Simulation time 1347631782 ps
CPU time 27.21 seconds
Started Jun 10 05:43:26 PM PDT 24
Finished Jun 10 05:43:54 PM PDT 24
Peak memory 200420 kb
Host smart-56ef1012-fb6f-48b3-8b9b-871d3e52eefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800001617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.800001617
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1441778636
Short name T474
Test name
Test status
Simulation time 1866118773 ps
CPU time 388.6 seconds
Started Jun 10 05:43:29 PM PDT 24
Finished Jun 10 05:49:57 PM PDT 24
Peak memory 515868 kb
Host smart-e8912367-d640-4282-823c-7485b4d5bcbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1441778636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1441778636
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.4165973660
Short name T385
Test name
Test status
Simulation time 5669421545 ps
CPU time 159.58 seconds
Started Jun 10 05:43:24 PM PDT 24
Finished Jun 10 05:46:04 PM PDT 24
Peak memory 200500 kb
Host smart-3e653147-3afc-49a8-b882-00df4fa03ca2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165973660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.4165973660
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_smoke.2287450664
Short name T197
Test name
Test status
Simulation time 499459781 ps
CPU time 5.05 seconds
Started Jun 10 05:43:34 PM PDT 24
Finished Jun 10 05:43:39 PM PDT 24
Peak memory 200400 kb
Host smart-9701e6db-5107-44e0-88aa-894112c200bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287450664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2287450664
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.3924899417
Short name T177
Test name
Test status
Simulation time 31324322826 ps
CPU time 2348.47 seconds
Started Jun 10 05:43:36 PM PDT 24
Finished Jun 10 06:22:46 PM PDT 24
Peak memory 694712 kb
Host smart-ff2114dd-2fa9-47a7-a853-a875bc49fcc4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924899417 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3924899417
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.917609709
Short name T369
Test name
Test status
Simulation time 277303601 ps
CPU time 1.4 seconds
Started Jun 10 05:43:38 PM PDT 24
Finished Jun 10 05:43:40 PM PDT 24
Peak memory 200480 kb
Host smart-ca529eff-b146-4ee5-becf-767998690f69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917609709 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_hmac_vectors.917609709
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.983785948
Short name T204
Test name
Test status
Simulation time 129442010994 ps
CPU time 454.78 seconds
Started Jun 10 05:43:36 PM PDT 24
Finished Jun 10 05:51:11 PM PDT 24
Peak memory 200464 kb
Host smart-e8157c20-00d7-4e48-8795-a2b249748b41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983785948 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.983785948
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3040209541
Short name T561
Test name
Test status
Simulation time 2249116808 ps
CPU time 43.71 seconds
Started Jun 10 05:43:29 PM PDT 24
Finished Jun 10 05:44:13 PM PDT 24
Peak memory 200524 kb
Host smart-2d0952aa-acd8-489d-8b2d-7da2129f8a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040209541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3040209541
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.4175926324
Short name T495
Test name
Test status
Simulation time 46703060 ps
CPU time 0.59 seconds
Started Jun 10 05:43:36 PM PDT 24
Finished Jun 10 05:43:38 PM PDT 24
Peak memory 196120 kb
Host smart-1b9c2fc1-9717-471f-83c4-805f53a16bd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175926324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.4175926324
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.283251304
Short name T378
Test name
Test status
Simulation time 808430296 ps
CPU time 30.56 seconds
Started Jun 10 05:43:37 PM PDT 24
Finished Jun 10 05:44:08 PM PDT 24
Peak memory 208632 kb
Host smart-0e583c6d-e8b8-4add-8640-07ac91fdba28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=283251304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.283251304
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2957392986
Short name T468
Test name
Test status
Simulation time 7331097958 ps
CPU time 42.76 seconds
Started Jun 10 05:43:37 PM PDT 24
Finished Jun 10 05:44:20 PM PDT 24
Peak memory 200464 kb
Host smart-0c420b28-b2e6-4577-8da5-a2a98f9caf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957392986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2957392986
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.1158968071
Short name T504
Test name
Test status
Simulation time 2892208342 ps
CPU time 210.72 seconds
Started Jun 10 05:43:36 PM PDT 24
Finished Jun 10 05:47:07 PM PDT 24
Peak memory 669156 kb
Host smart-399451e1-ea74-4c24-85cf-ef60fc6bdf1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1158968071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1158968071
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.3209789543
Short name T526
Test name
Test status
Simulation time 50428231677 ps
CPU time 95.61 seconds
Started Jun 10 05:43:39 PM PDT 24
Finished Jun 10 05:45:15 PM PDT 24
Peak memory 200300 kb
Host smart-faa6b2ee-0cb5-46e3-befc-4262ea5b8794
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209789543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3209789543
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.4153857329
Short name T486
Test name
Test status
Simulation time 2152456148 ps
CPU time 32.96 seconds
Started Jun 10 05:43:30 PM PDT 24
Finished Jun 10 05:44:04 PM PDT 24
Peak memory 200440 kb
Host smart-30c358a1-9441-4984-a6bb-4ba62ec55ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153857329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.4153857329
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.406099975
Short name T189
Test name
Test status
Simulation time 898258477 ps
CPU time 7.06 seconds
Started Jun 10 05:43:29 PM PDT 24
Finished Jun 10 05:43:37 PM PDT 24
Peak memory 200456 kb
Host smart-fa83e758-1028-4191-883b-7e88a251e4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406099975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.406099975
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3894926364
Short name T33
Test name
Test status
Simulation time 37337905926 ps
CPU time 445.96 seconds
Started Jun 10 05:43:33 PM PDT 24
Finished Jun 10 05:50:59 PM PDT 24
Peak memory 653736 kb
Host smart-65357090-1d23-478e-90c4-503df365ace6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894926364 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3894926364
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.3489498167
Short name T573
Test name
Test status
Simulation time 138832843 ps
CPU time 1.3 seconds
Started Jun 10 05:43:33 PM PDT 24
Finished Jun 10 05:43:35 PM PDT 24
Peak memory 200332 kb
Host smart-bd362f24-65bc-448a-84cc-ff469dcf58b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489498167 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.3489498167
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.44085070
Short name T168
Test name
Test status
Simulation time 20602665910 ps
CPU time 472.09 seconds
Started Jun 10 05:43:38 PM PDT 24
Finished Jun 10 05:51:31 PM PDT 24
Peak memory 200488 kb
Host smart-f0df04f1-25d7-49cf-bcc8-35f95edefa1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44085070 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.44085070
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.109417098
Short name T553
Test name
Test status
Simulation time 4520602584 ps
CPU time 83.66 seconds
Started Jun 10 05:43:36 PM PDT 24
Finished Jun 10 05:45:00 PM PDT 24
Peak memory 200552 kb
Host smart-2cf8b5bc-4aee-4714-829d-f6714d9154ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109417098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.109417098
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.4093784028
Short name T489
Test name
Test status
Simulation time 11977306 ps
CPU time 0.58 seconds
Started Jun 10 05:43:38 PM PDT 24
Finished Jun 10 05:43:39 PM PDT 24
Peak memory 195256 kb
Host smart-03c903f7-8406-4448-810c-95b466c0980a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093784028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.4093784028
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1136147839
Short name T479
Test name
Test status
Simulation time 1030911770 ps
CPU time 51.86 seconds
Started Jun 10 05:43:38 PM PDT 24
Finished Jun 10 05:44:30 PM PDT 24
Peak memory 232836 kb
Host smart-4f1cc7e2-ad22-4695-a18a-30efd43fa6ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1136147839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1136147839
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.151672516
Short name T509
Test name
Test status
Simulation time 7226508610 ps
CPU time 40.28 seconds
Started Jun 10 05:43:38 PM PDT 24
Finished Jun 10 05:44:19 PM PDT 24
Peak memory 200548 kb
Host smart-b56d95c0-9ef1-43d5-ab5d-359fb4139f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151672516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.151672516
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3352722752
Short name T299
Test name
Test status
Simulation time 11988198729 ps
CPU time 276.65 seconds
Started Jun 10 05:43:36 PM PDT 24
Finished Jun 10 05:48:13 PM PDT 24
Peak memory 469916 kb
Host smart-f9ea3516-0a77-4e4e-9e4b-e1ad6a8cd93a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3352722752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3352722752
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2781172902
Short name T283
Test name
Test status
Simulation time 6757595362 ps
CPU time 119.92 seconds
Started Jun 10 05:43:37 PM PDT 24
Finished Jun 10 05:45:37 PM PDT 24
Peak memory 200296 kb
Host smart-5905a953-6a0d-4008-b5b3-c84ac5cc6673
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781172902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2781172902
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.648172205
Short name T418
Test name
Test status
Simulation time 1672957293 ps
CPU time 23.97 seconds
Started Jun 10 05:43:34 PM PDT 24
Finished Jun 10 05:43:59 PM PDT 24
Peak memory 200396 kb
Host smart-a1f5c6e0-8052-40cf-a71f-faf48508cbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648172205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.648172205
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3721276408
Short name T559
Test name
Test status
Simulation time 145214130 ps
CPU time 1.58 seconds
Started Jun 10 05:43:35 PM PDT 24
Finished Jun 10 05:43:37 PM PDT 24
Peak memory 200444 kb
Host smart-9d87b6b6-397f-4f69-990b-72f697bf7ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721276408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3721276408
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3919450073
Short name T332
Test name
Test status
Simulation time 71140067 ps
CPU time 0.65 seconds
Started Jun 10 05:43:35 PM PDT 24
Finished Jun 10 05:43:36 PM PDT 24
Peak memory 196140 kb
Host smart-277787a2-4490-4f71-96b9-e3cc79e76418
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919450073 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3919450073
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.3256494882
Short name T333
Test name
Test status
Simulation time 112099377 ps
CPU time 1.16 seconds
Started Jun 10 05:43:39 PM PDT 24
Finished Jun 10 05:43:40 PM PDT 24
Peak memory 200300 kb
Host smart-09aee50e-df8e-420f-aa0d-afcf10b783e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256494882 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.3256494882
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.2365298831
Short name T522
Test name
Test status
Simulation time 325776260199 ps
CPU time 486.76 seconds
Started Jun 10 05:43:38 PM PDT 24
Finished Jun 10 05:51:45 PM PDT 24
Peak memory 200444 kb
Host smart-29916207-da80-4a0f-a09a-343b5366e12f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365298831 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.2365298831
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.997082555
Short name T422
Test name
Test status
Simulation time 26961470462 ps
CPU time 71.82 seconds
Started Jun 10 05:43:39 PM PDT 24
Finished Jun 10 05:44:51 PM PDT 24
Peak memory 200536 kb
Host smart-fdb3b7f9-edd8-41b9-acfe-53eddb50df7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997082555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.997082555
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3140250083
Short name T167
Test name
Test status
Simulation time 20434196 ps
CPU time 0.59 seconds
Started Jun 10 05:43:38 PM PDT 24
Finished Jun 10 05:43:39 PM PDT 24
Peak memory 196060 kb
Host smart-8ae024e5-cc9e-4db7-999a-8cb9f25f142f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140250083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3140250083
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2196992042
Short name T430
Test name
Test status
Simulation time 20218392892 ps
CPU time 61.25 seconds
Started Jun 10 05:43:37 PM PDT 24
Finished Jun 10 05:44:38 PM PDT 24
Peak memory 249632 kb
Host smart-3285aa5b-b30d-4814-a3af-d18a3f5c7c06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2196992042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2196992042
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2312653433
Short name T227
Test name
Test status
Simulation time 1585044996 ps
CPU time 33.11 seconds
Started Jun 10 05:43:35 PM PDT 24
Finished Jun 10 05:44:08 PM PDT 24
Peak memory 200476 kb
Host smart-b9adabdd-6008-461d-af97-eed3509e129e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312653433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2312653433
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_error.1562584243
Short name T572
Test name
Test status
Simulation time 14094050269 ps
CPU time 63.01 seconds
Started Jun 10 05:43:38 PM PDT 24
Finished Jun 10 05:44:41 PM PDT 24
Peak memory 200396 kb
Host smart-ef8cf3fd-247e-4a8d-95c1-5ce32a31cfcb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562584243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1562584243
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3698494981
Short name T119
Test name
Test status
Simulation time 235232593 ps
CPU time 5.05 seconds
Started Jun 10 05:43:38 PM PDT 24
Finished Jun 10 05:43:44 PM PDT 24
Peak memory 200416 kb
Host smart-9baa0fd5-7597-41f4-9ce7-6bd1e28779cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698494981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3698494981
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.4292766094
Short name T501
Test name
Test status
Simulation time 113738539 ps
CPU time 3.64 seconds
Started Jun 10 05:43:38 PM PDT 24
Finished Jun 10 05:43:42 PM PDT 24
Peak memory 200500 kb
Host smart-a24de956-ae95-4af7-8779-f981b62def51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292766094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.4292766094
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.1410233738
Short name T116
Test name
Test status
Simulation time 4918894111 ps
CPU time 531.82 seconds
Started Jun 10 05:43:38 PM PDT 24
Finished Jun 10 05:52:30 PM PDT 24
Peak memory 612552 kb
Host smart-87db4e63-fd3d-4de2-acc1-dfeda0e9b268
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410233738 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1410233738
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.621466608
Short name T241
Test name
Test status
Simulation time 189900680 ps
CPU time 1.34 seconds
Started Jun 10 05:43:40 PM PDT 24
Finished Jun 10 05:43:42 PM PDT 24
Peak memory 200252 kb
Host smart-5b8fa89c-3ed7-4154-a8e1-9c2a2286904d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621466608 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_hmac_vectors.621466608
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.1041243515
Short name T364
Test name
Test status
Simulation time 38519771562 ps
CPU time 552.38 seconds
Started Jun 10 05:43:39 PM PDT 24
Finished Jun 10 05:52:52 PM PDT 24
Peak memory 200428 kb
Host smart-102c36ef-c01b-4f3f-9886-66082dbea562
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041243515 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.1041243515
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.942947254
Short name T535
Test name
Test status
Simulation time 1257805500 ps
CPU time 5.35 seconds
Started Jun 10 05:43:41 PM PDT 24
Finished Jun 10 05:43:46 PM PDT 24
Peak memory 200356 kb
Host smart-82257fec-6d14-4190-9b8a-d39fa90e489d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942947254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.942947254
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3508853489
Short name T407
Test name
Test status
Simulation time 17708963 ps
CPU time 0.57 seconds
Started Jun 10 05:43:47 PM PDT 24
Finished Jun 10 05:43:48 PM PDT 24
Peak memory 196084 kb
Host smart-449b70f7-77cc-4341-a786-5c3491d084cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508853489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3508853489
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1072650890
Short name T244
Test name
Test status
Simulation time 1418721513 ps
CPU time 36.16 seconds
Started Jun 10 05:43:41 PM PDT 24
Finished Jun 10 05:44:18 PM PDT 24
Peak memory 223572 kb
Host smart-c936381c-17f7-4a2d-889d-ed3536d46db3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1072650890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1072650890
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.279021135
Short name T339
Test name
Test status
Simulation time 140958144 ps
CPU time 2.76 seconds
Started Jun 10 05:43:44 PM PDT 24
Finished Jun 10 05:43:47 PM PDT 24
Peak memory 200420 kb
Host smart-8590fe0e-43f6-45a1-b1f0-8bcb0ce605e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279021135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.279021135
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.203249407
Short name T361
Test name
Test status
Simulation time 3433994794 ps
CPU time 960.71 seconds
Started Jun 10 05:43:43 PM PDT 24
Finished Jun 10 05:59:44 PM PDT 24
Peak memory 732404 kb
Host smart-43e7dda9-c8c5-48c4-898b-5511303c07d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=203249407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.203249407
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2720652757
Short name T181
Test name
Test status
Simulation time 928554032 ps
CPU time 52.89 seconds
Started Jun 10 05:43:47 PM PDT 24
Finished Jun 10 05:44:40 PM PDT 24
Peak memory 200536 kb
Host smart-a6d2fe66-d995-461a-9043-2677979decbb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720652757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2720652757
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3917088416
Short name T455
Test name
Test status
Simulation time 362968955 ps
CPU time 11.48 seconds
Started Jun 10 05:43:41 PM PDT 24
Finished Jun 10 05:43:53 PM PDT 24
Peak memory 200392 kb
Host smart-5eb7dbd3-bee1-4806-b666-ac6216b17735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917088416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3917088416
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1585339811
Short name T475
Test name
Test status
Simulation time 150475916 ps
CPU time 5.13 seconds
Started Jun 10 05:43:38 PM PDT 24
Finished Jun 10 05:43:44 PM PDT 24
Peak memory 200408 kb
Host smart-4dc2db4c-c7d1-4610-87b4-22cc35cfa227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585339811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1585339811
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2547707642
Short name T401
Test name
Test status
Simulation time 72988512997 ps
CPU time 657.65 seconds
Started Jun 10 05:43:48 PM PDT 24
Finished Jun 10 05:54:46 PM PDT 24
Peak memory 200564 kb
Host smart-a90d2200-6ea8-48d3-89b1-d79f33a26b3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547707642 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2547707642
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.813166002
Short name T370
Test name
Test status
Simulation time 34863166 ps
CPU time 1.45 seconds
Started Jun 10 05:43:45 PM PDT 24
Finished Jun 10 05:43:47 PM PDT 24
Peak memory 200340 kb
Host smart-69b55cca-6636-4a14-b0eb-35eee8715ce2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813166002 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_hmac_vectors.813166002
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.1176756302
Short name T284
Test name
Test status
Simulation time 107314029121 ps
CPU time 547.38 seconds
Started Jun 10 05:43:48 PM PDT 24
Finished Jun 10 05:52:56 PM PDT 24
Peak memory 200504 kb
Host smart-e5f42906-b847-4171-bca9-da4fce3f3d70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176756302 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.1176756302
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.2861179875
Short name T427
Test name
Test status
Simulation time 7919140365 ps
CPU time 60.54 seconds
Started Jun 10 05:43:47 PM PDT 24
Finished Jun 10 05:44:48 PM PDT 24
Peak memory 200496 kb
Host smart-0e444aee-8d82-455b-a069-0d1c9c7d37aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861179875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2861179875
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2326458375
Short name T239
Test name
Test status
Simulation time 12773412 ps
CPU time 0.57 seconds
Started Jun 10 05:41:56 PM PDT 24
Finished Jun 10 05:41:57 PM PDT 24
Peak memory 196332 kb
Host smart-d8cea465-75a6-4612-8ec5-a33cfa3a4e64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326458375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2326458375
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2087629436
Short name T296
Test name
Test status
Simulation time 1017280454 ps
CPU time 53.3 seconds
Started Jun 10 05:41:47 PM PDT 24
Finished Jun 10 05:42:41 PM PDT 24
Peak memory 233144 kb
Host smart-d80d6900-80e8-4c21-a706-139c63cd8f85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2087629436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2087629436
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1613254050
Short name T51
Test name
Test status
Simulation time 2001851037 ps
CPU time 30.01 seconds
Started Jun 10 05:42:01 PM PDT 24
Finished Jun 10 05:42:32 PM PDT 24
Peak memory 200444 kb
Host smart-002afe2f-6cfc-455a-a1cb-5622be5acf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613254050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1613254050
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1417075738
Short name T124
Test name
Test status
Simulation time 789537157 ps
CPU time 136.92 seconds
Started Jun 10 05:41:46 PM PDT 24
Finished Jun 10 05:44:03 PM PDT 24
Peak memory 473772 kb
Host smart-d5c8bbcf-6572-495f-8ad7-bcdf4e0b14e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1417075738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1417075738
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3091183754
Short name T537
Test name
Test status
Simulation time 1823807496 ps
CPU time 33.26 seconds
Started Jun 10 05:41:46 PM PDT 24
Finished Jun 10 05:42:20 PM PDT 24
Peak memory 200424 kb
Host smart-3a332c82-69c9-448b-94dd-2dcdc1cbf509
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091183754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3091183754
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1447365373
Short name T273
Test name
Test status
Simulation time 1759287298 ps
CPU time 114.66 seconds
Started Jun 10 05:41:47 PM PDT 24
Finished Jun 10 05:43:42 PM PDT 24
Peak memory 200424 kb
Host smart-315ba31f-b004-44cb-8c00-d8ab649da1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447365373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1447365373
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3754049890
Short name T262
Test name
Test status
Simulation time 500210797 ps
CPU time 5 seconds
Started Jun 10 05:41:48 PM PDT 24
Finished Jun 10 05:41:54 PM PDT 24
Peak memory 200416 kb
Host smart-30e60e65-b785-4a43-b7e9-7025126460bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754049890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3754049890
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1875283493
Short name T15
Test name
Test status
Simulation time 25082953 ps
CPU time 0.66 seconds
Started Jun 10 05:41:47 PM PDT 24
Finished Jun 10 05:41:48 PM PDT 24
Peak memory 196116 kb
Host smart-e9e085b9-14a8-4a30-bd32-6d61344d3229
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875283493 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1875283493
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.418750389
Short name T246
Test name
Test status
Simulation time 216932217 ps
CPU time 1.18 seconds
Started Jun 10 05:41:56 PM PDT 24
Finished Jun 10 05:41:58 PM PDT 24
Peak memory 200208 kb
Host smart-edfc7ef6-f615-4dee-99f4-fd9ceaa42b6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418750389 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_hmac_vectors.418750389
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.2297705930
Short name T469
Test name
Test status
Simulation time 82840320773 ps
CPU time 542.82 seconds
Started Jun 10 05:41:41 PM PDT 24
Finished Jun 10 05:50:44 PM PDT 24
Peak memory 200432 kb
Host smart-08de664f-adf0-4cfb-be6f-e2443f31b367
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297705930 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.2297705930
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2206460848
Short name T390
Test name
Test status
Simulation time 26162060043 ps
CPU time 48.85 seconds
Started Jun 10 05:41:56 PM PDT 24
Finished Jun 10 05:42:45 PM PDT 24
Peak memory 200568 kb
Host smart-445df8a1-bb30-4345-b1e6-bef4a11c7ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206460848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2206460848
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2478668675
Short name T199
Test name
Test status
Simulation time 30686601 ps
CPU time 0.57 seconds
Started Jun 10 05:41:54 PM PDT 24
Finished Jun 10 05:41:55 PM PDT 24
Peak memory 195768 kb
Host smart-fc2f65a2-8e72-40e0-a018-6d95f405fae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478668675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2478668675
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.480096490
Short name T158
Test name
Test status
Simulation time 1807632655 ps
CPU time 57.24 seconds
Started Jun 10 05:41:53 PM PDT 24
Finished Jun 10 05:42:51 PM PDT 24
Peak memory 232572 kb
Host smart-e3b674d9-b944-4b43-8422-126f20af6440
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=480096490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.480096490
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3008651106
Short name T549
Test name
Test status
Simulation time 2555653484 ps
CPU time 50.94 seconds
Started Jun 10 05:41:46 PM PDT 24
Finished Jun 10 05:42:37 PM PDT 24
Peak memory 200484 kb
Host smart-e879efbb-4adb-49d5-a3c9-65794ecb989a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008651106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3008651106
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3882360592
Short name T192
Test name
Test status
Simulation time 3969897183 ps
CPU time 1050.5 seconds
Started Jun 10 05:41:56 PM PDT 24
Finished Jun 10 05:59:28 PM PDT 24
Peak memory 757280 kb
Host smart-7dd1958a-6d76-4315-b238-26401b8c436d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3882360592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3882360592
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3032667323
Short name T366
Test name
Test status
Simulation time 722894403 ps
CPU time 40.6 seconds
Started Jun 10 05:41:57 PM PDT 24
Finished Jun 10 05:42:38 PM PDT 24
Peak memory 200408 kb
Host smart-3e5e50c6-e2ac-44d4-9add-ce1f6078970c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032667323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3032667323
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1983685258
Short name T328
Test name
Test status
Simulation time 3975676017 ps
CPU time 12.22 seconds
Started Jun 10 05:41:57 PM PDT 24
Finished Jun 10 05:42:10 PM PDT 24
Peak memory 200424 kb
Host smart-6b24175e-b577-4a71-9c44-43470dbc7f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983685258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1983685258
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3924561666
Short name T251
Test name
Test status
Simulation time 1776006631 ps
CPU time 4.84 seconds
Started Jun 10 05:41:44 PM PDT 24
Finished Jun 10 05:41:49 PM PDT 24
Peak memory 200416 kb
Host smart-fddca7c6-0009-4c85-bd6e-86652f57c9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924561666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3924561666
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.45787093
Short name T406
Test name
Test status
Simulation time 5168694723 ps
CPU time 728.46 seconds
Started Jun 10 05:41:56 PM PDT 24
Finished Jun 10 05:54:05 PM PDT 24
Peak memory 721240 kb
Host smart-bcdbe2d5-1b10-4303-93c0-63a352ef1e00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45787093 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.45787093
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.3889650526
Short name T550
Test name
Test status
Simulation time 112755630 ps
CPU time 1.46 seconds
Started Jun 10 05:42:02 PM PDT 24
Finished Jun 10 05:42:04 PM PDT 24
Peak memory 200440 kb
Host smart-3755c419-1213-4130-b983-5a9c1bee3cbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889650526 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.3889650526
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3418277932
Short name T546
Test name
Test status
Simulation time 36286197136 ps
CPU time 521.82 seconds
Started Jun 10 05:41:53 PM PDT 24
Finished Jun 10 05:50:36 PM PDT 24
Peak memory 200424 kb
Host smart-95896912-dddc-4462-9524-6f5e2c9e10be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418277932 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.3418277932
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1186581984
Short name T123
Test name
Test status
Simulation time 4668157029 ps
CPU time 24.11 seconds
Started Jun 10 05:41:50 PM PDT 24
Finished Jun 10 05:42:15 PM PDT 24
Peak memory 200464 kb
Host smart-7b1cb088-b4c1-4fcf-93b0-89691d86c546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186581984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1186581984
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2932929409
Short name T316
Test name
Test status
Simulation time 12624113 ps
CPU time 0.59 seconds
Started Jun 10 05:41:55 PM PDT 24
Finished Jun 10 05:41:56 PM PDT 24
Peak memory 196428 kb
Host smart-b27dae28-8498-4a34-9ffc-315c7f7f342c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932929409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2932929409
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2055946751
Short name T143
Test name
Test status
Simulation time 1230481568 ps
CPU time 12.89 seconds
Started Jun 10 05:41:54 PM PDT 24
Finished Jun 10 05:42:08 PM PDT 24
Peak memory 226904 kb
Host smart-c18de361-4ebc-4032-b035-a16642be4936
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2055946751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2055946751
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.4081853415
Short name T274
Test name
Test status
Simulation time 1184917373 ps
CPU time 314.27 seconds
Started Jun 10 05:41:48 PM PDT 24
Finished Jun 10 05:47:03 PM PDT 24
Peak memory 601676 kb
Host smart-3dde76f1-71ca-4d32-8037-6dd6dbfb87b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4081853415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.4081853415
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2393483283
Short name T357
Test name
Test status
Simulation time 11437890097 ps
CPU time 158.77 seconds
Started Jun 10 05:41:56 PM PDT 24
Finished Jun 10 05:44:35 PM PDT 24
Peak memory 200416 kb
Host smart-0c4fed5d-3b51-4d7c-957e-828d1629f937
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393483283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2393483283
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1032787145
Short name T349
Test name
Test status
Simulation time 20814584861 ps
CPU time 60.49 seconds
Started Jun 10 05:41:55 PM PDT 24
Finished Jun 10 05:42:56 PM PDT 24
Peak memory 200480 kb
Host smart-4d33aa96-7099-4b36-9b2a-aace565597a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032787145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1032787145
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.454072650
Short name T132
Test name
Test status
Simulation time 4175246306 ps
CPU time 16.97 seconds
Started Jun 10 05:41:53 PM PDT 24
Finished Jun 10 05:42:10 PM PDT 24
Peak memory 200348 kb
Host smart-1b3f8473-dbae-415a-9bc4-ff10c00ec316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454072650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.454072650
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.4039009066
Short name T445
Test name
Test status
Simulation time 16097022215 ps
CPU time 830.82 seconds
Started Jun 10 05:42:03 PM PDT 24
Finished Jun 10 05:55:54 PM PDT 24
Peak memory 200544 kb
Host smart-3d82606e-d3ad-42c6-82c8-636db360cb61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039009066 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.4039009066
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.3001668207
Short name T584
Test name
Test status
Simulation time 1098712961 ps
CPU time 1.39 seconds
Started Jun 10 05:41:56 PM PDT 24
Finished Jun 10 05:41:58 PM PDT 24
Peak memory 200404 kb
Host smart-1526c3f1-6521-4614-ae66-b54412a48a9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001668207 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.3001668207
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.2224232013
Short name T579
Test name
Test status
Simulation time 39780168429 ps
CPU time 535.01 seconds
Started Jun 10 05:41:54 PM PDT 24
Finished Jun 10 05:50:50 PM PDT 24
Peak memory 200128 kb
Host smart-0f77ee7f-25f1-4c0b-8510-3d9090ff92a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224232013 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.2224232013
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.3755322182
Short name T187
Test name
Test status
Simulation time 2397629108 ps
CPU time 49.91 seconds
Started Jun 10 05:41:53 PM PDT 24
Finished Jun 10 05:42:43 PM PDT 24
Peak memory 200500 kb
Host smart-62ff28c5-717c-450d-a04b-4c885fd940c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755322182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3755322182
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2120929962
Short name T12
Test name
Test status
Simulation time 11732120 ps
CPU time 0.62 seconds
Started Jun 10 05:41:53 PM PDT 24
Finished Jun 10 05:41:54 PM PDT 24
Peak memory 196424 kb
Host smart-6ab43fe9-4c98-4460-bc74-49e63b786b22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120929962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2120929962
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1124615407
Short name T492
Test name
Test status
Simulation time 3744445626 ps
CPU time 39.65 seconds
Started Jun 10 05:41:58 PM PDT 24
Finished Jun 10 05:42:38 PM PDT 24
Peak memory 216688 kb
Host smart-8acdbd83-b145-47e5-9ab2-6180b8f96e25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1124615407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1124615407
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.929259267
Short name T478
Test name
Test status
Simulation time 595889301 ps
CPU time 11.66 seconds
Started Jun 10 05:42:12 PM PDT 24
Finished Jun 10 05:42:24 PM PDT 24
Peak memory 200348 kb
Host smart-4ccd7c58-7571-47d3-889f-2e71e9ee475d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929259267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.929259267
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3263953737
Short name T272
Test name
Test status
Simulation time 9046927555 ps
CPU time 422.83 seconds
Started Jun 10 05:41:53 PM PDT 24
Finished Jun 10 05:48:56 PM PDT 24
Peak memory 650500 kb
Host smart-977759f0-3df0-41df-9b0d-911d62748a58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3263953737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3263953737
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.436873216
Short name T30
Test name
Test status
Simulation time 3836783869 ps
CPU time 15.48 seconds
Started Jun 10 05:42:00 PM PDT 24
Finished Jun 10 05:42:16 PM PDT 24
Peak memory 200296 kb
Host smart-b8072f6b-fab3-45ec-9361-e551530ea04a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436873216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.436873216
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1886944999
Short name T266
Test name
Test status
Simulation time 12302955279 ps
CPU time 88.94 seconds
Started Jun 10 05:42:01 PM PDT 24
Finished Jun 10 05:43:31 PM PDT 24
Peak memory 200412 kb
Host smart-b6684e81-ed74-43ca-8f43-f2387c744000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886944999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1886944999
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.4049854136
Short name T538
Test name
Test status
Simulation time 1049706949 ps
CPU time 5.1 seconds
Started Jun 10 05:41:53 PM PDT 24
Finished Jun 10 05:41:59 PM PDT 24
Peak memory 200364 kb
Host smart-838ce1f7-bec3-43f8-a65d-806d4994ec62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049854136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.4049854136
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2373887404
Short name T459
Test name
Test status
Simulation time 405439134665 ps
CPU time 1803.81 seconds
Started Jun 10 05:41:56 PM PDT 24
Finished Jun 10 06:12:06 PM PDT 24
Peak memory 200416 kb
Host smart-03030855-e1a7-4ca2-9af0-756d6052aa94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373887404 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2373887404
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.469985879
Short name T351
Test name
Test status
Simulation time 171163402 ps
CPU time 1.42 seconds
Started Jun 10 05:41:54 PM PDT 24
Finished Jun 10 05:41:56 PM PDT 24
Peak memory 200392 kb
Host smart-6922f97a-5245-4ec4-9ad1-7c676650d6b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469985879 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.hmac_test_hmac_vectors.469985879
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.2911555391
Short name T202
Test name
Test status
Simulation time 25956633971 ps
CPU time 519.82 seconds
Started Jun 10 05:41:58 PM PDT 24
Finished Jun 10 05:50:38 PM PDT 24
Peak memory 200480 kb
Host smart-ded2a8e7-75d1-4293-a7fe-6c6ee7d7f1fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911555391 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.2911555391
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2721520808
Short name T464
Test name
Test status
Simulation time 4705077962 ps
CPU time 88.3 seconds
Started Jun 10 05:42:02 PM PDT 24
Finished Jun 10 05:43:31 PM PDT 24
Peak memory 200544 kb
Host smart-aa6160b2-cf5d-4dfc-9f3e-f75c32d06594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721520808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2721520808
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.4239347554
Short name T336
Test name
Test status
Simulation time 132658485 ps
CPU time 0.59 seconds
Started Jun 10 05:42:02 PM PDT 24
Finished Jun 10 05:42:03 PM PDT 24
Peak memory 196068 kb
Host smart-80847aa0-871b-4077-a44c-5b5c0eb705e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239347554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.4239347554
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2913047521
Short name T201
Test name
Test status
Simulation time 1324568698 ps
CPU time 52.42 seconds
Started Jun 10 05:41:54 PM PDT 24
Finished Jun 10 05:42:47 PM PDT 24
Peak memory 241368 kb
Host smart-31b14b1b-fdde-4ea5-a935-b7a1e17ddb9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2913047521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2913047521
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3786861630
Short name T258
Test name
Test status
Simulation time 5592543992 ps
CPU time 16.46 seconds
Started Jun 10 05:41:58 PM PDT 24
Finished Jun 10 05:42:15 PM PDT 24
Peak memory 200476 kb
Host smart-ff192bb6-11f7-43e0-80b3-c09ce6a27724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786861630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3786861630
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.4003462499
Short name T163
Test name
Test status
Simulation time 1336223029 ps
CPU time 321.03 seconds
Started Jun 10 05:42:11 PM PDT 24
Finished Jun 10 05:47:33 PM PDT 24
Peak memory 476840 kb
Host smart-e8595dc2-ec2a-4b3f-b610-685e3621ce31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4003462499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.4003462499
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3310250285
Short name T135
Test name
Test status
Simulation time 10672535321 ps
CPU time 141.42 seconds
Started Jun 10 05:41:55 PM PDT 24
Finished Jun 10 05:44:17 PM PDT 24
Peak memory 200496 kb
Host smart-02abe2d9-e810-48cf-bc7f-fda6c999f23a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310250285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3310250285
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2089333050
Short name T195
Test name
Test status
Simulation time 228161011 ps
CPU time 3.64 seconds
Started Jun 10 05:41:51 PM PDT 24
Finished Jun 10 05:41:55 PM PDT 24
Peak memory 200332 kb
Host smart-be309043-5dbd-41b6-bed0-91aac17ef494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089333050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2089333050
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3851940398
Short name T205
Test name
Test status
Simulation time 282397800 ps
CPU time 5.21 seconds
Started Jun 10 05:41:59 PM PDT 24
Finished Jun 10 05:42:04 PM PDT 24
Peak memory 200416 kb
Host smart-964eea94-bdef-462c-9a47-c30be9a582fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851940398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3851940398
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1995348452
Short name T319
Test name
Test status
Simulation time 33623099775 ps
CPU time 1827.69 seconds
Started Jun 10 05:41:55 PM PDT 24
Finished Jun 10 06:12:23 PM PDT 24
Peak memory 357500 kb
Host smart-9826c30f-3be9-4e29-8b1e-1c85d5611235
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995348452 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1995348452
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.3722297751
Short name T452
Test name
Test status
Simulation time 89019579 ps
CPU time 1.44 seconds
Started Jun 10 05:41:56 PM PDT 24
Finished Jun 10 05:41:58 PM PDT 24
Peak memory 200464 kb
Host smart-d6e20055-a32c-4f36-ac47-1286bb1033b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722297751 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.3722297751
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.3077049990
Short name T511
Test name
Test status
Simulation time 7953604212 ps
CPU time 424.02 seconds
Started Jun 10 05:41:59 PM PDT 24
Finished Jun 10 05:49:03 PM PDT 24
Peak memory 200288 kb
Host smart-22535025-e02c-40df-941f-15e55001813c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077049990 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.3077049990
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3975955908
Short name T185
Test name
Test status
Simulation time 4422044417 ps
CPU time 89.23 seconds
Started Jun 10 05:41:56 PM PDT 24
Finished Jun 10 05:43:26 PM PDT 24
Peak memory 200520 kb
Host smart-314abdf5-ce83-433c-acb2-4882fc7c16c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975955908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3975955908
Directory /workspace/9.hmac_wipe_secret/latest
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