Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	34093139	1			T1	460		T2	14361		T3	23734
all_values[1]	34093139	1			T1	460		T2	14361		T3	23734
all_values[2]	34093139	1			T1	460		T2	14361		T3	23734

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93993

1

T3

3513

T19

474

T18

4

auto[1]

102185424

1

T1

1380

T2

43083

T3

67689

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84671566

1

T1

1303

T2

30526

T3

51977

auto[1]

17607851

1

T1

77

T2

12557

T3

19225

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	34660	1			T3	1973		T5	421		T143	236
all_values[0]	auto[0]	auto[1]	179	1			T3	4		T5	4		T121	2
all_values[0]	auto[1]	auto[0]	34007261	1			T1	441		T2	14358		T3	21750
all_values[0]	auto[1]	auto[1]	51039	1			T1	19		T2	3		T3	7
all_values[1]	auto[0]	auto[0]	30649	1			T18	4		T6	2		T122	1
all_values[1]	auto[0]	auto[1]	118	1			T34	2		T65	2		T120	42
all_values[1]	auto[1]	auto[0]	34058457	1			T1	418		T2	14361		T3	23734
all_values[1]	auto[1]	auto[1]	3915	1			T1	42		T5	42		T6	42
all_values[2]	auto[0]	auto[0]	8650	1			T3	530		T19	1		T21	1
all_values[2]	auto[0]	auto[1]	19737	1			T3	1006		T19	473		T21	1
all_values[2]	auto[1]	auto[0]	16531889	1			T1	444		T2	1807		T3	3990
all_values[2]	auto[1]	auto[1]	17532863	1			T1	16		T2	12554		T3	18208