Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	2	16	88.89
Crosses	32	8	24	75.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	1	14	93.33	100	1	1	0
msg_len_upper_cp	1	1	0	0.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	6	24	80.00	100	1	1	0
msg_len_upper_cross	2	2	0	0.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105422

1

T1

24

T2

12

T3

24

auto[1]

55354

1

T1

18

T2

8

T3

22

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	1	14	93.33

User Defined Bins for msg_len_lower_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_511	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	25015	1			T1	6		T2	9		T3	7
len_1026_2046	16003	1			T1	9		T3	2		T4	5
len_514_1022	5250	1			T1	2		T4	3		T7	3
len_2_510	24611	1			T1	4		T3	2		T4	58
len_2049	6	1			T129	4		T130	2		-	-
len_2048	29	1			T131	1		T132	2		T35	2
len_2047	1	1			T133	1		-	-		-	-
len_1025	3	1			T134	1		T135	2		-	-
len_1024	67	1			T136	1		T137	2		T132	3
len_1023	3	1			T138	2		T139	1		-	-
len_513	4	1			T130	4		-	-		-	-
len_512	67	1			T136	2		T34	1		T140	1
len_1	575	1			T11	2		T12	11		T14	2
len_0	8754	1			T2	1		T3	12		T4	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for msg_len_upper_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_upper	0	1	1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	6	24	80.00	6

Automatically Generated Cross Bins for msg_len_lower_cross

Uncovered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[len_2049]	0	1	1
[auto[0]]	[len_2047 , len_1025]	--	--	2
[auto[0]]	[len_513]	0	1	1
[auto[0]]	[len_511]	0	1	1
[auto[1]]	[len_511]	0	1	1

Covered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	15549	1			T1	6		T2	6		T3	5
auto[0]	len_1026_2046	9786	1			T1	3		T4	5		T7	2
auto[0]	len_514_1022	3471	1			T1	1		T4	3		T7	3
auto[0]	len_2_510	20125	1			T1	2		T4	58		T7	126
auto[0]	len_2048	17	1			T131	1		T132	1		T35	2
auto[0]	len_1024	46	1			T136	1		T137	1		T132	2
auto[0]	len_1023	1	1			T138	1		-	-		-	-
auto[0]	len_512	39	1			T136	2		T34	1		T140	1
auto[0]	len_1	165	1			T11	2		T14	2		T13	2
auto[0]	len_0	3512	1			T3	7		T4	1		T7	2
auto[1]	len_2050_plus	9466	1			T2	3		T3	2		T10	2
auto[1]	len_1026_2046	6217	1			T1	6		T3	2		T54	1
auto[1]	len_514_1022	1779	1			T1	1		T16	2		T114	3
auto[1]	len_2_510	4486	1			T1	2		T3	2		T12	1
auto[1]	len_2049	6	1			T129	4		T130	2		-	-
auto[1]	len_2048	12	1			T132	1		T141	1		T46	1
auto[1]	len_2047	1	1			T133	1		-	-		-	-
auto[1]	len_1025	3	1			T134	1		T135	2		-	-
auto[1]	len_1024	21	1			T137	1		T132	1		T35	1
auto[1]	len_1023	2	1			T138	1		T139	1		-	-
auto[1]	len_513	4	1			T130	4		-	-		-	-
auto[1]	len_512	28	1			T137	3		T132	1		T35	1
auto[1]	len_1	410	1			T12	11		T142	13		T121	5
auto[1]	len_0	5242	1			T2	1		T3	5		T8	2

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	2	0	0.00	2

Automatically Generated Cross Bins for msg_len_upper_cross

Uncovered bins

hmac_en	msg_len_upper_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	2