Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16653157

1

T1

10

T2

813

T3

3087

auto[1]

1238024

1

T1

12

T2

2109

T3

3283

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1260773

1

T1

12

T2

316

T3

1729

auto[1]

16630408

1

T1

10

T2

2606

T3

4641

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16225358

1

T1

14

T2

1336

T3

3860

auto[1]

1665823

1

T1

8

T2

1586

T3

2510

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	15625635	1			T1	8		T2	2581		T3	5555
fifo_depth[1]	463874	1			T2	78		T3	167		T4	1330
fifo_depth[2]	350813	1			T2	70		T3	186		T4	539
fifo_depth[3]	280261	1			T2	71		T3	151		T4	217
fifo_depth[4]	220022	1			T2	60		T3	85		T4	59
fifo_depth[5]	170278	1			T2	41		T3	53		T4	20
fifo_depth[6]	147994	1			T2	14		T3	56		T7	6
fifo_depth[7]	131299	1			T2	7		T3	42		T7	2

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2265546

1

T1

14

T2

341

T3

815

auto[1]

15625635

1

T1

8

T2

2581

T3

5555

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17880712

1

T1

21

T2

2922

T3

6370

auto[1]

10469

1

T1

1

T16

22

T6

1

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

40681

1

T1

3

T3

281

T29

114

auto[0]

auto[0]

auto[0]

auto[1]

43816

1

T1

2

T17

1

T31

1335

auto[0]

auto[0]

auto[1]

auto[0]

1901960

1

T1

2

T4

2166

T7

4769

auto[0]

auto[0]

auto[1]

auto[1]

37470

1

T1

1

T2

133

T3

425

auto[0]

auto[1]

auto[0]

auto[0]

53988

1

T1

3

T3

36

T12

1242

auto[0]

auto[1]

auto[0]

auto[1]

66649

1

T1

2

T3

7

T12

778

auto[0]

auto[1]

auto[1]

auto[0]

55075

1

T1

1

T12

1311

T55

24

auto[0]

auto[1]

auto[1]

auto[1]

65907

1

T2

208

T3

66

T10

559

auto[1]

auto[0]

auto[0]

auto[0]

148199

1

T2

2

T3

159

T8

2

auto[1]

auto[0]

auto[0]

auto[1]

150944

1

T1

2

T2

2

T3

665

auto[1]

auto[0]

auto[1]

auto[0]

13743385

1

T1

1

T2

283

T3

794

auto[1]

auto[0]

auto[1]

auto[1]

158903

1

T1

3

T2

916

T3

1536

auto[1]

auto[1]

auto[0]

auto[0]

385578

1

T3

245

T8

1

T12

7437

auto[1]

auto[1]

auto[0]

auto[1]

370918

1

T2

312

T3

336

T8

4

auto[1]

auto[1]

auto[1]

auto[0]

324291

1

T2

528

T3

1572

T10

1

auto[1]

auto[1]

auto[1]

auto[1]

343417

1

T1

2

T2

538

T3

248

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

186113

1

T1

2

T2

2

T3

440

auto[0]

auto[0]

auto[0]

auto[1]

191656

1

T1

4

T2

2

T3

665

auto[0]

auto[0]

auto[1]

auto[0]

15644511

1

T1

3

T2

283

T3

794

auto[0]

auto[0]

auto[1]

auto[1]

195740

1

T1

4

T2

1049

T3

1961

auto[0]

auto[1]

auto[0]

auto[0]

438925

1

T1

3

T3

281

T8

1

auto[0]

auto[1]

auto[0]

auto[1]

437108

1

T1

2

T2

312

T3

343

auto[0]

auto[1]

auto[1]

auto[0]

379265

1

T1

1

T2

528

T3

1572

auto[0]

auto[1]

auto[1]

auto[1]

407394

1

T1

2

T2

746

T3

314

auto[1]

auto[0]

auto[0]

auto[0]

2767

1

T1

1

T16

3

T22

1

auto[1]

auto[0]

auto[0]

auto[1]

3104

1

T16

13

T22

1

T136

24

auto[1]

auto[0]

auto[1]

auto[0]

834

1

T6

1

T136

10

T89

1

auto[1]

auto[0]

auto[1]

auto[1]

633

1

T88

2

T140

1

T137

3

auto[1]

auto[1]

auto[0]

auto[0]

641

1

T89

1

T141

104

T152

3

auto[1]

auto[1]

auto[0]

auto[1]

459

1

T136

1

T137

134

T153

1

auto[1]

auto[1]

auto[1]

auto[0]

101

1

T16

6

T140

1

T153

4

auto[1]

auto[1]

auto[1]

auto[1]

1930

1

T136

523

T34

1

T152

19

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	148199	1			T2	2		T3	159		T8	2
fifo_depth[0]	auto[0]	auto[0]	auto[1]	150944	1			T1	2		T2	2		T3	665
fifo_depth[0]	auto[0]	auto[1]	auto[0]	13743385	1			T1	1		T2	283		T3	794
fifo_depth[0]	auto[0]	auto[1]	auto[1]	158903	1			T1	3		T2	916		T3	1536
fifo_depth[0]	auto[1]	auto[0]	auto[0]	385578	1			T3	245		T8	1		T12	7437
fifo_depth[0]	auto[1]	auto[0]	auto[1]	370918	1			T2	312		T3	336		T8	4
fifo_depth[0]	auto[1]	auto[1]	auto[0]	324291	1			T2	528		T3	1572		T10	1
fifo_depth[0]	auto[1]	auto[1]	auto[1]	343417	1			T1	2		T2	538		T3	248
fifo_depth[1]	auto[0]	auto[0]	auto[0]	3754	1			T3	24		T29	9		T18	43
fifo_depth[1]	auto[0]	auto[0]	auto[1]	3493	1			T17	1		T31	146		T18	50
fifo_depth[1]	auto[0]	auto[1]	auto[0]	429781	1			T4	1330		T7	2806		T11	4940
fifo_depth[1]	auto[0]	auto[1]	auto[1]	3593	1			T2	35		T3	111		T54	8
fifo_depth[1]	auto[1]	auto[0]	auto[0]	5822	1			T3	11		T12	116		T17	2
fifo_depth[1]	auto[1]	auto[0]	auto[1]	5938	1			T3	2		T12	88		T17	3
fifo_depth[1]	auto[1]	auto[1]	auto[0]	5507	1			T12	124		T55	3		T29	9
fifo_depth[1]	auto[1]	auto[1]	auto[1]	5986	1			T2	43		T3	19		T10	52
fifo_depth[2]	auto[0]	auto[0]	auto[0]	3141	1			T3	34		T29	7		T18	37
fifo_depth[2]	auto[0]	auto[0]	auto[1]	3106	1			T31	170		T18	28		T20	2
fifo_depth[2]	auto[0]	auto[1]	auto[0]	319673	1			T4	539		T7	1259		T11	4921
fifo_depth[2]	auto[0]	auto[1]	auto[1]	3401	1			T2	33		T3	116		T54	4
fifo_depth[2]	auto[1]	auto[0]	auto[0]	5386	1			T3	11		T12	105		T19	9
fifo_depth[2]	auto[1]	auto[0]	auto[1]	5728	1			T3	3		T12	84		T17	1
fifo_depth[2]	auto[1]	auto[1]	auto[0]	5068	1			T12	109		T55	3		T29	6
fifo_depth[2]	auto[1]	auto[1]	auto[1]	5310	1			T2	37		T3	22		T10	42
fifo_depth[3]	auto[0]	auto[0]	auto[0]	2554	1			T3	31		T29	10		T18	25
fifo_depth[3]	auto[0]	auto[0]	auto[1]	2384	1			T31	153		T18	15		T20	2
fifo_depth[3]	auto[0]	auto[1]	auto[0]	252982	1			T4	217		T7	504		T11	4658
fifo_depth[3]	auto[0]	auto[1]	auto[1]	2579	1			T2	31		T3	94		T54	2
fifo_depth[3]	auto[1]	auto[0]	auto[0]	4799	1			T3	9		T12	104		T17	1
fifo_depth[3]	auto[1]	auto[0]	auto[1]	5432	1			T3	2		T12	86		T19	19
fifo_depth[3]	auto[1]	auto[1]	auto[0]	4619	1			T12	127		T55	2		T29	6
fifo_depth[3]	auto[1]	auto[1]	auto[1]	4912	1			T2	40		T3	15		T10	43
fifo_depth[4]	auto[0]	auto[0]	auto[0]	2353	1			T3	33		T29	8		T18	9
fifo_depth[4]	auto[0]	auto[0]	auto[1]	2358	1			T31	162		T18	8		T20	3
fifo_depth[4]	auto[0]	auto[1]	auto[0]	193494	1			T4	59		T7	153		T11	3940
fifo_depth[4]	auto[0]	auto[1]	auto[1]	2413	1			T2	21		T3	42		T19	28
fifo_depth[4]	auto[1]	auto[0]	auto[0]	4542	1			T3	2		T12	94		T19	11
fifo_depth[4]	auto[1]	auto[0]	auto[1]	5435	1			T12	83		T19	16		T29	16
fifo_depth[4]	auto[1]	auto[1]	auto[0]	4456	1			T12	124		T55	2		T29	6
fifo_depth[4]	auto[1]	auto[1]	auto[1]	4971	1			T2	39		T3	8		T10	49
fifo_depth[5]	auto[0]	auto[0]	auto[0]	1845	1			T3	23		T29	11		T18	2
fifo_depth[5]	auto[0]	auto[0]	auto[1]	1894	1			T31	131		T18	1		T20	2
fifo_depth[5]	auto[0]	auto[1]	auto[0]	146772	1			T4	20		T7	39		T11	3116
fifo_depth[5]	auto[0]	auto[1]	auto[1]	1811	1			T2	12		T3	26		T54	2
fifo_depth[5]	auto[1]	auto[0]	auto[0]	4289	1			T3	2		T12	119		T19	9
fifo_depth[5]	auto[1]	auto[0]	auto[1]	5013	1			T12	78		T19	17		T29	15
fifo_depth[5]	auto[1]	auto[1]	auto[0]	4243	1			T12	110		T29	7		T18	2
fifo_depth[5]	auto[1]	auto[1]	auto[1]	4411	1			T2	29		T3	2		T10	44
fifo_depth[6]	auto[0]	auto[0]	auto[0]	1729	1			T3	35		T29	13		T18	1
fifo_depth[6]	auto[0]	auto[0]	auto[1]	1974	1			T31	153		T20	4		T16	12
fifo_depth[6]	auto[0]	auto[1]	auto[0]	124820	1			T7	6		T11	2824		T15	2552
fifo_depth[6]	auto[0]	auto[1]	auto[1]	1957	1			T2	1		T3	20		T19	33
fifo_depth[6]	auto[1]	auto[0]	auto[0]	4133	1			T3	1		T12	119		T19	11
fifo_depth[6]	auto[1]	auto[0]	auto[1]	4851	1			T12	75		T19	16		T29	11
fifo_depth[6]	auto[1]	auto[1]	auto[0]	4120	1			T12	112		T55	3		T29	8
fifo_depth[6]	auto[1]	auto[1]	auto[1]	4410	1			T2	13		T10	48		T12	112
fifo_depth[7]	auto[0]	auto[0]	auto[0]	1588	1			T3	36		T29	11		T20	27
fifo_depth[7]	auto[0]	auto[0]	auto[1]	1698	1			T31	130		T20	4		T16	16
fifo_depth[7]	auto[0]	auto[1]	auto[0]	109329	1			T7	2		T11	2597		T15	2233
fifo_depth[7]	auto[0]	auto[1]	auto[1]	1632	1			T3	6		T19	23		T20	6
fifo_depth[7]	auto[1]	auto[0]	auto[0]	4052	1			T12	111		T19	15		T29	12
fifo_depth[7]	auto[1]	auto[0]	auto[1]	4742	1			T12	81		T19	18		T29	15
fifo_depth[7]	auto[1]	auto[1]	auto[0]	3994	1			T12	96		T55	1		T29	6
fifo_depth[7]	auto[1]	auto[1]	auto[1]	4264	1			T2	7		T10	43		T12	116