Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	34093139	1			T1	460		T2	14361		T3	23734
all_pins[1]	34093139	1			T1	460		T2	14361		T3	23734
all_pins[2]	34093139	1			T1	460		T2	14361		T3	23734

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	84691019	1			T1	1299		T2	30526		T3	52987
values[0x1]	17588398	1			T1	81		T2	12557		T3	18215
transitions[0x0=>0x1]	17588184	1			T1	79		T2	12557		T3	18215
transitions[0x1=>0x0]	17588194	1			T1	79		T2	12557		T3	18215

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	34041619	1			T1	438		T2	14358		T3	23727
all_pins[0]	values[0x1]	51520	1			T1	22		T2	3		T3	7
all_pins[0]	transitions[0x0=>0x1]	51477	1			T1	22		T2	3		T3	7
all_pins[0]	transitions[0x1=>0x0]	17532830	1			T1	16		T2	12554		T3	18208
all_pins[1]	values[0x0]	34089124	1			T1	417		T2	14361		T3	23734
all_pins[1]	values[0x1]	4015	1			T1	43		T5	43		T6	43
all_pins[1]	transitions[0x0=>0x1]	3867	1			T1	41		T5	42		T6	41
all_pins[1]	transitions[0x1=>0x0]	51372	1			T1	20		T2	3		T3	7
all_pins[2]	values[0x0]	16560276	1			T1	444		T2	1807		T3	5526
all_pins[2]	values[0x1]	17532863	1			T1	16		T2	12554		T3	18208
all_pins[2]	transitions[0x0=>0x1]	17532840	1			T1	16		T2	12554		T3	18208
all_pins[2]	transitions[0x1=>0x0]	3992	1			T1	43		T5	43		T6	43