Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 383 1 T34 10 T65 10 T66 4
all_values[1] 383 1 T34 10 T65 10 T66 4
all_values[2] 383 1 T34 10 T65 10 T66 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 549 1 T34 12 T65 11 T66 6
auto[1] 600 1 T34 18 T65 19 T66 6


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 414 1 T34 11 T65 10 T66 2
auto[1] 735 1 T34 19 T65 20 T66 10


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 657 1 T34 19 T65 18 T66 7
auto[1] 492 1 T34 11 T65 12 T66 5


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 70 1 T34 1 T65 2 T66 1
all_values[0] auto[0] auto[0] auto[1] 35 1 T65 1 T144 1 T75 2
all_values[0] auto[0] auto[1] auto[0] 75 1 T34 1 T65 3 T144 3
all_values[0] auto[0] auto[1] auto[1] 44 1 T34 4 T65 1 T66 2
all_values[0] auto[1] auto[0] auto[1] 82 1 T34 2 T65 1 T66 1
all_values[0] auto[1] auto[1] auto[1] 77 1 T34 2 T65 2 T144 5
all_values[1] auto[0] auto[0] auto[0] 54 1 T34 1 T144 2 T73 1
all_values[1] auto[0] auto[0] auto[1] 47 1 T34 2 T65 1 T144 1
all_values[1] auto[0] auto[1] auto[0] 54 1 T34 1 T65 1 T76 1
all_values[1] auto[0] auto[1] auto[1] 60 1 T34 2 T65 2 T66 2
all_values[1] auto[1] auto[0] auto[1] 86 1 T34 3 T65 4 T66 1
all_values[1] auto[1] auto[1] auto[1] 82 1 T34 1 T65 2 T66 1
all_values[2] auto[0] auto[0] auto[0] 80 1 T34 3 T66 1 T144 1
all_values[2] auto[0] auto[0] auto[1] 29 1 T65 2 T66 1 T144 1
all_values[2] auto[0] auto[1] auto[0] 81 1 T34 4 T65 4 T144 6
all_values[2] auto[0] auto[1] auto[1] 28 1 T65 1 T75 1 T76 2
all_values[2] auto[1] auto[0] auto[1] 66 1 T66 1 T144 1 T73 3
all_values[2] auto[1] auto[1] auto[1] 99 1 T34 3 T65 3 T66 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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