Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.47	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	2	18	90.00
Crosses	82	22	60	73.17

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	1	4	80.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	1	6	85.71	100	1	1	0
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	8	0	8	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	11	24	68.57	100	1	1	0
key_length_x_digest_size	35	11	24	68.57	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	1	4	80.00

User Defined Bins for digest_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
sha2_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_none	82	1			T2	1		T3	2		T31	1
sha2_512	19415	1			T1	1		T3	9		T10	1
sha2_384	19606	1			T1	8		T2	3		T3	8
sha2_256	11553	1			T1	5		T2	8		T3	26

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48003

1

T1

9

T2

1

T3

23

auto[1]

2653

1

T1

5

T2

11

T3

22

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2560

1

T1

10

T3

22

T12

7

auto[1]

48096

1

T1

4

T2

12

T3

23

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

2546

1

T1

6

T2

10

T3

14

disabled

48110

1

T1

8

T2

2

T3

31

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for key_length

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
key_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	961	1			T1	2		T3	8		T17	2
key_1024	694	1			T1	2		T3	8		T12	1
key_512	864	1			T1	1		T2	1		T3	2
key_384	947	1			T1	5		T2	2		T3	3
key_256	46314	1			T1	3		T2	1		T3	11
key_128	876	1			T1	1		T2	8		T3	13

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

50464

1

T1

14

T2

10

T3

39

disabled

192

1

T2

2

T3

6

T31

3

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
enabled	auto[0]	auto[0]	557	1			T1	3		T3	9		T12	5
enabled	auto[0]	auto[1]	604	1			T1	2		T3	2		T12	2
enabled	auto[1]	auto[0]	751	1			T1	1		T3	2		T10	1
enabled	auto[1]	auto[1]	634	1			T2	10		T3	1		T10	1
disabled	auto[0]	auto[0]	707	1			T1	3		T3	11		T17	2
disabled	auto[0]	auto[1]	692	1			T1	2		T17	2		T19	1
disabled	auto[1]	auto[0]	45988	1			T1	2		T2	1		T3	1
disabled	auto[1]	auto[1]	723	1			T1	1		T2	1		T3	19

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

2438

1

T1

6

T2

9

T3

10

enabled

disabled

108

1

T2

1

T3

4

T31

1

disabled

disabled

84

1

T2

1

T3

2

T31

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

48026

1

T1

8

T2

1

T3

29

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	11	24	68.57	11
Automatically Generated Cross Bins	34	11	23	67.65	11
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid]	--	--	6

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_none	25	1			T3	2		T122	2		T123	1
key_none	sha2_512	305	1			T17	1		T19	2		T29	1
key_none	sha2_384	312	1			T1	1		T3	6		T17	1
key_none	sha2_256	319	1			T1	1		T19	3		T31	6
key_1024	sha2_none	11	1			T124	1		T125	1		T126	1
key_1024	sha2_512	268	1			T3	8		T19	1		T31	2
key_1024	sha2_384	281	1			T1	1		T12	1		T17	1
key_512	sha2_none	10	1			T122	1		T127	1		T128	1
key_512	sha2_512	286	1			T3	1		T18	5		T114	1
key_512	sha2_384	299	1			T1	1		T2	1		T19	1
key_512	sha2_256	269	1			T3	1		T17	2		T19	1
key_384	sha2_none	11	1			T122	1		T126	1		T128	1
key_384	sha2_512	267	1			T1	1		T12	1		T19	1
key_384	sha2_384	319	1			T1	3		T2	2		T3	1
key_384	sha2_256	350	1			T1	1		T3	2		T12	2
key_256	sha2_none	12	1			T2	1		T122	1		T123	1
key_256	sha2_512	18053	1			T10	1		T12	2		T17	1
key_256	sha2_384	18080	1			T1	1		T7	386		T8	1
key_256	sha2_256	10169	1			T1	2		T3	11		T4	194
key_128	sha2_none	13	1			T31	1		T124	1		T35	2
key_128	sha2_512	236	1			T12	1		T17	1		T19	2
key_128	sha2_384	315	1			T1	1		T3	1		T12	2
key_128	sha2_256	312	1			T2	8		T3	12		T19	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

134

1

T1

1

T29

1

T18

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	11	24	68.57	11

Automatically Generated Cross Bins for key_length_x_digest_size

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid]	--	--	6

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_none	25	1			T3	2		T122	2		T123	1
key_none	sha2_512	305	1			T17	1		T19	2		T29	1
key_none	sha2_384	312	1			T1	1		T3	6		T17	1
key_none	sha2_256	319	1			T1	1		T19	3		T31	6
key_1024	sha2_none	11	1			T124	1		T125	1		T126	1
key_1024	sha2_512	268	1			T3	8		T19	1		T31	2
key_1024	sha2_384	281	1			T1	1		T12	1		T17	1
key_1024	sha2_256	134	1			T1	1		T29	1		T18	1
key_512	sha2_none	10	1			T122	1		T127	1		T128	1
key_512	sha2_512	286	1			T3	1		T18	5		T114	1
key_512	sha2_384	299	1			T1	1		T2	1		T19	1
key_512	sha2_256	269	1			T3	1		T17	2		T19	1
key_384	sha2_none	11	1			T122	1		T126	1		T128	1
key_384	sha2_512	267	1			T1	1		T12	1		T19	1
key_384	sha2_384	319	1			T1	3		T2	2		T3	1
key_384	sha2_256	350	1			T1	1		T3	2		T12	2
key_256	sha2_none	12	1			T2	1		T122	1		T123	1
key_256	sha2_512	18053	1			T10	1		T12	2		T17	1
key_256	sha2_384	18080	1			T1	1		T7	386		T8	1
key_256	sha2_256	10169	1			T1	2		T3	11		T4	194
key_128	sha2_none	13	1			T31	1		T124	1		T35	2
key_128	sha2_512	236	1			T12	1		T17	1		T19	2
key_128	sha2_384	315	1			T1	1		T3	1		T12	2
key_128	sha2_256	312	1			T2	8		T3	12		T19	2