Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.58	95.85	92.94	100.00	74.36	91.89	99.49	93.58

Total test records in report: 768

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html

T754	/workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3861429704			Jun 21 06:00:38 PM PDT 24	Jun 21 06:00:40 PM PDT 24	41411520 ps
T755	/workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3102693542			Jun 21 06:00:53 PM PDT 24	Jun 21 06:00:56 PM PDT 24	27931708 ps
T102	/workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.4152721699			Jun 21 06:00:22 PM PDT 24	Jun 21 06:00:26 PM PDT 24	71712982 ps
T756	/workspace/coverage/cover_reg_top/11.hmac_tl_errors.3830761080			Jun 21 06:00:45 PM PDT 24	Jun 21 06:00:48 PM PDT 24	319055531 ps
T757	/workspace/coverage/cover_reg_top/40.hmac_intr_test.1657597170			Jun 21 06:01:01 PM PDT 24	Jun 21 06:01:04 PM PDT 24	37176582 ps
T758	/workspace/coverage/cover_reg_top/49.hmac_intr_test.1832518208			Jun 21 06:01:02 PM PDT 24	Jun 21 06:01:06 PM PDT 24	12189786 ps
T759	/workspace/coverage/cover_reg_top/9.hmac_tl_errors.2174613048			Jun 21 06:00:43 PM PDT 24	Jun 21 06:00:47 PM PDT 24	109329202 ps
T760	/workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3228345794			Jun 21 06:00:36 PM PDT 24	Jun 21 06:00:39 PM PDT 24	83201725 ps
T761	/workspace/coverage/cover_reg_top/7.hmac_tl_errors.2841353829			Jun 21 06:00:36 PM PDT 24	Jun 21 06:00:40 PM PDT 24	415565857 ps
T762	/workspace/coverage/cover_reg_top/21.hmac_intr_test.3600659675			Jun 21 06:00:51 PM PDT 24	Jun 21 06:00:53 PM PDT 24	11621055 ps
T763	/workspace/coverage/cover_reg_top/0.hmac_intr_test.2432831319			Jun 21 06:00:22 PM PDT 24	Jun 21 06:00:25 PM PDT 24	32748143 ps
T104	/workspace/coverage/cover_reg_top/19.hmac_csr_rw.2334356215			Jun 21 06:00:52 PM PDT 24	Jun 21 06:00:54 PM PDT 24	22373414 ps
T764	/workspace/coverage/cover_reg_top/47.hmac_intr_test.3629346144			Jun 21 06:01:00 PM PDT 24	Jun 21 06:01:02 PM PDT 24	47106114 ps
T765	/workspace/coverage/cover_reg_top/13.hmac_intr_test.2863276208			Jun 21 06:00:51 PM PDT 24	Jun 21 06:00:53 PM PDT 24	33148672 ps
T103	/workspace/coverage/cover_reg_top/3.hmac_csr_rw.2675392621			Jun 21 06:00:29 PM PDT 24	Jun 21 06:00:31 PM PDT 24	17435251 ps
T766	/workspace/coverage/cover_reg_top/41.hmac_intr_test.4166309092			Jun 21 06:01:01 PM PDT 24	Jun 21 06:01:03 PM PDT 24	16646404 ps
T767	/workspace/coverage/cover_reg_top/11.hmac_intr_test.2796779116			Jun 21 06:00:44 PM PDT 24	Jun 21 06:00:46 PM PDT 24	32993523 ps
T768	/workspace/coverage/cover_reg_top/33.hmac_intr_test.1071964592			Jun 21 06:00:59 PM PDT 24	Jun 21 06:01:01 PM PDT 24	75399709 ps

Test location	/workspace/coverage/default/22.hmac_back_pressure.4233938313
Short name	T1
Test name
Test status
Simulation time	1715954555 ps
CPU time	22.42 seconds
Started	Jun 21 06:02:05 PM PDT 24
Finished	Jun 21 06:02:29 PM PDT 24
Peak memory	200036 kb
Host	smart-155fea48-3ad0-485a-8802-cea55c76f65e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4233938313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.4233938313
Directory	/workspace/22.hmac_back_pressure/latest

Test location	/workspace/coverage/default/5.hmac_error.3234402809
Short name	T3
Test name
Test status
Simulation time	4339639436 ps
CPU time	124.59 seconds
Started	Jun 21 06:01:14 PM PDT 24
Finished	Jun 21 06:03:20 PM PDT 24
Peak memory	200136 kb
Host	smart-4ff32fad-e1db-497e-b9e7-f2637bc9d522
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234402809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3234402809
Directory	/workspace/5.hmac_error/latest

Test location	/workspace/coverage/cover_reg_top/19.hmac_tl_errors.158109574
Short name	T56
Test name
Test status
Simulation time	69872419 ps
CPU time	3.38 seconds
Started	Jun 21 06:00:56 PM PDT 24
Finished	Jun 21 06:01:01 PM PDT 24
Peak memory	199676 kb
Host	smart-4a3462c2-3ac0-4926-992f-e4c40104a3aa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158109574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.158109574
Directory	/workspace/19.hmac_tl_errors/latest

Test location	/workspace/coverage/default/28.hmac_stress_all.582594269
Short name	T34
Test name
Test status
Simulation time	103121657351 ps
CPU time	711.72 seconds
Started	Jun 21 06:02:40 PM PDT 24
Finished	Jun 21 06:14:32 PM PDT 24
Peak memory	694748 kb
Host	smart-2c19d7d2-dbb4-4002-b010-38497f47ad0b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582594269 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.582594269
Directory	/workspace/28.hmac_stress_all/latest

Test location	/workspace/coverage/default/33.hmac_long_msg.3482868961
Short name	T18
Test name
Test status
Simulation time	18392530136 ps
CPU time	112.41 seconds
Started	Jun 21 06:03:16 PM PDT 24
Finished	Jun 21 06:05:10 PM PDT 24
Peak memory	208296 kb
Host	smart-7f5fd668-5283-4b37-95d6-20727d43716b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3482868961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3482868961
Directory	/workspace/33.hmac_long_msg/latest

Test location	/workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.15574076
Short name	T39
Test name
Test status
Simulation time	323995644 ps
CPU time	4.46 seconds
Started	Jun 21 06:00:50 PM PDT 24
Finished	Jun 21 06:00:56 PM PDT 24
Peak memory	199700 kb
Host	smart-59ced51e-0314-45cb-aee7-c3738f02c255
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15574076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.15574076
Directory	/workspace/9.hmac_tl_intg_err/latest

Test location	/workspace/coverage/default/49.hmac_wipe_secret.352584338
Short name	T19
Test name
Test status
Simulation time	5091564806 ps
CPU time	67.32 seconds
Started	Jun 21 06:04:49 PM PDT 24
Finished	Jun 21 06:05:57 PM PDT 24
Peak memory	200124 kb
Host	smart-74cc5236-e0e6-4da9-93fd-6b7f1196e088
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=352584338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.352584338
Directory	/workspace/49.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/30.hmac_alert_test.2465215392
Short name	T9
Test name
Test status
Simulation time	27057804 ps
CPU time	0.58 seconds
Started	Jun 21 06:02:51 PM PDT 24
Finished	Jun 21 06:02:52 PM PDT 24
Peak memory	196732 kb
Host	smart-8b150d11-1087-4d4d-ba01-3846dd347bae
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465215392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2465215392
Directory	/workspace/30.hmac_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/0.hmac_csr_rw.3723977354
Short name	T90
Test name
Test status
Simulation time	20227929 ps
CPU time	0.92 seconds
Started	Jun 21 06:00:22 PM PDT 24
Finished	Jun 21 06:00:26 PM PDT 24
Peak memory	199460 kb
Host	smart-bdd0415d-002b-42ed-90b2-0341cfe1d7b6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723977354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3723977354
Directory	/workspace/0.hmac_csr_rw/latest

Test location	/workspace/coverage/default/19.hmac_burst_wr.641533942
Short name	T46
Test name
Test status
Simulation time	1390790960 ps
CPU time	75.16 seconds
Started	Jun 21 06:01:50 PM PDT 24
Finished	Jun 21 06:03:06 PM PDT 24
Peak memory	200076 kb
Host	smart-96062625-1bed-43fa-9a2a-a0d0ea7fc062
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=641533942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.641533942
Directory	/workspace/19.hmac_burst_wr/latest

Test location	/workspace/coverage/default/42.hmac_error.4247378828
Short name	T122
Test name
Test status
Simulation time	3537005439 ps
CPU time	165.16 seconds
Started	Jun 21 06:04:02 PM PDT 24
Finished	Jun 21 06:06:48 PM PDT 24
Peak memory	199988 kb
Host	smart-6485915a-ab3a-47c0-afdc-93f87458a2a9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247378828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.4247378828
Directory	/workspace/42.hmac_error/latest

Test location	/workspace/coverage/cover_reg_top/37.hmac_intr_test.3842243435
Short name	T75
Test name
Test status
Simulation time	44880284 ps
CPU time	0.6 seconds
Started	Jun 21 06:00:59 PM PDT 24
Finished	Jun 21 06:01:00 PM PDT 24
Peak memory	194448 kb
Host	smart-8e9fb5e0-352b-4b46-9e35-092e28bee103
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842243435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3842243435
Directory	/workspace/37.hmac_intr_test/latest

Test location	/workspace/coverage/default/0.hmac_sec_cm.3835081096
Short name	T43
Test name
Test status
Simulation time	85215356 ps
CPU time	1.03 seconds
Started	Jun 21 06:01:04 PM PDT 24
Finished	Jun 21 06:01:08 PM PDT 24
Peak memory	219220 kb
Host	smart-d9bf17ec-7044-445c-8e14-e0ee8484c16e
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835081096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3835081096
Directory	/workspace/0.hmac_sec_cm/latest

Test location	/workspace/coverage/default/23.hmac_stress_all.2502671420
Short name	T35
Test name
Test status
Simulation time	265504547295 ps
CPU time	1589.55 seconds
Started	Jun 21 06:02:16 PM PDT 24
Finished	Jun 21 06:28:47 PM PDT 24
Peak memory	734932 kb
Host	smart-0a1a547f-025d-4a65-bc27-3923cdb06eb2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502671420 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2502671420
Directory	/workspace/23.hmac_stress_all/latest

Test location	/workspace/coverage/default/31.hmac_burst_wr.936254092
Short name	T16
Test name
Test status
Simulation time	469878795 ps
CPU time	28.86 seconds
Started	Jun 21 06:03:02 PM PDT 24
Finished	Jun 21 06:03:32 PM PDT 24
Peak memory	200056 kb
Host	smart-d80d7c7a-632c-463e-904b-8d582cec90f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=936254092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.936254092
Directory	/workspace/31.hmac_burst_wr/latest

Test location	/workspace/coverage/default/6.hmac_datapath_stress.4020822153
Short name	T130
Test name
Test status
Simulation time	8048756393 ps
CPU time	500.42 seconds
Started	Jun 21 06:01:16 PM PDT 24
Finished	Jun 21 06:09:37 PM PDT 24
Peak memory	698580 kb
Host	smart-624dd5d2-fe49-4ff5-a264-6eb210e5c2b7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4020822153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.4020822153
Directory	/workspace/6.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/27.hmac_long_msg.2106471915
Short name	T138
Test name
Test status
Simulation time	1141618516 ps
CPU time	11.16 seconds
Started	Jun 21 06:02:31 PM PDT 24
Finished	Jun 21 06:02:43 PM PDT 24
Peak memory	200060 kb
Host	smart-ef1b537c-2e29-44ca-9a2a-256e0babae3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2106471915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2106471915
Directory	/workspace/27.hmac_long_msg/latest

Test location	/workspace/coverage/default/16.hmac_test_sha256_vectors.344958436
Short name	T157
Test name
Test status
Simulation time	115616548851 ps
CPU time	519.39 seconds
Started	Jun 21 06:01:45 PM PDT 24
Finished	Jun 21 06:10:27 PM PDT 24
Peak memory	200112 kb
Host	smart-6abb3dda-4ad7-4c60-b898-b10057650278
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=344958436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha256_vectors.344958436
Directory	/workspace/16.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.155771324
Short name	T733
Test name
Test status
Simulation time	5169486613 ps
CPU time	55.34 seconds
Started	Jun 21 06:00:44 PM PDT 24
Finished	Jun 21 06:01:40 PM PDT 24
Peak memory	216120 kb
Host	smart-148b2a2a-4c4e-4862-98fd-d5d1b9d90e81
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155771324 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.155771324
Directory	/workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1866244585
Short name	T148
Test name
Test status
Simulation time	274912119 ps
CPU time	1.73 seconds
Started	Jun 21 06:00:44 PM PDT 24
Finished	Jun 21 06:00:47 PM PDT 24
Peak memory	199576 kb
Host	smart-1207bd37-f55e-47e7-9035-e295c1271baa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866244585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1866244585
Directory	/workspace/11.hmac_tl_intg_err/latest

Test location	/workspace/coverage/default/16.hmac_error.1897006820
Short name	T585
Test name
Test status
Simulation time	25004061090 ps
CPU time	85.35 seconds
Started	Jun 21 06:01:44 PM PDT 24
Finished	Jun 21 06:03:10 PM PDT 24
Peak memory	200108 kb
Host	smart-f7d260a3-cbbc-410b-92c0-5d7af9372289
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897006820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1897006820
Directory	/workspace/16.hmac_error/latest

Test location	/workspace/coverage/default/34.hmac_datapath_stress.1656864460
Short name	T135
Test name
Test status
Simulation time	10671968128 ps
CPU time	621.76 seconds
Started	Jun 21 06:03:17 PM PDT 24
Finished	Jun 21 06:13:41 PM PDT 24
Peak memory	719652 kb
Host	smart-917560e0-1506-4a65-b6ee-5f63dce54e9e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1656864460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1656864460
Directory	/workspace/34.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/7.hmac_long_msg.730720296
Short name	T133
Test name
Test status
Simulation time	4947689316 ps
CPU time	76.52 seconds
Started	Jun 21 06:01:14 PM PDT 24
Finished	Jun 21 06:02:32 PM PDT 24
Peak memory	208340 kb
Host	smart-21e31973-52cd-43c9-8b54-5a66ce60f60a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=730720296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.730720296
Directory	/workspace/7.hmac_long_msg/latest

Test location	/workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2490247817
Short name	T147
Test name
Test status
Simulation time	129586721 ps
CPU time	4.04 seconds
Started	Jun 21 06:00:32 PM PDT 24
Finished	Jun 21 06:00:37 PM PDT 24
Peak memory	199652 kb
Host	smart-e65acc4d-7b16-46a3-9999-565901a5d80e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490247817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2490247817
Directory	/workspace/1.hmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2059106853
Short name	T37
Test name
Test status
Simulation time	501296716 ps
CPU time	2.98 seconds
Started	Jun 21 06:00:55 PM PDT 24
Finished	Jun 21 06:01:00 PM PDT 24
Peak memory	199652 kb
Host	smart-872a84bb-7982-424c-850c-de0057fe9ef5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059106853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2059106853
Directory	/workspace/14.hmac_tl_intg_err/latest

Test location	/workspace/coverage/default/12.hmac_long_msg.3101476555
Short name	T238
Test name
Test status
Simulation time	3548323676 ps
CPU time	72.91 seconds
Started	Jun 21 06:01:42 PM PDT 24
Finished	Jun 21 06:02:56 PM PDT 24
Peak memory	200024 kb
Host	smart-4f16724a-319f-4b59-aac6-495e16d8e8ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3101476555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3101476555
Directory	/workspace/12.hmac_long_msg/latest

Test location	/workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.369488286
Short name	T661
Test name
Test status
Simulation time	116456630 ps
CPU time	3.15 seconds
Started	Jun 21 06:00:22 PM PDT 24
Finished	Jun 21 06:00:28 PM PDT 24
Peak memory	199640 kb
Host	smart-cb73a052-6869-4384-bbf4-a9268876b7fa
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369488286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.369488286
Directory	/workspace/0.hmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3056329543
Short name	T716
Test name
Test status
Simulation time	111242148 ps
CPU time	5.31 seconds
Started	Jun 21 06:00:21 PM PDT 24
Finished	Jun 21 06:00:29 PM PDT 24
Peak memory	199580 kb
Host	smart-563b25ae-7d91-4486-be0b-71686ee04900
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056329543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3056329543
Directory	/workspace/0.hmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.4152721699
Short name	T102
Test name
Test status
Simulation time	71712982 ps
CPU time	1 seconds
Started	Jun 21 06:00:22 PM PDT 24
Finished	Jun 21 06:00:26 PM PDT 24
Peak memory	199468 kb
Host	smart-e004c642-1699-47a3-a37a-7285957920c3
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152721699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.4152721699
Directory	/workspace/0.hmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1818338732
Short name	T698
Test name
Test status
Simulation time	43550849 ps
CPU time	2.63 seconds
Started	Jun 21 06:00:28 PM PDT 24
Finished	Jun 21 06:00:32 PM PDT 24
Peak memory	199740 kb
Host	smart-0bf4e2de-13d4-4156-a524-79bd0a75b5b6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818338732 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1818338732
Directory	/workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.hmac_intr_test.2432831319
Short name	T763
Test name
Test status
Simulation time	32748143 ps
CPU time	0.57 seconds
Started	Jun 21 06:00:22 PM PDT 24
Finished	Jun 21 06:00:25 PM PDT 24
Peak memory	194376 kb
Host	smart-1f4811e2-c6c1-46f0-9ef8-a51b5e9e9521
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432831319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2432831319
Directory	/workspace/0.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1023205249
Short name	T673
Test name
Test status
Simulation time	44904577 ps
CPU time	2.21 seconds
Started	Jun 21 06:00:23 PM PDT 24
Finished	Jun 21 06:00:28 PM PDT 24
Peak memory	199616 kb
Host	smart-b2dc4b05-d97d-4c88-875a-b5b4833a46d7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023205249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr _outstanding.1023205249
Directory	/workspace/0.hmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.hmac_tl_errors.3783523613
Short name	T734
Test name
Test status
Simulation time	104262877 ps
CPU time	1.92 seconds
Started	Jun 21 06:00:22 PM PDT 24
Finished	Jun 21 06:00:27 PM PDT 24
Peak memory	199620 kb
Host	smart-9f1530c0-d9d2-419e-8e00-38fbb7d4250c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783523613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.3783523613
Directory	/workspace/0.hmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.517615721
Short name	T725
Test name
Test status
Simulation time	316908709 ps
CPU time	1.77 seconds
Started	Jun 21 06:00:21 PM PDT 24
Finished	Jun 21 06:00:24 PM PDT 24
Peak memory	199632 kb
Host	smart-919d60ad-4dea-48ae-8fc2-ef2142c05504
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517615721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.517615721
Directory	/workspace/0.hmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.4285335208
Short name	T675
Test name
Test status
Simulation time	371244816 ps
CPU time	3.26 seconds
Started	Jun 21 06:00:27 PM PDT 24
Finished	Jun 21 06:00:31 PM PDT 24
Peak memory	198360 kb
Host	smart-3f91f1d9-1ae1-4f3c-84a8-0fbd2e4e4856
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285335208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.4285335208
Directory	/workspace/1.hmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.342842605
Short name	T683
Test name
Test status
Simulation time	3348251593 ps
CPU time	10.59 seconds
Started	Jun 21 06:00:30 PM PDT 24
Finished	Jun 21 06:00:42 PM PDT 24
Peak memory	199032 kb
Host	smart-ec3a8bf4-f659-4f6d-8b7c-dda9b2dc2853
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342842605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.342842605
Directory	/workspace/1.hmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3668926358
Short name	T688
Test name
Test status
Simulation time	60501476 ps
CPU time	0.9 seconds
Started	Jun 21 06:00:29 PM PDT 24
Finished	Jun 21 06:00:31 PM PDT 24
Peak memory	199012 kb
Host	smart-fdc462d3-ee73-4dda-94b9-28e092771bfd
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668926358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3668926358
Directory	/workspace/1.hmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2245508161
Short name	T58
Test name
Test status
Simulation time	211062557 ps
CPU time	2.4 seconds
Started	Jun 21 06:00:32 PM PDT 24
Finished	Jun 21 06:00:35 PM PDT 24
Peak memory	199752 kb
Host	smart-ef473c39-0a73-405c-8fdb-e26a3ee7bfcc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245508161 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2245508161
Directory	/workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.hmac_csr_rw.1096336663
Short name	T748
Test name
Test status
Simulation time	15318138 ps
CPU time	0.75 seconds
Started	Jun 21 06:00:33 PM PDT 24
Finished	Jun 21 06:00:35 PM PDT 24
Peak memory	197332 kb
Host	smart-9d5f2be7-2680-45f7-866c-677c66f021a5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096336663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1096336663
Directory	/workspace/1.hmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.hmac_intr_test.3655762712
Short name	T144
Test name
Test status
Simulation time	42771601 ps
CPU time	0.66 seconds
Started	Jun 21 06:00:30 PM PDT 24
Finished	Jun 21 06:00:32 PM PDT 24
Peak memory	194472 kb
Host	smart-bfb2d853-e772-4cbe-baed-9c8bc2f22eed
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655762712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.3655762712
Directory	/workspace/1.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.4054287011
Short name	T721
Test name
Test status
Simulation time	116807057 ps
CPU time	2.39 seconds
Started	Jun 21 06:00:27 PM PDT 24
Finished	Jun 21 06:00:30 PM PDT 24
Peak memory	199632 kb
Host	smart-95e6ce67-ad4d-4c03-84db-2beafddaf4d7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054287011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr _outstanding.4054287011
Directory	/workspace/1.hmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.hmac_tl_errors.456293701
Short name	T750
Test name
Test status
Simulation time	544133644 ps
CPU time	2.33 seconds
Started	Jun 21 06:00:29 PM PDT 24
Finished	Jun 21 06:00:32 PM PDT 24
Peak memory	199604 kb
Host	smart-cb80995b-e9f1-462a-addf-f19eadbc716a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456293701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.456293701
Directory	/workspace/1.hmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3244006426
Short name	T726
Test name
Test status
Simulation time	37203561 ps
CPU time	2.47 seconds
Started	Jun 21 06:00:44 PM PDT 24
Finished	Jun 21 06:00:47 PM PDT 24
Peak memory	199740 kb
Host	smart-3c0f909d-1b10-4710-a87e-2dc7201292d2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244006426 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3244006426
Directory	/workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.hmac_csr_rw.3501677719
Short name	T93
Test name
Test status
Simulation time	26333807 ps
CPU time	0.84 seconds
Started	Jun 21 06:00:45 PM PDT 24
Finished	Jun 21 06:00:47 PM PDT 24
Peak memory	199268 kb
Host	smart-1b07b123-fa94-4090-bedd-b6adeff61066
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501677719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3501677719
Directory	/workspace/10.hmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.hmac_intr_test.355621401
Short name	T690
Test name
Test status
Simulation time	38399023 ps
CPU time	0.59 seconds
Started	Jun 21 06:00:50 PM PDT 24
Finished	Jun 21 06:00:52 PM PDT 24
Peak memory	194380 kb
Host	smart-bcd3d58b-8ef1-458e-850f-679d69d879d5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355621401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.355621401
Directory	/workspace/10.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.641579801
Short name	T741
Test name
Test status
Simulation time	83918478 ps
CPU time	1.12 seconds
Started	Jun 21 06:00:50 PM PDT 24
Finished	Jun 21 06:00:52 PM PDT 24
Peak memory	198108 kb
Host	smart-1f80ab9d-253c-4e12-b385-f70f33b445c1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641579801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr _outstanding.641579801
Directory	/workspace/10.hmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.hmac_tl_errors.3697011254
Short name	T742
Test name
Test status
Simulation time	99242418 ps
CPU time	2.76 seconds
Started	Jun 21 06:00:50 PM PDT 24
Finished	Jun 21 06:00:54 PM PDT 24
Peak memory	199624 kb
Host	smart-a97c4a44-4b76-4e84-bf24-3c3c87ff74da
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697011254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3697011254
Directory	/workspace/10.hmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1266769202
Short name	T149
Test name
Test status
Simulation time	173456156 ps
CPU time	1.82 seconds
Started	Jun 21 06:00:45 PM PDT 24
Finished	Jun 21 06:00:48 PM PDT 24
Peak memory	199636 kb
Host	smart-5a5c1cfd-2a5b-4078-a128-0405b046f4af
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266769202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1266769202
Directory	/workspace/10.hmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.hmac_csr_rw.4132275621
Short name	T696
Test name
Test status
Simulation time	28769030 ps
CPU time	0.84 seconds
Started	Jun 21 06:00:45 PM PDT 24
Finished	Jun 21 06:00:47 PM PDT 24
Peak memory	198792 kb
Host	smart-70268905-617e-4787-8cbb-ffef1536ecc2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132275621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.4132275621
Directory	/workspace/11.hmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.hmac_intr_test.2796779116
Short name	T767
Test name
Test status
Simulation time	32993523 ps
CPU time	0.67 seconds
Started	Jun 21 06:00:44 PM PDT 24
Finished	Jun 21 06:00:46 PM PDT 24
Peak memory	194456 kb
Host	smart-2e579b3e-c99f-46e1-9d3f-624fb46ab5bf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796779116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2796779116
Directory	/workspace/11.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3854743605
Short name	T705
Test name
Test status
Simulation time	84556688 ps
CPU time	1.22 seconds
Started	Jun 21 06:00:47 PM PDT 24
Finished	Jun 21 06:00:49 PM PDT 24
Peak memory	198112 kb
Host	smart-d040ca7d-aad4-4815-9b5b-8743de409be0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854743605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs r_outstanding.3854743605
Directory	/workspace/11.hmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.hmac_tl_errors.3830761080
Short name	T756
Test name
Test status
Simulation time	319055531 ps
CPU time	1.82 seconds
Started	Jun 21 06:00:45 PM PDT 24
Finished	Jun 21 06:00:48 PM PDT 24
Peak memory	199604 kb
Host	smart-a6f150a3-07b4-41e6-93bd-3f18ee0e96a1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830761080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3830761080
Directory	/workspace/11.hmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.20679898
Short name	T69
Test name
Test status
Simulation time	260355903 ps
CPU time	1.3 seconds
Started	Jun 21 06:00:50 PM PDT 24
Finished	Jun 21 06:00:52 PM PDT 24
Peak memory	199508 kb
Host	smart-acb48ae6-f86b-4009-9565-ef84ab16914f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20679898 -assert nopostproc +UVM_TESTNAME=h mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.20679898
Directory	/workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.hmac_csr_rw.4269418774
Short name	T665
Test name
Test status
Simulation time	107869142 ps
CPU time	0.99 seconds
Started	Jun 21 06:00:45 PM PDT 24
Finished	Jun 21 06:00:47 PM PDT 24
Peak memory	199224 kb
Host	smart-c57856e6-9765-44c9-8c6a-fa3c4ff0120e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269418774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.4269418774
Directory	/workspace/12.hmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.hmac_intr_test.424346283
Short name	T702
Test name
Test status
Simulation time	48122557 ps
CPU time	0.65 seconds
Started	Jun 21 06:00:44 PM PDT 24
Finished	Jun 21 06:00:45 PM PDT 24
Peak memory	194460 kb
Host	smart-9a181b9d-e5fc-4851-966a-22274ac7e017
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424346283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.424346283
Directory	/workspace/12.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3217115978
Short name	T687
Test name
Test status
Simulation time	117488763 ps
CPU time	2.33 seconds
Started	Jun 21 06:00:50 PM PDT 24
Finished	Jun 21 06:00:54 PM PDT 24
Peak memory	199656 kb
Host	smart-ed5dc697-ee1f-40e4-96c0-fed4e734131a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217115978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs r_outstanding.3217115978
Directory	/workspace/12.hmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.hmac_tl_errors.2742017041
Short name	T727
Test name
Test status
Simulation time	1116530593 ps
CPU time	1.42 seconds
Started	Jun 21 06:00:45 PM PDT 24
Finished	Jun 21 06:00:47 PM PDT 24
Peak memory	199604 kb
Host	smart-6cbe1e0b-0051-4313-b095-9b575e91cb28
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742017041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2742017041
Directory	/workspace/12.hmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1689852534
Short name	T38
Test name
Test status
Simulation time	487273092 ps
CPU time	3.82 seconds
Started	Jun 21 06:00:43 PM PDT 24
Finished	Jun 21 06:00:48 PM PDT 24
Peak memory	199680 kb
Host	smart-cab046db-1801-4461-947d-c5f4c643e966
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689852534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1689852534
Directory	/workspace/12.hmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1335949592
Short name	T746
Test name
Test status
Simulation time	149606797 ps
CPU time	1.18 seconds
Started	Jun 21 06:00:54 PM PDT 24
Finished	Jun 21 06:00:57 PM PDT 24
Peak memory	199428 kb
Host	smart-4c769b8b-1514-4b7d-aeec-0e7ba8c1912e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335949592 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1335949592
Directory	/workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.hmac_csr_rw.1152544954
Short name	T95
Test name
Test status
Simulation time	14352660 ps
CPU time	0.79 seconds
Started	Jun 21 06:00:56 PM PDT 24
Finished	Jun 21 06:00:59 PM PDT 24
Peak memory	198744 kb
Host	smart-01a776d3-f844-4a53-a21a-780c721ad23e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152544954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1152544954
Directory	/workspace/13.hmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.hmac_intr_test.2863276208
Short name	T765
Test name
Test status
Simulation time	33148672 ps
CPU time	0.6 seconds
Started	Jun 21 06:00:51 PM PDT 24
Finished	Jun 21 06:00:53 PM PDT 24
Peak memory	194452 kb
Host	smart-0f24f0fa-eb5c-41ff-8bf1-febc359a5555
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863276208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2863276208
Directory	/workspace/13.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.745897459
Short name	T107
Test name
Test status
Simulation time	159867007 ps
CPU time	2.17 seconds
Started	Jun 21 06:00:53 PM PDT 24
Finished	Jun 21 06:00:56 PM PDT 24
Peak memory	199660 kb
Host	smart-c02e9c54-2c46-4229-96f1-d565dbb7db1a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745897459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr _outstanding.745897459
Directory	/workspace/13.hmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.hmac_tl_errors.2763506648
Short name	T740
Test name
Test status
Simulation time	31256114 ps
CPU time	1.68 seconds
Started	Jun 21 06:00:47 PM PDT 24
Finished	Jun 21 06:00:50 PM PDT 24
Peak memory	199688 kb
Host	smart-456b991a-91d4-487b-89b9-54180e0d3fdf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763506648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2763506648
Directory	/workspace/13.hmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.109933523
Short name	T747
Test name
Test status
Simulation time	1231927611 ps
CPU time	3.14 seconds
Started	Jun 21 06:00:49 PM PDT 24
Finished	Jun 21 06:00:53 PM PDT 24
Peak memory	199688 kb
Host	smart-6414bef5-767f-4c8c-aa30-00c026f09364
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109933523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.109933523
Directory	/workspace/13.hmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3723895117
Short name	T70
Test name
Test status
Simulation time	143659483 ps
CPU time	2.44 seconds
Started	Jun 21 06:00:54 PM PDT 24
Finished	Jun 21 06:00:58 PM PDT 24
Peak memory	199660 kb
Host	smart-c80352f8-9e50-4248-8533-d8d9ba31d407
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723895117 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.3723895117
Directory	/workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.hmac_csr_rw.3407495168
Short name	T738
Test name
Test status
Simulation time	41495269 ps
CPU time	0.68 seconds
Started	Jun 21 06:00:56 PM PDT 24
Finished	Jun 21 06:00:59 PM PDT 24
Peak memory	197532 kb
Host	smart-0f42a352-3e6f-451f-9319-c052a0d5932f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407495168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3407495168
Directory	/workspace/14.hmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.hmac_intr_test.2365985172
Short name	T719
Test name
Test status
Simulation time	24180414 ps
CPU time	0.6 seconds
Started	Jun 21 06:00:56 PM PDT 24
Finished	Jun 21 06:00:59 PM PDT 24
Peak memory	194396 kb
Host	smart-f4df7025-e42a-483b-a77b-ca405452192f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365985172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2365985172
Directory	/workspace/14.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3102693542
Short name	T755
Test name
Test status
Simulation time	27931708 ps
CPU time	1.23 seconds
Started	Jun 21 06:00:53 PM PDT 24
Finished	Jun 21 06:00:56 PM PDT 24
Peak memory	199400 kb
Host	smart-c702a769-b62c-4197-80ea-df05326b9e89
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102693542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs r_outstanding.3102693542
Directory	/workspace/14.hmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.hmac_tl_errors.1102103738
Short name	T752
Test name
Test status
Simulation time	223375975 ps
CPU time	3.14 seconds
Started	Jun 21 06:00:50 PM PDT 24
Finished	Jun 21 06:00:55 PM PDT 24
Peak memory	199544 kb
Host	smart-84457455-3a11-41e0-9d1c-3f7aed216f9d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102103738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1102103738
Directory	/workspace/14.hmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.357350674
Short name	T729
Test name
Test status
Simulation time	36516634 ps
CPU time	2.38 seconds
Started	Jun 21 06:00:53 PM PDT 24
Finished	Jun 21 06:00:57 PM PDT 24
Peak memory	199680 kb
Host	smart-64bd3b3b-6267-47f6-949f-9b42b6d1bed0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357350674 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.357350674
Directory	/workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.hmac_csr_rw.633610244
Short name	T704
Test name
Test status
Simulation time	14069620 ps
CPU time	0.72 seconds
Started	Jun 21 06:00:54 PM PDT 24
Finished	Jun 21 06:00:57 PM PDT 24
Peak memory	197532 kb
Host	smart-443b24d0-fd15-42e6-99ac-b1f9b8d01ffe
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633610244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.633610244
Directory	/workspace/15.hmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.hmac_intr_test.152621698
Short name	T706
Test name
Test status
Simulation time	43402488 ps
CPU time	0.61 seconds
Started	Jun 21 06:00:54 PM PDT 24
Finished	Jun 21 06:00:57 PM PDT 24
Peak memory	194440 kb
Host	smart-4ee23f51-50d7-4a3e-bd19-b23060734126
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152621698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.152621698
Directory	/workspace/15.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1411298129
Short name	T110
Test name
Test status
Simulation time	793178151 ps
CPU time	1.12 seconds
Started	Jun 21 06:00:54 PM PDT 24
Finished	Jun 21 06:00:57 PM PDT 24
Peak memory	199376 kb
Host	smart-fea0320a-eb59-4461-9a83-e815f32db749
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411298129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs r_outstanding.1411298129
Directory	/workspace/15.hmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.hmac_tl_errors.715906792
Short name	T61
Test name
Test status
Simulation time	104687119 ps
CPU time	1.45 seconds
Started	Jun 21 06:00:53 PM PDT 24
Finished	Jun 21 06:00:56 PM PDT 24
Peak memory	199620 kb
Host	smart-e6b7d36f-168e-4361-99cc-daba43021505
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715906792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.715906792
Directory	/workspace/15.hmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2176155598
Short name	T703
Test name
Test status
Simulation time	760932418 ps
CPU time	3.15 seconds
Started	Jun 21 06:00:54 PM PDT 24
Finished	Jun 21 06:00:58 PM PDT 24
Peak memory	199668 kb
Host	smart-a2afb803-11e7-43e9-815a-4637b4183ac5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176155598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2176155598
Directory	/workspace/15.hmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.418396375
Short name	T744
Test name
Test status
Simulation time	36012793 ps
CPU time	1.12 seconds
Started	Jun 21 06:00:54 PM PDT 24
Finished	Jun 21 06:00:58 PM PDT 24
Peak memory	199440 kb
Host	smart-24526707-f0dc-4b20-a757-a196840c0672
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418396375 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.418396375
Directory	/workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.hmac_csr_rw.3382647342
Short name	T697
Test name
Test status
Simulation time	60561127 ps
CPU time	0.96 seconds
Started	Jun 21 06:00:56 PM PDT 24
Finished	Jun 21 06:00:59 PM PDT 24
Peak memory	199372 kb
Host	smart-26023e0a-1467-4144-bf35-985e38985a12
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382647342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3382647342
Directory	/workspace/16.hmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.hmac_intr_test.1522467357
Short name	T707
Test name
Test status
Simulation time	53247837 ps
CPU time	0.62 seconds
Started	Jun 21 06:00:54 PM PDT 24
Finished	Jun 21 06:00:56 PM PDT 24
Peak memory	194444 kb
Host	smart-c2a9f801-db33-4f1b-952c-8c98cc7131df
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522467357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1522467357
Directory	/workspace/16.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1385332241
Short name	T713
Test name
Test status
Simulation time	92386556 ps
CPU time	1.13 seconds
Started	Jun 21 06:00:53 PM PDT 24
Finished	Jun 21 06:00:55 PM PDT 24
Peak memory	199356 kb
Host	smart-c2cb2f80-700f-4c71-b92c-735db232be52
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385332241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs r_outstanding.1385332241
Directory	/workspace/16.hmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.hmac_tl_errors.3282018059
Short name	T693
Test name
Test status
Simulation time	153847214 ps
CPU time	2.83 seconds
Started	Jun 21 06:00:51 PM PDT 24
Finished	Jun 21 06:00:55 PM PDT 24
Peak memory	199620 kb
Host	smart-c3cf5f14-0e43-4240-89c6-1e295ccebec7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282018059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3282018059
Directory	/workspace/16.hmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3503071639
Short name	T728
Test name
Test status
Simulation time	83757883 ps
CPU time	1.9 seconds
Started	Jun 21 06:00:55 PM PDT 24
Finished	Jun 21 06:00:58 PM PDT 24
Peak memory	199628 kb
Host	smart-5849e890-d486-461e-8491-046c56be476d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503071639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3503071639
Directory	/workspace/16.hmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.4203831817
Short name	T680
Test name
Test status
Simulation time	25928088 ps
CPU time	1.51 seconds
Started	Jun 21 06:00:54 PM PDT 24
Finished	Jun 21 06:00:57 PM PDT 24
Peak memory	199660 kb
Host	smart-9b83266c-794b-4157-900d-2fe211c5de4d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203831817 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.4203831817
Directory	/workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.hmac_csr_rw.1341221883
Short name	T92
Test name
Test status
Simulation time	37312178 ps
CPU time	0.92 seconds
Started	Jun 21 06:00:51 PM PDT 24
Finished	Jun 21 06:00:54 PM PDT 24
Peak memory	199096 kb
Host	smart-2d474009-4a16-477b-b70c-ede830d534e3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341221883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1341221883
Directory	/workspace/17.hmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.hmac_intr_test.1595237110
Short name	T695
Test name
Test status
Simulation time	39879573 ps
CPU time	0.59 seconds
Started	Jun 21 06:00:54 PM PDT 24
Finished	Jun 21 06:00:56 PM PDT 24
Peak memory	194360 kb
Host	smart-dd14d5fb-a18f-4a2c-a248-1ee6990c95ba
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595237110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1595237110
Directory	/workspace/17.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2466043921
Short name	T671
Test name
Test status
Simulation time	184544379 ps
CPU time	1.13 seconds
Started	Jun 21 06:00:57 PM PDT 24
Finished	Jun 21 06:01:00 PM PDT 24
Peak memory	199452 kb
Host	smart-28268443-fe4c-465d-a817-99372712d8f1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466043921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs r_outstanding.2466043921
Directory	/workspace/17.hmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.hmac_tl_errors.4138194774
Short name	T737
Test name
Test status
Simulation time	371703255 ps
CPU time	3.75 seconds
Started	Jun 21 06:00:56 PM PDT 24
Finished	Jun 21 06:01:02 PM PDT 24
Peak memory	199640 kb
Host	smart-4e88220d-d633-4c14-9e82-61bfee433268
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138194774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.4138194774
Directory	/workspace/17.hmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1604986903
Short name	T749
Test name
Test status
Simulation time	110940733 ps
CPU time	1.92 seconds
Started	Jun 21 06:00:55 PM PDT 24
Finished	Jun 21 06:00:59 PM PDT 24
Peak memory	199708 kb
Host	smart-dac34444-acb7-4883-ad68-4e87060f8fc2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604986903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1604986903
Directory	/workspace/17.hmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2571342854
Short name	T57
Test name
Test status
Simulation time	102332335 ps
CPU time	2.42 seconds
Started	Jun 21 06:00:53 PM PDT 24
Finished	Jun 21 06:00:57 PM PDT 24
Peak memory	199752 kb
Host	smart-63c8d3fa-1a72-4646-a129-8c0f84670f71
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571342854 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2571342854
Directory	/workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.hmac_csr_rw.1066982851
Short name	T106
Test name
Test status
Simulation time	73002827 ps
CPU time	0.7 seconds
Started	Jun 21 06:00:54 PM PDT 24
Finished	Jun 21 06:00:56 PM PDT 24
Peak memory	197208 kb
Host	smart-ad84eddc-a36f-45d1-94e9-ef61bfe4f2bc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066982851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1066982851
Directory	/workspace/18.hmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.hmac_intr_test.690267355
Short name	T712
Test name
Test status
Simulation time	12043948 ps
CPU time	0.62 seconds
Started	Jun 21 06:00:54 PM PDT 24
Finished	Jun 21 06:00:57 PM PDT 24
Peak memory	194088 kb
Host	smart-780149cb-cad3-4244-9e6d-5add4c2a004c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690267355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.690267355
Directory	/workspace/18.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1693177303
Short name	T689
Test name
Test status
Simulation time	513655027 ps
CPU time	2.38 seconds
Started	Jun 21 06:00:54 PM PDT 24
Finished	Jun 21 06:00:58 PM PDT 24
Peak memory	199120 kb
Host	smart-7139a028-b607-4e4a-81b9-0fc8c449fc74
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693177303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs r_outstanding.1693177303
Directory	/workspace/18.hmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.hmac_tl_errors.1648720828
Short name	T709
Test name
Test status
Simulation time	228856039 ps
CPU time	4.17 seconds
Started	Jun 21 06:00:52 PM PDT 24
Finished	Jun 21 06:00:57 PM PDT 24
Peak memory	199584 kb
Host	smart-d304cc3c-2c0f-4970-892a-85ac6bfee22f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648720828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1648720828
Directory	/workspace/18.hmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2265505420
Short name	T145
Test name
Test status
Simulation time	169223872 ps
CPU time	3.16 seconds
Started	Jun 21 06:00:52 PM PDT 24
Finished	Jun 21 06:00:56 PM PDT 24
Peak memory	199676 kb
Host	smart-9ddd9dd6-70fd-4407-a9ec-a572ec28aa60
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265505420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2265505420
Directory	/workspace/18.hmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4128730430
Short name	T679
Test name
Test status
Simulation time	24245994 ps
CPU time	1.44 seconds
Started	Jun 21 06:00:52 PM PDT 24
Finished	Jun 21 06:00:54 PM PDT 24
Peak memory	199676 kb
Host	smart-6a3c824c-2ce1-414f-8ed1-f82750f8cdde
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128730430 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.4128730430
Directory	/workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.hmac_csr_rw.2334356215
Short name	T104
Test name
Test status
Simulation time	22373414 ps
CPU time	0.81 seconds
Started	Jun 21 06:00:52 PM PDT 24
Finished	Jun 21 06:00:54 PM PDT 24
Peak memory	198904 kb
Host	smart-ffc4e222-fea7-4284-8b24-08ce8b3880ea
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334356215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2334356215
Directory	/workspace/19.hmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.hmac_intr_test.66795854
Short name	T667
Test name
Test status
Simulation time	13958785 ps
CPU time	0.62 seconds
Started	Jun 21 06:00:50 PM PDT 24
Finished	Jun 21 06:00:52 PM PDT 24
Peak memory	194472 kb
Host	smart-52a30ba3-e61f-4250-9c58-00750e1c8f32
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66795854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.66795854
Directory	/workspace/19.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1841150282
Short name	T105
Test name
Test status
Simulation time	35062239 ps
CPU time	1.63 seconds
Started	Jun 21 06:00:56 PM PDT 24
Finished	Jun 21 06:00:59 PM PDT 24
Peak memory	199612 kb
Host	smart-f64380fa-0b9c-4ef5-a80b-31f206edd5fc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841150282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs r_outstanding.1841150282
Directory	/workspace/19.hmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3534961143
Short name	T722
Test name
Test status
Simulation time	166128543 ps
CPU time	1.88 seconds
Started	Jun 21 06:00:54 PM PDT 24
Finished	Jun 21 06:00:58 PM PDT 24
Peak memory	199628 kb
Host	smart-21518ba2-3a22-41de-9100-c2a411dbd501
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534961143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3534961143
Directory	/workspace/19.hmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1618058398
Short name	T94
Test name
Test status
Simulation time	110117985 ps
CPU time	5.37 seconds
Started	Jun 21 06:00:28 PM PDT 24
Finished	Jun 21 06:00:34 PM PDT 24
Peak memory	199720 kb
Host	smart-162898d4-56c7-4c27-8277-0b62dfd6505f
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618058398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1618058398
Directory	/workspace/2.hmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.804633786
Short name	T100
Test name
Test status
Simulation time	2312318035 ps
CPU time	6.07 seconds
Started	Jun 21 06:00:30 PM PDT 24
Finished	Jun 21 06:00:38 PM PDT 24
Peak memory	198564 kb
Host	smart-0c9390f8-6aae-4efe-b25e-898b7ccb5cbe
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804633786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.804633786
Directory	/workspace/2.hmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.513820968
Short name	T720
Test name
Test status
Simulation time	270758771 ps
CPU time	0.88 seconds
Started	Jun 21 06:00:30 PM PDT 24
Finished	Jun 21 06:00:32 PM PDT 24
Peak memory	198984 kb
Host	smart-a4db8db5-f812-492e-aef4-0169df4f7f54
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513820968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.513820968
Directory	/workspace/2.hmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1995937610
Short name	T681
Test name
Test status
Simulation time	66030600 ps
CPU time	1.92 seconds
Started	Jun 21 06:00:31 PM PDT 24
Finished	Jun 21 06:00:34 PM PDT 24
Peak memory	199672 kb
Host	smart-648eb36a-b1f3-4c27-8211-875e8d4fec6c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995937610 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1995937610
Directory	/workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.hmac_csr_rw.501532132
Short name	T109
Test name
Test status
Simulation time	29661019 ps
CPU time	0.99 seconds
Started	Jun 21 06:00:29 PM PDT 24
Finished	Jun 21 06:00:31 PM PDT 24
Peak memory	199308 kb
Host	smart-8ae8d4fb-4955-4ea7-8a37-a5f1d9595d2e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501532132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.501532132
Directory	/workspace/2.hmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.hmac_intr_test.1674077244
Short name	T678
Test name
Test status
Simulation time	45466977 ps
CPU time	0.61 seconds
Started	Jun 21 06:00:31 PM PDT 24
Finished	Jun 21 06:00:32 PM PDT 24
Peak memory	194364 kb
Host	smart-62118519-7a4d-4566-8af4-f60c2fe98f15
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674077244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1674077244
Directory	/workspace/2.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3525932554
Short name	T74
Test name
Test status
Simulation time	684280506 ps
CPU time	2.31 seconds
Started	Jun 21 06:00:36 PM PDT 24
Finished	Jun 21 06:00:39 PM PDT 24
Peak memory	199604 kb
Host	smart-66c29508-a3b9-4072-b692-f060e2557dac
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525932554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr _outstanding.3525932554
Directory	/workspace/2.hmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.hmac_tl_errors.1896153811
Short name	T64
Test name
Test status
Simulation time	255835692 ps
CPU time	2.59 seconds
Started	Jun 21 06:00:28 PM PDT 24
Finished	Jun 21 06:00:32 PM PDT 24
Peak memory	199604 kb
Host	smart-4d604ea9-a2c3-4fb6-ba8c-df48e8a3dda3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896153811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1896153811
Directory	/workspace/2.hmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2155331503
Short name	T146
Test name
Test status
Simulation time	203670923 ps
CPU time	2.9 seconds
Started	Jun 21 06:00:29 PM PDT 24
Finished	Jun 21 06:00:33 PM PDT 24
Peak memory	199676 kb
Host	smart-e81df710-935a-4297-9907-d6244c271446
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155331503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2155331503
Directory	/workspace/2.hmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.hmac_intr_test.2896087338
Short name	T718
Test name
Test status
Simulation time	26339243 ps
CPU time	0.65 seconds
Started	Jun 21 06:00:51 PM PDT 24
Finished	Jun 21 06:00:53 PM PDT 24
Peak memory	194520 kb
Host	smart-b97715c3-8d14-4893-87f9-7eeee0493240
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896087338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2896087338
Directory	/workspace/20.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.hmac_intr_test.3600659675
Short name	T762
Test name
Test status
Simulation time	11621055 ps
CPU time	0.59 seconds
Started	Jun 21 06:00:51 PM PDT 24
Finished	Jun 21 06:00:53 PM PDT 24
Peak memory	194572 kb
Host	smart-04bf9fdc-1138-4613-aaaf-057c43a98ddd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600659675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3600659675
Directory	/workspace/21.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.hmac_intr_test.2462354440
Short name	T670
Test name
Test status
Simulation time	26705943 ps
CPU time	0.64 seconds
Started	Jun 21 06:00:56 PM PDT 24
Finished	Jun 21 06:00:58 PM PDT 24
Peak memory	194476 kb
Host	smart-a449af90-6159-4032-b5b2-658487970bc4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462354440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2462354440
Directory	/workspace/22.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.hmac_intr_test.4104306602
Short name	T76
Test name
Test status
Simulation time	54986401 ps
CPU time	0.61 seconds
Started	Jun 21 06:00:54 PM PDT 24
Finished	Jun 21 06:00:56 PM PDT 24
Peak memory	194420 kb
Host	smart-92887511-a264-4c4c-9171-41addc1f7862
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104306602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.4104306602
Directory	/workspace/23.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.hmac_intr_test.2991234653
Short name	T658
Test name
Test status
Simulation time	15204705 ps
CPU time	0.63 seconds
Started	Jun 21 06:00:53 PM PDT 24
Finished	Jun 21 06:00:55 PM PDT 24
Peak memory	194376 kb
Host	smart-b8266319-38df-4728-ba83-c668274b3c3e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991234653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2991234653
Directory	/workspace/24.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.hmac_intr_test.1549604041
Short name	T732
Test name
Test status
Simulation time	18172881 ps
CPU time	0.64 seconds
Started	Jun 21 06:00:51 PM PDT 24
Finished	Jun 21 06:00:53 PM PDT 24
Peak memory	194460 kb
Host	smart-c896ded3-c432-4743-9545-981ac5d629b8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549604041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1549604041
Directory	/workspace/25.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.hmac_intr_test.3948975165
Short name	T745
Test name
Test status
Simulation time	18149742 ps
CPU time	0.58 seconds
Started	Jun 21 06:00:51 PM PDT 24
Finished	Jun 21 06:00:53 PM PDT 24
Peak memory	194368 kb
Host	smart-afc08594-8ad5-4814-a578-ca5b7d907851
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948975165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3948975165
Directory	/workspace/26.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.hmac_intr_test.3260334563
Short name	T660
Test name
Test status
Simulation time	13085348 ps
CPU time	0.55 seconds
Started	Jun 21 06:00:57 PM PDT 24
Finished	Jun 21 06:00:59 PM PDT 24
Peak memory	194336 kb
Host	smart-0602d0f5-ae06-4ed7-8eb7-e8936597d378
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260334563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3260334563
Directory	/workspace/27.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.hmac_intr_test.1854227272
Short name	T735
Test name
Test status
Simulation time	39627917 ps
CPU time	0.62 seconds
Started	Jun 21 06:01:02 PM PDT 24
Finished	Jun 21 06:01:05 PM PDT 24
Peak memory	194372 kb
Host	smart-95a9f169-6997-4b46-916c-8758b5d3074b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854227272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1854227272
Directory	/workspace/28.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.hmac_intr_test.29867021
Short name	T724
Test name
Test status
Simulation time	14102435 ps
CPU time	0.61 seconds
Started	Jun 21 06:01:03 PM PDT 24
Finished	Jun 21 06:01:06 PM PDT 24
Peak memory	194456 kb
Host	smart-7462a335-0114-4ff6-b391-b428ec2c992c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29867021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.29867021
Directory	/workspace/29.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1990584838
Short name	T91
Test name
Test status
Simulation time	2335185307 ps
CPU time	9.41 seconds
Started	Jun 21 06:00:34 PM PDT 24
Finished	Jun 21 06:00:44 PM PDT 24
Peak memory	199644 kb
Host	smart-126c5b3a-3860-46b3-bb43-339a4066b68d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990584838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1990584838
Directory	/workspace/3.hmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2870668757
Short name	T677
Test name
Test status
Simulation time	2833312755 ps
CPU time	10.95 seconds
Started	Jun 21 06:00:28 PM PDT 24
Finished	Jun 21 06:00:40 PM PDT 24
Peak memory	199660 kb
Host	smart-9b622a1d-d16b-4172-bcb1-425167a994f5
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870668757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2870668757
Directory	/workspace/3.hmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.482333971
Short name	T672
Test name
Test status
Simulation time	64366510 ps
CPU time	0.74 seconds
Started	Jun 21 06:00:28 PM PDT 24
Finished	Jun 21 06:00:29 PM PDT 24
Peak memory	197864 kb
Host	smart-9e7378e3-d5df-4112-a3cc-ece7e4b82263
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482333971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.482333971
Directory	/workspace/3.hmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2479886123
Short name	T743
Test name
Test status
Simulation time	81972349 ps
CPU time	1.23 seconds
Started	Jun 21 06:00:29 PM PDT 24
Finished	Jun 21 06:00:31 PM PDT 24
Peak memory	199548 kb
Host	smart-5b9224c2-21f0-4b4f-a400-5157f5585500
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479886123 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2479886123
Directory	/workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.hmac_csr_rw.2675392621
Short name	T103
Test name
Test status
Simulation time	17435251 ps
CPU time	0.87 seconds
Started	Jun 21 06:00:29 PM PDT 24
Finished	Jun 21 06:00:31 PM PDT 24
Peak memory	199460 kb
Host	smart-5abb7647-4ddc-4fe4-ad3b-ad681a6fcdbc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675392621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2675392621
Directory	/workspace/3.hmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.hmac_intr_test.2728453296
Short name	T73
Test name
Test status
Simulation time	29474188 ps
CPU time	0.6 seconds
Started	Jun 21 06:00:28 PM PDT 24
Finished	Jun 21 06:00:29 PM PDT 24
Peak memory	194536 kb
Host	smart-1f050b4f-0af7-4bfb-a5b9-46d0e5468c96
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728453296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2728453296
Directory	/workspace/3.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2511056663
Short name	T682
Test name
Test status
Simulation time	646103507 ps
CPU time	1.92 seconds
Started	Jun 21 06:00:30 PM PDT 24
Finished	Jun 21 06:00:33 PM PDT 24
Peak memory	199608 kb
Host	smart-90add528-53a4-4ebe-8963-8fd8134e4110
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511056663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr _outstanding.2511056663
Directory	/workspace/3.hmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.hmac_tl_errors.2243276535
Short name	T67
Test name
Test status
Simulation time	98463106 ps
CPU time	1.42 seconds
Started	Jun 21 06:00:37 PM PDT 24
Finished	Jun 21 06:00:40 PM PDT 24
Peak memory	199696 kb
Host	smart-7e8a467f-5847-4d8f-8458-8ad63cad1225
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243276535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2243276535
Directory	/workspace/3.hmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.98125860
Short name	T714
Test name
Test status
Simulation time	487864331 ps
CPU time	1.9 seconds
Started	Jun 21 06:00:33 PM PDT 24
Finished	Jun 21 06:00:36 PM PDT 24
Peak memory	199692 kb
Host	smart-8616834f-e0ab-4f32-8ba5-6c93b8b92acf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98125860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.98125860
Directory	/workspace/3.hmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.hmac_intr_test.315326388
Short name	T736
Test name
Test status
Simulation time	18975516 ps
CPU time	0.58 seconds
Started	Jun 21 06:00:58 PM PDT 24
Finished	Jun 21 06:01:00 PM PDT 24
Peak memory	194420 kb
Host	smart-cc33cc44-720a-4879-82ad-7e3b9059ed92
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315326388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.315326388
Directory	/workspace/30.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.hmac_intr_test.602252050
Short name	T674
Test name
Test status
Simulation time	25240117 ps
CPU time	0.61 seconds
Started	Jun 21 06:00:59 PM PDT 24
Finished	Jun 21 06:01:01 PM PDT 24
Peak memory	194632 kb
Host	smart-c0c9d189-bb9d-41b1-a53d-23baa738379d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602252050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.602252050
Directory	/workspace/31.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.hmac_intr_test.3999565107
Short name	T676
Test name
Test status
Simulation time	15696059 ps
CPU time	0.63 seconds
Started	Jun 21 06:01:01 PM PDT 24
Finished	Jun 21 06:01:04 PM PDT 24
Peak memory	194412 kb
Host	smart-9ffa3c16-57a0-40b4-802e-dac663a76d64
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999565107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3999565107
Directory	/workspace/32.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.hmac_intr_test.1071964592
Short name	T768
Test name
Test status
Simulation time	75399709 ps
CPU time	0.61 seconds
Started	Jun 21 06:00:59 PM PDT 24
Finished	Jun 21 06:01:01 PM PDT 24
Peak memory	194536 kb
Host	smart-ae9f7e5b-224e-475f-84a1-386e2d3a4a4a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071964592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1071964592
Directory	/workspace/33.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.hmac_intr_test.192904329
Short name	T710
Test name
Test status
Simulation time	111579145 ps
CPU time	0.63 seconds
Started	Jun 21 06:01:00 PM PDT 24
Finished	Jun 21 06:01:02 PM PDT 24
Peak memory	194576 kb
Host	smart-a98fb414-0d6c-4321-a842-236d0947daf2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192904329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.192904329
Directory	/workspace/34.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.hmac_intr_test.3594512880
Short name	T686
Test name
Test status
Simulation time	11242485 ps
CPU time	0.65 seconds
Started	Jun 21 06:01:01 PM PDT 24
Finished	Jun 21 06:01:04 PM PDT 24
Peak memory	194536 kb
Host	smart-dec0615d-b6b3-42de-a23e-f3cbb927f241
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594512880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3594512880
Directory	/workspace/35.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.hmac_intr_test.264444718
Short name	T701
Test name
Test status
Simulation time	29216470 ps
CPU time	0.6 seconds
Started	Jun 21 06:01:02 PM PDT 24
Finished	Jun 21 06:01:06 PM PDT 24
Peak memory	194396 kb
Host	smart-25cb5c62-6050-4ea8-9976-84720349ca0a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264444718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.264444718
Directory	/workspace/36.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.hmac_intr_test.1036819065
Short name	T664
Test name
Test status
Simulation time	28249586 ps
CPU time	0.69 seconds
Started	Jun 21 06:00:59 PM PDT 24
Finished	Jun 21 06:01:01 PM PDT 24
Peak memory	194420 kb
Host	smart-fb71f97f-9fd6-40a3-bd7d-c5f6e6979c2b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036819065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1036819065
Directory	/workspace/38.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.hmac_intr_test.726646812
Short name	T669
Test name
Test status
Simulation time	13772121 ps
CPU time	0.66 seconds
Started	Jun 21 06:01:01 PM PDT 24
Finished	Jun 21 06:01:04 PM PDT 24
Peak memory	194428 kb
Host	smart-daaef779-d9c5-4b46-be99-ace8e592d3d6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726646812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.726646812
Directory	/workspace/39.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1485694773
Short name	T751
Test name
Test status
Simulation time	183580097 ps
CPU time	3.33 seconds
Started	Jun 21 06:00:38 PM PDT 24
Finished	Jun 21 06:00:43 PM PDT 24
Peak memory	199532 kb
Host	smart-898924fd-fcf6-4f4f-9bc0-9e4c43332372
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485694773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1485694773
Directory	/workspace/4.hmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3751581175
Short name	T101
Test name
Test status
Simulation time	5486120510 ps
CPU time	16.85 seconds
Started	Jun 21 06:00:38 PM PDT 24
Finished	Jun 21 06:00:56 PM PDT 24
Peak memory	199684 kb
Host	smart-3445d22e-f09a-4ffc-99df-4326aaa4b018
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751581175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3751581175
Directory	/workspace/4.hmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.704592490
Short name	T657
Test name
Test status
Simulation time	34117166 ps
CPU time	1.03 seconds
Started	Jun 21 06:00:35 PM PDT 24
Finished	Jun 21 06:00:37 PM PDT 24
Peak memory	199416 kb
Host	smart-d6eb5212-51d8-4419-b3e8-7992c68b88c5
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704592490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.704592490
Directory	/workspace/4.hmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.982008703
Short name	T68
Test name
Test status
Simulation time	19326124072 ps
CPU time	306.85 seconds
Started	Jun 21 06:00:36 PM PDT 24
Finished	Jun 21 06:05:44 PM PDT 24
Peak memory	215872 kb
Host	smart-5f04f7d7-5a3a-45e6-b26a-7645af9e5369
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982008703 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.982008703
Directory	/workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.hmac_csr_rw.1553049853
Short name	T99
Test name
Test status
Simulation time	35825993 ps
CPU time	0.69 seconds
Started	Jun 21 06:00:35 PM PDT 24
Finished	Jun 21 06:00:36 PM PDT 24
Peak memory	197332 kb
Host	smart-ab9b91c3-49fe-4949-87c2-ccca69104e3a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553049853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1553049853
Directory	/workspace/4.hmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.hmac_intr_test.3191495716
Short name	T739
Test name
Test status
Simulation time	11263071 ps
CPU time	0.61 seconds
Started	Jun 21 06:00:38 PM PDT 24
Finished	Jun 21 06:00:39 PM PDT 24
Peak memory	194420 kb
Host	smart-4e6cfafb-aae5-4709-833b-c7da2832b36f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191495716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3191495716
Directory	/workspace/4.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1837554932
Short name	T111
Test name
Test status
Simulation time	94099766 ps
CPU time	1.84 seconds
Started	Jun 21 06:00:35 PM PDT 24
Finished	Jun 21 06:00:38 PM PDT 24
Peak memory	199564 kb
Host	smart-03d167b3-8ee2-4602-9559-5328df9c3a97
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837554932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr _outstanding.1837554932
Directory	/workspace/4.hmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.hmac_tl_errors.3035801842
Short name	T62
Test name
Test status
Simulation time	307613534 ps
CPU time	4.16 seconds
Started	Jun 21 06:00:29 PM PDT 24
Finished	Jun 21 06:00:35 PM PDT 24
Peak memory	199584 kb
Host	smart-d9b91569-1366-4006-8540-224d4b1318c8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035801842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3035801842
Directory	/workspace/4.hmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4098516727
Short name	T753
Test name
Test status
Simulation time	352465882 ps
CPU time	1.94 seconds
Started	Jun 21 06:00:31 PM PDT 24
Finished	Jun 21 06:00:34 PM PDT 24
Peak memory	199672 kb
Host	smart-bf861b88-855a-4545-bbac-9f4b1bb653fb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098516727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.4098516727
Directory	/workspace/4.hmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.hmac_intr_test.1657597170
Short name	T757
Test name
Test status
Simulation time	37176582 ps
CPU time	0.59 seconds
Started	Jun 21 06:01:01 PM PDT 24
Finished	Jun 21 06:01:04 PM PDT 24
Peak memory	194380 kb
Host	smart-992a7007-9371-476e-9e10-1228d9b8e24d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657597170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1657597170
Directory	/workspace/40.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.hmac_intr_test.4166309092
Short name	T766
Test name
Test status
Simulation time	16646404 ps
CPU time	0.62 seconds
Started	Jun 21 06:01:01 PM PDT 24
Finished	Jun 21 06:01:03 PM PDT 24
Peak memory	194484 kb
Host	smart-a2bcac01-895a-47a2-9c94-1b70f9b0bace
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166309092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.4166309092
Directory	/workspace/41.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.hmac_intr_test.3487231031
Short name	T666
Test name
Test status
Simulation time	18479966 ps
CPU time	0.69 seconds
Started	Jun 21 06:01:00 PM PDT 24
Finished	Jun 21 06:01:01 PM PDT 24
Peak memory	194372 kb
Host	smart-9d8d53ad-6493-487d-ba8f-50107d635434
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487231031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3487231031
Directory	/workspace/42.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.hmac_intr_test.1842674233
Short name	T723
Test name
Test status
Simulation time	18557657 ps
CPU time	0.65 seconds
Started	Jun 21 06:01:01 PM PDT 24
Finished	Jun 21 06:01:05 PM PDT 24
Peak memory	194548 kb
Host	smart-3be5fe08-3821-49dc-a925-8d7b025c54b1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842674233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1842674233
Directory	/workspace/43.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.hmac_intr_test.3382266899
Short name	T711
Test name
Test status
Simulation time	13359342 ps
CPU time	0.64 seconds
Started	Jun 21 06:01:03 PM PDT 24
Finished	Jun 21 06:01:06 PM PDT 24
Peak memory	194468 kb
Host	smart-eb0d3ace-46e9-4308-b8f3-c899d40b8764
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382266899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3382266899
Directory	/workspace/44.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.hmac_intr_test.1922166481
Short name	T694
Test name
Test status
Simulation time	13269098 ps
CPU time	0.59 seconds
Started	Jun 21 06:01:01 PM PDT 24
Finished	Jun 21 06:01:04 PM PDT 24
Peak memory	194380 kb
Host	smart-39d342f9-0d10-4162-8298-28b6a57f5bb1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922166481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1922166481
Directory	/workspace/45.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.hmac_intr_test.1416049318
Short name	T668
Test name
Test status
Simulation time	34334154 ps
CPU time	0.59 seconds
Started	Jun 21 06:01:01 PM PDT 24
Finished	Jun 21 06:01:04 PM PDT 24
Peak memory	194388 kb
Host	smart-3fd2160d-abea-47a9-9efc-8fa5868a5929
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416049318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1416049318
Directory	/workspace/46.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.hmac_intr_test.3629346144
Short name	T764
Test name
Test status
Simulation time	47106114 ps
CPU time	0.69 seconds
Started	Jun 21 06:01:00 PM PDT 24
Finished	Jun 21 06:01:02 PM PDT 24
Peak memory	194448 kb
Host	smart-1c97e225-206c-47da-8a6f-2d5af733956a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629346144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3629346144
Directory	/workspace/47.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.hmac_intr_test.295716763
Short name	T663
Test name
Test status
Simulation time	42108879 ps
CPU time	0.58 seconds
Started	Jun 21 06:01:00 PM PDT 24
Finished	Jun 21 06:01:01 PM PDT 24
Peak memory	194392 kb
Host	smart-f7cfe2f1-3704-4d03-9fae-099f223c0e3a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295716763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.295716763
Directory	/workspace/48.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.hmac_intr_test.1832518208
Short name	T758
Test name
Test status
Simulation time	12189786 ps
CPU time	0.68 seconds
Started	Jun 21 06:01:02 PM PDT 24
Finished	Jun 21 06:01:06 PM PDT 24
Peak memory	194376 kb
Host	smart-d3e13683-ddd6-4d48-9833-d35882f413ee
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832518208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1832518208
Directory	/workspace/49.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1012657626
Short name	T700
Test name
Test status
Simulation time	228523150 ps
CPU time	1.34 seconds
Started	Jun 21 06:00:38 PM PDT 24
Finished	Jun 21 06:00:41 PM PDT 24
Peak memory	199504 kb
Host	smart-a7ffecb1-6844-4427-83bf-dfd687f64a57
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012657626 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1012657626
Directory	/workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.hmac_csr_rw.3349331792
Short name	T659
Test name
Test status
Simulation time	18895637 ps
CPU time	0.71 seconds
Started	Jun 21 06:00:36 PM PDT 24
Finished	Jun 21 06:00:37 PM PDT 24
Peak memory	196968 kb
Host	smart-7783e6ce-c8d4-485c-b5ee-c8b033a7e058
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349331792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3349331792
Directory	/workspace/5.hmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.hmac_intr_test.3500129496
Short name	T715
Test name
Test status
Simulation time	29454686 ps
CPU time	0.62 seconds
Started	Jun 21 06:00:36 PM PDT 24
Finished	Jun 21 06:00:38 PM PDT 24
Peak memory	194448 kb
Host	smart-7a504ed5-b4dd-453a-962e-85a2cd521669
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500129496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3500129496
Directory	/workspace/5.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3228345794
Short name	T760
Test name
Test status
Simulation time	83201725 ps
CPU time	1.74 seconds
Started	Jun 21 06:00:36 PM PDT 24
Finished	Jun 21 06:00:39 PM PDT 24
Peak memory	199608 kb
Host	smart-7d34b5af-bc44-4340-a0da-4939e8c34b3a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228345794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr _outstanding.3228345794
Directory	/workspace/5.hmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.hmac_tl_errors.1094979999
Short name	T63
Test name
Test status
Simulation time	70559459 ps
CPU time	1.54 seconds
Started	Jun 21 06:00:35 PM PDT 24
Finished	Jun 21 06:00:37 PM PDT 24
Peak memory	199636 kb
Host	smart-6af1e844-996a-47b3-aef1-b10288b168cd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094979999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1094979999
Directory	/workspace/5.hmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.790733505
Short name	T731
Test name
Test status
Simulation time	626549225 ps
CPU time	1.91 seconds
Started	Jun 21 06:00:35 PM PDT 24
Finished	Jun 21 06:00:38 PM PDT 24
Peak memory	199636 kb
Host	smart-b9ea7e90-951d-4dc8-ac7b-809c3c920bcf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790733505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.790733505
Directory	/workspace/5.hmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.4212162977
Short name	T59
Test name
Test status
Simulation time	56608339 ps
CPU time	1.76 seconds
Started	Jun 21 06:00:37 PM PDT 24
Finished	Jun 21 06:00:40 PM PDT 24
Peak memory	199576 kb
Host	smart-e6a83ce2-5f12-4171-8d62-d782bfc6e6ca
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212162977 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.4212162977
Directory	/workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.hmac_csr_rw.3167923492
Short name	T96
Test name
Test status
Simulation time	97585597 ps
CPU time	0.96 seconds
Started	Jun 21 06:00:37 PM PDT 24
Finished	Jun 21 06:00:39 PM PDT 24
Peak memory	199336 kb
Host	smart-098f9f68-f901-4916-8430-8211b7300b82
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167923492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3167923492
Directory	/workspace/6.hmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.hmac_intr_test.3663060841
Short name	T662
Test name
Test status
Simulation time	55039344 ps
CPU time	0.62 seconds
Started	Jun 21 06:00:36 PM PDT 24
Finished	Jun 21 06:00:38 PM PDT 24
Peak memory	194416 kb
Host	smart-9c060505-8e52-4a1b-82a5-242b72ece4f2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663060841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3663060841
Directory	/workspace/6.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3729360958
Short name	T108
Test name
Test status
Simulation time	158341574 ps
CPU time	2.6 seconds
Started	Jun 21 06:00:36 PM PDT 24
Finished	Jun 21 06:00:39 PM PDT 24
Peak memory	199772 kb
Host	smart-f5bd2467-c93a-4615-8dbf-c987a8d4d31e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729360958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr _outstanding.3729360958
Directory	/workspace/6.hmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.hmac_tl_errors.1737740391
Short name	T60
Test name
Test status
Simulation time	99309022 ps
CPU time	1.37 seconds
Started	Jun 21 06:00:38 PM PDT 24
Finished	Jun 21 06:00:40 PM PDT 24
Peak memory	199688 kb
Host	smart-82b93c26-8c4d-4388-850b-985f4454d7d2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737740391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1737740391
Directory	/workspace/6.hmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2879363741
Short name	T71
Test name
Test status
Simulation time	95567977 ps
CPU time	3.02 seconds
Started	Jun 21 06:00:34 PM PDT 24
Finished	Jun 21 06:00:37 PM PDT 24
Peak memory	199636 kb
Host	smart-ef3eda93-b238-4550-92e0-2297c1dc9f70
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879363741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2879363741
Directory	/workspace/6.hmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.101656412
Short name	T730
Test name
Test status
Simulation time	42962379 ps
CPU time	1.21 seconds
Started	Jun 21 06:00:35 PM PDT 24
Finished	Jun 21 06:00:37 PM PDT 24
Peak memory	199448 kb
Host	smart-eb74e991-f9b8-4087-b366-2c6b6a1f2433
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101656412 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.101656412
Directory	/workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.hmac_csr_rw.956101364
Short name	T97
Test name
Test status
Simulation time	45997565 ps
CPU time	0.7 seconds
Started	Jun 21 06:00:34 PM PDT 24
Finished	Jun 21 06:00:36 PM PDT 24
Peak memory	197560 kb
Host	smart-4353bad9-2b80-4201-9b10-395415ea1310
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956101364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.956101364
Directory	/workspace/7.hmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.hmac_intr_test.1689002219
Short name	T717
Test name
Test status
Simulation time	15943663 ps
CPU time	0.58 seconds
Started	Jun 21 06:00:38 PM PDT 24
Finished	Jun 21 06:00:39 PM PDT 24
Peak memory	194488 kb
Host	smart-cf081fc3-6e08-47bb-8d4e-2ea74e48dd5f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689002219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1689002219
Directory	/workspace/7.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3861429704
Short name	T754
Test name
Test status
Simulation time	41411520 ps
CPU time	1.03 seconds
Started	Jun 21 06:00:38 PM PDT 24
Finished	Jun 21 06:00:40 PM PDT 24
Peak memory	198212 kb
Host	smart-a0e6cbe1-5a19-4126-986d-d8f44aed005e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861429704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr _outstanding.3861429704
Directory	/workspace/7.hmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.hmac_tl_errors.2841353829
Short name	T761
Test name
Test status
Simulation time	415565857 ps
CPU time	2.92 seconds
Started	Jun 21 06:00:36 PM PDT 24
Finished	Jun 21 06:00:40 PM PDT 24
Peak memory	199656 kb
Host	smart-feb0ecd2-fa74-414a-aff1-21efc16b7b1e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841353829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2841353829
Directory	/workspace/7.hmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.302078206
Short name	T83
Test name
Test status
Simulation time	159074566 ps
CPU time	3.88 seconds
Started	Jun 21 06:00:34 PM PDT 24
Finished	Jun 21 06:00:39 PM PDT 24
Peak memory	199656 kb
Host	smart-0d93c5f9-8c00-48de-bb8e-574452aeefdf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302078206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.302078206
Directory	/workspace/7.hmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.4149842058
Short name	T685
Test name
Test status
Simulation time	78732828 ps
CPU time	1.91 seconds
Started	Jun 21 06:00:45 PM PDT 24
Finished	Jun 21 06:00:48 PM PDT 24
Peak memory	199616 kb
Host	smart-4641d49f-6d58-4045-8292-c3a8468c1ef2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149842058 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.4149842058
Directory	/workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.hmac_csr_rw.3680964745
Short name	T708
Test name
Test status
Simulation time	16949088 ps
CPU time	0.7 seconds
Started	Jun 21 06:00:48 PM PDT 24
Finished	Jun 21 06:00:50 PM PDT 24
Peak memory	196988 kb
Host	smart-abca4b81-65d4-4e8a-9178-bf001e2e5d2e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680964745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3680964745
Directory	/workspace/8.hmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.hmac_intr_test.2983760580
Short name	T691
Test name
Test status
Simulation time	22840118 ps
CPU time	0.64 seconds
Started	Jun 21 06:00:42 PM PDT 24
Finished	Jun 21 06:00:43 PM PDT 24
Peak memory	194556 kb
Host	smart-df520017-a330-41af-9151-cd676915062e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983760580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2983760580
Directory	/workspace/8.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2242178373
Short name	T684
Test name
Test status
Simulation time	23613331 ps
CPU time	1.14 seconds
Started	Jun 21 06:00:47 PM PDT 24
Finished	Jun 21 06:00:49 PM PDT 24
Peak memory	198184 kb
Host	smart-aa17fa73-db47-4c53-bc47-bad5c78466dd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242178373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr _outstanding.2242178373
Directory	/workspace/8.hmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.hmac_tl_errors.2037764392
Short name	T692
Test name
Test status
Simulation time	86480902 ps
CPU time	4.33 seconds
Started	Jun 21 06:00:36 PM PDT 24
Finished	Jun 21 06:00:41 PM PDT 24
Peak memory	199680 kb
Host	smart-067164b8-7e67-4082-aba7-4fce621e32c9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037764392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2037764392
Directory	/workspace/8.hmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3926366128
Short name	T72
Test name
Test status
Simulation time	695690453 ps
CPU time	3.83 seconds
Started	Jun 21 06:00:36 PM PDT 24
Finished	Jun 21 06:00:41 PM PDT 24
Peak memory	199632 kb
Host	smart-75f546fb-7df5-4311-b0d5-6a668f358549
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926366128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3926366128
Directory	/workspace/8.hmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.368769429
Short name	T77
Test name
Test status
Simulation time	74145592 ps
CPU time	1.72 seconds
Started	Jun 21 06:00:50 PM PDT 24
Finished	Jun 21 06:00:54 PM PDT 24
Peak memory	199600 kb
Host	smart-3e9d5234-c400-4234-b0d2-e24f00311466
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368769429 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.368769429
Directory	/workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.hmac_csr_rw.2930531497
Short name	T98
Test name
Test status
Simulation time	30552310 ps
CPU time	0.82 seconds
Started	Jun 21 06:00:45 PM PDT 24
Finished	Jun 21 06:00:47 PM PDT 24
Peak memory	198784 kb
Host	smart-60402ba4-8423-41f9-b025-057717194b45
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930531497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2930531497
Directory	/workspace/9.hmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.hmac_intr_test.967224277
Short name	T699
Test name
Test status
Simulation time	15086231 ps
CPU time	0.61 seconds
Started	Jun 21 06:00:47 PM PDT 24
Finished	Jun 21 06:00:49 PM PDT 24
Peak memory	194448 kb
Host	smart-e35a5775-f382-4f3d-8cce-bbcc581fa1ff
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967224277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.967224277
Directory	/workspace/9.hmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2114298235
Short name	T112
Test name
Test status
Simulation time	431876502 ps
CPU time	2.36 seconds
Started	Jun 21 06:00:44 PM PDT 24
Finished	Jun 21 06:00:47 PM PDT 24
Peak memory	199624 kb
Host	smart-76a4f860-8c05-4ec9-a4f3-64af69eb588c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114298235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr _outstanding.2114298235
Directory	/workspace/9.hmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.hmac_tl_errors.2174613048
Short name	T759
Test name
Test status
Simulation time	109329202 ps
CPU time	2.13 seconds
Started	Jun 21 06:00:43 PM PDT 24
Finished	Jun 21 06:00:47 PM PDT 24
Peak memory	199584 kb
Host	smart-f43f966d-6f4a-45ee-b674-89d1e1f6302d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174613048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2174613048
Directory	/workspace/9.hmac_tl_errors/latest

Test location	/workspace/coverage/default/0.hmac_alert_test.2722858865
Short name	T570
Test name
Test status
Simulation time	13278612 ps
CPU time	0.6 seconds
Started	Jun 21 06:01:01 PM PDT 24
Finished	Jun 21 06:01:04 PM PDT 24
Peak memory	196052 kb
Host	smart-44908e57-e31b-47a0-a849-369611c70bc2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722858865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2722858865
Directory	/workspace/0.hmac_alert_test/latest

Test location	/workspace/coverage/default/0.hmac_back_pressure.356111781
Short name	T337
Test name
Test status
Simulation time	1176381774 ps
CPU time	53.33 seconds
Started	Jun 21 06:01:01 PM PDT 24
Finished	Jun 21 06:01:58 PM PDT 24
Peak memory	200056 kb
Host	smart-0d260499-f909-4df2-8e9a-8a775ce6b856
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=356111781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.356111781
Directory	/workspace/0.hmac_back_pressure/latest

Test location	/workspace/coverage/default/0.hmac_burst_wr.3724519783
Short name	T318
Test name
Test status
Simulation time	329471534 ps
CPU time	3.29 seconds
Started	Jun 21 06:01:02 PM PDT 24
Finished	Jun 21 06:01:08 PM PDT 24
Peak memory	200028 kb
Host	smart-00aa5542-278e-463f-90b0-825064ab1eb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3724519783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3724519783
Directory	/workspace/0.hmac_burst_wr/latest

Test location	/workspace/coverage/default/0.hmac_datapath_stress.2695235209
Short name	T413
Test name
Test status
Simulation time	999334755 ps
CPU time	251.73 seconds
Started	Jun 21 06:01:01 PM PDT 24
Finished	Jun 21 06:05:16 PM PDT 24
Peak memory	649584 kb
Host	smart-3eaecc4e-fc27-498b-a749-398de9f74eed
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2695235209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2695235209
Directory	/workspace/0.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/0.hmac_error.1646257768
Short name	T452
Test name
Test status
Simulation time	18296192444 ps
CPU time	120.54 seconds
Started	Jun 21 06:00:59 PM PDT 24
Finished	Jun 21 06:03:01 PM PDT 24
Peak memory	200076 kb
Host	smart-2315ecf9-4b1e-421a-86f1-ff90faa717d2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646257768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1646257768
Directory	/workspace/0.hmac_error/latest

Test location	/workspace/coverage/default/0.hmac_long_msg.1063022950
Short name	T387
Test name
Test status
Simulation time	5132948696 ps
CPU time	70.49 seconds
Started	Jun 21 06:01:05 PM PDT 24
Finished	Jun 21 06:02:18 PM PDT 24
Peak memory	200048 kb
Host	smart-093b9951-2745-4fb2-af47-8cc810bc4297
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1063022950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1063022950
Directory	/workspace/0.hmac_long_msg/latest

Test location	/workspace/coverage/default/0.hmac_smoke.3399912109
Short name	T249
Test name
Test status
Simulation time	2149285416 ps
CPU time	13.52 seconds
Started	Jun 21 06:01:01 PM PDT 24
Finished	Jun 21 06:01:17 PM PDT 24
Peak memory	200128 kb
Host	smart-72fa38a3-b579-4355-8bf8-258afe863c7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3399912109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3399912109
Directory	/workspace/0.hmac_smoke/latest

Test location	/workspace/coverage/default/0.hmac_test_hmac_vectors.121686213
Short name	T219
Test name
Test status
Simulation time	241882199 ps
CPU time	1.45 seconds
Started	Jun 21 06:01:01 PM PDT 24
Finished	Jun 21 06:01:05 PM PDT 24
Peak memory	200040 kb
Host	smart-8e79f00c-522d-4c12-8285-9b91d030705e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121686213 -assert nopostpr oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac_vectors.121686213
Directory	/workspace/0.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/0.hmac_test_sha256_vectors.4057900406
Short name	T482
Test name
Test status
Simulation time	42871378761 ps
CPU time	538.14 seconds
Started	Jun 21 06:00:58 PM PDT 24
Finished	Jun 21 06:09:58 PM PDT 24
Peak memory	200124 kb
Host	smart-336b2dec-fe1c-41a7-90b7-dc7e702e3e4d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4057900406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.4057900406
Directory	/workspace/0.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/0.hmac_test_sha384_vectors.3792870612
Short name	T548
Test name
Test status
Simulation time	457163647619 ps
CPU time	2032.54 seconds
Started	Jun 21 06:01:04 PM PDT 24
Finished	Jun 21 06:34:59 PM PDT 24
Peak memory	216524 kb
Host	smart-154bc773-ee5d-4c3e-8302-2b0c86eb848e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3792870612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.3792870612
Directory	/workspace/0.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/0.hmac_test_sha512_vectors.1368848122
Short name	T504
Test name
Test status
Simulation time	496012804076 ps
CPU time	2128.98 seconds
Started	Jun 21 06:01:02 PM PDT 24
Finished	Jun 21 06:36:35 PM PDT 24
Peak memory	216032 kb
Host	smart-7c9a9cf6-74c9-47bf-84e4-c12c108e5a56
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1368848122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.1368848122
Directory	/workspace/0.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/0.hmac_wipe_secret.1901535473
Short name	T21
Test name
Test status
Simulation time	603430717 ps
CPU time	14.67 seconds
Started	Jun 21 06:01:02 PM PDT 24
Finished	Jun 21 06:01:19 PM PDT 24
Peak memory	200016 kb
Host	smart-95e5c061-2f53-460d-8c51-2d21a1136a5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1901535473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1901535473
Directory	/workspace/0.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/1.hmac_alert_test.3307273739
Short name	T519
Test name
Test status
Simulation time	12259999 ps
CPU time	0.6 seconds
Started	Jun 21 06:01:07 PM PDT 24
Finished	Jun 21 06:01:09 PM PDT 24
Peak memory	195624 kb
Host	smart-fdae585a-3bb2-49bf-9420-5dbe83314aba
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307273739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3307273739
Directory	/workspace/1.hmac_alert_test/latest

Test location	/workspace/coverage/default/1.hmac_back_pressure.1011037795
Short name	T5
Test name
Test status
Simulation time	1471688303 ps
CPU time	17.07 seconds
Started	Jun 21 06:01:01 PM PDT 24
Finished	Jun 21 06:01:21 PM PDT 24
Peak memory	200056 kb
Host	smart-ab0533a7-76a8-4665-bc7f-d0c90c93676a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1011037795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1011037795
Directory	/workspace/1.hmac_back_pressure/latest

Test location	/workspace/coverage/default/1.hmac_burst_wr.3272376409
Short name	T644
Test name
Test status
Simulation time	11698939792 ps
CPU time	58.38 seconds
Started	Jun 21 06:01:04 PM PDT 24
Finished	Jun 21 06:02:05 PM PDT 24
Peak memory	200248 kb
Host	smart-2de4a0af-aed6-43d7-b9a1-6a5ebddd0d0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3272376409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3272376409
Directory	/workspace/1.hmac_burst_wr/latest

Test location	/workspace/coverage/default/1.hmac_datapath_stress.3539225200
Short name	T30
Test name
Test status
Simulation time	718011797 ps
CPU time	31.79 seconds
Started	Jun 21 06:01:01 PM PDT 24
Finished	Jun 21 06:01:36 PM PDT 24
Peak memory	303164 kb
Host	smart-c59e7982-31b9-4491-b752-b15fbfcabcf4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3539225200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3539225200
Directory	/workspace/1.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/1.hmac_error.3998410305
Short name	T259
Test name
Test status
Simulation time	1760357756 ps
CPU time	103.7 seconds
Started	Jun 21 06:01:02 PM PDT 24
Finished	Jun 21 06:02:49 PM PDT 24
Peak memory	200044 kb
Host	smart-01872b50-91b3-4189-b6ef-824fcf1f7891
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998410305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3998410305
Directory	/workspace/1.hmac_error/latest

Test location	/workspace/coverage/default/1.hmac_long_msg.4135269837
Short name	T325
Test name
Test status
Simulation time	10860339368 ps
CPU time	83.68 seconds
Started	Jun 21 06:01:04 PM PDT 24
Finished	Jun 21 06:02:30 PM PDT 24
Peak memory	216432 kb
Host	smart-66b7de98-6922-46a6-862b-bbdf3b5ae2bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4135269837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.4135269837
Directory	/workspace/1.hmac_long_msg/latest

Test location	/workspace/coverage/default/1.hmac_sec_cm.99715750
Short name	T42
Test name
Test status
Simulation time	226790677 ps
CPU time	0.94 seconds
Started	Jun 21 06:01:09 PM PDT 24
Finished	Jun 21 06:01:12 PM PDT 24
Peak memory	218196 kb
Host	smart-3cac8da9-4f29-44ca-9754-d809fb614f40
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99715750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.99715750
Directory	/workspace/1.hmac_sec_cm/latest

Test location	/workspace/coverage/default/1.hmac_smoke.645537200
Short name	T164
Test name
Test status
Simulation time	221504699 ps
CPU time	5.88 seconds
Started	Jun 21 06:00:59 PM PDT 24
Finished	Jun 21 06:01:06 PM PDT 24
Peak memory	200072 kb
Host	smart-ff2c7407-a972-406c-a5dd-35801f91e4ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=645537200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.645537200
Directory	/workspace/1.hmac_smoke/latest

Test location	/workspace/coverage/default/1.hmac_stress_all.3539332486
Short name	T66
Test name
Test status
Simulation time	9256510610 ps
CPU time	124.35 seconds
Started	Jun 21 06:01:01 PM PDT 24
Finished	Jun 21 06:03:07 PM PDT 24
Peak memory	216480 kb
Host	smart-6ab8e0cc-06c1-4856-9735-b0c407707a95
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539332486 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3539332486
Directory	/workspace/1.hmac_stress_all/latest

Test location	/workspace/coverage/default/1.hmac_test_hmac_vectors.4164296765
Short name	T582
Test name
Test status
Simulation time	49336798 ps
CPU time	1.23 seconds
Started	Jun 21 06:01:03 PM PDT 24
Finished	Jun 21 06:01:07 PM PDT 24
Peak memory	200048 kb
Host	smart-2e667340-ca6e-4f56-869e-c33b2cce8d42
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164296765 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac_vectors.4164296765
Directory	/workspace/1.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/1.hmac_test_sha256_vectors.2734052863
Short name	T513
Test name
Test status
Simulation time	147941514467 ps
CPU time	480.92 seconds
Started	Jun 21 06:01:02 PM PDT 24
Finished	Jun 21 06:09:06 PM PDT 24
Peak memory	200096 kb
Host	smart-80ed6b4c-368e-4b86-bcf3-a70e25cfd827
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2734052863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.2734052863
Directory	/workspace/1.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/1.hmac_test_sha512_vectors.2169701823
Short name	T324
Test name
Test status
Simulation time	163466740321 ps
CPU time	2108.96 seconds
Started	Jun 21 06:01:02 PM PDT 24
Finished	Jun 21 06:36:14 PM PDT 24
Peak memory	215956 kb
Host	smart-e946064c-72de-41e3-8a32-e1812996be45
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2169701823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.2169701823
Directory	/workspace/1.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/1.hmac_wipe_secret.3865979422
Short name	T379
Test name
Test status
Simulation time	11480455256 ps
CPU time	54.98 seconds
Started	Jun 21 06:01:06 PM PDT 24
Finished	Jun 21 06:02:03 PM PDT 24
Peak memory	200120 kb
Host	smart-5f551ffa-e578-4d90-b1ac-6044c2bf7c71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3865979422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3865979422
Directory	/workspace/1.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/10.hmac_alert_test.2985530443
Short name	T602
Test name
Test status
Simulation time	66316835 ps
CPU time	0.62 seconds
Started	Jun 21 06:01:28 PM PDT 24
Finished	Jun 21 06:01:29 PM PDT 24
Peak memory	194956 kb
Host	smart-17e86d1c-85de-4a1b-abe8-aa83604ffb32
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985530443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2985530443
Directory	/workspace/10.hmac_alert_test/latest

Test location	/workspace/coverage/default/10.hmac_back_pressure.1639152086
Short name	T333
Test name
Test status
Simulation time	215879288 ps
CPU time	8.39 seconds
Started	Jun 21 06:01:27 PM PDT 24
Finished	Jun 21 06:01:37 PM PDT 24
Peak memory	200040 kb
Host	smart-4c4f8a7a-ee7f-4890-96d8-cc0bede8ee7c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1639152086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1639152086
Directory	/workspace/10.hmac_back_pressure/latest

Test location	/workspace/coverage/default/10.hmac_burst_wr.2012635161
Short name	T558
Test name
Test status
Simulation time	905818221 ps
CPU time	49.71 seconds
Started	Jun 21 06:01:29 PM PDT 24
Finished	Jun 21 06:02:20 PM PDT 24
Peak memory	200040 kb
Host	smart-b7533c2a-0b83-43a6-b0a1-eaa477349b02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2012635161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2012635161
Directory	/workspace/10.hmac_burst_wr/latest

Test location	/workspace/coverage/default/10.hmac_datapath_stress.3940056949
Short name	T618
Test name
Test status
Simulation time	1624014309 ps
CPU time	542.42 seconds
Started	Jun 21 06:01:28 PM PDT 24
Finished	Jun 21 06:10:32 PM PDT 24
Peak memory	695340 kb
Host	smart-6a1d43ba-1188-42f8-906e-fb795a4c85b5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3940056949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3940056949
Directory	/workspace/10.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/10.hmac_error.3822257421
Short name	T289
Test name
Test status
Simulation time	16395309 ps
CPU time	0.82 seconds
Started	Jun 21 06:01:29 PM PDT 24
Finished	Jun 21 06:01:31 PM PDT 24
Peak memory	197708 kb
Host	smart-51169fe7-7f6d-456d-9da5-6f2c67d4d6fb
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822257421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3822257421
Directory	/workspace/10.hmac_error/latest

Test location	/workspace/coverage/default/10.hmac_long_msg.2311011246
Short name	T461
Test name
Test status
Simulation time	12119343415 ps
CPU time	60.7 seconds
Started	Jun 21 06:01:28 PM PDT 24
Finished	Jun 21 06:02:30 PM PDT 24
Peak memory	200148 kb
Host	smart-678320ad-3997-48bd-ae60-7fa82c1a53b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2311011246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2311011246
Directory	/workspace/10.hmac_long_msg/latest

Test location	/workspace/coverage/default/10.hmac_smoke.3020006964
Short name	T316
Test name
Test status
Simulation time	604760389 ps
CPU time	10.85 seconds
Started	Jun 21 06:01:32 PM PDT 24
Finished	Jun 21 06:01:43 PM PDT 24
Peak memory	200036 kb
Host	smart-b420d128-2a57-48ab-82aa-97d6d81cb023
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3020006964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3020006964
Directory	/workspace/10.hmac_smoke/latest

Test location	/workspace/coverage/default/10.hmac_test_hmac_vectors.3214439112
Short name	T172
Test name
Test status
Simulation time	245311044 ps
CPU time	1.41 seconds
Started	Jun 21 06:01:30 PM PDT 24
Finished	Jun 21 06:01:33 PM PDT 24
Peak memory	200072 kb
Host	smart-de13024d-20e5-4e45-ab39-04c732450d77
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214439112 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_hmac_vectors.3214439112
Directory	/workspace/10.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/10.hmac_test_sha256_vectors.247344269
Short name	T528
Test name
Test status
Simulation time	41943487179 ps
CPU time	485.17 seconds
Started	Jun 21 06:01:29 PM PDT 24
Finished	Jun 21 06:09:36 PM PDT 24
Peak memory	200084 kb
Host	smart-717ecfda-d079-444d-af0b-5bbddf1c4849
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=247344269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha256_vectors.247344269
Directory	/workspace/10.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/10.hmac_test_sha384_vectors.1243179094
Short name	T524
Test name
Test status
Simulation time	118563675129 ps
CPU time	2052.57 seconds
Started	Jun 21 06:01:31 PM PDT 24
Finished	Jun 21 06:35:44 PM PDT 24
Peak memory	216260 kb
Host	smart-668e53de-35c1-4403-b43a-0cb1fe746830
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1243179094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha384_vectors.1243179094
Directory	/workspace/10.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/10.hmac_test_sha512_vectors.2889161021
Short name	T577
Test name
Test status
Simulation time	343179197886 ps
CPU time	1825.84 seconds
Started	Jun 21 06:01:28 PM PDT 24
Finished	Jun 21 06:31:55 PM PDT 24
Peak memory	216212 kb
Host	smart-98bcf97a-5948-49e1-b993-d967fb2b45b7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2889161021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha512_vectors.2889161021
Directory	/workspace/10.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/10.hmac_wipe_secret.3046180061
Short name	T266
Test name
Test status
Simulation time	1009534557 ps
CPU time	45.17 seconds
Started	Jun 21 06:01:28 PM PDT 24
Finished	Jun 21 06:02:15 PM PDT 24
Peak memory	200056 kb
Host	smart-3a2e183f-577d-483f-ac85-f52d0deee794
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3046180061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.3046180061
Directory	/workspace/10.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/11.hmac_alert_test.2114695393
Short name	T454
Test name
Test status
Simulation time	12114537 ps
CPU time	0.58 seconds
Started	Jun 21 06:01:35 PM PDT 24
Finished	Jun 21 06:01:37 PM PDT 24
Peak memory	195628 kb
Host	smart-3a2d27a6-67e3-440c-abb6-ef33222f1d27
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114695393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2114695393
Directory	/workspace/11.hmac_alert_test/latest

Test location	/workspace/coverage/default/11.hmac_back_pressure.1101360500
Short name	T52
Test name
Test status
Simulation time	4688204734 ps
CPU time	51.78 seconds
Started	Jun 21 06:01:28 PM PDT 24
Finished	Jun 21 06:02:22 PM PDT 24
Peak memory	200132 kb
Host	smart-c2bebbb0-0a0e-4b32-bb18-c33bf9579e81
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1101360500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1101360500
Directory	/workspace/11.hmac_back_pressure/latest

Test location	/workspace/coverage/default/11.hmac_burst_wr.1263909800
Short name	T641
Test name
Test status
Simulation time	4743397835 ps
CPU time	45.33 seconds
Started	Jun 21 06:01:29 PM PDT 24
Finished	Jun 21 06:02:15 PM PDT 24
Peak memory	200060 kb
Host	smart-d3a2bef8-bace-4d52-b722-172a058dc54f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1263909800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1263909800
Directory	/workspace/11.hmac_burst_wr/latest

Test location	/workspace/coverage/default/11.hmac_datapath_stress.2171659232
Short name	T491
Test name
Test status
Simulation time	4503363833 ps
CPU time	302.15 seconds
Started	Jun 21 06:01:27 PM PDT 24
Finished	Jun 21 06:06:31 PM PDT 24
Peak memory	644800 kb
Host	smart-1802fc36-9828-482d-ad25-aa47dde77a90
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2171659232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2171659232
Directory	/workspace/11.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/11.hmac_error.1703920475
Short name	T520
Test name
Test status
Simulation time	503215273 ps
CPU time	7.66 seconds
Started	Jun 21 06:01:28 PM PDT 24
Finished	Jun 21 06:01:36 PM PDT 24
Peak memory	200040 kb
Host	smart-a977a59e-fb25-404e-aa42-acc6e6b13785
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703920475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1703920475
Directory	/workspace/11.hmac_error/latest

Test location	/workspace/coverage/default/11.hmac_long_msg.1073154425
Short name	T293
Test name
Test status
Simulation time	195171165 ps
CPU time	11.41 seconds
Started	Jun 21 06:01:27 PM PDT 24
Finished	Jun 21 06:01:40 PM PDT 24
Peak memory	200120 kb
Host	smart-95cc6134-b379-4f20-925d-200779d6f2cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1073154425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1073154425
Directory	/workspace/11.hmac_long_msg/latest

Test location	/workspace/coverage/default/11.hmac_smoke.3340799893
Short name	T158
Test name
Test status
Simulation time	467906224 ps
CPU time	7.21 seconds
Started	Jun 21 06:01:26 PM PDT 24
Finished	Jun 21 06:01:34 PM PDT 24
Peak memory	200040 kb
Host	smart-abdeb80e-f745-400d-865a-a2306706a368
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3340799893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3340799893
Directory	/workspace/11.hmac_smoke/latest

Test location	/workspace/coverage/default/11.hmac_test_hmac_vectors.684794874
Short name	T310
Test name
Test status
Simulation time	46023371 ps
CPU time	1.42 seconds
Started	Jun 21 06:01:31 PM PDT 24
Finished	Jun 21 06:01:33 PM PDT 24
Peak memory	199996 kb
Host	smart-198b9914-c0f9-41fa-923d-75fe1a568519
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684794874 -assert nopostpr oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_hmac_vectors.684794874
Directory	/workspace/11.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/11.hmac_test_sha256_vectors.4168074501
Short name	T180
Test name
Test status
Simulation time	7299144192 ps
CPU time	398.62 seconds
Started	Jun 21 06:01:27 PM PDT 24
Finished	Jun 21 06:08:06 PM PDT 24
Peak memory	200124 kb
Host	smart-2784f35e-95ff-4714-82d6-27e081b3b50d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4168074501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha256_vectors.4168074501
Directory	/workspace/11.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/11.hmac_test_sha384_vectors.954887381
Short name	T284
Test name
Test status
Simulation time	193363051144 ps
CPU time	1926.67 seconds
Started	Jun 21 06:01:28 PM PDT 24
Finished	Jun 21 06:33:36 PM PDT 24
Peak memory	215632 kb
Host	smart-2d858fb7-5fc0-43b6-82bd-ae843b0828f1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=954887381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha384_vectors.954887381
Directory	/workspace/11.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/11.hmac_test_sha512_vectors.2794940061
Short name	T445
Test name
Test status
Simulation time	93350844676 ps
CPU time	1775.82 seconds
Started	Jun 21 06:01:27 PM PDT 24
Finished	Jun 21 06:31:04 PM PDT 24
Peak memory	215548 kb
Host	smart-65c0a17a-d847-429d-b2e8-6058074d3641
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2794940061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha512_vectors.2794940061
Directory	/workspace/11.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/11.hmac_wipe_secret.918834088
Short name	T286
Test name
Test status
Simulation time	7202931204 ps
CPU time	68.55 seconds
Started	Jun 21 06:01:31 PM PDT 24
Finished	Jun 21 06:02:41 PM PDT 24
Peak memory	200136 kb
Host	smart-3fa3f407-d90f-45fa-9933-75eca57ab33b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=918834088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.918834088
Directory	/workspace/11.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/12.hmac_alert_test.2691847620
Short name	T576
Test name
Test status
Simulation time	14282387 ps
CPU time	0.55 seconds
Started	Jun 21 06:01:35 PM PDT 24
Finished	Jun 21 06:01:37 PM PDT 24
Peak memory	195632 kb
Host	smart-09eb506f-9d6c-4f6d-bd2f-44793dd4b192
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691847620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2691847620
Directory	/workspace/12.hmac_alert_test/latest

Test location	/workspace/coverage/default/12.hmac_back_pressure.3380540975
Short name	T600
Test name
Test status
Simulation time	9540956653 ps
CPU time	37.3 seconds
Started	Jun 21 06:01:36 PM PDT 24
Finished	Jun 21 06:02:14 PM PDT 24
Peak memory	200108 kb
Host	smart-33f6dd8f-a6d9-4d36-91a0-a673189fe110
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3380540975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3380540975
Directory	/workspace/12.hmac_back_pressure/latest

Test location	/workspace/coverage/default/12.hmac_burst_wr.389784691
Short name	T243
Test name
Test status
Simulation time	374210117 ps
CPU time	19.71 seconds
Started	Jun 21 06:01:46 PM PDT 24
Finished	Jun 21 06:02:07 PM PDT 24
Peak memory	200088 kb
Host	smart-0670c4fc-7ee6-4b1e-892d-7bac6b094516
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=389784691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.389784691
Directory	/workspace/12.hmac_burst_wr/latest

Test location	/workspace/coverage/default/12.hmac_datapath_stress.2535696207
Short name	T328
Test name
Test status
Simulation time	3362301586 ps
CPU time	1193.98 seconds
Started	Jun 21 06:01:34 PM PDT 24
Finished	Jun 21 06:21:29 PM PDT 24
Peak memory	749624 kb
Host	smart-f7364536-4800-47a5-a051-bbe194d3fd68
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2535696207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2535696207
Directory	/workspace/12.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/12.hmac_error.1984530652
Short name	T305
Test name
Test status
Simulation time	14465593960 ps
CPU time	139.14 seconds
Started	Jun 21 06:01:38 PM PDT 24
Finished	Jun 21 06:03:58 PM PDT 24
Peak memory	200136 kb
Host	smart-7663e39f-9d13-4104-afed-bc8bc81982ed
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984530652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1984530652
Directory	/workspace/12.hmac_error/latest

Test location	/workspace/coverage/default/12.hmac_smoke.2726157286
Short name	T420
Test name
Test status
Simulation time	51735381 ps
CPU time	2.42 seconds
Started	Jun 21 06:01:44 PM PDT 24
Finished	Jun 21 06:01:49 PM PDT 24
Peak memory	200052 kb
Host	smart-af07ff1a-b2c4-4bf6-ad4a-ea80fa887d4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2726157286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2726157286
Directory	/workspace/12.hmac_smoke/latest

Test location	/workspace/coverage/default/12.hmac_test_hmac_vectors.124042095
Short name	T190
Test name
Test status
Simulation time	122713285 ps
CPU time	1.25 seconds
Started	Jun 21 06:01:34 PM PDT 24
Finished	Jun 21 06:01:36 PM PDT 24
Peak memory	200032 kb
Host	smart-456e43ac-93d7-4549-87e4-e0f42b26ed27
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124042095 -assert nopostpr oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_hmac_vectors.124042095
Directory	/workspace/12.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/12.hmac_test_sha256_vectors.554698244
Short name	T467
Test name
Test status
Simulation time	16427178381 ps
CPU time	442.21 seconds
Started	Jun 21 06:01:45 PM PDT 24
Finished	Jun 21 06:09:09 PM PDT 24
Peak memory	200128 kb
Host	smart-162d9afd-97cd-4489-b773-dc84866dae0d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=554698244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha256_vectors.554698244
Directory	/workspace/12.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/12.hmac_test_sha384_vectors.1997244934
Short name	T277
Test name
Test status
Simulation time	33745233692 ps
CPU time	1874.54 seconds
Started	Jun 21 06:01:37 PM PDT 24
Finished	Jun 21 06:32:53 PM PDT 24
Peak memory	215556 kb
Host	smart-96409167-189f-40ff-bd6a-d0bed3d2ac78
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1997244934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha384_vectors.1997244934
Directory	/workspace/12.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/12.hmac_test_sha512_vectors.1149217273
Short name	T175
Test name
Test status
Simulation time	60175894135 ps
CPU time	1665.33 seconds
Started	Jun 21 06:01:35 PM PDT 24
Finished	Jun 21 06:29:22 PM PDT 24
Peak memory	215620 kb
Host	smart-feedb96f-333a-4ca4-a78d-f9ad2bbed973
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1149217273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha512_vectors.1149217273
Directory	/workspace/12.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/12.hmac_wipe_secret.3397120855
Short name	T163
Test name
Test status
Simulation time	12304992758 ps
CPU time	67 seconds
Started	Jun 21 06:01:35 PM PDT 24
Finished	Jun 21 06:02:43 PM PDT 24
Peak memory	200128 kb
Host	smart-cd7b4816-528d-414a-8ad3-b4c511a95de6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3397120855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3397120855
Directory	/workspace/12.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/13.hmac_alert_test.2733340494
Short name	T531
Test name
Test status
Simulation time	22507781 ps
CPU time	0.62 seconds
Started	Jun 21 06:01:34 PM PDT 24
Finished	Jun 21 06:01:36 PM PDT 24
Peak memory	195984 kb
Host	smart-cae95cdf-c45b-4495-b9d1-bbd2313d555f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733340494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2733340494
Directory	/workspace/13.hmac_alert_test/latest

Test location	/workspace/coverage/default/13.hmac_back_pressure.2503529113
Short name	T477
Test name
Test status
Simulation time	1766139182 ps
CPU time	45.36 seconds
Started	Jun 21 06:01:36 PM PDT 24
Finished	Jun 21 06:02:23 PM PDT 24
Peak memory	200060 kb
Host	smart-14290c15-6386-455c-9921-1562823897a3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2503529113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2503529113
Directory	/workspace/13.hmac_back_pressure/latest

Test location	/workspace/coverage/default/13.hmac_burst_wr.3091414351
Short name	T556
Test name
Test status
Simulation time	1018820681 ps
CPU time	54.49 seconds
Started	Jun 21 06:01:36 PM PDT 24
Finished	Jun 21 06:02:33 PM PDT 24
Peak memory	200076 kb
Host	smart-f04d8408-6670-4600-bb06-5147e8774b29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3091414351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3091414351
Directory	/workspace/13.hmac_burst_wr/latest

Test location	/workspace/coverage/default/13.hmac_datapath_stress.501843039
Short name	T412
Test name
Test status
Simulation time	2592830695 ps
CPU time	753.13 seconds
Started	Jun 21 06:01:34 PM PDT 24
Finished	Jun 21 06:14:08 PM PDT 24
Peak memory	705948 kb
Host	smart-93e13e13-fe32-458c-b156-43b58697aceb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=501843039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.501843039
Directory	/workspace/13.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/13.hmac_error.2585569591
Short name	T331
Test name
Test status
Simulation time	17406767089 ps
CPU time	227.69 seconds
Started	Jun 21 06:01:35 PM PDT 24
Finished	Jun 21 06:05:24 PM PDT 24
Peak memory	200212 kb
Host	smart-272ffd69-12af-4976-a97e-7ed38eba404d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585569591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2585569591
Directory	/workspace/13.hmac_error/latest

Test location	/workspace/coverage/default/13.hmac_long_msg.4162476186
Short name	T571
Test name
Test status
Simulation time	813361726 ps
CPU time	24.06 seconds
Started	Jun 21 06:01:34 PM PDT 24
Finished	Jun 21 06:01:59 PM PDT 24
Peak memory	200092 kb
Host	smart-4b0a6ac9-e646-4261-9fba-602523710586
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4162476186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.4162476186
Directory	/workspace/13.hmac_long_msg/latest

Test location	/workspace/coverage/default/13.hmac_smoke.2121402001
Short name	T285
Test name
Test status
Simulation time	197926075 ps
CPU time	4.92 seconds
Started	Jun 21 06:01:36 PM PDT 24
Finished	Jun 21 06:01:43 PM PDT 24
Peak memory	200064 kb
Host	smart-1edf572e-1694-4594-9cd2-ec6cb9d9ce24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2121402001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2121402001
Directory	/workspace/13.hmac_smoke/latest

Test location	/workspace/coverage/default/13.hmac_test_hmac_vectors.1034777946
Short name	T386
Test name
Test status
Simulation time	53395255 ps
CPU time	1.05 seconds
Started	Jun 21 06:01:37 PM PDT 24
Finished	Jun 21 06:01:40 PM PDT 24
Peak memory	199788 kb
Host	smart-2d5d4241-cf7a-4eb4-9fe4-0dfc7a1c42ff
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034777946 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_hmac_vectors.1034777946
Directory	/workspace/13.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/13.hmac_test_sha256_vectors.3369875620
Short name	T388
Test name
Test status
Simulation time	8143690431 ps
CPU time	448.49 seconds
Started	Jun 21 06:01:35 PM PDT 24
Finished	Jun 21 06:09:05 PM PDT 24
Peak memory	200244 kb
Host	smart-dded7542-e68e-401a-8aa7-8b86f3d9a1d5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3369875620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha256_vectors.3369875620
Directory	/workspace/13.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/13.hmac_test_sha384_vectors.3567780486
Short name	T300
Test name
Test status
Simulation time	352143947902 ps
CPU time	2101.06 seconds
Started	Jun 21 06:01:36 PM PDT 24
Finished	Jun 21 06:36:39 PM PDT 24
Peak memory	216272 kb
Host	smart-440fab3f-298f-4945-8fbd-55bb4c5dfe86
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3567780486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha384_vectors.3567780486
Directory	/workspace/13.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/13.hmac_test_sha512_vectors.1617453392
Short name	T258
Test name
Test status
Simulation time	119961431170 ps
CPU time	1771.71 seconds
Started	Jun 21 06:01:38 PM PDT 24
Finished	Jun 21 06:31:11 PM PDT 24
Peak memory	215520 kb
Host	smart-a7654975-ade3-4c46-aeb1-2d21ccf313c0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1617453392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha512_vectors.1617453392
Directory	/workspace/13.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/13.hmac_wipe_secret.2202880776
Short name	T430
Test name
Test status
Simulation time	748240974 ps
CPU time	31.76 seconds
Started	Jun 21 06:01:35 PM PDT 24
Finished	Jun 21 06:02:08 PM PDT 24
Peak memory	200068 kb
Host	smart-9d7f3296-8290-4a79-87e3-4dc1c6ebe4b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2202880776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2202880776
Directory	/workspace/13.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/14.hmac_alert_test.1531540339
Short name	T213
Test name
Test status
Simulation time	30925436 ps
CPU time	0.57 seconds
Started	Jun 21 06:01:37 PM PDT 24
Finished	Jun 21 06:01:39 PM PDT 24
Peak memory	194908 kb
Host	smart-e1c2c0c7-3820-45e7-8a4f-79e75abc4d44
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531540339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1531540339
Directory	/workspace/14.hmac_alert_test/latest

Test location	/workspace/coverage/default/14.hmac_back_pressure.4167988202
Short name	T315
Test name
Test status
Simulation time	1099908603 ps
CPU time	52.14 seconds
Started	Jun 21 06:01:37 PM PDT 24
Finished	Jun 21 06:02:31 PM PDT 24
Peak memory	200044 kb
Host	smart-f1236537-7567-4804-a97e-d35267feb392
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4167988202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.4167988202
Directory	/workspace/14.hmac_back_pressure/latest

Test location	/workspace/coverage/default/14.hmac_burst_wr.1827862623
Short name	T268
Test name
Test status
Simulation time	239059296 ps
CPU time	11.56 seconds
Started	Jun 21 06:01:45 PM PDT 24
Finished	Jun 21 06:01:58 PM PDT 24
Peak memory	199992 kb
Host	smart-f0ca648d-b896-433b-8b27-fab0d5f0ec9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1827862623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.1827862623
Directory	/workspace/14.hmac_burst_wr/latest

Test location	/workspace/coverage/default/14.hmac_datapath_stress.1038640533
Short name	T591
Test name
Test status
Simulation time	13191125117 ps
CPU time	936 seconds
Started	Jun 21 06:01:36 PM PDT 24
Finished	Jun 21 06:17:14 PM PDT 24
Peak memory	688716 kb
Host	smart-1b8dcb3e-b22f-4549-abda-437b8b7740f2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1038640533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1038640533
Directory	/workspace/14.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/14.hmac_error.607235370
Short name	T166
Test name
Test status
Simulation time	13044362274 ps
CPU time	47.63 seconds
Started	Jun 21 06:01:33 PM PDT 24
Finished	Jun 21 06:02:22 PM PDT 24
Peak memory	200036 kb
Host	smart-aabd07b8-5b3c-44e1-b668-20a2f96335da
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607235370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.607235370
Directory	/workspace/14.hmac_error/latest

Test location	/workspace/coverage/default/14.hmac_long_msg.3679866770
Short name	T590
Test name
Test status
Simulation time	20416222798 ps
CPU time	79.13 seconds
Started	Jun 21 06:01:37 PM PDT 24
Finished	Jun 21 06:02:58 PM PDT 24
Peak memory	200052 kb
Host	smart-44004e26-e21b-4795-87e1-0e7e41bb3dd0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3679866770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3679866770
Directory	/workspace/14.hmac_long_msg/latest

Test location	/workspace/coverage/default/14.hmac_smoke.1538834904
Short name	T17
Test name
Test status
Simulation time	2363143878 ps
CPU time	10.67 seconds
Started	Jun 21 06:01:35 PM PDT 24
Finished	Jun 21 06:01:47 PM PDT 24
Peak memory	200128 kb
Host	smart-27bc5b8f-3aa1-4666-b14b-e59c92771dbb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1538834904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1538834904
Directory	/workspace/14.hmac_smoke/latest

Test location	/workspace/coverage/default/14.hmac_test_hmac_vectors.3847521417
Short name	T642
Test name
Test status
Simulation time	86910346 ps
CPU time	1.1 seconds
Started	Jun 21 06:01:45 PM PDT 24
Finished	Jun 21 06:01:48 PM PDT 24
Peak memory	200028 kb
Host	smart-5c752da0-eefb-4731-b650-f56fa3db5e0e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847521417 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_hmac_vectors.3847521417
Directory	/workspace/14.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/14.hmac_test_sha256_vectors.1447155074
Short name	T113
Test name
Test status
Simulation time	54807611604 ps
CPU time	495.33 seconds
Started	Jun 21 06:01:37 PM PDT 24
Finished	Jun 21 06:09:54 PM PDT 24
Peak memory	200124 kb
Host	smart-5af51c58-4b6e-479c-b18d-a352fc7f057b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1447155074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha256_vectors.1447155074
Directory	/workspace/14.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/14.hmac_test_sha384_vectors.2738376243
Short name	T281
Test name
Test status
Simulation time	118006212871 ps
CPU time	1719.49 seconds
Started	Jun 21 06:01:34 PM PDT 24
Finished	Jun 21 06:30:14 PM PDT 24
Peak memory	216436 kb
Host	smart-79f1c375-c900-4326-8a13-402324112a89
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2738376243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha384_vectors.2738376243
Directory	/workspace/14.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/14.hmac_test_sha512_vectors.3158116810
Short name	T404
Test name
Test status
Simulation time	158029394228 ps
CPU time	1959.28 seconds
Started	Jun 21 06:01:37 PM PDT 24
Finished	Jun 21 06:34:18 PM PDT 24
Peak memory	215960 kb
Host	smart-6818167a-585b-4035-86e0-fcb994c04b11
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3158116810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha512_vectors.3158116810
Directory	/workspace/14.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/14.hmac_wipe_secret.1195934689
Short name	T78
Test name
Test status
Simulation time	605369188 ps
CPU time	18.3 seconds
Started	Jun 21 06:01:45 PM PDT 24
Finished	Jun 21 06:02:06 PM PDT 24
Peak memory	200088 kb
Host	smart-745fd18d-4a8d-4f0f-9060-5a0abb454844
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1195934689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.1195934689
Directory	/workspace/14.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/15.hmac_alert_test.1271952255
Short name	T487
Test name
Test status
Simulation time	13618927 ps
CPU time	0.62 seconds
Started	Jun 21 06:01:44 PM PDT 24
Finished	Jun 21 06:01:47 PM PDT 24
Peak memory	196080 kb
Host	smart-9e98a8f2-8759-4a24-b82e-4f7936eeaea3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271952255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1271952255
Directory	/workspace/15.hmac_alert_test/latest

Test location	/workspace/coverage/default/15.hmac_back_pressure.3781297262
Short name	T120
Test name
Test status
Simulation time	1292823260 ps
CPU time	32.01 seconds
Started	Jun 21 06:01:38 PM PDT 24
Finished	Jun 21 06:02:11 PM PDT 24
Peak memory	200072 kb
Host	smart-9962bca9-5665-4532-82b2-daef1e9acd7d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3781297262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3781297262
Directory	/workspace/15.hmac_back_pressure/latest

Test location	/workspace/coverage/default/15.hmac_burst_wr.2117157380
Short name	T131
Test name
Test status
Simulation time	4833507045 ps
CPU time	20.25 seconds
Started	Jun 21 06:01:38 PM PDT 24
Finished	Jun 21 06:02:00 PM PDT 24
Peak memory	200104 kb
Host	smart-6c768c4b-627b-4b6a-85aa-f95f163479a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2117157380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2117157380
Directory	/workspace/15.hmac_burst_wr/latest

Test location	/workspace/coverage/default/15.hmac_datapath_stress.821631900
Short name	T355
Test name
Test status
Simulation time	9733276293 ps
CPU time	618.8 seconds
Started	Jun 21 06:01:36 PM PDT 24
Finished	Jun 21 06:11:57 PM PDT 24
Peak memory	695620 kb
Host	smart-b3463ae7-2a78-44b4-a030-daeed0fdb1bc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=821631900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.821631900
Directory	/workspace/15.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/15.hmac_error.1604950887
Short name	T394
Test name
Test status
Simulation time	26269599979 ps
CPU time	116.15 seconds
Started	Jun 21 06:01:35 PM PDT 24
Finished	Jun 21 06:03:32 PM PDT 24
Peak memory	200068 kb
Host	smart-b55fe5e3-79c0-42d9-8674-a718dfc0a154
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604950887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1604950887
Directory	/workspace/15.hmac_error/latest

Test location	/workspace/coverage/default/15.hmac_long_msg.2075049032
Short name	T483
Test name
Test status
Simulation time	803806554 ps
CPU time	10.43 seconds
Started	Jun 21 06:01:34 PM PDT 24
Finished	Jun 21 06:01:45 PM PDT 24
Peak memory	200032 kb
Host	smart-0487721d-19b2-41c1-b48a-caabf6bfc450
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2075049032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2075049032
Directory	/workspace/15.hmac_long_msg/latest

Test location	/workspace/coverage/default/15.hmac_smoke.4210875155
Short name	T239
Test name
Test status
Simulation time	651933527 ps
CPU time	12.35 seconds
Started	Jun 21 06:01:38 PM PDT 24
Finished	Jun 21 06:01:52 PM PDT 24
Peak memory	200044 kb
Host	smart-65f909f4-4209-47e1-95ba-e176f07568a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4210875155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.4210875155
Directory	/workspace/15.hmac_smoke/latest

Test location	/workspace/coverage/default/15.hmac_test_hmac_vectors.1034492328
Short name	T417
Test name
Test status
Simulation time	161340096 ps
CPU time	1.42 seconds
Started	Jun 21 06:01:36 PM PDT 24
Finished	Jun 21 06:01:39 PM PDT 24
Peak memory	200060 kb
Host	smart-f2df53e6-3088-4c96-8aba-50b7074175be
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034492328 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_hmac_vectors.1034492328
Directory	/workspace/15.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/15.hmac_test_sha256_vectors.1889017052
Short name	T607
Test name
Test status
Simulation time	85392419539 ps
CPU time	535.59 seconds
Started	Jun 21 06:01:37 PM PDT 24
Finished	Jun 21 06:10:35 PM PDT 24
Peak memory	200152 kb
Host	smart-e0f4c4ea-cc8b-4886-a56a-d646abdb46c6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1889017052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha256_vectors.1889017052
Directory	/workspace/15.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/15.hmac_test_sha384_vectors.805800050
Short name	T177
Test name
Test status
Simulation time	28524645534 ps
CPU time	1668.07 seconds
Started	Jun 21 06:01:42 PM PDT 24
Finished	Jun 21 06:29:31 PM PDT 24
Peak memory	215580 kb
Host	smart-92134a89-c9fd-4cbc-94e4-670759c694a5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=805800050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha384_vectors.805800050
Directory	/workspace/15.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/15.hmac_test_sha512_vectors.3470389838
Short name	T510
Test name
Test status
Simulation time	212349220267 ps
CPU time	2018.7 seconds
Started	Jun 21 06:01:36 PM PDT 24
Finished	Jun 21 06:35:16 PM PDT 24
Peak memory	215540 kb
Host	smart-52ac9ff4-582a-4394-916a-8c864d5802e4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3470389838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha512_vectors.3470389838
Directory	/workspace/15.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/15.hmac_wipe_secret.2384482016
Short name	T119
Test name
Test status
Simulation time	7668097012 ps
CPU time	81.34 seconds
Started	Jun 21 06:01:42 PM PDT 24
Finished	Jun 21 06:03:04 PM PDT 24
Peak memory	199928 kb
Host	smart-d15abb45-dec7-48ca-b77b-5bb8756a773b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2384482016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.2384482016
Directory	/workspace/15.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/16.hmac_alert_test.536155620
Short name	T418
Test name
Test status
Simulation time	28494464 ps
CPU time	0.57 seconds
Started	Jun 21 06:01:43 PM PDT 24
Finished	Jun 21 06:01:45 PM PDT 24
Peak memory	195032 kb
Host	smart-2fdaf42f-c760-4915-88d8-6c3878f3a208
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536155620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.536155620
Directory	/workspace/16.hmac_alert_test/latest

Test location	/workspace/coverage/default/16.hmac_back_pressure.1691958926
Short name	T500
Test name
Test status
Simulation time	300124575 ps
CPU time	9.77 seconds
Started	Jun 21 06:01:45 PM PDT 24
Finished	Jun 21 06:01:56 PM PDT 24
Peak memory	200052 kb
Host	smart-d13547dd-4888-4f34-a8e6-1a24481ec2b0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1691958926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1691958926
Directory	/workspace/16.hmac_back_pressure/latest

Test location	/workspace/coverage/default/16.hmac_burst_wr.4157453017
Short name	T237
Test name
Test status
Simulation time	40692544 ps
CPU time	1.8 seconds
Started	Jun 21 06:01:44 PM PDT 24
Finished	Jun 21 06:01:48 PM PDT 24
Peak memory	200092 kb
Host	smart-05718c4f-b214-4c24-8b38-62edd521d66c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4157453017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.4157453017
Directory	/workspace/16.hmac_burst_wr/latest

Test location	/workspace/coverage/default/16.hmac_datapath_stress.3836858879
Short name	T399
Test name
Test status
Simulation time	401603459 ps
CPU time	42.43 seconds
Started	Jun 21 06:01:42 PM PDT 24
Finished	Jun 21 06:02:26 PM PDT 24
Peak memory	327228 kb
Host	smart-00c305e4-faa1-4415-b61b-05268b5e3106
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3836858879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3836858879
Directory	/workspace/16.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/16.hmac_long_msg.1428230140
Short name	T330
Test name
Test status
Simulation time	1280381048 ps
CPU time	17.16 seconds
Started	Jun 21 06:01:43 PM PDT 24
Finished	Jun 21 06:02:02 PM PDT 24
Peak memory	200100 kb
Host	smart-40894a79-0d19-4acd-9f08-66758714346c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1428230140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1428230140
Directory	/workspace/16.hmac_long_msg/latest

Test location	/workspace/coverage/default/16.hmac_smoke.2791803523
Short name	T224
Test name
Test status
Simulation time	65615982 ps
CPU time	1.6 seconds
Started	Jun 21 06:01:37 PM PDT 24
Finished	Jun 21 06:01:40 PM PDT 24
Peak memory	200000 kb
Host	smart-87520051-4111-493a-8a3e-b2e62dcef938
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2791803523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2791803523
Directory	/workspace/16.hmac_smoke/latest

Test location	/workspace/coverage/default/16.hmac_test_hmac_vectors.1159064403
Short name	T391
Test name
Test status
Simulation time	120005879 ps
CPU time	1.31 seconds
Started	Jun 21 06:01:45 PM PDT 24
Finished	Jun 21 06:01:48 PM PDT 24
Peak memory	200040 kb
Host	smart-0bcb4c2d-1181-4e63-95b0-59c84e0b21eb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159064403 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_hmac_vectors.1159064403
Directory	/workspace/16.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/16.hmac_test_sha384_vectors.146444729
Short name	T405
Test name
Test status
Simulation time	667452367916 ps
CPU time	2157.43 seconds
Started	Jun 21 06:01:49 PM PDT 24
Finished	Jun 21 06:37:48 PM PDT 24
Peak memory	216388 kb
Host	smart-1ba9ef5f-3fdf-4f9f-8d5e-2f3c94cc2ebd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=146444729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha384_vectors.146444729
Directory	/workspace/16.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/16.hmac_test_sha512_vectors.1235877063
Short name	T156
Test name
Test status
Simulation time	163686045967 ps
CPU time	2146.86 seconds
Started	Jun 21 06:01:44 PM PDT 24
Finished	Jun 21 06:37:33 PM PDT 24
Peak memory	216128 kb
Host	smart-f1b3a1fd-8f6c-4a2b-8a22-9f8720f30b0c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1235877063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha512_vectors.1235877063
Directory	/workspace/16.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/16.hmac_wipe_secret.1170337575
Short name	T118
Test name
Test status
Simulation time	1369151810 ps
CPU time	21.3 seconds
Started	Jun 21 06:01:46 PM PDT 24
Finished	Jun 21 06:02:09 PM PDT 24
Peak memory	200068 kb
Host	smart-a80b740f-c19d-44c1-8c46-817cd0c95a56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1170337575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1170337575
Directory	/workspace/16.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/17.hmac_alert_test.2955036419
Short name	T503
Test name
Test status
Simulation time	32981362 ps
CPU time	0.61 seconds
Started	Jun 21 06:01:44 PM PDT 24
Finished	Jun 21 06:01:47 PM PDT 24
Peak memory	195944 kb
Host	smart-a341b1a3-f2ae-46df-b223-9143c474a30b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955036419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2955036419
Directory	/workspace/17.hmac_alert_test/latest

Test location	/workspace/coverage/default/17.hmac_back_pressure.1968867100
Short name	T340
Test name
Test status
Simulation time	1859983519 ps
CPU time	40.8 seconds
Started	Jun 21 06:01:44 PM PDT 24
Finished	Jun 21 06:02:27 PM PDT 24
Peak memory	200044 kb
Host	smart-e0b2e0a5-d5f0-4d65-aa55-a2fac6707564
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1968867100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1968867100
Directory	/workspace/17.hmac_back_pressure/latest

Test location	/workspace/coverage/default/17.hmac_burst_wr.4021695825
Short name	T634
Test name
Test status
Simulation time	1473083932 ps
CPU time	39.77 seconds
Started	Jun 21 06:01:49 PM PDT 24
Finished	Jun 21 06:02:30 PM PDT 24
Peak memory	199968 kb
Host	smart-c7e76174-3cb5-4c1e-bedf-56efdfd25e9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4021695825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.4021695825
Directory	/workspace/17.hmac_burst_wr/latest

Test location	/workspace/coverage/default/17.hmac_datapath_stress.1237652409
Short name	T159
Test name
Test status
Simulation time	194590270 ps
CPU time	35.02 seconds
Started	Jun 21 06:01:43 PM PDT 24
Finished	Jun 21 06:02:20 PM PDT 24
Peak memory	315908 kb
Host	smart-23e6cdf6-072b-40ca-baae-68e8779d1dc1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1237652409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1237652409
Directory	/workspace/17.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/17.hmac_error.2768445636
Short name	T208
Test name
Test status
Simulation time	1909523484 ps
CPU time	108.65 seconds
Started	Jun 21 06:01:44 PM PDT 24
Finished	Jun 21 06:03:35 PM PDT 24
Peak memory	200060 kb
Host	smart-1e87689d-6cd4-4e4f-b8d9-d87b81278845
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768445636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2768445636
Directory	/workspace/17.hmac_error/latest

Test location	/workspace/coverage/default/17.hmac_long_msg.3483180972
Short name	T505
Test name
Test status
Simulation time	18066694914 ps
CPU time	87.21 seconds
Started	Jun 21 06:01:49 PM PDT 24
Finished	Jun 21 06:03:17 PM PDT 24
Peak memory	200036 kb
Host	smart-976e29ef-dfa0-403c-9929-66293a4004d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3483180972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3483180972
Directory	/workspace/17.hmac_long_msg/latest

Test location	/workspace/coverage/default/17.hmac_smoke.2656201964
Short name	T584
Test name
Test status
Simulation time	481313874 ps
CPU time	10.26 seconds
Started	Jun 21 06:01:42 PM PDT 24
Finished	Jun 21 06:01:53 PM PDT 24
Peak memory	200020 kb
Host	smart-28d8f1f0-5af9-408b-a3cb-05493fc18a9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2656201964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2656201964
Directory	/workspace/17.hmac_smoke/latest

Test location	/workspace/coverage/default/17.hmac_test_hmac_vectors.531133027
Short name	T220
Test name
Test status
Simulation time	233049923 ps
CPU time	1.05 seconds
Started	Jun 21 06:01:43 PM PDT 24
Finished	Jun 21 06:01:45 PM PDT 24
Peak memory	199736 kb
Host	smart-0ac097ae-bf08-4d24-9386-5f93c0d8bb47
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531133027 -assert nopostpr oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_hmac_vectors.531133027
Directory	/workspace/17.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/17.hmac_test_sha256_vectors.2016032579
Short name	T547
Test name
Test status
Simulation time	8586050336 ps
CPU time	454.94 seconds
Started	Jun 21 06:01:43 PM PDT 24
Finished	Jun 21 06:09:19 PM PDT 24
Peak memory	200152 kb
Host	smart-c0f079cb-e769-4a52-a32b-0127a1fa7f31
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2016032579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha256_vectors.2016032579
Directory	/workspace/17.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/17.hmac_test_sha384_vectors.4154358416
Short name	T201
Test name
Test status
Simulation time	251591708482 ps
CPU time	1750.8 seconds
Started	Jun 21 06:01:45 PM PDT 24
Finished	Jun 21 06:30:58 PM PDT 24
Peak memory	215644 kb
Host	smart-193199c0-d482-4d0a-b3e0-7f6c71315a94
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=4154358416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha384_vectors.4154358416
Directory	/workspace/17.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/17.hmac_test_sha512_vectors.1978495454
Short name	T181
Test name
Test status
Simulation time	30820723924 ps
CPU time	1590.11 seconds
Started	Jun 21 06:01:43 PM PDT 24
Finished	Jun 21 06:28:14 PM PDT 24
Peak memory	216180 kb
Host	smart-8e5cecb3-3443-44ac-b3dc-92d78b8edd5e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1978495454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha512_vectors.1978495454
Directory	/workspace/17.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/17.hmac_wipe_secret.629344481
Short name	T384
Test name
Test status
Simulation time	1423231945 ps
CPU time	22.35 seconds
Started	Jun 21 06:01:43 PM PDT 24
Finished	Jun 21 06:02:06 PM PDT 24
Peak memory	200084 kb
Host	smart-de74b14c-70a7-4955-908d-c98c4c452bc6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=629344481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.629344481
Directory	/workspace/17.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/18.hmac_alert_test.1729302379
Short name	T267
Test name
Test status
Simulation time	11200156 ps
CPU time	0.57 seconds
Started	Jun 21 06:01:47 PM PDT 24
Finished	Jun 21 06:01:49 PM PDT 24
Peak memory	194972 kb
Host	smart-764e758b-486a-4912-9095-e7846e7abab5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729302379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1729302379
Directory	/workspace/18.hmac_alert_test/latest

Test location	/workspace/coverage/default/18.hmac_back_pressure.536138361
Short name	T648
Test name
Test status
Simulation time	389033309 ps
CPU time	4.91 seconds
Started	Jun 21 06:01:46 PM PDT 24
Finished	Jun 21 06:01:53 PM PDT 24
Peak memory	200072 kb
Host	smart-228f38ac-9433-408e-8b22-12d82a3a18d2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=536138361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.536138361
Directory	/workspace/18.hmac_back_pressure/latest

Test location	/workspace/coverage/default/18.hmac_burst_wr.3281695972
Short name	T252
Test name
Test status
Simulation time	5418376011 ps
CPU time	76.05 seconds
Started	Jun 21 06:01:52 PM PDT 24
Finished	Jun 21 06:03:08 PM PDT 24
Peak memory	200088 kb
Host	smart-f53db125-53e8-46a1-86f8-be39a4db7945
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3281695972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3281695972
Directory	/workspace/18.hmac_burst_wr/latest

Test location	/workspace/coverage/default/18.hmac_datapath_stress.2898966942
Short name	T622
Test name
Test status
Simulation time	4094987364 ps
CPU time	1191.15 seconds
Started	Jun 21 06:01:45 PM PDT 24
Finished	Jun 21 06:21:38 PM PDT 24
Peak memory	738300 kb
Host	smart-1af8a598-f6f9-4207-bca3-58af74ee3fc2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2898966942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2898966942
Directory	/workspace/18.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/18.hmac_error.3954247417
Short name	T2
Test name
Test status
Simulation time	1313028873 ps
CPU time	77.05 seconds
Started	Jun 21 06:01:41 PM PDT 24
Finished	Jun 21 06:02:59 PM PDT 24
Peak memory	200008 kb
Host	smart-c3179c36-d6aa-4192-b28f-2a991228783b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954247417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3954247417
Directory	/workspace/18.hmac_error/latest

Test location	/workspace/coverage/default/18.hmac_long_msg.2409482007
Short name	T29
Test name
Test status
Simulation time	4490157544 ps
CPU time	67.51 seconds
Started	Jun 21 06:01:43 PM PDT 24
Finished	Jun 21 06:02:52 PM PDT 24
Peak memory	200148 kb
Host	smart-c72a0237-c290-459d-93c4-bea4e362ac13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2409482007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2409482007
Directory	/workspace/18.hmac_long_msg/latest

Test location	/workspace/coverage/default/18.hmac_smoke.1631565460
Short name	T276
Test name
Test status
Simulation time	1273628984 ps
CPU time	12.1 seconds
Started	Jun 21 06:01:42 PM PDT 24
Finished	Jun 21 06:01:55 PM PDT 24
Peak memory	200020 kb
Host	smart-f14dca54-1042-4ad3-8c01-8506c89253db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1631565460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1631565460
Directory	/workspace/18.hmac_smoke/latest

Test location	/workspace/coverage/default/18.hmac_test_hmac_vectors.3044861858
Short name	T583
Test name
Test status
Simulation time	254585169 ps
CPU time	1.15 seconds
Started	Jun 21 06:01:50 PM PDT 24
Finished	Jun 21 06:01:52 PM PDT 24
Peak memory	199976 kb
Host	smart-50ff2b74-7b19-4367-9a8b-6d0e9022fab2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044861858 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_hmac_vectors.3044861858
Directory	/workspace/18.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/18.hmac_test_sha256_vectors.832276190
Short name	T655
Test name
Test status
Simulation time	25689218957 ps
CPU time	453.56 seconds
Started	Jun 21 06:01:46 PM PDT 24
Finished	Jun 21 06:09:21 PM PDT 24
Peak memory	200140 kb
Host	smart-c3a38bd1-2d52-487c-93e2-5f70044ab02a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=832276190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha256_vectors.832276190
Directory	/workspace/18.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/18.hmac_test_sha384_vectors.1012492562
Short name	T189
Test name
Test status
Simulation time	336735454751 ps
CPU time	1912.29 seconds
Started	Jun 21 06:01:44 PM PDT 24
Finished	Jun 21 06:33:39 PM PDT 24
Peak memory	215624 kb
Host	smart-f7cf4e1d-b472-4f35-a41b-510dc062e8eb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1012492562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha384_vectors.1012492562
Directory	/workspace/18.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/18.hmac_test_sha512_vectors.693878106
Short name	T498
Test name
Test status
Simulation time	31371501392 ps
CPU time	1629.3 seconds
Started	Jun 21 06:01:51 PM PDT 24
Finished	Jun 21 06:29:02 PM PDT 24
Peak memory	215088 kb
Host	smart-d643a727-127e-4f57-a91e-aeb1e5f96322
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=693878106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha512_vectors.693878106
Directory	/workspace/18.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/18.hmac_wipe_secret.3925639008
Short name	T307
Test name
Test status
Simulation time	2060426583 ps
CPU time	26.31 seconds
Started	Jun 21 06:01:50 PM PDT 24
Finished	Jun 21 06:02:17 PM PDT 24
Peak memory	200000 kb
Host	smart-6b7100b2-83cf-49d8-b37e-e0070989aaf6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3925639008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3925639008
Directory	/workspace/18.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/19.hmac_alert_test.2432897327
Short name	T257
Test name
Test status
Simulation time	47676963 ps
CPU time	0.59 seconds
Started	Jun 21 06:01:50 PM PDT 24
Finished	Jun 21 06:01:52 PM PDT 24
Peak memory	195040 kb
Host	smart-d419ecc0-99f5-401d-a3db-95cd2a32b9ab
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432897327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2432897327
Directory	/workspace/19.hmac_alert_test/latest

Test location	/workspace/coverage/default/19.hmac_back_pressure.1346511764
Short name	T23
Test name
Test status
Simulation time	3542065560 ps
CPU time	46.72 seconds
Started	Jun 21 06:01:51 PM PDT 24
Finished	Jun 21 06:02:39 PM PDT 24
Peak memory	200112 kb
Host	smart-d9629e32-0bce-4cec-9187-733a9acf44ed
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1346511764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1346511764
Directory	/workspace/19.hmac_back_pressure/latest

Test location	/workspace/coverage/default/19.hmac_datapath_stress.2447926224
Short name	T165
Test name
Test status
Simulation time	70778490 ps
CPU time	4.25 seconds
Started	Jun 21 06:01:51 PM PDT 24
Finished	Jun 21 06:01:56 PM PDT 24
Peak memory	210492 kb
Host	smart-77e3d7c2-010c-4206-bfb4-af9d1750fcb5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2447926224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2447926224
Directory	/workspace/19.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/19.hmac_error.2650489626
Short name	T447
Test name
Test status
Simulation time	38505102599 ps
CPU time	96.73 seconds
Started	Jun 21 06:01:51 PM PDT 24
Finished	Jun 21 06:03:29 PM PDT 24
Peak memory	200124 kb
Host	smart-b6cd4d41-4d9c-41d2-aca0-2f943bd66602
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650489626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2650489626
Directory	/workspace/19.hmac_error/latest

Test location	/workspace/coverage/default/19.hmac_long_msg.2011865316
Short name	T450
Test name
Test status
Simulation time	2759412802 ps
CPU time	84.72 seconds
Started	Jun 21 06:01:49 PM PDT 24
Finished	Jun 21 06:03:15 PM PDT 24
Peak memory	200136 kb
Host	smart-a72b2161-c2d5-432a-8325-0aad73b7ab40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2011865316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2011865316
Directory	/workspace/19.hmac_long_msg/latest

Test location	/workspace/coverage/default/19.hmac_smoke.49728713
Short name	T363
Test name
Test status
Simulation time	180144600 ps
CPU time	4.53 seconds
Started	Jun 21 06:01:50 PM PDT 24
Finished	Jun 21 06:01:55 PM PDT 24
Peak memory	200072 kb
Host	smart-f78fe54a-cc1f-4f05-86b5-d9e346cf0b87
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=49728713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.49728713
Directory	/workspace/19.hmac_smoke/latest

Test location	/workspace/coverage/default/19.hmac_test_hmac_vectors.2333870630
Short name	T341
Test name
Test status
Simulation time	30099635 ps
CPU time	1.21 seconds
Started	Jun 21 06:01:51 PM PDT 24
Finished	Jun 21 06:01:53 PM PDT 24
Peak memory	199812 kb
Host	smart-b155f08d-24a9-4560-8fe0-92d5a8dbacd1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333870630 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_hmac_vectors.2333870630
Directory	/workspace/19.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/19.hmac_test_sha256_vectors.212505970
Short name	T559
Test name
Test status
Simulation time	110560880490 ps
CPU time	519.9 seconds
Started	Jun 21 06:01:53 PM PDT 24
Finished	Jun 21 06:10:33 PM PDT 24
Peak memory	200100 kb
Host	smart-33d36281-7ab2-4321-8ba7-bb0e762d3955
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=212505970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha256_vectors.212505970
Directory	/workspace/19.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/19.hmac_test_sha384_vectors.1705417676
Short name	T463
Test name
Test status
Simulation time	724665348037 ps
CPU time	1971.79 seconds
Started	Jun 21 06:01:50 PM PDT 24
Finished	Jun 21 06:34:43 PM PDT 24
Peak memory	216308 kb
Host	smart-7d357f59-4fb9-4242-8ec8-49c03287f612
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1705417676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha384_vectors.1705417676
Directory	/workspace/19.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/19.hmac_test_sha512_vectors.122093520
Short name	T507
Test name
Test status
Simulation time	99959223140 ps
CPU time	1864.7 seconds
Started	Jun 21 06:01:50 PM PDT 24
Finished	Jun 21 06:32:56 PM PDT 24
Peak memory	216592 kb
Host	smart-9e492449-0af2-4e12-9ed9-9ad765174577
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=122093520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha512_vectors.122093520
Directory	/workspace/19.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/19.hmac_wipe_secret.1434357681
Short name	T298
Test name
Test status
Simulation time	6823585169 ps
CPU time	64.04 seconds
Started	Jun 21 06:01:51 PM PDT 24
Finished	Jun 21 06:02:56 PM PDT 24
Peak memory	200152 kb
Host	smart-d361e106-1c01-4d33-a096-b8bd5e61fe15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1434357681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1434357681
Directory	/workspace/19.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/2.hmac_alert_test.1869008880
Short name	T538
Test name
Test status
Simulation time	53940941 ps
CPU time	0.65 seconds
Started	Jun 21 06:01:07 PM PDT 24
Finished	Jun 21 06:01:09 PM PDT 24
Peak memory	196056 kb
Host	smart-410de0fe-b54b-47fd-a239-3f465c0338ff
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869008880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1869008880
Directory	/workspace/2.hmac_alert_test/latest

Test location	/workspace/coverage/default/2.hmac_back_pressure.1330664397
Short name	T229
Test name
Test status
Simulation time	1963273300 ps
CPU time	45.99 seconds
Started	Jun 21 06:01:07 PM PDT 24
Finished	Jun 21 06:01:54 PM PDT 24
Peak memory	200048 kb
Host	smart-c83c39f4-343f-4ced-8dd2-6ef709da1574
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1330664397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1330664397
Directory	/workspace/2.hmac_back_pressure/latest

Test location	/workspace/coverage/default/2.hmac_burst_wr.2272296367
Short name	T640
Test name
Test status
Simulation time	5044611776 ps
CPU time	66.45 seconds
Started	Jun 21 06:01:08 PM PDT 24
Finished	Jun 21 06:02:16 PM PDT 24
Peak memory	200132 kb
Host	smart-83fdfcb4-17aa-438f-911a-84321cc4af17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2272296367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2272296367
Directory	/workspace/2.hmac_burst_wr/latest

Test location	/workspace/coverage/default/2.hmac_datapath_stress.689579881
Short name	T53
Test name
Test status
Simulation time	3763105804 ps
CPU time	651.93 seconds
Started	Jun 21 06:01:08 PM PDT 24
Finished	Jun 21 06:12:01 PM PDT 24
Peak memory	729468 kb
Host	smart-bea6968b-c73c-4464-950b-aaa65bdd8877
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=689579881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.689579881
Directory	/workspace/2.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/2.hmac_error.2359992102
Short name	T8
Test name
Test status
Simulation time	2087517847 ps
CPU time	36.88 seconds
Started	Jun 21 06:01:09 PM PDT 24
Finished	Jun 21 06:01:47 PM PDT 24
Peak memory	200056 kb
Host	smart-3db4604c-05bb-4615-ab8a-dae3271cb704
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359992102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2359992102
Directory	/workspace/2.hmac_error/latest

Test location	/workspace/coverage/default/2.hmac_long_msg.1973360207
Short name	T246
Test name
Test status
Simulation time	5193022655 ps
CPU time	20.89 seconds
Started	Jun 21 06:01:06 PM PDT 24
Finished	Jun 21 06:01:29 PM PDT 24
Peak memory	200148 kb
Host	smart-637c159c-e616-4867-917c-a3ea7a807238
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1973360207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1973360207
Directory	/workspace/2.hmac_long_msg/latest

Test location	/workspace/coverage/default/2.hmac_sec_cm.398615256
Short name	T40
Test name
Test status
Simulation time	203139783 ps
CPU time	1.06 seconds
Started	Jun 21 06:01:08 PM PDT 24
Finished	Jun 21 06:01:10 PM PDT 24
Peak memory	218168 kb
Host	smart-a8194201-897b-40ab-9606-d41e3853b33b
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398615256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.398615256
Directory	/workspace/2.hmac_sec_cm/latest

Test location	/workspace/coverage/default/2.hmac_smoke.4271936890
Short name	T312
Test name
Test status
Simulation time	2330130873 ps
CPU time	12.33 seconds
Started	Jun 21 06:01:09 PM PDT 24
Finished	Jun 21 06:01:23 PM PDT 24
Peak memory	200056 kb
Host	smart-9a3d88b1-20c9-46be-9c22-5141ff7dcd39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4271936890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.4271936890
Directory	/workspace/2.hmac_smoke/latest

Test location	/workspace/coverage/default/2.hmac_test_hmac_vectors.4111603401
Short name	T55
Test name
Test status
Simulation time	30727891 ps
CPU time	1.08 seconds
Started	Jun 21 06:01:07 PM PDT 24
Finished	Jun 21 06:01:10 PM PDT 24
Peak memory	199808 kb
Host	smart-bf3a8d3e-b1ae-44d2-93ca-15fe4f87e325
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111603401 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac_vectors.4111603401
Directory	/workspace/2.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/2.hmac_test_sha256_vectors.457265103
Short name	T436
Test name
Test status
Simulation time	7849716636 ps
CPU time	454.35 seconds
Started	Jun 21 06:01:06 PM PDT 24
Finished	Jun 21 06:08:42 PM PDT 24
Peak memory	200252 kb
Host	smart-b36001fc-51f6-48af-939b-dd36cc41570e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=457265103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.457265103
Directory	/workspace/2.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/2.hmac_test_sha384_vectors.4111116856
Short name	T217
Test name
Test status
Simulation time	32848495289 ps
CPU time	1768.35 seconds
Started	Jun 21 06:01:09 PM PDT 24
Finished	Jun 21 06:30:40 PM PDT 24
Peak memory	215588 kb
Host	smart-4989daa6-5a45-4825-8496-ff4d2acde669
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=4111116856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.4111116856
Directory	/workspace/2.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/2.hmac_test_sha512_vectors.1602399957
Short name	T247
Test name
Test status
Simulation time	89219102533 ps
CPU time	1870.09 seconds
Started	Jun 21 06:01:09 PM PDT 24
Finished	Jun 21 06:32:21 PM PDT 24
Peak memory	215592 kb
Host	smart-cd8908c1-670c-439b-829a-7b08ed019517
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1602399957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1602399957
Directory	/workspace/2.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/2.hmac_wipe_secret.4129303512
Short name	T250
Test name
Test status
Simulation time	3363625242 ps
CPU time	63.41 seconds
Started	Jun 21 06:01:09 PM PDT 24
Finished	Jun 21 06:02:14 PM PDT 24
Peak memory	200164 kb
Host	smart-876f8454-aa3e-4706-b631-4972990471e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4129303512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.4129303512
Directory	/workspace/2.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/20.hmac_alert_test.374714763
Short name	T392
Test name
Test status
Simulation time	42934426 ps
CPU time	0.63 seconds
Started	Jun 21 06:02:00 PM PDT 24
Finished	Jun 21 06:02:01 PM PDT 24
Peak memory	194908 kb
Host	smart-6389174f-cc02-46b2-ad58-508e84f562f0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374714763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.374714763
Directory	/workspace/20.hmac_alert_test/latest

Test location	/workspace/coverage/default/20.hmac_back_pressure.2305182144
Short name	T140
Test name
Test status
Simulation time	264900176 ps
CPU time	12.84 seconds
Started	Jun 21 06:02:06 PM PDT 24
Finished	Jun 21 06:02:19 PM PDT 24
Peak memory	199908 kb
Host	smart-bb2982ae-e705-4793-a7e2-84f409478c59
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2305182144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2305182144
Directory	/workspace/20.hmac_back_pressure/latest

Test location	/workspace/coverage/default/20.hmac_burst_wr.3710728099
Short name	T348
Test name
Test status
Simulation time	3580604833 ps
CPU time	53.45 seconds
Started	Jun 21 06:01:58 PM PDT 24
Finished	Jun 21 06:02:52 PM PDT 24
Peak memory	200152 kb
Host	smart-fc04cb45-bd76-40cb-934b-4b3326cf9d73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3710728099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3710728099
Directory	/workspace/20.hmac_burst_wr/latest

Test location	/workspace/coverage/default/20.hmac_datapath_stress.52828705
Short name	T572
Test name
Test status
Simulation time	3739555198 ps
CPU time	554.36 seconds
Started	Jun 21 06:01:58 PM PDT 24
Finished	Jun 21 06:11:13 PM PDT 24
Peak memory	734504 kb
Host	smart-547eef76-494d-4df0-b398-81f1c9deb737
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=52828705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.52828705
Directory	/workspace/20.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/20.hmac_error.1357734901
Short name	T488
Test name
Test status
Simulation time	20619589019 ps
CPU time	65.08 seconds
Started	Jun 21 06:02:00 PM PDT 24
Finished	Jun 21 06:03:05 PM PDT 24
Peak memory	200040 kb
Host	smart-9302f4f1-297c-498e-a7a3-abc5ffd7b699
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357734901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1357734901
Directory	/workspace/20.hmac_error/latest

Test location	/workspace/coverage/default/20.hmac_long_msg.946679292
Short name	T299
Test name
Test status
Simulation time	609906407 ps
CPU time	36.73 seconds
Started	Jun 21 06:01:51 PM PDT 24
Finished	Jun 21 06:02:29 PM PDT 24
Peak memory	200080 kb
Host	smart-c5017c2b-0e94-40d5-b7d7-08af598b2029
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=946679292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.946679292
Directory	/workspace/20.hmac_long_msg/latest

Test location	/workspace/coverage/default/20.hmac_smoke.821005665
Short name	T415
Test name
Test status
Simulation time	415803305 ps
CPU time	6.55 seconds
Started	Jun 21 06:01:53 PM PDT 24
Finished	Jun 21 06:02:00 PM PDT 24
Peak memory	200060 kb
Host	smart-13dbb724-eabe-451f-a348-b06193664a2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=821005665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.821005665
Directory	/workspace/20.hmac_smoke/latest

Test location	/workspace/coverage/default/20.hmac_test_hmac_vectors.1955066432
Short name	T311
Test name
Test status
Simulation time	125014160 ps
CPU time	1.36 seconds
Started	Jun 21 06:02:07 PM PDT 24
Finished	Jun 21 06:02:09 PM PDT 24
Peak memory	199876 kb
Host	smart-da5e5894-5f7d-4736-aebd-a9a804053c64
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955066432 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_hmac_vectors.1955066432
Directory	/workspace/20.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/20.hmac_test_sha256_vectors.89533671
Short name	T545
Test name
Test status
Simulation time	54259145265 ps
CPU time	478.53 seconds
Started	Jun 21 06:01:56 PM PDT 24
Finished	Jun 21 06:09:55 PM PDT 24
Peak memory	200100 kb
Host	smart-46bf0bed-d831-4202-8c1b-50bf9cd2f790
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=89533671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha256_vectors.89533671
Directory	/workspace/20.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/20.hmac_test_sha384_vectors.864739024
Short name	T512
Test name
Test status
Simulation time	437461171268 ps
CPU time	1837.22 seconds
Started	Jun 21 06:01:57 PM PDT 24
Finished	Jun 21 06:32:35 PM PDT 24
Peak memory	215668 kb
Host	smart-253f639b-19ef-4067-b332-4e4dae8c6fc8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=864739024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha384_vectors.864739024
Directory	/workspace/20.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/20.hmac_test_sha512_vectors.2533046013
Short name	T342
Test name
Test status
Simulation time	316557844671 ps
CPU time	1960.7 seconds
Started	Jun 21 06:02:05 PM PDT 24
Finished	Jun 21 06:34:47 PM PDT 24
Peak memory	215392 kb
Host	smart-80fabbcb-28fc-429a-a925-3da0ecd844cf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2533046013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha512_vectors.2533046013
Directory	/workspace/20.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/20.hmac_wipe_secret.3130500835
Short name	T51
Test name
Test status
Simulation time	4415838333 ps
CPU time	8.67 seconds
Started	Jun 21 06:01:56 PM PDT 24
Finished	Jun 21 06:02:06 PM PDT 24
Peak memory	200124 kb
Host	smart-2f83270e-ac42-4cd1-8674-03a5a55f92e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3130500835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3130500835
Directory	/workspace/20.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/21.hmac_alert_test.2276987136
Short name	T274
Test name
Test status
Simulation time	11133299 ps
CPU time	0.6 seconds
Started	Jun 21 06:02:06 PM PDT 24
Finished	Jun 21 06:02:07 PM PDT 24
Peak memory	194972 kb
Host	smart-89cf8dbf-172c-455d-84af-fa5cc205c36e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276987136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2276987136
Directory	/workspace/21.hmac_alert_test/latest

Test location	/workspace/coverage/default/21.hmac_back_pressure.859438021
Short name	T6
Test name
Test status
Simulation time	1397937825 ps
CPU time	18.13 seconds
Started	Jun 21 06:01:58 PM PDT 24
Finished	Jun 21 06:02:17 PM PDT 24
Peak memory	200100 kb
Host	smart-320def4a-3f9b-46dc-b1ec-c5d0121cbbea
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=859438021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.859438021
Directory	/workspace/21.hmac_back_pressure/latest

Test location	/workspace/coverage/default/21.hmac_burst_wr.1726283992
Short name	T625
Test name
Test status
Simulation time	13515413483 ps
CPU time	67.36 seconds
Started	Jun 21 06:02:08 PM PDT 24
Finished	Jun 21 06:03:16 PM PDT 24
Peak memory	200124 kb
Host	smart-69160abf-1805-47e5-a06b-259fccdc8517
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1726283992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1726283992
Directory	/workspace/21.hmac_burst_wr/latest

Test location	/workspace/coverage/default/21.hmac_datapath_stress.264169102
Short name	T495
Test name
Test status
Simulation time	662810556 ps
CPU time	91.99 seconds
Started	Jun 21 06:02:06 PM PDT 24
Finished	Jun 21 06:03:40 PM PDT 24
Peak memory	273600 kb
Host	smart-f49859bc-7cc6-4b5c-bb93-a4ecb1516013
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=264169102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.264169102
Directory	/workspace/21.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/21.hmac_error.1604549018
Short name	T514
Test name
Test status
Simulation time	3291061706 ps
CPU time	43.31 seconds
Started	Jun 21 06:02:06 PM PDT 24
Finished	Jun 21 06:02:50 PM PDT 24
Peak memory	200036 kb
Host	smart-073a9a12-b993-4fdb-af50-67f7c8266ddf
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604549018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1604549018
Directory	/workspace/21.hmac_error/latest

Test location	/workspace/coverage/default/21.hmac_long_msg.1234716787
Short name	T434
Test name
Test status
Simulation time	5073956847 ps
CPU time	75.47 seconds
Started	Jun 21 06:02:06 PM PDT 24
Finished	Jun 21 06:03:23 PM PDT 24
Peak memory	200044 kb
Host	smart-7b19fd09-3477-4359-a5e8-ca698c066f77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1234716787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1234716787
Directory	/workspace/21.hmac_long_msg/latest

Test location	/workspace/coverage/default/21.hmac_smoke.2505801529
Short name	T233
Test name
Test status
Simulation time	86986678 ps
CPU time	1.83 seconds
Started	Jun 21 06:01:58 PM PDT 24
Finished	Jun 21 06:02:01 PM PDT 24
Peak memory	200024 kb
Host	smart-b031d367-a0ce-421b-bc76-69a944bc2a40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2505801529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2505801529
Directory	/workspace/21.hmac_smoke/latest

Test location	/workspace/coverage/default/21.hmac_test_hmac_vectors.2892625794
Short name	T579
Test name
Test status
Simulation time	32023184 ps
CPU time	1.27 seconds
Started	Jun 21 06:02:05 PM PDT 24
Finished	Jun 21 06:02:08 PM PDT 24
Peak memory	200016 kb
Host	smart-80eadaf5-88f9-4bd2-ae8d-38323d3f7670
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892625794 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_hmac_vectors.2892625794
Directory	/workspace/21.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/21.hmac_test_sha256_vectors.1561301445
Short name	T366
Test name
Test status
Simulation time	7624352788 ps
CPU time	448 seconds
Started	Jun 21 06:02:08 PM PDT 24
Finished	Jun 21 06:09:37 PM PDT 24
Peak memory	200108 kb
Host	smart-44dfb439-bddd-45a7-a29d-2ffbbbad4258
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1561301445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha256_vectors.1561301445
Directory	/workspace/21.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/21.hmac_test_sha384_vectors.195968012
Short name	T314
Test name
Test status
Simulation time	32003903581 ps
CPU time	1922.52 seconds
Started	Jun 21 06:02:07 PM PDT 24
Finished	Jun 21 06:34:11 PM PDT 24
Peak memory	215816 kb
Host	smart-9f0adc46-3f45-48f4-bb35-ce3830f8f5f8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=195968012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha384_vectors.195968012
Directory	/workspace/21.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/21.hmac_test_sha512_vectors.4071470672
Short name	T86
Test name
Test status
Simulation time	270094220495 ps
CPU time	1959.27 seconds
Started	Jun 21 06:02:09 PM PDT 24
Finished	Jun 21 06:34:49 PM PDT 24
Peak memory	215540 kb
Host	smart-3176452a-2697-4727-975a-8c70e88aa7e5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=4071470672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha512_vectors.4071470672
Directory	/workspace/21.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/21.hmac_wipe_secret.2784583446
Short name	T403
Test name
Test status
Simulation time	28739639480 ps
CPU time	72.05 seconds
Started	Jun 21 06:02:05 PM PDT 24
Finished	Jun 21 06:03:17 PM PDT 24
Peak memory	200124 kb
Host	smart-ca2daf6c-d4e3-4a8b-b855-6ea02001ad73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2784583446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2784583446
Directory	/workspace/21.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/22.hmac_alert_test.1608134192
Short name	T191
Test name
Test status
Simulation time	12493215 ps
CPU time	0.57 seconds
Started	Jun 21 06:02:16 PM PDT 24
Finished	Jun 21 06:02:18 PM PDT 24
Peak memory	195704 kb
Host	smart-c6592eb8-fe7d-4408-857e-f9a50ea463eb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608134192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1608134192
Directory	/workspace/22.hmac_alert_test/latest

Test location	/workspace/coverage/default/22.hmac_burst_wr.1354371488
Short name	T141
Test name
Test status
Simulation time	720771851 ps
CPU time	32.25 seconds
Started	Jun 21 06:02:06 PM PDT 24
Finished	Jun 21 06:02:39 PM PDT 24
Peak memory	200080 kb
Host	smart-fc7b5a33-0ee2-4eaf-be21-2935820d6bb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1354371488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1354371488
Directory	/workspace/22.hmac_burst_wr/latest

Test location	/workspace/coverage/default/22.hmac_datapath_stress.2934720165
Short name	T12
Test name
Test status
Simulation time	3118535000 ps
CPU time	816.94 seconds
Started	Jun 21 06:02:13 PM PDT 24
Finished	Jun 21 06:15:51 PM PDT 24
Peak memory	710024 kb
Host	smart-9948d09e-23d9-477e-a572-ea4923efebce
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2934720165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2934720165
Directory	/workspace/22.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/22.hmac_error.512558016
Short name	T653
Test name
Test status
Simulation time	6059365512 ps
CPU time	102.17 seconds
Started	Jun 21 06:02:06 PM PDT 24
Finished	Jun 21 06:03:49 PM PDT 24
Peak memory	200016 kb
Host	smart-ef19462f-a43d-4d50-b3a3-c3b96d0ef52c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512558016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.512558016
Directory	/workspace/22.hmac_error/latest

Test location	/workspace/coverage/default/22.hmac_long_msg.547016809
Short name	T223
Test name
Test status
Simulation time	21433319656 ps
CPU time	97.35 seconds
Started	Jun 21 06:02:07 PM PDT 24
Finished	Jun 21 06:03:46 PM PDT 24
Peak memory	216324 kb
Host	smart-668a2d3f-64c0-4b7a-9e91-0efdc58ff8f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=547016809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.547016809
Directory	/workspace/22.hmac_long_msg/latest

Test location	/workspace/coverage/default/22.hmac_smoke.3644320295
Short name	T433
Test name
Test status
Simulation time	718578139 ps
CPU time	8.9 seconds
Started	Jun 21 06:02:07 PM PDT 24
Finished	Jun 21 06:02:17 PM PDT 24
Peak memory	200032 kb
Host	smart-e4edb3ec-cde9-46d9-bd6e-2ae8f4aac94c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3644320295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3644320295
Directory	/workspace/22.hmac_smoke/latest

Test location	/workspace/coverage/default/22.hmac_test_hmac_vectors.2507384551
Short name	T544
Test name
Test status
Simulation time	57532842 ps
CPU time	1.03 seconds
Started	Jun 21 06:02:13 PM PDT 24
Finished	Jun 21 06:02:15 PM PDT 24
Peak memory	199804 kb
Host	smart-b86b7638-6bbe-4dd9-b5e8-54b09a823f33
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507384551 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_hmac_vectors.2507384551
Directory	/workspace/22.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/22.hmac_test_sha256_vectors.2214432722
Short name	T4
Test name
Test status
Simulation time	120346951760 ps
CPU time	522.08 seconds
Started	Jun 21 06:02:05 PM PDT 24
Finished	Jun 21 06:10:48 PM PDT 24
Peak memory	200084 kb
Host	smart-0280ca51-f9c0-4f2a-9ce9-9d771e7fcbd3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2214432722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha256_vectors.2214432722
Directory	/workspace/22.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/22.hmac_test_sha384_vectors.3102056001
Short name	T518
Test name
Test status
Simulation time	168771050978 ps
CPU time	2171.68 seconds
Started	Jun 21 06:02:13 PM PDT 24
Finished	Jun 21 06:38:26 PM PDT 24
Peak memory	215412 kb
Host	smart-bea0df08-c3f8-4687-9a2c-b7523928f7e9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3102056001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha384_vectors.3102056001
Directory	/workspace/22.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/22.hmac_test_sha512_vectors.1757093027
Short name	T472
Test name
Test status
Simulation time	211132987129 ps
CPU time	1946.28 seconds
Started	Jun 21 06:02:08 PM PDT 24
Finished	Jun 21 06:34:35 PM PDT 24
Peak memory	215524 kb
Host	smart-beb84896-e70c-40a2-ae91-2b0f98d685be
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1757093027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha512_vectors.1757093027
Directory	/workspace/22.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/22.hmac_wipe_secret.822721877
Short name	T629
Test name
Test status
Simulation time	14372642319 ps
CPU time	107.02 seconds
Started	Jun 21 06:02:04 PM PDT 24
Finished	Jun 21 06:03:51 PM PDT 24
Peak memory	200120 kb
Host	smart-cc9e56aa-953d-41d5-a1c0-ed15a1b2d0f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=822721877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.822721877
Directory	/workspace/22.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/23.hmac_alert_test.1331800851
Short name	T561
Test name
Test status
Simulation time	19163410 ps
CPU time	0.6 seconds
Started	Jun 21 06:02:15 PM PDT 24
Finished	Jun 21 06:02:16 PM PDT 24
Peak memory	195984 kb
Host	smart-8eb6b1e0-a1c5-4029-b713-41d53a1f4c16
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331800851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1331800851
Directory	/workspace/23.hmac_alert_test/latest

Test location	/workspace/coverage/default/23.hmac_back_pressure.2752186921
Short name	T419
Test name
Test status
Simulation time	832362933 ps
CPU time	38.09 seconds
Started	Jun 21 06:02:13 PM PDT 24
Finished	Jun 21 06:02:52 PM PDT 24
Peak memory	200024 kb
Host	smart-dcc970db-0489-4d05-bf5f-aadff79c7ffb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2752186921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2752186921
Directory	/workspace/23.hmac_back_pressure/latest

Test location	/workspace/coverage/default/23.hmac_burst_wr.1739499978
Short name	T636
Test name
Test status
Simulation time	1511257753 ps
CPU time	78.17 seconds
Started	Jun 21 06:02:16 PM PDT 24
Finished	Jun 21 06:03:36 PM PDT 24
Peak memory	200076 kb
Host	smart-3636bda6-0bd3-4ce9-af5a-63671a7ae133
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1739499978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1739499978
Directory	/workspace/23.hmac_burst_wr/latest

Test location	/workspace/coverage/default/23.hmac_datapath_stress.2071576564
Short name	T595
Test name
Test status
Simulation time	11113158189 ps
CPU time	747.7 seconds
Started	Jun 21 06:02:15 PM PDT 24
Finished	Jun 21 06:14:43 PM PDT 24
Peak memory	720704 kb
Host	smart-99b33c51-1c6b-4e7f-bbce-9051c56867b3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2071576564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2071576564
Directory	/workspace/23.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/23.hmac_error.2373870088
Short name	T457
Test name
Test status
Simulation time	102078382 ps
CPU time	5.71 seconds
Started	Jun 21 06:02:16 PM PDT 24
Finished	Jun 21 06:02:22 PM PDT 24
Peak memory	199980 kb
Host	smart-a35b2c3b-5b89-438e-a768-28b535f32505
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373870088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2373870088
Directory	/workspace/23.hmac_error/latest

Test location	/workspace/coverage/default/23.hmac_long_msg.3890487011
Short name	T54
Test name
Test status
Simulation time	5794124316 ps
CPU time	20.2 seconds
Started	Jun 21 06:02:13 PM PDT 24
Finished	Jun 21 06:02:34 PM PDT 24
Peak memory	200116 kb
Host	smart-d24ee2b3-7b86-4576-9c10-5778673ab1d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3890487011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3890487011
Directory	/workspace/23.hmac_long_msg/latest

Test location	/workspace/coverage/default/23.hmac_smoke.2080545467
Short name	T265
Test name
Test status
Simulation time	1216598814 ps
CPU time	8.76 seconds
Started	Jun 21 06:02:16 PM PDT 24
Finished	Jun 21 06:02:26 PM PDT 24
Peak memory	200068 kb
Host	smart-5bed732b-29a4-4478-8775-a7c9135bf327
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2080545467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2080545467
Directory	/workspace/23.hmac_smoke/latest

Test location	/workspace/coverage/default/23.hmac_test_hmac_vectors.1567010338
Short name	T367
Test name
Test status
Simulation time	86780966 ps
CPU time	1.49 seconds
Started	Jun 21 06:02:14 PM PDT 24
Finished	Jun 21 06:02:17 PM PDT 24
Peak memory	200000 kb
Host	smart-86a1f846-3b23-431b-81c5-3d7c6c128f3d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567010338 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_hmac_vectors.1567010338
Directory	/workspace/23.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/23.hmac_test_sha256_vectors.3551586402
Short name	T526
Test name
Test status
Simulation time	19184308653 ps
CPU time	450.12 seconds
Started	Jun 21 06:02:16 PM PDT 24
Finished	Jun 21 06:09:48 PM PDT 24
Peak memory	200116 kb
Host	smart-5073f1ee-133d-47a5-9b24-5c08c6cef9a8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3551586402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha256_vectors.3551586402
Directory	/workspace/23.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/23.hmac_test_sha384_vectors.2196985605
Short name	T426
Test name
Test status
Simulation time	512813941353 ps
CPU time	1747.47 seconds
Started	Jun 21 06:02:15 PM PDT 24
Finished	Jun 21 06:31:23 PM PDT 24
Peak memory	216368 kb
Host	smart-bde4301f-4f73-49c3-a85f-471e598f4bb7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2196985605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha384_vectors.2196985605
Directory	/workspace/23.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/23.hmac_wipe_secret.2172303455
Short name	T117
Test name
Test status
Simulation time	5439286121 ps
CPU time	51.81 seconds
Started	Jun 21 06:02:16 PM PDT 24
Finished	Jun 21 06:03:09 PM PDT 24
Peak memory	200132 kb
Host	smart-4941c2aa-7b57-46e7-8bfe-47880a9d5c43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2172303455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2172303455
Directory	/workspace/23.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/24.hmac_alert_test.3216594403
Short name	T296
Test name
Test status
Simulation time	37929675 ps
CPU time	0.62 seconds
Started	Jun 21 06:02:21 PM PDT 24
Finished	Jun 21 06:02:23 PM PDT 24
Peak memory	196056 kb
Host	smart-8ce9f081-062c-4b7e-bf49-65f18b134515
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216594403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3216594403
Directory	/workspace/24.hmac_alert_test/latest

Test location	/workspace/coverage/default/24.hmac_back_pressure.1303378026
Short name	T194
Test name
Test status
Simulation time	3759931683 ps
CPU time	31.64 seconds
Started	Jun 21 06:02:16 PM PDT 24
Finished	Jun 21 06:02:49 PM PDT 24
Peak memory	200112 kb
Host	smart-9e80a827-21d9-4963-aa7d-cff6bdb90613
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1303378026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1303378026
Directory	/workspace/24.hmac_back_pressure/latest

Test location	/workspace/coverage/default/24.hmac_burst_wr.3319525363
Short name	T397
Test name
Test status
Simulation time	209710411 ps
CPU time	11.15 seconds
Started	Jun 21 06:02:13 PM PDT 24
Finished	Jun 21 06:02:25 PM PDT 24
Peak memory	200036 kb
Host	smart-f2f07cd7-e0b1-470a-9e82-afb709d88858
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3319525363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3319525363
Directory	/workspace/24.hmac_burst_wr/latest

Test location	/workspace/coverage/default/24.hmac_datapath_stress.3199553765
Short name	T151
Test name
Test status
Simulation time	2915514076 ps
CPU time	869.78 seconds
Started	Jun 21 06:02:16 PM PDT 24
Finished	Jun 21 06:16:47 PM PDT 24
Peak memory	756212 kb
Host	smart-3d4a8494-8b58-4698-bd0c-2f78a4d69ae9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3199553765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3199553765
Directory	/workspace/24.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/24.hmac_error.159273257
Short name	T193
Test name
Test status
Simulation time	5171748583 ps
CPU time	138.81 seconds
Started	Jun 21 06:02:14 PM PDT 24
Finished	Jun 21 06:04:34 PM PDT 24
Peak memory	200072 kb
Host	smart-9b409bc0-d6d9-40b4-a898-c96a4deeba66
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159273257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.159273257
Directory	/workspace/24.hmac_error/latest

Test location	/workspace/coverage/default/24.hmac_long_msg.3152330449
Short name	T428
Test name
Test status
Simulation time	24058881354 ps
CPU time	69.15 seconds
Started	Jun 21 06:02:14 PM PDT 24
Finished	Jun 21 06:03:24 PM PDT 24
Peak memory	200100 kb
Host	smart-495bebd9-96ab-45ac-ae60-67a74b3e7a08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3152330449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3152330449
Directory	/workspace/24.hmac_long_msg/latest

Test location	/workspace/coverage/default/24.hmac_smoke.2136315690
Short name	T453
Test name
Test status
Simulation time	1882664188 ps
CPU time	7.27 seconds
Started	Jun 21 06:02:14 PM PDT 24
Finished	Jun 21 06:02:22 PM PDT 24
Peak memory	200020 kb
Host	smart-b52656c0-0473-4f5c-90d9-d8d705fb1f49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2136315690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2136315690
Directory	/workspace/24.hmac_smoke/latest

Test location	/workspace/coverage/default/24.hmac_test_hmac_vectors.379116850
Short name	T372
Test name
Test status
Simulation time	35218754 ps
CPU time	1.38 seconds
Started	Jun 21 06:02:26 PM PDT 24
Finished	Jun 21 06:02:28 PM PDT 24
Peak memory	200068 kb
Host	smart-62a53c56-82c7-45ad-a7cd-c4308fcc8358
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379116850 -assert nopostpr oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_hmac_vectors.379116850
Directory	/workspace/24.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/24.hmac_test_sha256_vectors.2730893458
Short name	T210
Test name
Test status
Simulation time	7923181928 ps
CPU time	448.12 seconds
Started	Jun 21 06:02:22 PM PDT 24
Finished	Jun 21 06:09:51 PM PDT 24
Peak memory	200124 kb
Host	smart-b3aeba80-c721-4189-a0c4-743d0efe4919
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2730893458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha256_vectors.2730893458
Directory	/workspace/24.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/24.hmac_test_sha384_vectors.2689593690
Short name	T260
Test name
Test status
Simulation time	49469039906 ps
CPU time	1809.74 seconds
Started	Jun 21 06:02:23 PM PDT 24
Finished	Jun 21 06:32:34 PM PDT 24
Peak memory	215548 kb
Host	smart-c4cca972-fec8-4f06-8c70-55e36f02f251
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2689593690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha384_vectors.2689593690
Directory	/workspace/24.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/24.hmac_test_sha512_vectors.3511819405
Short name	T649
Test name
Test status
Simulation time	61625629782 ps
CPU time	1789.19 seconds
Started	Jun 21 06:02:21 PM PDT 24
Finished	Jun 21 06:32:11 PM PDT 24
Peak memory	215608 kb
Host	smart-252bbf46-cf3f-4052-a42d-55bbe5752d8c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3511819405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha512_vectors.3511819405
Directory	/workspace/24.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/24.hmac_wipe_secret.1030424045
Short name	T317
Test name
Test status
Simulation time	572347079 ps
CPU time	30.4 seconds
Started	Jun 21 06:02:26 PM PDT 24
Finished	Jun 21 06:02:57 PM PDT 24
Peak memory	200080 kb
Host	smart-d163cb91-cd04-4899-b3c7-08b10dae5648
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1030424045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1030424045
Directory	/workspace/24.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/25.hmac_alert_test.3921296597
Short name	T173
Test name
Test status
Simulation time	43447357 ps
CPU time	0.58 seconds
Started	Jun 21 06:02:33 PM PDT 24
Finished	Jun 21 06:02:34 PM PDT 24
Peak memory	194960 kb
Host	smart-09137f38-9831-40c1-bfa5-d0a3ea177ebc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921296597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3921296597
Directory	/workspace/25.hmac_alert_test/latest

Test location	/workspace/coverage/default/25.hmac_back_pressure.313745823
Short name	T643
Test name
Test status
Simulation time	287612833 ps
CPU time	6.3 seconds
Started	Jun 21 06:02:23 PM PDT 24
Finished	Jun 21 06:02:30 PM PDT 24
Peak memory	199952 kb
Host	smart-360819e1-bf1b-4146-9127-7da1a23fcb63
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=313745823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.313745823
Directory	/workspace/25.hmac_back_pressure/latest

Test location	/workspace/coverage/default/25.hmac_burst_wr.2967417820
Short name	T283
Test name
Test status
Simulation time	3150954021 ps
CPU time	23.11 seconds
Started	Jun 21 06:02:23 PM PDT 24
Finished	Jun 21 06:02:47 PM PDT 24
Peak memory	200136 kb
Host	smart-296618e3-9615-4a35-acc6-0b0af68612bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2967417820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2967417820
Directory	/workspace/25.hmac_burst_wr/latest

Test location	/workspace/coverage/default/25.hmac_datapath_stress.4008382513
Short name	T142
Test name
Test status
Simulation time	6935532137 ps
CPU time	817.67 seconds
Started	Jun 21 06:02:21 PM PDT 24
Finished	Jun 21 06:15:59 PM PDT 24
Peak memory	751228 kb
Host	smart-ac7558d4-c78a-45f9-a7d6-1956a33ea2ae
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4008382513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.4008382513
Directory	/workspace/25.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/25.hmac_error.375167344
Short name	T439
Test name
Test status
Simulation time	49800783919 ps
CPU time	155.19 seconds
Started	Jun 21 06:02:23 PM PDT 24
Finished	Jun 21 06:04:59 PM PDT 24
Peak memory	200072 kb
Host	smart-0ec4c918-f2c1-49ae-93d3-a2cf2159c2ae
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375167344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.375167344
Directory	/workspace/25.hmac_error/latest

Test location	/workspace/coverage/default/25.hmac_long_msg.1155847838
Short name	T610
Test name
Test status
Simulation time	866880673 ps
CPU time	7.14 seconds
Started	Jun 21 06:02:26 PM PDT 24
Finished	Jun 21 06:02:34 PM PDT 24
Peak memory	200072 kb
Host	smart-bb19a3e5-afd3-4d5f-aa4a-3cd762403a10
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1155847838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1155847838
Directory	/workspace/25.hmac_long_msg/latest

Test location	/workspace/coverage/default/25.hmac_smoke.3083227186
Short name	T272
Test name
Test status
Simulation time	198001955 ps
CPU time	0.73 seconds
Started	Jun 21 06:02:24 PM PDT 24
Finished	Jun 21 06:02:25 PM PDT 24
Peak memory	196652 kb
Host	smart-a0d26bfc-f3b4-47dd-a653-e919f5700ea1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3083227186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3083227186
Directory	/workspace/25.hmac_smoke/latest

Test location	/workspace/coverage/default/25.hmac_test_hmac_vectors.2095587798
Short name	T353
Test name
Test status
Simulation time	45865928 ps
CPU time	1.14 seconds
Started	Jun 21 06:02:23 PM PDT 24
Finished	Jun 21 06:02:25 PM PDT 24
Peak memory	199856 kb
Host	smart-57164947-8a00-4a72-a350-2c406682c75c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095587798 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_hmac_vectors.2095587798
Directory	/workspace/25.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/25.hmac_test_sha256_vectors.4277125754
Short name	T273
Test name
Test status
Simulation time	138149841357 ps
CPU time	544.73 seconds
Started	Jun 21 06:02:22 PM PDT 24
Finished	Jun 21 06:11:27 PM PDT 24
Peak memory	200124 kb
Host	smart-5452e7d4-f756-4a72-9126-ab736d2ab03e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4277125754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha256_vectors.4277125754
Directory	/workspace/25.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/25.hmac_test_sha384_vectors.1237380466
Short name	T232
Test name
Test status
Simulation time	166569012262 ps
CPU time	2020.68 seconds
Started	Jun 21 06:02:23 PM PDT 24
Finished	Jun 21 06:36:05 PM PDT 24
Peak memory	216360 kb
Host	smart-87f496df-2bb0-485c-975c-a0df51804e8c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1237380466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha384_vectors.1237380466
Directory	/workspace/25.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/25.hmac_wipe_secret.1430441381
Short name	T184
Test name
Test status
Simulation time	3682440433 ps
CPU time	64.43 seconds
Started	Jun 21 06:02:22 PM PDT 24
Finished	Jun 21 06:03:27 PM PDT 24
Peak memory	200100 kb
Host	smart-41987a2e-2de4-4a83-8e29-74d94c408281
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1430441381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1430441381
Directory	/workspace/25.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/26.hmac_alert_test.1704119567
Short name	T449
Test name
Test status
Simulation time	17713310 ps
CPU time	0.59 seconds
Started	Jun 21 06:02:34 PM PDT 24
Finished	Jun 21 06:02:35 PM PDT 24
Peak memory	194976 kb
Host	smart-930d0577-1550-4beb-9b29-bf202608f486
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704119567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1704119567
Directory	/workspace/26.hmac_alert_test/latest

Test location	/workspace/coverage/default/26.hmac_back_pressure.2270932489
Short name	T423
Test name
Test status
Simulation time	482850164 ps
CPU time	23.86 seconds
Started	Jun 21 06:02:33 PM PDT 24
Finished	Jun 21 06:02:58 PM PDT 24
Peak memory	200084 kb
Host	smart-1fb5d2b5-5594-41aa-98c0-90c6be25885e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2270932489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2270932489
Directory	/workspace/26.hmac_back_pressure/latest

Test location	/workspace/coverage/default/26.hmac_burst_wr.2355073065
Short name	T598
Test name
Test status
Simulation time	5131783909 ps
CPU time	51.87 seconds
Started	Jun 21 06:02:33 PM PDT 24
Finished	Jun 21 06:03:26 PM PDT 24
Peak memory	200056 kb
Host	smart-db056ef3-58e4-414a-b034-ef18d7c9c20e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2355073065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2355073065
Directory	/workspace/26.hmac_burst_wr/latest

Test location	/workspace/coverage/default/26.hmac_datapath_stress.423917576
Short name	T339
Test name
Test status
Simulation time	7299057650 ps
CPU time	548.56 seconds
Started	Jun 21 06:02:35 PM PDT 24
Finished	Jun 21 06:11:44 PM PDT 24
Peak memory	683848 kb
Host	smart-780a67f9-8ee0-4ad0-ba24-208b397dc617
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=423917576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.423917576
Directory	/workspace/26.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/26.hmac_error.2956625259
Short name	T124
Test name
Test status
Simulation time	194341804459 ps
CPU time	203.08 seconds
Started	Jun 21 06:02:32 PM PDT 24
Finished	Jun 21 06:05:56 PM PDT 24
Peak memory	200040 kb
Host	smart-f5f50140-79c1-46af-91f3-bdf2d70b0061
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956625259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2956625259
Directory	/workspace/26.hmac_error/latest

Test location	/workspace/coverage/default/26.hmac_long_msg.3248107534
Short name	T540
Test name
Test status
Simulation time	100090072171 ps
CPU time	143.92 seconds
Started	Jun 21 06:02:35 PM PDT 24
Finished	Jun 21 06:05:00 PM PDT 24
Peak memory	216448 kb
Host	smart-f7d85b4b-6049-41a8-8389-31c2f9419089
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3248107534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3248107534
Directory	/workspace/26.hmac_long_msg/latest

Test location	/workspace/coverage/default/26.hmac_smoke.2506761057
Short name	T349
Test name
Test status
Simulation time	407489534 ps
CPU time	5.21 seconds
Started	Jun 21 06:02:32 PM PDT 24
Finished	Jun 21 06:02:39 PM PDT 24
Peak memory	200048 kb
Host	smart-967d555d-5f76-478d-9908-79a19cd4204d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2506761057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2506761057
Directory	/workspace/26.hmac_smoke/latest

Test location	/workspace/coverage/default/26.hmac_test_hmac_vectors.947929909
Short name	T255
Test name
Test status
Simulation time	213988518 ps
CPU time	1.34 seconds
Started	Jun 21 06:02:32 PM PDT 24
Finished	Jun 21 06:02:34 PM PDT 24
Peak memory	200168 kb
Host	smart-989c56f3-50ae-454e-948b-88b22b52c451
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947929909 -assert nopostpr oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_hmac_vectors.947929909
Directory	/workspace/26.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/26.hmac_test_sha256_vectors.623765078
Short name	T13
Test name
Test status
Simulation time	7652735555 ps
CPU time	428.24 seconds
Started	Jun 21 06:02:34 PM PDT 24
Finished	Jun 21 06:09:43 PM PDT 24
Peak memory	200124 kb
Host	smart-60ff9d6a-22ce-4ed2-b68e-cd26b282762e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=623765078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha256_vectors.623765078
Directory	/workspace/26.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/26.hmac_test_sha384_vectors.4027987951
Short name	T473
Test name
Test status
Simulation time	105248530628 ps
CPU time	2001.2 seconds
Started	Jun 21 06:02:34 PM PDT 24
Finished	Jun 21 06:35:56 PM PDT 24
Peak memory	215544 kb
Host	smart-56be1f2b-f7cb-41c3-bd9a-6d6f94f2799c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=4027987951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha384_vectors.4027987951
Directory	/workspace/26.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/26.hmac_test_sha512_vectors.1119287250
Short name	T542
Test name
Test status
Simulation time	30888925936 ps
CPU time	1709.09 seconds
Started	Jun 21 06:02:33 PM PDT 24
Finished	Jun 21 06:31:03 PM PDT 24
Peak memory	216072 kb
Host	smart-639321e4-3c9a-4eba-a8af-02013204198c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1119287250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha512_vectors.1119287250
Directory	/workspace/26.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/26.hmac_wipe_secret.3238523571
Short name	T599
Test name
Test status
Simulation time	3211368118 ps
CPU time	61.83 seconds
Started	Jun 21 06:02:32 PM PDT 24
Finished	Jun 21 06:03:35 PM PDT 24
Peak memory	200156 kb
Host	smart-ad65c22e-0b54-44b0-8045-aae30843befd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3238523571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3238523571
Directory	/workspace/26.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/27.hmac_alert_test.1763059891
Short name	T560
Test name
Test status
Simulation time	14045498 ps
CPU time	0.62 seconds
Started	Jun 21 06:02:32 PM PDT 24
Finished	Jun 21 06:02:34 PM PDT 24
Peak memory	196744 kb
Host	smart-11520e3e-642d-4423-9af8-f6a2b05c7c3b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763059891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1763059891
Directory	/workspace/27.hmac_alert_test/latest

Test location	/workspace/coverage/default/27.hmac_back_pressure.603276413
Short name	T211
Test name
Test status
Simulation time	49957309 ps
CPU time	2.55 seconds
Started	Jun 21 06:02:34 PM PDT 24
Finished	Jun 21 06:02:37 PM PDT 24
Peak memory	200012 kb
Host	smart-b66eb15e-1202-4a76-b5cb-ae602780a9f2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=603276413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.603276413
Directory	/workspace/27.hmac_back_pressure/latest

Test location	/workspace/coverage/default/27.hmac_burst_wr.3011994653
Short name	T205
Test name
Test status
Simulation time	454360226 ps
CPU time	4.97 seconds
Started	Jun 21 06:02:32 PM PDT 24
Finished	Jun 21 06:02:38 PM PDT 24
Peak memory	200024 kb
Host	smart-9ee1e09d-1e3e-4a3c-9679-2cc27c62cb02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3011994653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3011994653
Directory	/workspace/27.hmac_burst_wr/latest

Test location	/workspace/coverage/default/27.hmac_datapath_stress.1930763784
Short name	T241
Test name
Test status
Simulation time	63060852 ps
CPU time	1.61 seconds
Started	Jun 21 06:02:31 PM PDT 24
Finished	Jun 21 06:02:34 PM PDT 24
Peak memory	200044 kb
Host	smart-8fa1c84f-9706-4817-8cde-2042e27a99f3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1930763784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1930763784
Directory	/workspace/27.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/27.hmac_error.1682033155
Short name	T533
Test name
Test status
Simulation time	7284734197 ps
CPU time	33.16 seconds
Started	Jun 21 06:02:32 PM PDT 24
Finished	Jun 21 06:03:06 PM PDT 24
Peak memory	200096 kb
Host	smart-b1956ced-1434-4b2b-9d1c-61d7f0618aef
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682033155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1682033155
Directory	/workspace/27.hmac_error/latest

Test location	/workspace/coverage/default/27.hmac_smoke.2165807226
Short name	T624
Test name
Test status
Simulation time	163524055 ps
CPU time	2.32 seconds
Started	Jun 21 06:02:32 PM PDT 24
Finished	Jun 21 06:02:35 PM PDT 24
Peak memory	200100 kb
Host	smart-924dfabc-f996-416e-944f-b2916c7742cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2165807226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2165807226
Directory	/workspace/27.hmac_smoke/latest

Test location	/workspace/coverage/default/27.hmac_test_hmac_vectors.2309244096
Short name	T536
Test name
Test status
Simulation time	509777217 ps
CPU time	1.47 seconds
Started	Jun 21 06:02:33 PM PDT 24
Finished	Jun 21 06:02:35 PM PDT 24
Peak memory	200016 kb
Host	smart-9d180e31-3960-442b-8b37-8a9a7e6c7024
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309244096 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_hmac_vectors.2309244096
Directory	/workspace/27.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/27.hmac_test_sha256_vectors.3704557253
Short name	T168
Test name
Test status
Simulation time	44058633088 ps
CPU time	417.33 seconds
Started	Jun 21 06:02:31 PM PDT 24
Finished	Jun 21 06:09:29 PM PDT 24
Peak memory	200144 kb
Host	smart-163f45ad-de5f-451d-9f52-b490802df8cc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3704557253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha256_vectors.3704557253
Directory	/workspace/27.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/27.hmac_test_sha384_vectors.2483515960
Short name	T84
Test name
Test status
Simulation time	62362900814 ps
CPU time	1719.17 seconds
Started	Jun 21 06:02:31 PM PDT 24
Finished	Jun 21 06:31:12 PM PDT 24
Peak memory	215676 kb
Host	smart-ce13991b-3be7-4867-9365-9a224d30bb30
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2483515960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha384_vectors.2483515960
Directory	/workspace/27.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/27.hmac_test_sha512_vectors.541819471
Short name	T212
Test name
Test status
Simulation time	593885501424 ps
CPU time	1911 seconds
Started	Jun 21 06:02:32 PM PDT 24
Finished	Jun 21 06:34:25 PM PDT 24
Peak memory	216512 kb
Host	smart-8712c7d3-1238-4b28-ac53-b52685d0444b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=541819471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha512_vectors.541819471
Directory	/workspace/27.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/27.hmac_wipe_secret.392444916
Short name	T601
Test name
Test status
Simulation time	12107675294 ps
CPU time	87.46 seconds
Started	Jun 21 06:02:32 PM PDT 24
Finished	Jun 21 06:04:00 PM PDT 24
Peak memory	200120 kb
Host	smart-120a05b9-25d1-462a-97f5-e6b8aaa2bed7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=392444916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.392444916
Directory	/workspace/27.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/28.hmac_alert_test.3472672332
Short name	T631
Test name
Test status
Simulation time	29928587 ps
CPU time	0.55 seconds
Started	Jun 21 06:02:41 PM PDT 24
Finished	Jun 21 06:02:42 PM PDT 24
Peak memory	195704 kb
Host	smart-90429c2e-6ccd-4450-8084-5ae9a21a573d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472672332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3472672332
Directory	/workspace/28.hmac_alert_test/latest

Test location	/workspace/coverage/default/28.hmac_back_pressure.780609550
Short name	T139
Test name
Test status
Simulation time	10345564789 ps
CPU time	56 seconds
Started	Jun 21 06:02:41 PM PDT 24
Finished	Jun 21 06:03:37 PM PDT 24
Peak memory	200156 kb
Host	smart-18bf29a1-fd4f-423a-a366-7069c234bb77
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=780609550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.780609550
Directory	/workspace/28.hmac_back_pressure/latest

Test location	/workspace/coverage/default/28.hmac_burst_wr.2279489997
Short name	T448
Test name
Test status
Simulation time	1260534570 ps
CPU time	24.97 seconds
Started	Jun 21 06:02:40 PM PDT 24
Finished	Jun 21 06:03:06 PM PDT 24
Peak memory	200072 kb
Host	smart-acfff379-9d24-4827-a574-f07d7a3d736e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2279489997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2279489997
Directory	/workspace/28.hmac_burst_wr/latest

Test location	/workspace/coverage/default/28.hmac_datapath_stress.45070482
Short name	T345
Test name
Test status
Simulation time	3064718471 ps
CPU time	798.41 seconds
Started	Jun 21 06:02:40 PM PDT 24
Finished	Jun 21 06:15:59 PM PDT 24
Peak memory	666888 kb
Host	smart-280aaaa2-70f1-45b4-865a-b45a8039d387
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=45070482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.45070482
Directory	/workspace/28.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/28.hmac_error.972234360
Short name	T228
Test name
Test status
Simulation time	1433038473 ps
CPU time	79.75 seconds
Started	Jun 21 06:02:43 PM PDT 24
Finished	Jun 21 06:04:04 PM PDT 24
Peak memory	200036 kb
Host	smart-f350e5a8-09cf-48a0-a6dd-60240d6fdcd5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972234360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.972234360
Directory	/workspace/28.hmac_error/latest

Test location	/workspace/coverage/default/28.hmac_long_msg.2390977726
Short name	T373
Test name
Test status
Simulation time	31520097431 ps
CPU time	100.39 seconds
Started	Jun 21 06:02:39 PM PDT 24
Finished	Jun 21 06:04:20 PM PDT 24
Peak memory	200108 kb
Host	smart-d9123de5-3dc1-45a8-984c-a95edfadb8db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2390977726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2390977726
Directory	/workspace/28.hmac_long_msg/latest

Test location	/workspace/coverage/default/28.hmac_smoke.1879991740
Short name	T606
Test name
Test status
Simulation time	773630800 ps
CPU time	11.23 seconds
Started	Jun 21 06:02:44 PM PDT 24
Finished	Jun 21 06:02:56 PM PDT 24
Peak memory	200076 kb
Host	smart-e4cf84f8-bb48-4041-aa68-cb49173472fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1879991740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1879991740
Directory	/workspace/28.hmac_smoke/latest

Test location	/workspace/coverage/default/28.hmac_test_hmac_vectors.3375159112
Short name	T466
Test name
Test status
Simulation time	195527980 ps
CPU time	1.09 seconds
Started	Jun 21 06:02:41 PM PDT 24
Finished	Jun 21 06:02:42 PM PDT 24
Peak memory	199652 kb
Host	smart-e268ca8e-c3c0-473f-87a6-6d2a9897774b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375159112 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_hmac_vectors.3375159112
Directory	/workspace/28.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/28.hmac_test_sha256_vectors.420601798
Short name	T231
Test name
Test status
Simulation time	42711896221 ps
CPU time	468.32 seconds
Started	Jun 21 06:02:44 PM PDT 24
Finished	Jun 21 06:10:33 PM PDT 24
Peak memory	200140 kb
Host	smart-c3962fb4-e986-4300-829d-10ac8ce74e64
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=420601798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha256_vectors.420601798
Directory	/workspace/28.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/28.hmac_test_sha384_vectors.1566997935
Short name	T476
Test name
Test status
Simulation time	64258865330 ps
CPU time	1776.15 seconds
Started	Jun 21 06:02:42 PM PDT 24
Finished	Jun 21 06:32:19 PM PDT 24
Peak memory	215744 kb
Host	smart-a81ad107-7cac-4991-9563-c16417ab7e47
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1566997935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha384_vectors.1566997935
Directory	/workspace/28.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/28.hmac_test_sha512_vectors.334541986
Short name	T427
Test name
Test status
Simulation time	367943121865 ps
CPU time	2155.47 seconds
Started	Jun 21 06:02:45 PM PDT 24
Finished	Jun 21 06:38:42 PM PDT 24
Peak memory	215508 kb
Host	smart-4bfbcce3-955c-4617-93b0-5c1f0830cc07
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=334541986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha512_vectors.334541986
Directory	/workspace/28.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/28.hmac_wipe_secret.58869449
Short name	T350
Test name
Test status
Simulation time	3675355565 ps
CPU time	27.61 seconds
Started	Jun 21 06:02:44 PM PDT 24
Finished	Jun 21 06:03:12 PM PDT 24
Peak memory	199828 kb
Host	smart-b5c0002d-4714-48c0-b020-1d6b490278eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=58869449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.58869449
Directory	/workspace/28.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/29.hmac_alert_test.3616018426
Short name	T587
Test name
Test status
Simulation time	19922398 ps
CPU time	0.61 seconds
Started	Jun 21 06:02:53 PM PDT 24
Finished	Jun 21 06:02:54 PM PDT 24
Peak memory	196080 kb
Host	smart-72541e5a-d6f1-49fa-8a06-6d0204023fad
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616018426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3616018426
Directory	/workspace/29.hmac_alert_test/latest

Test location	/workspace/coverage/default/29.hmac_back_pressure.873251163
Short name	T407
Test name
Test status
Simulation time	2056718701 ps
CPU time	25.07 seconds
Started	Jun 21 06:02:44 PM PDT 24
Finished	Jun 21 06:03:09 PM PDT 24
Peak memory	199696 kb
Host	smart-29d16a60-2b1f-4cbf-8e61-7d0c736b5c90
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=873251163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.873251163
Directory	/workspace/29.hmac_back_pressure/latest

Test location	/workspace/coverage/default/29.hmac_burst_wr.3267143207
Short name	T153
Test name
Test status
Simulation time	1512716690 ps
CPU time	21.32 seconds
Started	Jun 21 06:02:40 PM PDT 24
Finished	Jun 21 06:03:02 PM PDT 24
Peak memory	200116 kb
Host	smart-48551e56-58e8-4552-b9fa-b4c70a53ce11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3267143207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3267143207
Directory	/workspace/29.hmac_burst_wr/latest

Test location	/workspace/coverage/default/29.hmac_datapath_stress.2351366569
Short name	T129
Test name
Test status
Simulation time	2830733710 ps
CPU time	793.04 seconds
Started	Jun 21 06:02:39 PM PDT 24
Finished	Jun 21 06:15:53 PM PDT 24
Peak memory	725492 kb
Host	smart-1cd101aa-8175-41d4-8ab7-bf21628f1dad
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2351366569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2351366569
Directory	/workspace/29.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/29.hmac_error.467007061
Short name	T199
Test name
Test status
Simulation time	31438613255 ps
CPU time	87.65 seconds
Started	Jun 21 06:02:40 PM PDT 24
Finished	Jun 21 06:04:09 PM PDT 24
Peak memory	200124 kb
Host	smart-ea9b048d-dcfc-43ed-864b-2252ee294d1d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467007061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.467007061
Directory	/workspace/29.hmac_error/latest

Test location	/workspace/coverage/default/29.hmac_long_msg.74873119
Short name	T537
Test name
Test status
Simulation time	451119194 ps
CPU time	6.65 seconds
Started	Jun 21 06:02:39 PM PDT 24
Finished	Jun 21 06:02:47 PM PDT 24
Peak memory	200100 kb
Host	smart-fbba6e97-f876-40df-8b2a-bbe24e72cd73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=74873119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.74873119
Directory	/workspace/29.hmac_long_msg/latest

Test location	/workspace/coverage/default/29.hmac_smoke.294833361
Short name	T225
Test name
Test status
Simulation time	139163371 ps
CPU time	3.04 seconds
Started	Jun 21 06:02:39 PM PDT 24
Finished	Jun 21 06:02:42 PM PDT 24
Peak memory	200008 kb
Host	smart-037db7b4-aa55-4d64-b55d-0e4d58195ecf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=294833361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.294833361
Directory	/workspace/29.hmac_smoke/latest

Test location	/workspace/coverage/default/29.hmac_test_hmac_vectors.2352583425
Short name	T214
Test name
Test status
Simulation time	125086635 ps
CPU time	1.21 seconds
Started	Jun 21 06:02:49 PM PDT 24
Finished	Jun 21 06:02:50 PM PDT 24
Peak memory	200056 kb
Host	smart-f62fad40-8518-4f26-8828-326b7d712504
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352583425 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_hmac_vectors.2352583425
Directory	/workspace/29.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/29.hmac_test_sha256_vectors.1569961698
Short name	T302
Test name
Test status
Simulation time	40523221258 ps
CPU time	440.55 seconds
Started	Jun 21 06:02:51 PM PDT 24
Finished	Jun 21 06:10:13 PM PDT 24
Peak memory	200032 kb
Host	smart-b29bbdc2-715e-4b36-9b42-9e62f34d46ea
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1569961698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha256_vectors.1569961698
Directory	/workspace/29.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/29.hmac_test_sha384_vectors.1724927050
Short name	T627
Test name
Test status
Simulation time	577654471301 ps
CPU time	2072.11 seconds
Started	Jun 21 06:02:50 PM PDT 24
Finished	Jun 21 06:37:23 PM PDT 24
Peak memory	215608 kb
Host	smart-25e294d2-e915-4a39-9ab8-a827de453751
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1724927050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha384_vectors.1724927050
Directory	/workspace/29.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/29.hmac_test_sha512_vectors.2042816291
Short name	T275
Test name
Test status
Simulation time	105918025563 ps
CPU time	1702.71 seconds
Started	Jun 21 06:02:51 PM PDT 24
Finished	Jun 21 06:31:15 PM PDT 24
Peak memory	216492 kb
Host	smart-0bea453e-466f-43dc-80b8-5485e42f2c19
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2042816291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha512_vectors.2042816291
Directory	/workspace/29.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/29.hmac_wipe_secret.1866333529
Short name	T371
Test name
Test status
Simulation time	103693421938 ps
CPU time	124.22 seconds
Started	Jun 21 06:02:39 PM PDT 24
Finished	Jun 21 06:04:44 PM PDT 24
Peak memory	200156 kb
Host	smart-0c92d04d-fac6-4c83-bcbd-f12933d0604f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1866333529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1866333529
Directory	/workspace/29.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/3.hmac_alert_test.1621721038
Short name	T581
Test name
Test status
Simulation time	119378099 ps
CPU time	0.6 seconds
Started	Jun 21 06:01:08 PM PDT 24
Finished	Jun 21 06:01:10 PM PDT 24
Peak memory	194948 kb
Host	smart-4547a811-aa98-48b3-a032-119bbd84ec71
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621721038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1621721038
Directory	/workspace/3.hmac_alert_test/latest

Test location	/workspace/coverage/default/3.hmac_back_pressure.787889523
Short name	T563
Test name
Test status
Simulation time	2959088884 ps
CPU time	35.05 seconds
Started	Jun 21 06:01:05 PM PDT 24
Finished	Jun 21 06:01:42 PM PDT 24
Peak memory	200124 kb
Host	smart-f7472858-fbfa-49c7-a986-21ab039e4497
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=787889523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.787889523
Directory	/workspace/3.hmac_back_pressure/latest

Test location	/workspace/coverage/default/3.hmac_burst_wr.4004985515
Short name	T292
Test name
Test status
Simulation time	66502090362 ps
CPU time	83.37 seconds
Started	Jun 21 06:01:10 PM PDT 24
Finished	Jun 21 06:02:35 PM PDT 24
Peak memory	200024 kb
Host	smart-23680db4-e5f9-481f-934a-bbbb7a48c39e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4004985515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.4004985515
Directory	/workspace/3.hmac_burst_wr/latest

Test location	/workspace/coverage/default/3.hmac_datapath_stress.3525016898
Short name	T593
Test name
Test status
Simulation time	16270422463 ps
CPU time	1187.5 seconds
Started	Jun 21 06:01:10 PM PDT 24
Finished	Jun 21 06:21:00 PM PDT 24
Peak memory	772632 kb
Host	smart-b85e638a-9985-4db5-89ae-109fd7d0afd1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3525016898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3525016898
Directory	/workspace/3.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/3.hmac_error.1764050809
Short name	T50
Test name
Test status
Simulation time	791873788 ps
CPU time	11.03 seconds
Started	Jun 21 06:01:11 PM PDT 24
Finished	Jun 21 06:01:23 PM PDT 24
Peak memory	199980 kb
Host	smart-b6ad322b-d1d8-4ffa-a7ac-d3b5f565e3e7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764050809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1764050809
Directory	/workspace/3.hmac_error/latest

Test location	/workspace/coverage/default/3.hmac_long_msg.2219556796
Short name	T389
Test name
Test status
Simulation time	22091222105 ps
CPU time	95.28 seconds
Started	Jun 21 06:01:09 PM PDT 24
Finished	Jun 21 06:02:45 PM PDT 24
Peak memory	208260 kb
Host	smart-529820f6-d27a-4ae7-892e-0c698276e074
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2219556796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2219556796
Directory	/workspace/3.hmac_long_msg/latest

Test location	/workspace/coverage/default/3.hmac_sec_cm.2388647272
Short name	T44
Test name
Test status
Simulation time	435088303 ps
CPU time	0.94 seconds
Started	Jun 21 06:01:09 PM PDT 24
Finished	Jun 21 06:01:12 PM PDT 24
Peak memory	218280 kb
Host	smart-cc510e16-2b3a-4559-ad1b-add5e49e2944
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388647272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2388647272
Directory	/workspace/3.hmac_sec_cm/latest

Test location	/workspace/coverage/default/3.hmac_smoke.1750036787
Short name	T443
Test name
Test status
Simulation time	143175449 ps
CPU time	5.8 seconds
Started	Jun 21 06:01:09 PM PDT 24
Finished	Jun 21 06:01:16 PM PDT 24
Peak memory	200004 kb
Host	smart-7ef4bd83-4551-4239-bca8-004227c3a92a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1750036787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1750036787
Directory	/workspace/3.hmac_smoke/latest

Test location	/workspace/coverage/default/3.hmac_test_hmac_vectors.213424085
Short name	T359
Test name
Test status
Simulation time	233799108 ps
CPU time	1.36 seconds
Started	Jun 21 06:01:07 PM PDT 24
Finished	Jun 21 06:01:10 PM PDT 24
Peak memory	200016 kb
Host	smart-d447ab60-29ea-4369-9dc0-7b5965ed6e45
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213424085 -assert nopostpr oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac_vectors.213424085
Directory	/workspace/3.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/3.hmac_test_sha256_vectors.212858653
Short name	T14
Test name
Test status
Simulation time	339181384904 ps
CPU time	490.71 seconds
Started	Jun 21 06:01:07 PM PDT 24
Finished	Jun 21 06:09:19 PM PDT 24
Peak memory	200112 kb
Host	smart-a46e03ff-073c-49fe-9b2d-7081e19f28a2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=212858653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.212858653
Directory	/workspace/3.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/3.hmac_test_sha512_vectors.2625987374
Short name	T395
Test name
Test status
Simulation time	617230258342 ps
CPU time	1930.86 seconds
Started	Jun 21 06:01:09 PM PDT 24
Finished	Jun 21 06:33:22 PM PDT 24
Peak memory	216324 kb
Host	smart-422988a4-9bc9-485a-9add-a5db1c026bfc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2625987374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2625987374
Directory	/workspace/3.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/3.hmac_wipe_secret.4132904163
Short name	T501
Test name
Test status
Simulation time	4808144734 ps
CPU time	56.39 seconds
Started	Jun 21 06:01:12 PM PDT 24
Finished	Jun 21 06:02:09 PM PDT 24
Peak memory	200120 kb
Host	smart-92fa323a-abef-4cd4-bd45-a6c2e673dbd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4132904163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.4132904163
Directory	/workspace/3.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/30.hmac_back_pressure.2468475230
Short name	T24
Test name
Test status
Simulation time	279002278 ps
CPU time	3.91 seconds
Started	Jun 21 06:02:50 PM PDT 24
Finished	Jun 21 06:02:55 PM PDT 24
Peak memory	200084 kb
Host	smart-babf5a54-ef37-44f5-ae4e-b66702b799dc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2468475230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2468475230
Directory	/workspace/30.hmac_back_pressure/latest

Test location	/workspace/coverage/default/30.hmac_burst_wr.262939110
Short name	T136
Test name
Test status
Simulation time	1220271815 ps
CPU time	31.24 seconds
Started	Jun 21 06:02:53 PM PDT 24
Finished	Jun 21 06:03:25 PM PDT 24
Peak memory	200064 kb
Host	smart-84708fc9-82be-439b-aa0b-2df6b5838fe0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=262939110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.262939110
Directory	/workspace/30.hmac_burst_wr/latest

Test location	/workspace/coverage/default/30.hmac_datapath_stress.2280947835
Short name	T178
Test name
Test status
Simulation time	1214260243 ps
CPU time	145.95 seconds
Started	Jun 21 06:02:51 PM PDT 24
Finished	Jun 21 06:05:17 PM PDT 24
Peak memory	455292 kb
Host	smart-fea7dd44-f1b5-4deb-95be-a14063cd6549
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2280947835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2280947835
Directory	/workspace/30.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/30.hmac_error.2806064568
Short name	T380
Test name
Test status
Simulation time	14227602391 ps
CPU time	89.41 seconds
Started	Jun 21 06:02:51 PM PDT 24
Finished	Jun 21 06:04:21 PM PDT 24
Peak memory	200096 kb
Host	smart-ef85abf5-f295-45c8-92b6-0cc038decc65
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806064568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2806064568
Directory	/workspace/30.hmac_error/latest

Test location	/workspace/coverage/default/30.hmac_long_msg.2691338627
Short name	T421
Test name
Test status
Simulation time	13502509125 ps
CPU time	93.64 seconds
Started	Jun 21 06:02:50 PM PDT 24
Finished	Jun 21 06:04:24 PM PDT 24
Peak memory	200268 kb
Host	smart-97500ee4-1434-4a18-88da-fbc79d779d40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2691338627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2691338627
Directory	/workspace/30.hmac_long_msg/latest

Test location	/workspace/coverage/default/30.hmac_smoke.1385814037
Short name	T323
Test name
Test status
Simulation time	195068985 ps
CPU time	9.59 seconds
Started	Jun 21 06:02:50 PM PDT 24
Finished	Jun 21 06:03:00 PM PDT 24
Peak memory	200060 kb
Host	smart-acb9d18f-f0a7-4dbc-b0f6-460b80170923
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1385814037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1385814037
Directory	/workspace/30.hmac_smoke/latest

Test location	/workspace/coverage/default/30.hmac_test_hmac_vectors.903267493
Short name	T539
Test name
Test status
Simulation time	76151546 ps
CPU time	1.4 seconds
Started	Jun 21 06:02:49 PM PDT 24
Finished	Jun 21 06:02:51 PM PDT 24
Peak memory	200068 kb
Host	smart-3c09a9ca-a459-4319-86f4-72f65cc90199
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903267493 -assert nopostpr oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_hmac_vectors.903267493
Directory	/workspace/30.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/30.hmac_test_sha256_vectors.930697097
Short name	T162
Test name
Test status
Simulation time	154127674968 ps
CPU time	477.71 seconds
Started	Jun 21 06:02:51 PM PDT 24
Finished	Jun 21 06:10:49 PM PDT 24
Peak memory	200112 kb
Host	smart-577460aa-b5aa-428f-be9a-818f746ce852
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=930697097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha256_vectors.930697097
Directory	/workspace/30.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/30.hmac_test_sha384_vectors.1591836047
Short name	T490
Test name
Test status
Simulation time	65828307200 ps
CPU time	1759.64 seconds
Started	Jun 21 06:02:53 PM PDT 24
Finished	Jun 21 06:32:13 PM PDT 24
Peak memory	215964 kb
Host	smart-db532665-f3b7-4224-80ef-df493e91516b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1591836047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha384_vectors.1591836047
Directory	/workspace/30.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/30.hmac_test_sha512_vectors.1203033668
Short name	T475
Test name
Test status
Simulation time	443492298323 ps
CPU time	2003.37 seconds
Started	Jun 21 06:02:51 PM PDT 24
Finished	Jun 21 06:36:15 PM PDT 24
Peak memory	216484 kb
Host	smart-f00546d4-e9d6-48cc-8ff3-d69949b4dfd3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1203033668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha512_vectors.1203033668
Directory	/workspace/30.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/30.hmac_wipe_secret.1909791292
Short name	T20
Test name
Test status
Simulation time	912486090 ps
CPU time	43.39 seconds
Started	Jun 21 06:02:54 PM PDT 24
Finished	Jun 21 06:03:38 PM PDT 24
Peak memory	200156 kb
Host	smart-97603f66-8fa6-4be7-832c-8744b127924d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1909791292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1909791292
Directory	/workspace/30.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/31.hmac_alert_test.3961543536
Short name	T383
Test name
Test status
Simulation time	15446441 ps
CPU time	0.61 seconds
Started	Jun 21 06:03:05 PM PDT 24
Finished	Jun 21 06:03:07 PM PDT 24
Peak memory	195848 kb
Host	smart-fd18b081-a9c2-48d6-9e88-1bbd343b295e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961543536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3961543536
Directory	/workspace/31.hmac_alert_test/latest

Test location	/workspace/coverage/default/31.hmac_back_pressure.3647156481
Short name	T25
Test name
Test status
Simulation time	235138352 ps
CPU time	12.58 seconds
Started	Jun 21 06:03:06 PM PDT 24
Finished	Jun 21 06:03:19 PM PDT 24
Peak memory	199936 kb
Host	smart-5d6c752c-6fe4-4f86-a9d0-011da0bdbe5a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3647156481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3647156481
Directory	/workspace/31.hmac_back_pressure/latest

Test location	/workspace/coverage/default/31.hmac_datapath_stress.1533133230
Short name	T169
Test name
Test status
Simulation time	2335820354 ps
CPU time	577.95 seconds
Started	Jun 21 06:03:04 PM PDT 24
Finished	Jun 21 06:12:42 PM PDT 24
Peak memory	686600 kb
Host	smart-91512fbb-ccaa-4ef7-a92c-837a108fe77a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1533133230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1533133230
Directory	/workspace/31.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/31.hmac_error.2106976203
Short name	T31
Test name
Test status
Simulation time	6538185468 ps
CPU time	97.6 seconds
Started	Jun 21 06:03:03 PM PDT 24
Finished	Jun 21 06:04:41 PM PDT 24
Peak memory	200072 kb
Host	smart-9a03650d-1e2d-4dfd-82ff-623359d83796
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106976203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2106976203
Directory	/workspace/31.hmac_error/latest

Test location	/workspace/coverage/default/31.hmac_long_msg.813267994
Short name	T479
Test name
Test status
Simulation time	4744542581 ps
CPU time	72.54 seconds
Started	Jun 21 06:03:06 PM PDT 24
Finished	Jun 21 06:04:19 PM PDT 24
Peak memory	200140 kb
Host	smart-0398896b-000c-4d57-954e-2377b7be40d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=813267994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.813267994
Directory	/workspace/31.hmac_long_msg/latest

Test location	/workspace/coverage/default/31.hmac_smoke.1435284509
Short name	T401
Test name
Test status
Simulation time	1871894996 ps
CPU time	12.71 seconds
Started	Jun 21 06:02:51 PM PDT 24
Finished	Jun 21 06:03:05 PM PDT 24
Peak memory	200024 kb
Host	smart-e4fea714-ce35-461a-ae0e-499d6bd17979
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1435284509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1435284509
Directory	/workspace/31.hmac_smoke/latest

Test location	/workspace/coverage/default/31.hmac_stress_all.1237110133
Short name	T368
Test name
Test status
Simulation time	4213106105 ps
CPU time	47.88 seconds
Started	Jun 21 06:03:05 PM PDT 24
Finished	Jun 21 06:03:54 PM PDT 24
Peak memory	208320 kb
Host	smart-a9310062-d613-416a-a789-3bb6117a9ee0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237110133 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1237110133
Directory	/workspace/31.hmac_stress_all/latest

Test location	/workspace/coverage/default/31.hmac_test_hmac_vectors.475958138
Short name	T244
Test name
Test status
Simulation time	30148407 ps
CPU time	1.1 seconds
Started	Jun 21 06:03:03 PM PDT 24
Finished	Jun 21 06:03:05 PM PDT 24
Peak memory	199976 kb
Host	smart-2e358282-26e9-47f1-af8d-1757623adc46
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475958138 -assert nopostpr oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_hmac_vectors.475958138
Directory	/workspace/31.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/31.hmac_test_sha256_vectors.13259795
Short name	T435
Test name
Test status
Simulation time	166499584462 ps
CPU time	491.8 seconds
Started	Jun 21 06:03:05 PM PDT 24
Finished	Jun 21 06:11:18 PM PDT 24
Peak memory	200136 kb
Host	smart-0b0d418e-0aea-4959-b607-161d7d09f6ae
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=13259795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha256_vectors.13259795
Directory	/workspace/31.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/31.hmac_test_sha512_vectors.961757794
Short name	T347
Test name
Test status
Simulation time	834840758533 ps
CPU time	2120.85 seconds
Started	Jun 21 06:03:04 PM PDT 24
Finished	Jun 21 06:38:26 PM PDT 24
Peak memory	215716 kb
Host	smart-96037f1d-4977-4099-a62d-bf50ee4b20e0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=961757794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha512_vectors.961757794
Directory	/workspace/31.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/31.hmac_wipe_secret.1708388326
Short name	T115
Test name
Test status
Simulation time	536351657 ps
CPU time	26.02 seconds
Started	Jun 21 06:03:06 PM PDT 24
Finished	Jun 21 06:03:33 PM PDT 24
Peak memory	200064 kb
Host	smart-1294503a-b827-40b7-8f5d-f914498625c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1708388326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1708388326
Directory	/workspace/31.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/32.hmac_alert_test.558439326
Short name	T361
Test name
Test status
Simulation time	13919182 ps
CPU time	0.63 seconds
Started	Jun 21 06:03:18 PM PDT 24
Finished	Jun 21 06:03:19 PM PDT 24
Peak memory	196136 kb
Host	smart-c66cfcd8-0c00-43bb-a2ac-284928819361
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558439326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.558439326
Directory	/workspace/32.hmac_alert_test/latest

Test location	/workspace/coverage/default/32.hmac_back_pressure.3574307125
Short name	T326
Test name
Test status
Simulation time	1433570638 ps
CPU time	17.67 seconds
Started	Jun 21 06:03:04 PM PDT 24
Finished	Jun 21 06:03:22 PM PDT 24
Peak memory	200004 kb
Host	smart-17fafd1f-43d3-4f5d-9505-68a848e044f7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3574307125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3574307125
Directory	/workspace/32.hmac_back_pressure/latest

Test location	/workspace/coverage/default/32.hmac_burst_wr.4155455054
Short name	T499
Test name
Test status
Simulation time	423074976 ps
CPU time	12.48 seconds
Started	Jun 21 06:03:03 PM PDT 24
Finished	Jun 21 06:03:16 PM PDT 24
Peak memory	200040 kb
Host	smart-b8b6758b-2d94-4b4a-a7c1-c971cc2f6865
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4155455054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.4155455054
Directory	/workspace/32.hmac_burst_wr/latest

Test location	/workspace/coverage/default/32.hmac_datapath_stress.1511652124
Short name	T121
Test name
Test status
Simulation time	4991150551 ps
CPU time	336.7 seconds
Started	Jun 21 06:03:05 PM PDT 24
Finished	Jun 21 06:08:43 PM PDT 24
Peak memory	663400 kb
Host	smart-b5747689-6cec-45d0-b4a3-c2963ca66f87
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1511652124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1511652124
Directory	/workspace/32.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/32.hmac_error.2165816025
Short name	T376
Test name
Test status
Simulation time	10715899994 ps
CPU time	69.15 seconds
Started	Jun 21 06:03:05 PM PDT 24
Finished	Jun 21 06:04:15 PM PDT 24
Peak memory	200036 kb
Host	smart-d62e34cf-9bf3-4d22-b5f2-3f83eade09a4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165816025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2165816025
Directory	/workspace/32.hmac_error/latest

Test location	/workspace/coverage/default/32.hmac_long_msg.2221710743
Short name	T269
Test name
Test status
Simulation time	3003194867 ps
CPU time	46.38 seconds
Started	Jun 21 06:03:04 PM PDT 24
Finished	Jun 21 06:03:52 PM PDT 24
Peak memory	200152 kb
Host	smart-9b8d8b6c-256d-48ae-9e9b-5fecf8954a89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2221710743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2221710743
Directory	/workspace/32.hmac_long_msg/latest

Test location	/workspace/coverage/default/32.hmac_smoke.2341494690
Short name	T619
Test name
Test status
Simulation time	2620390908 ps
CPU time	14.48 seconds
Started	Jun 21 06:03:04 PM PDT 24
Finished	Jun 21 06:03:19 PM PDT 24
Peak memory	200148 kb
Host	smart-71796644-26d0-4142-be07-e4bdf9cd8399
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2341494690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2341494690
Directory	/workspace/32.hmac_smoke/latest

Test location	/workspace/coverage/default/32.hmac_test_hmac_vectors.2444443280
Short name	T517
Test name
Test status
Simulation time	65279036 ps
CPU time	1.04 seconds
Started	Jun 21 06:03:06 PM PDT 24
Finished	Jun 21 06:03:08 PM PDT 24
Peak memory	199868 kb
Host	smart-346984ca-4d24-4101-8d5d-7212acdcd194
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444443280 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_hmac_vectors.2444443280
Directory	/workspace/32.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/32.hmac_test_sha256_vectors.2912366939
Short name	T49
Test name
Test status
Simulation time	16247272601 ps
CPU time	444.83 seconds
Started	Jun 21 06:03:05 PM PDT 24
Finished	Jun 21 06:10:31 PM PDT 24
Peak memory	200112 kb
Host	smart-2b3a9e3c-09b0-4161-b908-091627182080
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2912366939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha256_vectors.2912366939
Directory	/workspace/32.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/32.hmac_test_sha384_vectors.1538602524
Short name	T645
Test name
Test status
Simulation time	101596130474 ps
CPU time	1774.37 seconds
Started	Jun 21 06:03:04 PM PDT 24
Finished	Jun 21 06:32:39 PM PDT 24
Peak memory	215664 kb
Host	smart-60cd846a-b4f1-479b-880c-6db3a89da707
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1538602524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha384_vectors.1538602524
Directory	/workspace/32.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/32.hmac_test_sha512_vectors.3427421790
Short name	T506
Test name
Test status
Simulation time	253371745140 ps
CPU time	1800.64 seconds
Started	Jun 21 06:03:05 PM PDT 24
Finished	Jun 21 06:33:07 PM PDT 24
Peak memory	215516 kb
Host	smart-9ceb5a08-8408-45e8-9872-383a0d6700f1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3427421790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha512_vectors.3427421790
Directory	/workspace/32.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/32.hmac_wipe_secret.3850094930
Short name	T114
Test name
Test status
Simulation time	4324357353 ps
CPU time	88.69 seconds
Started	Jun 21 06:03:05 PM PDT 24
Finished	Jun 21 06:04:35 PM PDT 24
Peak memory	199940 kb
Host	smart-dd3196a0-06dc-47d1-be04-745d7bb7a556
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3850094930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3850094930
Directory	/workspace/32.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/33.hmac_alert_test.1025524786
Short name	T568
Test name
Test status
Simulation time	38320309 ps
CPU time	0.6 seconds
Started	Jun 21 06:03:16 PM PDT 24
Finished	Jun 21 06:03:17 PM PDT 24
Peak memory	195996 kb
Host	smart-902f4539-c047-4e06-b9e2-021480546fb4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025524786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1025524786
Directory	/workspace/33.hmac_alert_test/latest

Test location	/workspace/coverage/default/33.hmac_back_pressure.631596477
Short name	T603
Test name
Test status
Simulation time	1119880217 ps
CPU time	58.57 seconds
Started	Jun 21 06:03:20 PM PDT 24
Finished	Jun 21 06:04:19 PM PDT 24
Peak memory	199980 kb
Host	smart-c0cdd242-c678-44ac-b89d-edace91c89e0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=631596477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.631596477
Directory	/workspace/33.hmac_back_pressure/latest

Test location	/workspace/coverage/default/33.hmac_burst_wr.2372533523
Short name	T442
Test name
Test status
Simulation time	696154455 ps
CPU time	37.48 seconds
Started	Jun 21 06:03:15 PM PDT 24
Finished	Jun 21 06:03:54 PM PDT 24
Peak memory	200064 kb
Host	smart-ebdd4789-f279-432b-b4af-38caddd60721
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2372533523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2372533523
Directory	/workspace/33.hmac_burst_wr/latest

Test location	/workspace/coverage/default/33.hmac_datapath_stress.3777347908
Short name	T656
Test name
Test status
Simulation time	8435203322 ps
CPU time	223.95 seconds
Started	Jun 21 06:03:15 PM PDT 24
Finished	Jun 21 06:06:59 PM PDT 24
Peak memory	650268 kb
Host	smart-7660e191-cbf8-4922-9b2e-3024b782d8e6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3777347908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3777347908
Directory	/workspace/33.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/33.hmac_error.3162138603
Short name	T127
Test name
Test status
Simulation time	48041497865 ps
CPU time	158.82 seconds
Started	Jun 21 06:03:17 PM PDT 24
Finished	Jun 21 06:05:57 PM PDT 24
Peak memory	200032 kb
Host	smart-866cf868-c7d8-4d24-9e68-6a918452b7e7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162138603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.3162138603
Directory	/workspace/33.hmac_error/latest

Test location	/workspace/coverage/default/33.hmac_smoke.854749541
Short name	T240
Test name
Test status
Simulation time	343914937 ps
CPU time	4.33 seconds
Started	Jun 21 06:03:17 PM PDT 24
Finished	Jun 21 06:03:23 PM PDT 24
Peak memory	200060 kb
Host	smart-7a606cba-aa2f-478a-98dc-d58905bf8771
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=854749541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.854749541
Directory	/workspace/33.hmac_smoke/latest

Test location	/workspace/coverage/default/33.hmac_test_hmac_vectors.1462857108
Short name	T408
Test name
Test status
Simulation time	82615728 ps
CPU time	1.08 seconds
Started	Jun 21 06:03:16 PM PDT 24
Finished	Jun 21 06:03:18 PM PDT 24
Peak memory	200056 kb
Host	smart-1b72bb39-7da1-4e3e-b886-e16a6bf45769
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462857108 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_hmac_vectors.1462857108
Directory	/workspace/33.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/33.hmac_test_sha256_vectors.961202068
Short name	T192
Test name
Test status
Simulation time	25450640667 ps
CPU time	456.57 seconds
Started	Jun 21 06:03:14 PM PDT 24
Finished	Jun 21 06:10:51 PM PDT 24
Peak memory	200092 kb
Host	smart-5952b230-ae87-4758-b669-47529f408dc1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=961202068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha256_vectors.961202068
Directory	/workspace/33.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/33.hmac_test_sha384_vectors.519391073
Short name	T80
Test name
Test status
Simulation time	127329384845 ps
CPU time	1760.38 seconds
Started	Jun 21 06:03:18 PM PDT 24
Finished	Jun 21 06:32:40 PM PDT 24
Peak memory	215624 kb
Host	smart-2b42ad69-3048-4391-9f2a-2c5a8bbe604b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=519391073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha384_vectors.519391073
Directory	/workspace/33.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/33.hmac_test_sha512_vectors.2849037081
Short name	T605
Test name
Test status
Simulation time	34279439224 ps
CPU time	1825.93 seconds
Started	Jun 21 06:03:15 PM PDT 24
Finished	Jun 21 06:33:42 PM PDT 24
Peak memory	215812 kb
Host	smart-67c7c63d-fadf-4f09-98cc-83eba905f096
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2849037081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha512_vectors.2849037081
Directory	/workspace/33.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/33.hmac_wipe_secret.828413958
Short name	T470
Test name
Test status
Simulation time	3099554552 ps
CPU time	17.86 seconds
Started	Jun 21 06:03:18 PM PDT 24
Finished	Jun 21 06:03:37 PM PDT 24
Peak memory	200136 kb
Host	smart-0f4d42b0-be77-48ce-951d-92f08b43b0f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=828413958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.828413958
Directory	/workspace/33.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/34.hmac_alert_test.1364366790
Short name	T465
Test name
Test status
Simulation time	13475253 ps
CPU time	0.61 seconds
Started	Jun 21 06:03:15 PM PDT 24
Finished	Jun 21 06:03:17 PM PDT 24
Peak memory	196056 kb
Host	smart-0eb4e88a-360e-4b31-b79e-a7488a66a4c1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364366790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1364366790
Directory	/workspace/34.hmac_alert_test/latest

Test location	/workspace/coverage/default/34.hmac_back_pressure.1149369926
Short name	T26
Test name
Test status
Simulation time	578224309 ps
CPU time	27.18 seconds
Started	Jun 21 06:03:18 PM PDT 24
Finished	Jun 21 06:03:46 PM PDT 24
Peak memory	200056 kb
Host	smart-e212b420-2e2e-42eb-b9f9-a2bce373043d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1149369926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1149369926
Directory	/workspace/34.hmac_back_pressure/latest

Test location	/workspace/coverage/default/34.hmac_burst_wr.1976345902
Short name	T152
Test name
Test status
Simulation time	3411124610 ps
CPU time	59.3 seconds
Started	Jun 21 06:03:15 PM PDT 24
Finished	Jun 21 06:04:15 PM PDT 24
Peak memory	200136 kb
Host	smart-8e2f771e-a3bf-484c-a00b-e3a455adeb52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1976345902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1976345902
Directory	/workspace/34.hmac_burst_wr/latest

Test location	/workspace/coverage/default/34.hmac_error.1225103897
Short name	T551
Test name
Test status
Simulation time	3555688837 ps
CPU time	201.76 seconds
Started	Jun 21 06:03:14 PM PDT 24
Finished	Jun 21 06:06:37 PM PDT 24
Peak memory	200112 kb
Host	smart-80505d8c-46d8-48ec-b472-6362871889f4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225103897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1225103897
Directory	/workspace/34.hmac_error/latest

Test location	/workspace/coverage/default/34.hmac_long_msg.345274715
Short name	T248
Test name
Test status
Simulation time	11552319582 ps
CPU time	57.11 seconds
Started	Jun 21 06:03:16 PM PDT 24
Finished	Jun 21 06:04:14 PM PDT 24
Peak memory	199992 kb
Host	smart-0e769eef-e1eb-4f7a-8bc4-a651c1691d0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=345274715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.345274715
Directory	/workspace/34.hmac_long_msg/latest

Test location	/workspace/coverage/default/34.hmac_smoke.977063213
Short name	T79
Test name
Test status
Simulation time	1914859569 ps
CPU time	17.14 seconds
Started	Jun 21 06:03:16 PM PDT 24
Finished	Jun 21 06:03:35 PM PDT 24
Peak memory	200088 kb
Host	smart-5f5f2a16-67d4-44ac-a888-1cc2240a2bd1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=977063213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.977063213
Directory	/workspace/34.hmac_smoke/latest

Test location	/workspace/coverage/default/34.hmac_test_hmac_vectors.3443153756
Short name	T617
Test name
Test status
Simulation time	324698092 ps
CPU time	1.45 seconds
Started	Jun 21 06:03:15 PM PDT 24
Finished	Jun 21 06:03:17 PM PDT 24
Peak memory	200068 kb
Host	smart-1ffd1168-d5f7-4960-8f2d-92416fd376a5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443153756 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_hmac_vectors.3443153756
Directory	/workspace/34.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/34.hmac_test_sha256_vectors.3416366889
Short name	T565
Test name
Test status
Simulation time	34427612489 ps
CPU time	463.4 seconds
Started	Jun 21 06:03:16 PM PDT 24
Finished	Jun 21 06:11:01 PM PDT 24
Peak memory	200140 kb
Host	smart-e7a1b599-426e-44b9-bfc9-43dbabed1d70
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3416366889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha256_vectors.3416366889
Directory	/workspace/34.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/34.hmac_test_sha384_vectors.3596861258
Short name	T7
Test name
Test status
Simulation time	512274995939 ps
CPU time	1839.36 seconds
Started	Jun 21 06:03:13 PM PDT 24
Finished	Jun 21 06:33:53 PM PDT 24
Peak memory	215604 kb
Host	smart-fd3eb197-4651-479e-96e3-c5635d008a73
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3596861258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha384_vectors.3596861258
Directory	/workspace/34.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/34.hmac_test_sha512_vectors.621506301
Short name	T396
Test name
Test status
Simulation time	159680862954 ps
CPU time	1996.23 seconds
Started	Jun 21 06:03:17 PM PDT 24
Finished	Jun 21 06:36:35 PM PDT 24
Peak memory	215640 kb
Host	smart-449861e6-6f56-4ce3-9d3b-5a6b1c86774c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=621506301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha512_vectors.621506301
Directory	/workspace/34.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/34.hmac_wipe_secret.4136410286
Short name	T290
Test name
Test status
Simulation time	5234152573 ps
CPU time	71.12 seconds
Started	Jun 21 06:03:15 PM PDT 24
Finished	Jun 21 06:04:27 PM PDT 24
Peak memory	200136 kb
Host	smart-51156659-39e1-4ed1-b9e9-8bb59fb6d4a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4136410286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.4136410286
Directory	/workspace/34.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/35.hmac_alert_test.703652043
Short name	T612
Test name
Test status
Simulation time	30569316 ps
CPU time	0.61 seconds
Started	Jun 21 06:03:20 PM PDT 24
Finished	Jun 21 06:03:21 PM PDT 24
Peak memory	195900 kb
Host	smart-c4f0000e-12f9-4923-b599-efb4677b344d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703652043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.703652043
Directory	/workspace/35.hmac_alert_test/latest

Test location	/workspace/coverage/default/35.hmac_back_pressure.1459123712
Short name	T182
Test name
Test status
Simulation time	1595297297 ps
CPU time	19.43 seconds
Started	Jun 21 06:03:17 PM PDT 24
Finished	Jun 21 06:03:38 PM PDT 24
Peak memory	200028 kb
Host	smart-1a0dbdca-a080-4cbc-a4d5-2dcae78bf05e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1459123712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1459123712
Directory	/workspace/35.hmac_back_pressure/latest

Test location	/workspace/coverage/default/35.hmac_burst_wr.3516020186
Short name	T385
Test name
Test status
Simulation time	12573062279 ps
CPU time	61.03 seconds
Started	Jun 21 06:03:16 PM PDT 24
Finished	Jun 21 06:04:19 PM PDT 24
Peak memory	208296 kb
Host	smart-ef544966-9c1b-46f7-94b9-e00f9d0c5f9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3516020186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3516020186
Directory	/workspace/35.hmac_burst_wr/latest

Test location	/workspace/coverage/default/35.hmac_datapath_stress.3512722349
Short name	T280
Test name
Test status
Simulation time	424868201 ps
CPU time	108.01 seconds
Started	Jun 21 06:03:15 PM PDT 24
Finished	Jun 21 06:05:04 PM PDT 24
Peak memory	449776 kb
Host	smart-fe32951d-d864-447a-bec9-e2d0934ed693
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3512722349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3512722349
Directory	/workspace/35.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/35.hmac_error.3466942165
Short name	T128
Test name
Test status
Simulation time	1281204286 ps
CPU time	65.01 seconds
Started	Jun 21 06:03:20 PM PDT 24
Finished	Jun 21 06:04:25 PM PDT 24
Peak memory	199956 kb
Host	smart-b31e20dc-46a7-4105-a332-95d2198772b3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466942165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3466942165
Directory	/workspace/35.hmac_error/latest

Test location	/workspace/coverage/default/35.hmac_long_msg.1630313576
Short name	T616
Test name
Test status
Simulation time	184826118 ps
CPU time	10.55 seconds
Started	Jun 21 06:03:14 PM PDT 24
Finished	Jun 21 06:03:25 PM PDT 24
Peak memory	200012 kb
Host	smart-20c603d1-6991-424f-bdd4-dea65fc3557b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1630313576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1630313576
Directory	/workspace/35.hmac_long_msg/latest

Test location	/workspace/coverage/default/35.hmac_smoke.2596110634
Short name	T256
Test name
Test status
Simulation time	451910291 ps
CPU time	10.42 seconds
Started	Jun 21 06:03:16 PM PDT 24
Finished	Jun 21 06:03:28 PM PDT 24
Peak memory	200040 kb
Host	smart-86713807-02bc-4a3a-a938-7f0ce8383149
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2596110634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2596110634
Directory	/workspace/35.hmac_smoke/latest

Test location	/workspace/coverage/default/35.hmac_test_hmac_vectors.2349069254
Short name	T486
Test name
Test status
Simulation time	30968633 ps
CPU time	1.11 seconds
Started	Jun 21 06:03:19 PM PDT 24
Finished	Jun 21 06:03:21 PM PDT 24
Peak memory	199944 kb
Host	smart-66444c24-4993-4c12-bfa2-646f25828672
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349069254 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_hmac_vectors.2349069254
Directory	/workspace/35.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/35.hmac_test_sha256_vectors.493838629
Short name	T271
Test name
Test status
Simulation time	41884270567 ps
CPU time	563.9 seconds
Started	Jun 21 06:03:16 PM PDT 24
Finished	Jun 21 06:12:41 PM PDT 24
Peak memory	200124 kb
Host	smart-4dc7f425-bdfb-49e0-901c-e89c53b7387a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=493838629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha256_vectors.493838629
Directory	/workspace/35.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/35.hmac_test_sha384_vectors.2923928747
Short name	T303
Test name
Test status
Simulation time	264129584536 ps
CPU time	1969.1 seconds
Started	Jun 21 06:03:15 PM PDT 24
Finished	Jun 21 06:36:04 PM PDT 24
Peak memory	216496 kb
Host	smart-3096524e-ad50-4a8b-b475-64e82d6d754d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2923928747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha384_vectors.2923928747
Directory	/workspace/35.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/35.hmac_test_sha512_vectors.2683544165
Short name	T633
Test name
Test status
Simulation time	392891017205 ps
CPU time	1821.15 seconds
Started	Jun 21 06:03:17 PM PDT 24
Finished	Jun 21 06:33:40 PM PDT 24
Peak memory	208384 kb
Host	smart-87cfc83f-068d-42e8-9e12-2807ee2adafa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2683544165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha512_vectors.2683544165
Directory	/workspace/35.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/35.hmac_wipe_secret.2761704094
Short name	T320
Test name
Test status
Simulation time	1115244674 ps
CPU time	48.89 seconds
Started	Jun 21 06:03:17 PM PDT 24
Finished	Jun 21 06:04:07 PM PDT 24
Peak memory	200108 kb
Host	smart-22135b39-e8ca-4090-9fb8-6fd215ab4aba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2761704094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2761704094
Directory	/workspace/35.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/36.hmac_alert_test.1123815775
Short name	T431
Test name
Test status
Simulation time	33703446 ps
CPU time	0.6 seconds
Started	Jun 21 06:03:24 PM PDT 24
Finished	Jun 21 06:03:25 PM PDT 24
Peak memory	194976 kb
Host	smart-2ab8e7dc-e8db-48c6-979c-cd6b228e89ef
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123815775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1123815775
Directory	/workspace/36.hmac_alert_test/latest

Test location	/workspace/coverage/default/36.hmac_back_pressure.2015316758
Short name	T550
Test name
Test status
Simulation time	6678156027 ps
CPU time	26.73 seconds
Started	Jun 21 06:03:24 PM PDT 24
Finished	Jun 21 06:03:52 PM PDT 24
Peak memory	200116 kb
Host	smart-7cd06c4d-52f0-4dd9-be80-bdf141558569
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2015316758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2015316758
Directory	/workspace/36.hmac_back_pressure/latest

Test location	/workspace/coverage/default/36.hmac_burst_wr.3711874865
Short name	T409
Test name
Test status
Simulation time	1682209254 ps
CPU time	24.47 seconds
Started	Jun 21 06:03:24 PM PDT 24
Finished	Jun 21 06:03:49 PM PDT 24
Peak memory	200088 kb
Host	smart-1bd5dbdd-5852-474b-886b-a62eb4dd0950
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3711874865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3711874865
Directory	/workspace/36.hmac_burst_wr/latest

Test location	/workspace/coverage/default/36.hmac_datapath_stress.4261782146
Short name	T564
Test name
Test status
Simulation time	6249294623 ps
CPU time	725.58 seconds
Started	Jun 21 06:03:23 PM PDT 24
Finished	Jun 21 06:15:30 PM PDT 24
Peak memory	547612 kb
Host	smart-49a8596b-675d-43e4-b7c6-ef51ddaa7bf8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4261782146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.4261782146
Directory	/workspace/36.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/36.hmac_error.2451489959
Short name	T626
Test name
Test status
Simulation time	3925118476 ps
CPU time	24.58 seconds
Started	Jun 21 06:03:22 PM PDT 24
Finished	Jun 21 06:03:47 PM PDT 24
Peak memory	200084 kb
Host	smart-aee31ce9-d20b-4d76-ab4a-6de04cac92b4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451489959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2451489959
Directory	/workspace/36.hmac_error/latest

Test location	/workspace/coverage/default/36.hmac_long_msg.1318866337
Short name	T338
Test name
Test status
Simulation time	4800414256 ps
CPU time	90.93 seconds
Started	Jun 21 06:03:24 PM PDT 24
Finished	Jun 21 06:04:56 PM PDT 24
Peak memory	200128 kb
Host	smart-56ef382e-7191-4c04-a58d-1f509126f505
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1318866337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1318866337
Directory	/workspace/36.hmac_long_msg/latest

Test location	/workspace/coverage/default/36.hmac_smoke.1387144938
Short name	T502
Test name
Test status
Simulation time	178409546 ps
CPU time	6.97 seconds
Started	Jun 21 06:03:23 PM PDT 24
Finished	Jun 21 06:03:30 PM PDT 24
Peak memory	200092 kb
Host	smart-149d8828-e6ef-49ed-9261-f776ba56eb46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1387144938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1387144938
Directory	/workspace/36.hmac_smoke/latest

Test location	/workspace/coverage/default/36.hmac_test_hmac_vectors.2725958388
Short name	T464
Test name
Test status
Simulation time	213026339 ps
CPU time	1.17 seconds
Started	Jun 21 06:03:21 PM PDT 24
Finished	Jun 21 06:03:22 PM PDT 24
Peak memory	199796 kb
Host	smart-d8bc97fa-b346-4387-96bd-f4d69581c371
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725958388 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_hmac_vectors.2725958388
Directory	/workspace/36.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/36.hmac_test_sha256_vectors.1608197147
Short name	T604
Test name
Test status
Simulation time	127365923576 ps
CPU time	419.85 seconds
Started	Jun 21 06:03:26 PM PDT 24
Finished	Jun 21 06:10:27 PM PDT 24
Peak memory	200048 kb
Host	smart-835d3211-4a8d-4921-b47e-e3969586977b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1608197147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha256_vectors.1608197147
Directory	/workspace/36.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/36.hmac_test_sha384_vectors.2616507205
Short name	T297
Test name
Test status
Simulation time	151310343239 ps
CPU time	1923.05 seconds
Started	Jun 21 06:03:25 PM PDT 24
Finished	Jun 21 06:35:29 PM PDT 24
Peak memory	216000 kb
Host	smart-79f5e4f0-b002-4346-93f7-1e3eb8a24f80
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2616507205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha384_vectors.2616507205
Directory	/workspace/36.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/36.hmac_test_sha512_vectors.4294598481
Short name	T549
Test name
Test status
Simulation time	328422392145 ps
CPU time	2193.57 seconds
Started	Jun 21 06:03:22 PM PDT 24
Finished	Jun 21 06:39:57 PM PDT 24
Peak memory	215564 kb
Host	smart-6bdf266d-8639-4b28-815a-625994c3e35c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=4294598481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha512_vectors.4294598481
Directory	/workspace/36.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/36.hmac_wipe_secret.3861864577
Short name	T543
Test name
Test status
Simulation time	13693264842 ps
CPU time	59.56 seconds
Started	Jun 21 06:03:24 PM PDT 24
Finished	Jun 21 06:04:25 PM PDT 24
Peak memory	200140 kb
Host	smart-820155d4-a64b-49ed-ad6d-f1f07674d471
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3861864577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3861864577
Directory	/workspace/36.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/37.hmac_alert_test.623024633
Short name	T508
Test name
Test status
Simulation time	23573009 ps
CPU time	0.64 seconds
Started	Jun 21 06:03:33 PM PDT 24
Finished	Jun 21 06:03:34 PM PDT 24
Peak memory	195976 kb
Host	smart-f49d9383-e743-454e-931d-38e1cbc876e4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623024633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.623024633
Directory	/workspace/37.hmac_alert_test/latest

Test location	/workspace/coverage/default/37.hmac_back_pressure.454297672
Short name	T89
Test name
Test status
Simulation time	1493009890 ps
CPU time	42.16 seconds
Started	Jun 21 06:03:23 PM PDT 24
Finished	Jun 21 06:04:07 PM PDT 24
Peak memory	200016 kb
Host	smart-cc4e9c86-d33c-4618-bdc5-b90a42d1809c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=454297672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.454297672
Directory	/workspace/37.hmac_back_pressure/latest

Test location	/workspace/coverage/default/37.hmac_burst_wr.404163083
Short name	T215
Test name
Test status
Simulation time	99522592 ps
CPU time	2.23 seconds
Started	Jun 21 06:03:25 PM PDT 24
Finished	Jun 21 06:03:28 PM PDT 24
Peak memory	199876 kb
Host	smart-eef6d755-b793-4f72-8cab-6b4b0b171249
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=404163083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.404163083
Directory	/workspace/37.hmac_burst_wr/latest

Test location	/workspace/coverage/default/37.hmac_datapath_stress.2223976869
Short name	T651
Test name
Test status
Simulation time	3322931744 ps
CPU time	650.06 seconds
Started	Jun 21 06:03:23 PM PDT 24
Finished	Jun 21 06:14:15 PM PDT 24
Peak memory	691644 kb
Host	smart-d38b70f6-3a46-4abd-ac4e-cd134aaa5cd6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2223976869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2223976869
Directory	/workspace/37.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/37.hmac_error.2528579232
Short name	T611
Test name
Test status
Simulation time	11993062465 ps
CPU time	152.58 seconds
Started	Jun 21 06:03:32 PM PDT 24
Finished	Jun 21 06:06:06 PM PDT 24
Peak memory	200100 kb
Host	smart-b4219b09-21c5-446c-9140-b86765caf40a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528579232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2528579232
Directory	/workspace/37.hmac_error/latest

Test location	/workspace/coverage/default/37.hmac_long_msg.1139464497
Short name	T360
Test name
Test status
Simulation time	468813055 ps
CPU time	7.13 seconds
Started	Jun 21 06:03:25 PM PDT 24
Finished	Jun 21 06:03:33 PM PDT 24
Peak memory	200072 kb
Host	smart-4eef14d0-645f-4ce7-af04-3a06beb608a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1139464497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1139464497
Directory	/workspace/37.hmac_long_msg/latest

Test location	/workspace/coverage/default/37.hmac_smoke.1623924102
Short name	T541
Test name
Test status
Simulation time	581581055 ps
CPU time	11.48 seconds
Started	Jun 21 06:03:24 PM PDT 24
Finished	Jun 21 06:03:37 PM PDT 24
Peak memory	200068 kb
Host	smart-69e32af3-bfeb-4e87-98f0-c99cf2c157e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1623924102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1623924102
Directory	/workspace/37.hmac_smoke/latest

Test location	/workspace/coverage/default/37.hmac_test_hmac_vectors.3188035337
Short name	T242
Test name
Test status
Simulation time	115724298 ps
CPU time	1.19 seconds
Started	Jun 21 06:03:32 PM PDT 24
Finished	Jun 21 06:03:34 PM PDT 24
Peak memory	199972 kb
Host	smart-75c2ba3a-58dd-4d1e-88b3-5fb5f6bccab6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188035337 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_hmac_vectors.3188035337
Directory	/workspace/37.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/37.hmac_test_sha256_vectors.2733521007
Short name	T546
Test name
Test status
Simulation time	8468755951 ps
CPU time	458.67 seconds
Started	Jun 21 06:03:31 PM PDT 24
Finished	Jun 21 06:11:10 PM PDT 24
Peak memory	200072 kb
Host	smart-5f81c8de-6705-4a55-b723-9ea110cab8c7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2733521007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha256_vectors.2733521007
Directory	/workspace/37.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/37.hmac_test_sha384_vectors.2023232412
Short name	T264
Test name
Test status
Simulation time	121884477352 ps
CPU time	1652.83 seconds
Started	Jun 21 06:03:32 PM PDT 24
Finished	Jun 21 06:31:06 PM PDT 24
Peak memory	215684 kb
Host	smart-939a2db9-b3ce-40ef-8e53-3554324dfe4a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2023232412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha384_vectors.2023232412
Directory	/workspace/37.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/37.hmac_test_sha512_vectors.3163281752
Short name	T471
Test name
Test status
Simulation time	124745083434 ps
CPU time	1866.21 seconds
Started	Jun 21 06:03:31 PM PDT 24
Finished	Jun 21 06:34:38 PM PDT 24
Peak memory	215676 kb
Host	smart-2cf9f9b4-eb82-4404-b8c6-800039ae4577
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3163281752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha512_vectors.3163281752
Directory	/workspace/37.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/37.hmac_wipe_secret.989624267
Short name	T294
Test name
Test status
Simulation time	10158018651 ps
CPU time	74.82 seconds
Started	Jun 21 06:03:31 PM PDT 24
Finished	Jun 21 06:04:47 PM PDT 24
Peak memory	200136 kb
Host	smart-4b1fad26-f720-48d2-9f55-ce1dd0f720b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=989624267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.989624267
Directory	/workspace/37.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/38.hmac_alert_test.758772620
Short name	T33
Test name
Test status
Simulation time	51504004 ps
CPU time	0.6 seconds
Started	Jun 21 06:03:45 PM PDT 24
Finished	Jun 21 06:03:46 PM PDT 24
Peak memory	196648 kb
Host	smart-f7805aa0-929b-47ca-abc5-b6080b9116ef
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758772620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.758772620
Directory	/workspace/38.hmac_alert_test/latest

Test location	/workspace/coverage/default/38.hmac_back_pressure.3238993894
Short name	T357
Test name
Test status
Simulation time	2609126455 ps
CPU time	31.36 seconds
Started	Jun 21 06:03:32 PM PDT 24
Finished	Jun 21 06:04:04 PM PDT 24
Peak memory	200148 kb
Host	smart-c6254a87-63b2-4559-aa34-4c1d5bac4e0f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3238993894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3238993894
Directory	/workspace/38.hmac_back_pressure/latest

Test location	/workspace/coverage/default/38.hmac_burst_wr.412582543
Short name	T637
Test name
Test status
Simulation time	954046838 ps
CPU time	34.89 seconds
Started	Jun 21 06:03:34 PM PDT 24
Finished	Jun 21 06:04:09 PM PDT 24
Peak memory	200048 kb
Host	smart-7c4e0faf-29c0-48fc-8a7d-55010a0a0f54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=412582543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.412582543
Directory	/workspace/38.hmac_burst_wr/latest

Test location	/workspace/coverage/default/38.hmac_datapath_stress.3592924952
Short name	T527
Test name
Test status
Simulation time	316008495 ps
CPU time	86.34 seconds
Started	Jun 21 06:03:33 PM PDT 24
Finished	Jun 21 06:05:00 PM PDT 24
Peak memory	546608 kb
Host	smart-7a670cbb-a517-4641-ad6a-64a88a1fd65a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3592924952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3592924952
Directory	/workspace/38.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/38.hmac_error.1927948340
Short name	T573
Test name
Test status
Simulation time	2675839645 ps
CPU time	140.94 seconds
Started	Jun 21 06:03:31 PM PDT 24
Finished	Jun 21 06:05:52 PM PDT 24
Peak memory	200084 kb
Host	smart-b7f61437-e13e-4aed-844c-03cdb83709a5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927948340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.1927948340
Directory	/workspace/38.hmac_error/latest

Test location	/workspace/coverage/default/38.hmac_long_msg.2538198581
Short name	T596
Test name
Test status
Simulation time	9819538448 ps
CPU time	91.82 seconds
Started	Jun 21 06:03:32 PM PDT 24
Finished	Jun 21 06:05:05 PM PDT 24
Peak memory	200232 kb
Host	smart-5a0ea4f8-b534-4bba-8e62-cb24901f2ffd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2538198581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2538198581
Directory	/workspace/38.hmac_long_msg/latest

Test location	/workspace/coverage/default/38.hmac_smoke.2758739840
Short name	T150
Test name
Test status
Simulation time	1206358899 ps
CPU time	9.74 seconds
Started	Jun 21 06:03:32 PM PDT 24
Finished	Jun 21 06:03:43 PM PDT 24
Peak memory	200088 kb
Host	smart-da981bf8-8148-4438-841e-5783eea23eef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758739840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2758739840
Directory	/workspace/38.hmac_smoke/latest

Test location	/workspace/coverage/default/38.hmac_test_hmac_vectors.150236214
Short name	T322
Test name
Test status
Simulation time	93543063 ps
CPU time	1.07 seconds
Started	Jun 21 06:03:32 PM PDT 24
Finished	Jun 21 06:03:35 PM PDT 24
Peak memory	199856 kb
Host	smart-d7a63330-12f9-45ac-8430-52f445598b8a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150236214 -assert nopostpr oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_hmac_vectors.150236214
Directory	/workspace/38.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/38.hmac_test_sha256_vectors.1289026257
Short name	T654
Test name
Test status
Simulation time	28544992493 ps
CPU time	500.6 seconds
Started	Jun 21 06:03:33 PM PDT 24
Finished	Jun 21 06:11:54 PM PDT 24
Peak memory	200096 kb
Host	smart-4131c704-634f-4f67-b496-90443d2949aa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1289026257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha256_vectors.1289026257
Directory	/workspace/38.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/38.hmac_test_sha384_vectors.255268576
Short name	T262
Test name
Test status
Simulation time	112646326929 ps
CPU time	1661.18 seconds
Started	Jun 21 06:03:34 PM PDT 24
Finished	Jun 21 06:31:16 PM PDT 24
Peak memory	216436 kb
Host	smart-3ddfda9e-1a2c-4fb3-9f99-eeff8d823e9f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=255268576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha384_vectors.255268576
Directory	/workspace/38.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/38.hmac_test_sha512_vectors.589888751
Short name	T554
Test name
Test status
Simulation time	860629744692 ps
CPU time	1920.19 seconds
Started	Jun 21 06:03:34 PM PDT 24
Finished	Jun 21 06:35:35 PM PDT 24
Peak memory	215480 kb
Host	smart-ca6e98c4-e8fc-422b-abbd-2b67890b190e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=589888751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha512_vectors.589888751
Directory	/workspace/38.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/38.hmac_wipe_secret.3355421741
Short name	T344
Test name
Test status
Simulation time	18815953307 ps
CPU time	68.45 seconds
Started	Jun 21 06:03:33 PM PDT 24
Finished	Jun 21 06:04:42 PM PDT 24
Peak memory	200168 kb
Host	smart-795d27fe-c76c-4f06-91e5-78018432ff29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3355421741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.3355421741
Directory	/workspace/38.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/39.hmac_alert_test.4228402514
Short name	T530
Test name
Test status
Simulation time	13773291 ps
CPU time	0.58 seconds
Started	Jun 21 06:03:42 PM PDT 24
Finished	Jun 21 06:03:44 PM PDT 24
Peak memory	194964 kb
Host	smart-859bba05-45e9-4701-b037-5d19d1a13cb9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228402514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.4228402514
Directory	/workspace/39.hmac_alert_test/latest

Test location	/workspace/coverage/default/39.hmac_back_pressure.1755667623
Short name	T336
Test name
Test status
Simulation time	128610145 ps
CPU time	6.57 seconds
Started	Jun 21 06:03:43 PM PDT 24
Finished	Jun 21 06:03:51 PM PDT 24
Peak memory	199976 kb
Host	smart-cd14b592-8da1-4132-bbcf-5cfbd096c7aa
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1755667623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1755667623
Directory	/workspace/39.hmac_back_pressure/latest

Test location	/workspace/coverage/default/39.hmac_burst_wr.1143543467
Short name	T469
Test name
Test status
Simulation time	4099752068 ps
CPU time	72.94 seconds
Started	Jun 21 06:03:42 PM PDT 24
Finished	Jun 21 06:04:56 PM PDT 24
Peak memory	200176 kb
Host	smart-064341bc-dfb0-4720-987c-ae1451ff7964
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1143543467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1143543467
Directory	/workspace/39.hmac_burst_wr/latest

Test location	/workspace/coverage/default/39.hmac_datapath_stress.544004937
Short name	T575
Test name
Test status
Simulation time	15102107580 ps
CPU time	223.11 seconds
Started	Jun 21 06:03:43 PM PDT 24
Finished	Jun 21 06:07:27 PM PDT 24
Peak memory	663796 kb
Host	smart-7d638213-b959-47cc-8649-5ee292669f1a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=544004937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.544004937
Directory	/workspace/39.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/39.hmac_error.2669132466
Short name	T263
Test name
Test status
Simulation time	13030101595 ps
CPU time	186.26 seconds
Started	Jun 21 06:03:43 PM PDT 24
Finished	Jun 21 06:06:50 PM PDT 24
Peak memory	200228 kb
Host	smart-2808bb81-a916-47f3-b2c4-4b83f2d72949
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669132466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.2669132466
Directory	/workspace/39.hmac_error/latest

Test location	/workspace/coverage/default/39.hmac_long_msg.1499269941
Short name	T381
Test name
Test status
Simulation time	18590143683 ps
CPU time	138.57 seconds
Started	Jun 21 06:03:45 PM PDT 24
Finished	Jun 21 06:06:04 PM PDT 24
Peak memory	200148 kb
Host	smart-e4272824-da26-4904-8f99-ad87666de702
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1499269941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1499269941
Directory	/workspace/39.hmac_long_msg/latest

Test location	/workspace/coverage/default/39.hmac_smoke.2716592211
Short name	T620
Test name
Test status
Simulation time	887859798 ps
CPU time	11.05 seconds
Started	Jun 21 06:03:42 PM PDT 24
Finished	Jun 21 06:03:54 PM PDT 24
Peak memory	200076 kb
Host	smart-dffa1929-2ba9-4062-b2a5-a8918ab86725
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2716592211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2716592211
Directory	/workspace/39.hmac_smoke/latest

Test location	/workspace/coverage/default/39.hmac_test_hmac_vectors.3202980742
Short name	T254
Test name
Test status
Simulation time	90349084 ps
CPU time	1.53 seconds
Started	Jun 21 06:03:44 PM PDT 24
Finished	Jun 21 06:03:46 PM PDT 24
Peak memory	200060 kb
Host	smart-cdaab577-bbbc-430f-8cdc-5a4413a9a07d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202980742 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_hmac_vectors.3202980742
Directory	/workspace/39.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/39.hmac_test_sha256_vectors.4057850475
Short name	T414
Test name
Test status
Simulation time	25722675862 ps
CPU time	484.39 seconds
Started	Jun 21 06:03:43 PM PDT 24
Finished	Jun 21 06:11:49 PM PDT 24
Peak memory	200152 kb
Host	smart-bdd7cff4-004e-4b26-b47f-48534a46a2a7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4057850475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha256_vectors.4057850475
Directory	/workspace/39.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/39.hmac_test_sha384_vectors.2777970863
Short name	T614
Test name
Test status
Simulation time	448607259937 ps
CPU time	2065.09 seconds
Started	Jun 21 06:03:44 PM PDT 24
Finished	Jun 21 06:38:10 PM PDT 24
Peak memory	216248 kb
Host	smart-f3256783-e315-4fac-b797-b9161efb2843
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2777970863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha384_vectors.2777970863
Directory	/workspace/39.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/39.hmac_test_sha512_vectors.3884734864
Short name	T206
Test name
Test status
Simulation time	145454545816 ps
CPU time	1943.11 seconds
Started	Jun 21 06:03:41 PM PDT 24
Finished	Jun 21 06:36:05 PM PDT 24
Peak memory	216420 kb
Host	smart-44ad2d9c-e6e8-40f2-aa00-9eb5b7aae878
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3884734864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha512_vectors.3884734864
Directory	/workspace/39.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/39.hmac_wipe_secret.459330457
Short name	T393
Test name
Test status
Simulation time	6924670460 ps
CPU time	63.23 seconds
Started	Jun 21 06:03:43 PM PDT 24
Finished	Jun 21 06:04:47 PM PDT 24
Peak memory	200064 kb
Host	smart-f6db5452-fa7d-4c01-8a87-ccda5e2b5d7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=459330457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.459330457
Directory	/workspace/39.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/4.hmac_alert_test.1441286402
Short name	T235
Test name
Test status
Simulation time	13374617 ps
CPU time	0.62 seconds
Started	Jun 21 06:01:12 PM PDT 24
Finished	Jun 21 06:01:14 PM PDT 24
Peak memory	195800 kb
Host	smart-8ac5e6b3-7d57-4b44-a476-9c2340b95ab2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441286402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1441286402
Directory	/workspace/4.hmac_alert_test/latest

Test location	/workspace/coverage/default/4.hmac_back_pressure.415413066
Short name	T638
Test name
Test status
Simulation time	3456635937 ps
CPU time	40.84 seconds
Started	Jun 21 06:01:09 PM PDT 24
Finished	Jun 21 06:01:52 PM PDT 24
Peak memory	200080 kb
Host	smart-abc95261-64cf-4ebf-b479-a2f6afd96915
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=415413066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.415413066
Directory	/workspace/4.hmac_back_pressure/latest

Test location	/workspace/coverage/default/4.hmac_burst_wr.4164637476
Short name	T282
Test name
Test status
Simulation time	226487339 ps
CPU time	12.15 seconds
Started	Jun 21 06:01:10 PM PDT 24
Finished	Jun 21 06:01:24 PM PDT 24
Peak memory	200032 kb
Host	smart-e25e903e-f89d-429a-97ae-157a490ed375
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4164637476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.4164637476
Directory	/workspace/4.hmac_burst_wr/latest

Test location	/workspace/coverage/default/4.hmac_datapath_stress.2298922260
Short name	T134
Test name
Test status
Simulation time	12297671809 ps
CPU time	644.09 seconds
Started	Jun 21 06:01:09 PM PDT 24
Finished	Jun 21 06:11:55 PM PDT 24
Peak memory	620428 kb
Host	smart-0ab14d8f-b270-4a95-969a-2b33790c7c49
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2298922260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2298922260
Directory	/workspace/4.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/4.hmac_error.1674177370
Short name	T126
Test name
Test status
Simulation time	37706355562 ps
CPU time	156.87 seconds
Started	Jun 21 06:01:12 PM PDT 24
Finished	Jun 21 06:03:49 PM PDT 24
Peak memory	200128 kb
Host	smart-9933f3e7-b72e-45bc-9ff3-4cbaf4bdc2dc
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674177370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1674177370
Directory	/workspace/4.hmac_error/latest

Test location	/workspace/coverage/default/4.hmac_long_msg.42206317
Short name	T569
Test name
Test status
Simulation time	310566248 ps
CPU time	17.67 seconds
Started	Jun 21 06:01:11 PM PDT 24
Finished	Jun 21 06:01:30 PM PDT 24
Peak memory	200064 kb
Host	smart-a9b9402e-e2d4-4d51-af8c-234626f219c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=42206317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.42206317
Directory	/workspace/4.hmac_long_msg/latest

Test location	/workspace/coverage/default/4.hmac_sec_cm.1512283569
Short name	T41
Test name
Test status
Simulation time	37670220 ps
CPU time	0.83 seconds
Started	Jun 21 06:01:13 PM PDT 24
Finished	Jun 21 06:01:14 PM PDT 24
Peak memory	218164 kb
Host	smart-e6ddf6f5-b1ae-4538-b0c1-5733726f3851
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512283569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1512283569
Directory	/workspace/4.hmac_sec_cm/latest

Test location	/workspace/coverage/default/4.hmac_smoke.1014254625
Short name	T400
Test name
Test status
Simulation time	551666699 ps
CPU time	10.12 seconds
Started	Jun 21 06:01:07 PM PDT 24
Finished	Jun 21 06:01:18 PM PDT 24
Peak memory	200088 kb
Host	smart-265c487d-3ced-48fb-a52b-2c6ed684c77d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1014254625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1014254625
Directory	/workspace/4.hmac_smoke/latest

Test location	/workspace/coverage/default/4.hmac_test_hmac_vectors.254108032
Short name	T497
Test name
Test status
Simulation time	58743644 ps
CPU time	1.2 seconds
Started	Jun 21 06:01:10 PM PDT 24
Finished	Jun 21 06:01:13 PM PDT 24
Peak memory	199748 kb
Host	smart-bcca05d8-fd42-43a7-aeae-736e0e026fc5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254108032 -assert nopostpr oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac_vectors.254108032
Directory	/workspace/4.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/4.hmac_test_sha256_vectors.2734259138
Short name	T85
Test name
Test status
Simulation time	16908615869 ps
CPU time	465.95 seconds
Started	Jun 21 06:01:09 PM PDT 24
Finished	Jun 21 06:08:56 PM PDT 24
Peak memory	200140 kb
Host	smart-c8916814-273d-4df6-91bf-1506e2a5d70f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2734259138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2734259138
Directory	/workspace/4.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/4.hmac_test_sha384_vectors.3506662283
Short name	T253
Test name
Test status
Simulation time	217135435692 ps
CPU time	2018.37 seconds
Started	Jun 21 06:01:11 PM PDT 24
Finished	Jun 21 06:34:51 PM PDT 24
Peak memory	215548 kb
Host	smart-a1f93761-9a0e-4106-a4ec-e7f0e62440f3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3506662283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.3506662283
Directory	/workspace/4.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/4.hmac_test_sha512_vectors.3475817388
Short name	T608
Test name
Test status
Simulation time	328463814056 ps
CPU time	1884.42 seconds
Started	Jun 21 06:01:08 PM PDT 24
Finished	Jun 21 06:32:34 PM PDT 24
Peak memory	208344 kb
Host	smart-6fe70bc2-151a-4d80-a79a-1616e1d572eb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3475817388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.3475817388
Directory	/workspace/4.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/4.hmac_wipe_secret.3516421946
Short name	T278
Test name
Test status
Simulation time	19979428677 ps
CPU time	36.93 seconds
Started	Jun 21 06:01:08 PM PDT 24
Finished	Jun 21 06:01:47 PM PDT 24
Peak memory	200156 kb
Host	smart-07a874dc-f80d-43f9-a088-80fab3f97ddb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3516421946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3516421946
Directory	/workspace/4.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/40.hmac_alert_test.659170592
Short name	T375
Test name
Test status
Simulation time	13398668 ps
CPU time	0.6 seconds
Started	Jun 21 06:03:51 PM PDT 24
Finished	Jun 21 06:03:53 PM PDT 24
Peak memory	195984 kb
Host	smart-9ef385d8-6e50-46c0-a429-3110d5a3aff8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659170592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.659170592
Directory	/workspace/40.hmac_alert_test/latest

Test location	/workspace/coverage/default/40.hmac_back_pressure.2382394171
Short name	T451
Test name
Test status
Simulation time	741175207 ps
CPU time	36.59 seconds
Started	Jun 21 06:03:51 PM PDT 24
Finished	Jun 21 06:04:29 PM PDT 24
Peak memory	200052 kb
Host	smart-8066015d-c66a-4386-aaec-9de5a0396054
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2382394171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2382394171
Directory	/workspace/40.hmac_back_pressure/latest

Test location	/workspace/coverage/default/40.hmac_burst_wr.1926970633
Short name	T555
Test name
Test status
Simulation time	36768491983 ps
CPU time	68.14 seconds
Started	Jun 21 06:03:52 PM PDT 24
Finished	Jun 21 06:05:01 PM PDT 24
Peak memory	208336 kb
Host	smart-ae319c91-41fb-486b-9a76-d616328068f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1926970633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1926970633
Directory	/workspace/40.hmac_burst_wr/latest

Test location	/workspace/coverage/default/40.hmac_datapath_stress.1836750608
Short name	T365
Test name
Test status
Simulation time	324565299 ps
CPU time	79.19 seconds
Started	Jun 21 06:03:55 PM PDT 24
Finished	Jun 21 06:05:15 PM PDT 24
Peak memory	447140 kb
Host	smart-c1ae3179-ca0c-4826-adeb-f11ab79e5cd1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1836750608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1836750608
Directory	/workspace/40.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/40.hmac_error.3332180017
Short name	T346
Test name
Test status
Simulation time	32926625029 ps
CPU time	162.79 seconds
Started	Jun 21 06:04:00 PM PDT 24
Finished	Jun 21 06:06:43 PM PDT 24
Peak memory	200148 kb
Host	smart-2f35492f-7301-48bd-95e9-69f2621be56f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332180017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3332180017
Directory	/workspace/40.hmac_error/latest

Test location	/workspace/coverage/default/40.hmac_long_msg.822823685
Short name	T382
Test name
Test status
Simulation time	3780860792 ps
CPU time	118.96 seconds
Started	Jun 21 06:03:44 PM PDT 24
Finished	Jun 21 06:05:43 PM PDT 24
Peak memory	208336 kb
Host	smart-6a817776-aff0-42b0-a8ff-fb92fa45a65b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=822823685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.822823685
Directory	/workspace/40.hmac_long_msg/latest

Test location	/workspace/coverage/default/40.hmac_smoke.4288825292
Short name	T416
Test name
Test status
Simulation time	330232211 ps
CPU time	8.58 seconds
Started	Jun 21 06:03:42 PM PDT 24
Finished	Jun 21 06:03:52 PM PDT 24
Peak memory	200048 kb
Host	smart-19cc4182-fb22-42e9-832a-de4a31d94401
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4288825292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.4288825292
Directory	/workspace/40.hmac_smoke/latest

Test location	/workspace/coverage/default/40.hmac_test_hmac_vectors.2041106591
Short name	T171
Test name
Test status
Simulation time	244167834 ps
CPU time	1.16 seconds
Started	Jun 21 06:03:51 PM PDT 24
Finished	Jun 21 06:03:53 PM PDT 24
Peak memory	200056 kb
Host	smart-2061eb26-17eb-4069-b173-bc27fe4e2c14
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041106591 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_hmac_vectors.2041106591
Directory	/workspace/40.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/40.hmac_test_sha256_vectors.3148587622
Short name	T196
Test name
Test status
Simulation time	126991578051 ps
CPU time	509.3 seconds
Started	Jun 21 06:03:59 PM PDT 24
Finished	Jun 21 06:12:29 PM PDT 24
Peak memory	200136 kb
Host	smart-6b1f6581-6b16-49b8-b4aa-8207429d9aeb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3148587622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha256_vectors.3148587622
Directory	/workspace/40.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/40.hmac_test_sha384_vectors.708997828
Short name	T521
Test name
Test status
Simulation time	356526598886 ps
CPU time	1693.97 seconds
Started	Jun 21 06:03:59 PM PDT 24
Finished	Jun 21 06:32:15 PM PDT 24
Peak memory	215936 kb
Host	smart-1e891ac0-b8cf-41b5-915b-427ec0b204f5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=708997828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha384_vectors.708997828
Directory	/workspace/40.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/40.hmac_test_sha512_vectors.1516642186
Short name	T176
Test name
Test status
Simulation time	533658768733 ps
CPU time	2002.18 seconds
Started	Jun 21 06:03:51 PM PDT 24
Finished	Jun 21 06:37:15 PM PDT 24
Peak memory	215696 kb
Host	smart-faa80e65-81d8-43ca-a037-9b3279faa165
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1516642186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha512_vectors.1516642186
Directory	/workspace/40.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/40.hmac_wipe_secret.2898224423
Short name	T515
Test name
Test status
Simulation time	16562340 ps
CPU time	0.93 seconds
Started	Jun 21 06:03:53 PM PDT 24
Finished	Jun 21 06:03:54 PM PDT 24
Peak memory	199236 kb
Host	smart-7af00457-c7a1-4dfd-92d3-fd2eb681e419
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2898224423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2898224423
Directory	/workspace/40.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/41.hmac_alert_test.1841829620
Short name	T522
Test name
Test status
Simulation time	36489875 ps
CPU time	0.6 seconds
Started	Jun 21 06:04:01 PM PDT 24
Finished	Jun 21 06:04:03 PM PDT 24
Peak memory	196068 kb
Host	smart-acf9bdc2-00bf-44ea-830a-c59bf58e9dcd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841829620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1841829620
Directory	/workspace/41.hmac_alert_test/latest

Test location	/workspace/coverage/default/41.hmac_back_pressure.1519696479
Short name	T288
Test name
Test status
Simulation time	1065524023 ps
CPU time	11.45 seconds
Started	Jun 21 06:03:50 PM PDT 24
Finished	Jun 21 06:04:02 PM PDT 24
Peak memory	200044 kb
Host	smart-aa64a621-4eb8-4b3d-88a5-09c9713a6255
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1519696479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1519696479
Directory	/workspace/41.hmac_back_pressure/latest

Test location	/workspace/coverage/default/41.hmac_burst_wr.3872700325
Short name	T566
Test name
Test status
Simulation time	73041544585 ps
CPU time	83.26 seconds
Started	Jun 21 06:04:00 PM PDT 24
Finished	Jun 21 06:05:24 PM PDT 24
Peak memory	200152 kb
Host	smart-0cbc660c-d84c-4dda-a282-ffeae2119ce9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3872700325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3872700325
Directory	/workspace/41.hmac_burst_wr/latest

Test location	/workspace/coverage/default/41.hmac_datapath_stress.3801790874
Short name	T351
Test name
Test status
Simulation time	2546418449 ps
CPU time	193 seconds
Started	Jun 21 06:03:54 PM PDT 24
Finished	Jun 21 06:07:08 PM PDT 24
Peak memory	448408 kb
Host	smart-99e6554a-2efd-47ff-bb2b-db0eb736b007
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3801790874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3801790874
Directory	/workspace/41.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/41.hmac_error.100495084
Short name	T321
Test name
Test status
Simulation time	18919294371 ps
CPU time	170.87 seconds
Started	Jun 21 06:03:52 PM PDT 24
Finished	Jun 21 06:06:44 PM PDT 24
Peak memory	200108 kb
Host	smart-2451a17b-9326-49c7-ab51-f172769ba9b3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100495084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.100495084
Directory	/workspace/41.hmac_error/latest

Test location	/workspace/coverage/default/41.hmac_long_msg.803409587
Short name	T204
Test name
Test status
Simulation time	1001286973 ps
CPU time	27.58 seconds
Started	Jun 21 06:04:00 PM PDT 24
Finished	Jun 21 06:04:29 PM PDT 24
Peak memory	200088 kb
Host	smart-a934fcd9-b7e3-41e8-9db5-91928f325672
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=803409587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.803409587
Directory	/workspace/41.hmac_long_msg/latest

Test location	/workspace/coverage/default/41.hmac_smoke.4185180892
Short name	T270
Test name
Test status
Simulation time	1268709625 ps
CPU time	14.03 seconds
Started	Jun 21 06:03:53 PM PDT 24
Finished	Jun 21 06:04:07 PM PDT 24
Peak memory	200092 kb
Host	smart-6219b437-cacb-4142-8ac8-369f8c181673
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4185180892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.4185180892
Directory	/workspace/41.hmac_smoke/latest

Test location	/workspace/coverage/default/41.hmac_test_hmac_vectors.562111139
Short name	T308
Test name
Test status
Simulation time	303086820 ps
CPU time	1.39 seconds
Started	Jun 21 06:04:00 PM PDT 24
Finished	Jun 21 06:04:02 PM PDT 24
Peak memory	199968 kb
Host	smart-12f6a639-3c2d-490b-a7b7-21e736ffc71b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562111139 -assert nopostpr oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_hmac_vectors.562111139
Directory	/workspace/41.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/41.hmac_test_sha256_vectors.873460235
Short name	T446
Test name
Test status
Simulation time	109071042401 ps
CPU time	544.32 seconds
Started	Jun 21 06:04:01 PM PDT 24
Finished	Jun 21 06:13:07 PM PDT 24
Peak memory	200112 kb
Host	smart-31589596-18be-4003-a8de-db14c2ba2420
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=873460235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha256_vectors.873460235
Directory	/workspace/41.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/41.hmac_test_sha384_vectors.2930939594
Short name	T11
Test name
Test status
Simulation time	131150259749 ps
CPU time	1674.8 seconds
Started	Jun 21 06:04:00 PM PDT 24
Finished	Jun 21 06:31:56 PM PDT 24
Peak memory	216104 kb
Host	smart-7fc410c5-3960-4b66-855f-1b0af085f773
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2930939594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha384_vectors.2930939594
Directory	/workspace/41.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/41.hmac_test_sha512_vectors.42441154
Short name	T422
Test name
Test status
Simulation time	108681524873 ps
CPU time	1619.34 seconds
Started	Jun 21 06:04:00 PM PDT 24
Finished	Jun 21 06:31:01 PM PDT 24
Peak memory	216072 kb
Host	smart-361a03bc-380c-44cc-ae23-142acd586033
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=42441154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha512_vectors.42441154
Directory	/workspace/41.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/41.hmac_wipe_secret.3572978518
Short name	T586
Test name
Test status
Simulation time	206881227 ps
CPU time	11.81 seconds
Started	Jun 21 06:04:02 PM PDT 24
Finished	Jun 21 06:04:14 PM PDT 24
Peak memory	200128 kb
Host	smart-13c5b82f-04ef-4678-9cee-d3b000218b85
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3572978518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3572978518
Directory	/workspace/41.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/42.hmac_alert_test.4273258471
Short name	T630
Test name
Test status
Simulation time	11920433 ps
CPU time	0.61 seconds
Started	Jun 21 06:03:59 PM PDT 24
Finished	Jun 21 06:04:00 PM PDT 24
Peak memory	195032 kb
Host	smart-8c227408-4aff-40e4-9c61-3f3146dd7a73
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273258471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.4273258471
Directory	/workspace/42.hmac_alert_test/latest

Test location	/workspace/coverage/default/42.hmac_back_pressure.454341073
Short name	T496
Test name
Test status
Simulation time	2492523273 ps
CPU time	32.05 seconds
Started	Jun 21 06:04:00 PM PDT 24
Finished	Jun 21 06:04:33 PM PDT 24
Peak memory	200108 kb
Host	smart-f08e5005-0526-44ef-9ceb-cd41a3b12d7c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=454341073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.454341073
Directory	/workspace/42.hmac_back_pressure/latest

Test location	/workspace/coverage/default/42.hmac_burst_wr.3246936160
Short name	T588
Test name
Test status
Simulation time	2628497785 ps
CPU time	8.58 seconds
Started	Jun 21 06:04:01 PM PDT 24
Finished	Jun 21 06:04:10 PM PDT 24
Peak memory	200048 kb
Host	smart-0435d0bf-3485-4315-8ec9-601dafc2cd2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3246936160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3246936160
Directory	/workspace/42.hmac_burst_wr/latest

Test location	/workspace/coverage/default/42.hmac_datapath_stress.3767710893
Short name	T578
Test name
Test status
Simulation time	2979969151 ps
CPU time	204.95 seconds
Started	Jun 21 06:04:00 PM PDT 24
Finished	Jun 21 06:07:26 PM PDT 24
Peak memory	650248 kb
Host	smart-fe8d38d3-d29c-45d1-b11c-b0ab51322d33
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3767710893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3767710893
Directory	/workspace/42.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/42.hmac_long_msg.3754742440
Short name	T234
Test name
Test status
Simulation time	888274598 ps
CPU time	49.24 seconds
Started	Jun 21 06:04:00 PM PDT 24
Finished	Jun 21 06:04:50 PM PDT 24
Peak memory	200072 kb
Host	smart-1266dd2a-e1f1-4f3b-9986-f0412fedcc2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3754742440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3754742440
Directory	/workspace/42.hmac_long_msg/latest

Test location	/workspace/coverage/default/42.hmac_smoke.94637138
Short name	T186
Test name
Test status
Simulation time	851026160 ps
CPU time	5.51 seconds
Started	Jun 21 06:04:02 PM PDT 24
Finished	Jun 21 06:04:08 PM PDT 24
Peak memory	200096 kb
Host	smart-3dca494d-276d-4306-a22c-0926be8af386
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=94637138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.94637138
Directory	/workspace/42.hmac_smoke/latest

Test location	/workspace/coverage/default/42.hmac_test_hmac_vectors.1996294436
Short name	T236
Test name
Test status
Simulation time	34301100 ps
CPU time	1.34 seconds
Started	Jun 21 06:03:59 PM PDT 24
Finished	Jun 21 06:04:01 PM PDT 24
Peak memory	200040 kb
Host	smart-6d863abc-d0cf-4fea-8a3e-ac821c0d8291
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996294436 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_hmac_vectors.1996294436
Directory	/workspace/42.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/42.hmac_test_sha256_vectors.1739106669
Short name	T534
Test name
Test status
Simulation time	30102312229 ps
CPU time	524.35 seconds
Started	Jun 21 06:04:03 PM PDT 24
Finished	Jun 21 06:12:48 PM PDT 24
Peak memory	200088 kb
Host	smart-517a4611-7971-4841-b05d-54b81f5d7873
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1739106669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha256_vectors.1739106669
Directory	/workspace/42.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/42.hmac_test_sha384_vectors.893853731
Short name	T429
Test name
Test status
Simulation time	103184474475 ps
CPU time	1913.83 seconds
Started	Jun 21 06:04:03 PM PDT 24
Finished	Jun 21 06:35:58 PM PDT 24
Peak memory	215628 kb
Host	smart-55f532a4-103c-46c2-8f8c-6bd22995a793
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=893853731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha384_vectors.893853731
Directory	/workspace/42.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/42.hmac_test_sha512_vectors.614180825
Short name	T154
Test name
Test status
Simulation time	512887208643 ps
CPU time	1734.33 seconds
Started	Jun 21 06:04:00 PM PDT 24
Finished	Jun 21 06:32:55 PM PDT 24
Peak memory	215724 kb
Host	smart-076368a4-d03d-40aa-88f1-d2d2ec054604
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=614180825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha512_vectors.614180825
Directory	/workspace/42.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/42.hmac_wipe_secret.1394955202
Short name	T327
Test name
Test status
Simulation time	1896875045 ps
CPU time	56.37 seconds
Started	Jun 21 06:04:01 PM PDT 24
Finished	Jun 21 06:04:58 PM PDT 24
Peak memory	199980 kb
Host	smart-b2b2f68e-d084-49a0-81ae-f0d06a01bb5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1394955202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1394955202
Directory	/workspace/42.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/43.hmac_alert_test.3930414855
Short name	T209
Test name
Test status
Simulation time	40791718 ps
CPU time	0.59 seconds
Started	Jun 21 06:04:10 PM PDT 24
Finished	Jun 21 06:04:11 PM PDT 24
Peak memory	194964 kb
Host	smart-921dbd84-047b-4a99-8703-0807b0f33ff8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930414855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3930414855
Directory	/workspace/43.hmac_alert_test/latest

Test location	/workspace/coverage/default/43.hmac_back_pressure.2697694806
Short name	T22
Test name
Test status
Simulation time	3724864861 ps
CPU time	39.12 seconds
Started	Jun 21 06:04:10 PM PDT 24
Finished	Jun 21 06:04:50 PM PDT 24
Peak memory	200104 kb
Host	smart-3c3c627d-0659-483f-998e-78359b3695f6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2697694806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2697694806
Directory	/workspace/43.hmac_back_pressure/latest

Test location	/workspace/coverage/default/43.hmac_burst_wr.636022576
Short name	T492
Test name
Test status
Simulation time	1424100466 ps
CPU time	25.49 seconds
Started	Jun 21 06:04:10 PM PDT 24
Finished	Jun 21 06:04:37 PM PDT 24
Peak memory	199952 kb
Host	smart-d4d1ec26-2b2b-4229-b347-f2ebe1182a28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=636022576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.636022576
Directory	/workspace/43.hmac_burst_wr/latest

Test location	/workspace/coverage/default/43.hmac_datapath_stress.2117534689
Short name	T354
Test name
Test status
Simulation time	959262348 ps
CPU time	48.12 seconds
Started	Jun 21 06:04:10 PM PDT 24
Finished	Jun 21 06:04:59 PM PDT 24
Peak memory	335508 kb
Host	smart-7c8172ad-81ee-4d8b-9ba3-5284f6df3c92
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2117534689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2117534689
Directory	/workspace/43.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/43.hmac_error.3393658569
Short name	T474
Test name
Test status
Simulation time	12069096576 ps
CPU time	79.13 seconds
Started	Jun 21 06:04:11 PM PDT 24
Finished	Jun 21 06:05:31 PM PDT 24
Peak memory	200096 kb
Host	smart-01d46e52-31ff-4fb6-b4d0-57c7cc84bc58
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393658569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3393658569
Directory	/workspace/43.hmac_error/latest

Test location	/workspace/coverage/default/43.hmac_long_msg.1141686885
Short name	T143
Test name
Test status
Simulation time	10880440728 ps
CPU time	46.41 seconds
Started	Jun 21 06:04:02 PM PDT 24
Finished	Jun 21 06:04:49 PM PDT 24
Peak memory	200136 kb
Host	smart-3fe32a97-3432-4c4a-935e-9c68cdab52b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1141686885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1141686885
Directory	/workspace/43.hmac_long_msg/latest

Test location	/workspace/coverage/default/43.hmac_smoke.2062370592
Short name	T377
Test name
Test status
Simulation time	1722908340 ps
CPU time	15.1 seconds
Started	Jun 21 06:04:01 PM PDT 24
Finished	Jun 21 06:04:17 PM PDT 24
Peak memory	200088 kb
Host	smart-9668f224-cd52-4b8f-a755-52b97d9c3aff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2062370592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2062370592
Directory	/workspace/43.hmac_smoke/latest

Test location	/workspace/coverage/default/43.hmac_test_hmac_vectors.2701291484
Short name	T218
Test name
Test status
Simulation time	55211289 ps
CPU time	1.14 seconds
Started	Jun 21 06:04:10 PM PDT 24
Finished	Jun 21 06:04:12 PM PDT 24
Peak memory	199572 kb
Host	smart-016fe7eb-34d7-4467-87b5-2669ebcfca3f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701291484 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_hmac_vectors.2701291484
Directory	/workspace/43.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/43.hmac_test_sha256_vectors.2247263405
Short name	T179
Test name
Test status
Simulation time	88821225801 ps
CPU time	570.54 seconds
Started	Jun 21 06:04:11 PM PDT 24
Finished	Jun 21 06:13:42 PM PDT 24
Peak memory	200152 kb
Host	smart-e9daf08a-abbd-4d85-9e39-3ceb01a41690
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2247263405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha256_vectors.2247263405
Directory	/workspace/43.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/43.hmac_test_sha384_vectors.3596304978
Short name	T352
Test name
Test status
Simulation time	860380553772 ps
CPU time	1974.44 seconds
Started	Jun 21 06:04:10 PM PDT 24
Finished	Jun 21 06:37:05 PM PDT 24
Peak memory	215572 kb
Host	smart-b42a9cad-ff9f-4503-8062-cafc69abca4a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3596304978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha384_vectors.3596304978
Directory	/workspace/43.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/43.hmac_wipe_secret.3472735043
Short name	T523
Test name
Test status
Simulation time	3333879339 ps
CPU time	62.15 seconds
Started	Jun 21 06:04:11 PM PDT 24
Finished	Jun 21 06:05:13 PM PDT 24
Peak memory	200152 kb
Host	smart-1266f99f-9b04-4f0d-9238-ea34f6f4ada8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3472735043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3472735043
Directory	/workspace/43.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/44.hmac_alert_test.1664059176
Short name	T402
Test name
Test status
Simulation time	15113188 ps
CPU time	0.57 seconds
Started	Jun 21 06:04:19 PM PDT 24
Finished	Jun 21 06:04:21 PM PDT 24
Peak memory	195924 kb
Host	smart-0096a603-8bf1-41c1-bad1-4143992f6fcd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664059176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1664059176
Directory	/workspace/44.hmac_alert_test/latest

Test location	/workspace/coverage/default/44.hmac_back_pressure.3892806745
Short name	T287
Test name
Test status
Simulation time	1018363672 ps
CPU time	48.78 seconds
Started	Jun 21 06:04:09 PM PDT 24
Finished	Jun 21 06:04:58 PM PDT 24
Peak memory	200076 kb
Host	smart-74876c78-8720-424f-9e28-f6ff40447ac9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3892806745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3892806745
Directory	/workspace/44.hmac_back_pressure/latest

Test location	/workspace/coverage/default/44.hmac_burst_wr.2910442667
Short name	T647
Test name
Test status
Simulation time	467182780 ps
CPU time	26.49 seconds
Started	Jun 21 06:04:12 PM PDT 24
Finished	Jun 21 06:04:38 PM PDT 24
Peak memory	200032 kb
Host	smart-a5c55ff2-9f0f-40eb-ac5f-707ebd4e7341
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2910442667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2910442667
Directory	/workspace/44.hmac_burst_wr/latest

Test location	/workspace/coverage/default/44.hmac_datapath_stress.1496512684
Short name	T82
Test name
Test status
Simulation time	4265711820 ps
CPU time	251.12 seconds
Started	Jun 21 06:04:10 PM PDT 24
Finished	Jun 21 06:08:21 PM PDT 24
Peak memory	607852 kb
Host	smart-789adfa6-428e-40e5-83ed-1661f2e4ea59
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1496512684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1496512684
Directory	/workspace/44.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/44.hmac_error.114598895
Short name	T485
Test name
Test status
Simulation time	7764681521 ps
CPU time	141.69 seconds
Started	Jun 21 06:04:09 PM PDT 24
Finished	Jun 21 06:06:31 PM PDT 24
Peak memory	200100 kb
Host	smart-317b3fbc-7c55-4164-9176-3ca2b8d723aa
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114598895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.114598895
Directory	/workspace/44.hmac_error/latest

Test location	/workspace/coverage/default/44.hmac_long_msg.3501377185
Short name	T170
Test name
Test status
Simulation time	4385279985 ps
CPU time	64.5 seconds
Started	Jun 21 06:04:09 PM PDT 24
Finished	Jun 21 06:05:14 PM PDT 24
Peak memory	200076 kb
Host	smart-e39784c8-213c-401a-8d50-507df775ad90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3501377185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3501377185
Directory	/workspace/44.hmac_long_msg/latest

Test location	/workspace/coverage/default/44.hmac_smoke.2864586484
Short name	T459
Test name
Test status
Simulation time	540842530 ps
CPU time	8.42 seconds
Started	Jun 21 06:04:10 PM PDT 24
Finished	Jun 21 06:04:19 PM PDT 24
Peak memory	200060 kb
Host	smart-86d0aae4-88dc-459a-a324-976233b65d4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2864586484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2864586484
Directory	/workspace/44.hmac_smoke/latest

Test location	/workspace/coverage/default/44.hmac_test_hmac_vectors.3508139122
Short name	T200
Test name
Test status
Simulation time	126964392 ps
CPU time	1.38 seconds
Started	Jun 21 06:04:18 PM PDT 24
Finished	Jun 21 06:04:20 PM PDT 24
Peak memory	200056 kb
Host	smart-6a27c614-6005-48f9-8159-08a94abe69c7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508139122 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_hmac_vectors.3508139122
Directory	/workspace/44.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/44.hmac_test_sha256_vectors.1062107615
Short name	T484
Test name
Test status
Simulation time	7719876587 ps
CPU time	457.72 seconds
Started	Jun 21 06:04:18 PM PDT 24
Finished	Jun 21 06:11:57 PM PDT 24
Peak memory	200080 kb
Host	smart-2a28732e-c5bf-4dad-9c36-455ef80445ec
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1062107615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha256_vectors.1062107615
Directory	/workspace/44.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/44.hmac_test_sha384_vectors.1478520287
Short name	T511
Test name
Test status
Simulation time	31435037185 ps
CPU time	1831.89 seconds
Started	Jun 21 06:04:19 PM PDT 24
Finished	Jun 21 06:34:52 PM PDT 24
Peak memory	215516 kb
Host	smart-3a495d0c-895d-4796-9ba4-461ae7b6556a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1478520287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha384_vectors.1478520287
Directory	/workspace/44.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/44.hmac_test_sha512_vectors.462776297
Short name	T87
Test name
Test status
Simulation time	551537981041 ps
CPU time	1791.03 seconds
Started	Jun 21 06:04:17 PM PDT 24
Finished	Jun 21 06:34:09 PM PDT 24
Peak memory	215900 kb
Host	smart-8b538056-21eb-4e1d-bf61-e42178a516f5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=462776297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha512_vectors.462776297
Directory	/workspace/44.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/44.hmac_wipe_secret.3143653848
Short name	T562
Test name
Test status
Simulation time	794292669 ps
CPU time	41.23 seconds
Started	Jun 21 06:04:18 PM PDT 24
Finished	Jun 21 06:05:00 PM PDT 24
Peak memory	200076 kb
Host	smart-0fba72eb-c341-45f8-9e79-02bbe8f217a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3143653848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3143653848
Directory	/workspace/44.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/45.hmac_alert_test.3828119617
Short name	T425
Test name
Test status
Simulation time	29284771 ps
CPU time	0.58 seconds
Started	Jun 21 06:04:28 PM PDT 24
Finished	Jun 21 06:04:29 PM PDT 24
Peak memory	194964 kb
Host	smart-fa103f7c-5098-429b-84ca-505d74f421ef
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828119617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3828119617
Directory	/workspace/45.hmac_alert_test/latest

Test location	/workspace/coverage/default/45.hmac_back_pressure.1877104401
Short name	T81
Test name
Test status
Simulation time	480831918 ps
CPU time	10.84 seconds
Started	Jun 21 06:04:20 PM PDT 24
Finished	Jun 21 06:04:32 PM PDT 24
Peak memory	199992 kb
Host	smart-aa8fcdcf-ac46-43c2-9adf-8f3c6eba250e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1877104401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1877104401
Directory	/workspace/45.hmac_back_pressure/latest

Test location	/workspace/coverage/default/45.hmac_burst_wr.1706081575
Short name	T47
Test name
Test status
Simulation time	5600042216 ps
CPU time	31.18 seconds
Started	Jun 21 06:04:18 PM PDT 24
Finished	Jun 21 06:04:51 PM PDT 24
Peak memory	200184 kb
Host	smart-5a5bdd8c-446f-4218-9a2a-5d7f0f4b649a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1706081575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1706081575
Directory	/workspace/45.hmac_burst_wr/latest

Test location	/workspace/coverage/default/45.hmac_datapath_stress.95460103
Short name	T301
Test name
Test status
Simulation time	6931999489 ps
CPU time	951.63 seconds
Started	Jun 21 06:04:18 PM PDT 24
Finished	Jun 21 06:20:11 PM PDT 24
Peak memory	722536 kb
Host	smart-4cb39508-491c-4397-ad49-19eef8d7b5fd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=95460103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.95460103
Directory	/workspace/45.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/45.hmac_error.138236220
Short name	T632
Test name
Test status
Simulation time	24003570680 ps
CPU time	118.89 seconds
Started	Jun 21 06:04:18 PM PDT 24
Finished	Jun 21 06:06:18 PM PDT 24
Peak memory	200140 kb
Host	smart-354c233b-098d-4a42-9e1a-ae3730bd949c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138236220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.138236220
Directory	/workspace/45.hmac_error/latest

Test location	/workspace/coverage/default/45.hmac_long_msg.2024749515
Short name	T261
Test name
Test status
Simulation time	1833211563 ps
CPU time	57.93 seconds
Started	Jun 21 06:04:19 PM PDT 24
Finished	Jun 21 06:05:18 PM PDT 24
Peak memory	200100 kb
Host	smart-a5791b37-51e4-4acf-b087-2d7d3b819311
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2024749515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.2024749515
Directory	/workspace/45.hmac_long_msg/latest

Test location	/workspace/coverage/default/45.hmac_smoke.401847632
Short name	T313
Test name
Test status
Simulation time	58500003 ps
CPU time	2.61 seconds
Started	Jun 21 06:04:19 PM PDT 24
Finished	Jun 21 06:04:23 PM PDT 24
Peak memory	200064 kb
Host	smart-6222486e-64bc-4ac5-86d2-c782250f8c5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=401847632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.401847632
Directory	/workspace/45.hmac_smoke/latest

Test location	/workspace/coverage/default/45.hmac_test_hmac_vectors.1779662309
Short name	T650
Test name
Test status
Simulation time	62393345 ps
CPU time	1.2 seconds
Started	Jun 21 06:04:27 PM PDT 24
Finished	Jun 21 06:04:29 PM PDT 24
Peak memory	200060 kb
Host	smart-569ecb7f-77f2-42fe-a93f-740f938fe35b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779662309 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_hmac_vectors.1779662309
Directory	/workspace/45.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/45.hmac_test_sha256_vectors.2518307460
Short name	T635
Test name
Test status
Simulation time	234064713360 ps
CPU time	503 seconds
Started	Jun 21 06:04:19 PM PDT 24
Finished	Jun 21 06:12:43 PM PDT 24
Peak memory	200140 kb
Host	smart-e6d1d8ea-80be-471f-9d54-be280288dba5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2518307460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha256_vectors.2518307460
Directory	/workspace/45.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/45.hmac_test_sha384_vectors.391145928
Short name	T574
Test name
Test status
Simulation time	35637328947 ps
CPU time	1942.57 seconds
Started	Jun 21 06:04:18 PM PDT 24
Finished	Jun 21 06:36:43 PM PDT 24
Peak memory	215540 kb
Host	smart-806f5d3e-b988-44dc-8952-388f5c54c3f8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=391145928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha384_vectors.391145928
Directory	/workspace/45.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/45.hmac_test_sha512_vectors.1745679944
Short name	T410
Test name
Test status
Simulation time	775900611702 ps
CPU time	1997.86 seconds
Started	Jun 21 06:04:28 PM PDT 24
Finished	Jun 21 06:37:46 PM PDT 24
Peak memory	215608 kb
Host	smart-6628aeb2-b9fd-4e4f-b5a9-b1873dd6d1fb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1745679944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha512_vectors.1745679944
Directory	/workspace/45.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/45.hmac_wipe_secret.129792339
Short name	T462
Test name
Test status
Simulation time	1146060127 ps
CPU time	67.85 seconds
Started	Jun 21 06:04:19 PM PDT 24
Finished	Jun 21 06:05:28 PM PDT 24
Peak memory	200064 kb
Host	smart-6094a7c2-d9eb-4929-abaa-e3d80f29c25e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=129792339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.129792339
Directory	/workspace/45.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/46.hmac_alert_test.299620634
Short name	T652
Test name
Test status
Simulation time	60001737 ps
CPU time	0.61 seconds
Started	Jun 21 06:04:34 PM PDT 24
Finished	Jun 21 06:04:36 PM PDT 24
Peak memory	195692 kb
Host	smart-77223cdc-9ebc-4922-9927-ad190beb7e26
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299620634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.299620634
Directory	/workspace/46.hmac_alert_test/latest

Test location	/workspace/coverage/default/46.hmac_back_pressure.4161941087
Short name	T613
Test name
Test status
Simulation time	553403430 ps
CPU time	15.75 seconds
Started	Jun 21 06:04:27 PM PDT 24
Finished	Jun 21 06:04:43 PM PDT 24
Peak memory	200008 kb
Host	smart-ef8820ec-5f76-4b20-9782-a8175f957eb0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4161941087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.4161941087
Directory	/workspace/46.hmac_back_pressure/latest

Test location	/workspace/coverage/default/46.hmac_burst_wr.3582389415
Short name	T137
Test name
Test status
Simulation time	5314392240 ps
CPU time	65.49 seconds
Started	Jun 21 06:04:28 PM PDT 24
Finished	Jun 21 06:05:34 PM PDT 24
Peak memory	200084 kb
Host	smart-d4077eeb-94ad-4caf-a1d6-c16ff5ca8b47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3582389415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3582389415
Directory	/workspace/46.hmac_burst_wr/latest

Test location	/workspace/coverage/default/46.hmac_datapath_stress.1054721344
Short name	T364
Test name
Test status
Simulation time	13747180026 ps
CPU time	970.12 seconds
Started	Jun 21 06:04:27 PM PDT 24
Finished	Jun 21 06:20:37 PM PDT 24
Peak memory	771708 kb
Host	smart-88ca97f7-6f4d-4a0f-a965-7c6383cd6f62
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1054721344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1054721344
Directory	/workspace/46.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/46.hmac_error.4031577031
Short name	T183
Test name
Test status
Simulation time	2233695977 ps
CPU time	138.85 seconds
Started	Jun 21 06:04:27 PM PDT 24
Finished	Jun 21 06:06:46 PM PDT 24
Peak memory	200120 kb
Host	smart-03576f40-01bf-4ddd-b292-4ee52164150f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031577031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.4031577031
Directory	/workspace/46.hmac_error/latest

Test location	/workspace/coverage/default/46.hmac_long_msg.2688815328
Short name	T343
Test name
Test status
Simulation time	7180152222 ps
CPU time	75.58 seconds
Started	Jun 21 06:04:27 PM PDT 24
Finished	Jun 21 06:05:44 PM PDT 24
Peak memory	200124 kb
Host	smart-9c644303-ca0f-4fb4-82f7-99eb3dc362cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2688815328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2688815328
Directory	/workspace/46.hmac_long_msg/latest

Test location	/workspace/coverage/default/46.hmac_smoke.1476137156
Short name	T207
Test name
Test status
Simulation time	1332705820 ps
CPU time	7.94 seconds
Started	Jun 21 06:04:26 PM PDT 24
Finished	Jun 21 06:04:35 PM PDT 24
Peak memory	200016 kb
Host	smart-d180f720-73d9-40bb-a56b-18262e50806c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1476137156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1476137156
Directory	/workspace/46.hmac_smoke/latest

Test location	/workspace/coverage/default/46.hmac_test_hmac_vectors.2138343068
Short name	T358
Test name
Test status
Simulation time	103128646 ps
CPU time	1.11 seconds
Started	Jun 21 06:04:39 PM PDT 24
Finished	Jun 21 06:04:41 PM PDT 24
Peak memory	199788 kb
Host	smart-6df8c695-1d34-44b2-82e7-7b9cfb9923c8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138343068 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_hmac_vectors.2138343068
Directory	/workspace/46.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/46.hmac_test_sha256_vectors.1706581986
Short name	T188
Test name
Test status
Simulation time	164295312201 ps
CPU time	555.64 seconds
Started	Jun 21 06:04:28 PM PDT 24
Finished	Jun 21 06:13:45 PM PDT 24
Peak memory	200140 kb
Host	smart-c24a104a-29fd-4db3-a1f8-d738a6669d5d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1706581986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha256_vectors.1706581986
Directory	/workspace/46.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/46.hmac_test_sha384_vectors.1598389018
Short name	T291
Test name
Test status
Simulation time	134774763124 ps
CPU time	1834.5 seconds
Started	Jun 21 06:04:35 PM PDT 24
Finished	Jun 21 06:35:11 PM PDT 24
Peak memory	215620 kb
Host	smart-c111fd19-a35e-438d-b9b4-d30c9525a906
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1598389018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha384_vectors.1598389018
Directory	/workspace/46.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/46.hmac_test_sha512_vectors.4269961874
Short name	T609
Test name
Test status
Simulation time	152764562309 ps
CPU time	1906.94 seconds
Started	Jun 21 06:04:34 PM PDT 24
Finished	Jun 21 06:36:22 PM PDT 24
Peak memory	215992 kb
Host	smart-f56367e7-dff7-496a-b213-7f6cc38d73d9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=4269961874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha512_vectors.4269961874
Directory	/workspace/46.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/46.hmac_wipe_secret.865398771
Short name	T116
Test name
Test status
Simulation time	15945810274 ps
CPU time	61.03 seconds
Started	Jun 21 06:04:27 PM PDT 24
Finished	Jun 21 06:05:29 PM PDT 24
Peak memory	200124 kb
Host	smart-47bcbf43-2404-41fc-872d-f9af11778e23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=865398771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.865398771
Directory	/workspace/46.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/47.hmac_alert_test.426135671
Short name	T216
Test name
Test status
Simulation time	29954426 ps
CPU time	0.59 seconds
Started	Jun 21 06:04:41 PM PDT 24
Finished	Jun 21 06:04:43 PM PDT 24
Peak memory	195636 kb
Host	smart-af1ac875-699a-42e3-8fa5-66fff30943ca
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426135671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.426135671
Directory	/workspace/47.hmac_alert_test/latest

Test location	/workspace/coverage/default/47.hmac_back_pressure.3358490276
Short name	T28
Test name
Test status
Simulation time	16894227729 ps
CPU time	46.78 seconds
Started	Jun 21 06:04:32 PM PDT 24
Finished	Jun 21 06:05:19 PM PDT 24
Peak memory	208324 kb
Host	smart-f9efcfe8-a263-49ae-b175-bdf361564568
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3358490276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3358490276
Directory	/workspace/47.hmac_back_pressure/latest

Test location	/workspace/coverage/default/47.hmac_burst_wr.3611367913
Short name	T494
Test name
Test status
Simulation time	10045312865 ps
CPU time	51.75 seconds
Started	Jun 21 06:04:35 PM PDT 24
Finished	Jun 21 06:05:27 PM PDT 24
Peak memory	216440 kb
Host	smart-8f9141cd-ea6e-43bd-a0cb-6c737882d479
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3611367913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3611367913
Directory	/workspace/47.hmac_burst_wr/latest

Test location	/workspace/coverage/default/47.hmac_datapath_stress.2450129114
Short name	T251
Test name
Test status
Simulation time	14663276314 ps
CPU time	366.9 seconds
Started	Jun 21 06:04:39 PM PDT 24
Finished	Jun 21 06:10:47 PM PDT 24
Peak memory	604480 kb
Host	smart-c907f0d0-cb44-416b-b953-8c3d42863fbf
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2450129114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2450129114
Directory	/workspace/47.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/47.hmac_error.3798803420
Short name	T227
Test name
Test status
Simulation time	32716785769 ps
CPU time	145.47 seconds
Started	Jun 21 06:04:33 PM PDT 24
Finished	Jun 21 06:06:59 PM PDT 24
Peak memory	200092 kb
Host	smart-f80c6b87-af12-43d1-83ec-0922a382f9ec
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798803420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3798803420
Directory	/workspace/47.hmac_error/latest

Test location	/workspace/coverage/default/47.hmac_long_msg.3003295251
Short name	T532
Test name
Test status
Simulation time	1494110957 ps
CPU time	85.13 seconds
Started	Jun 21 06:04:34 PM PDT 24
Finished	Jun 21 06:06:00 PM PDT 24
Peak memory	200084 kb
Host	smart-05903663-4773-4734-9828-a7bfad48fbbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3003295251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3003295251
Directory	/workspace/47.hmac_long_msg/latest

Test location	/workspace/coverage/default/47.hmac_smoke.2485533337
Short name	T195
Test name
Test status
Simulation time	4371609908 ps
CPU time	23.1 seconds
Started	Jun 21 06:04:34 PM PDT 24
Finished	Jun 21 06:04:58 PM PDT 24
Peak memory	200152 kb
Host	smart-14547429-86c1-41ca-95e6-3261a3abfa50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2485533337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2485533337
Directory	/workspace/47.hmac_smoke/latest

Test location	/workspace/coverage/default/47.hmac_stress_all.906437906
Short name	T65
Test name
Test status
Simulation time	151000413824 ps
CPU time	1603.99 seconds
Started	Jun 21 06:04:43 PM PDT 24
Finished	Jun 21 06:31:28 PM PDT 24
Peak memory	774132 kb
Host	smart-c448bb9d-856f-47d4-b7de-f1534f3de35c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906437906 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.906437906
Directory	/workspace/47.hmac_stress_all/latest

Test location	/workspace/coverage/default/47.hmac_test_hmac_vectors.3342751452
Short name	T226
Test name
Test status
Simulation time	115633526 ps
CPU time	1.39 seconds
Started	Jun 21 06:04:34 PM PDT 24
Finished	Jun 21 06:04:36 PM PDT 24
Peak memory	200012 kb
Host	smart-08d28963-da54-410f-be8a-75e87db5a098
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342751452 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_hmac_vectors.3342751452
Directory	/workspace/47.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/47.hmac_test_sha256_vectors.3719991999
Short name	T202
Test name
Test status
Simulation time	34817410485 ps
CPU time	497.8 seconds
Started	Jun 21 06:04:39 PM PDT 24
Finished	Jun 21 06:12:58 PM PDT 24
Peak memory	200108 kb
Host	smart-7859291e-b482-4915-a0a4-b86af7d89c4c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3719991999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha256_vectors.3719991999
Directory	/workspace/47.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/47.hmac_test_sha384_vectors.433719672
Short name	T516
Test name
Test status
Simulation time	158289584119 ps
CPU time	2112.04 seconds
Started	Jun 21 06:04:33 PM PDT 24
Finished	Jun 21 06:39:46 PM PDT 24
Peak memory	216064 kb
Host	smart-7e21b94a-bd92-4c65-8443-e7d8c1c1fcd5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=433719672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha384_vectors.433719672
Directory	/workspace/47.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/47.hmac_test_sha512_vectors.1924605324
Short name	T592
Test name
Test status
Simulation time	649468061702 ps
CPU time	2023.39 seconds
Started	Jun 21 06:04:34 PM PDT 24
Finished	Jun 21 06:38:18 PM PDT 24
Peak memory	215976 kb
Host	smart-2a17ffa1-deda-4734-8dcc-0c8720fff3d7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1924605324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha512_vectors.1924605324
Directory	/workspace/47.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/47.hmac_wipe_secret.3524068294
Short name	T432
Test name
Test status
Simulation time	1791001452 ps
CPU time	58.66 seconds
Started	Jun 21 06:04:39 PM PDT 24
Finished	Jun 21 06:05:39 PM PDT 24
Peak memory	200092 kb
Host	smart-664efb1e-57ef-4002-a927-894fb5397380
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3524068294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3524068294
Directory	/workspace/47.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/48.hmac_alert_test.3953734812
Short name	T32
Test name
Test status
Simulation time	28991157 ps
CPU time	0.61 seconds
Started	Jun 21 06:04:44 PM PDT 24
Finished	Jun 21 06:04:45 PM PDT 24
Peak memory	196732 kb
Host	smart-e91a23b8-4b03-4862-97fa-12f34fbfb95a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953734812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3953734812
Directory	/workspace/48.hmac_alert_test/latest

Test location	/workspace/coverage/default/48.hmac_back_pressure.1691432540
Short name	T88
Test name
Test status
Simulation time	4069332125 ps
CPU time	40.25 seconds
Started	Jun 21 06:04:41 PM PDT 24
Finished	Jun 21 06:05:22 PM PDT 24
Peak memory	208348 kb
Host	smart-35946f71-c6c3-4965-a662-34c146ae0eed
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1691432540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.1691432540
Directory	/workspace/48.hmac_back_pressure/latest

Test location	/workspace/coverage/default/48.hmac_burst_wr.3818071852
Short name	T304
Test name
Test status
Simulation time	8662461699 ps
CPU time	63.17 seconds
Started	Jun 21 06:04:42 PM PDT 24
Finished	Jun 21 06:05:46 PM PDT 24
Peak memory	200332 kb
Host	smart-fbee2651-c9f0-43a2-b590-579b80e30797
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3818071852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3818071852
Directory	/workspace/48.hmac_burst_wr/latest

Test location	/workspace/coverage/default/48.hmac_datapath_stress.4108110155
Short name	T10
Test name
Test status
Simulation time	296135037 ps
CPU time	44.1 seconds
Started	Jun 21 06:04:43 PM PDT 24
Finished	Jun 21 06:05:28 PM PDT 24
Peak memory	267536 kb
Host	smart-d18bfb66-65e4-419c-adaf-70614484c1ef
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4108110155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.4108110155
Directory	/workspace/48.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/48.hmac_error.1694463952
Short name	T567
Test name
Test status
Simulation time	5240384688 ps
CPU time	67.62 seconds
Started	Jun 21 06:04:42 PM PDT 24
Finished	Jun 21 06:05:50 PM PDT 24
Peak memory	200084 kb
Host	smart-a0dbf334-c1c9-41a6-a77e-e8f53109caa3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694463952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1694463952
Directory	/workspace/48.hmac_error/latest

Test location	/workspace/coverage/default/48.hmac_long_msg.4015693384
Short name	T615
Test name
Test status
Simulation time	16151359950 ps
CPU time	114.73 seconds
Started	Jun 21 06:04:42 PM PDT 24
Finished	Jun 21 06:06:37 PM PDT 24
Peak memory	200136 kb
Host	smart-c2c10ce2-88e4-410e-a205-90c59a44812f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4015693384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.4015693384
Directory	/workspace/48.hmac_long_msg/latest

Test location	/workspace/coverage/default/48.hmac_smoke.2193182250
Short name	T48
Test name
Test status
Simulation time	232030891 ps
CPU time	10.81 seconds
Started	Jun 21 06:04:42 PM PDT 24
Finished	Jun 21 06:04:54 PM PDT 24
Peak memory	200024 kb
Host	smart-31ec84a1-7504-491e-ab6c-9cdbfd9d3641
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2193182250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2193182250
Directory	/workspace/48.hmac_smoke/latest

Test location	/workspace/coverage/default/48.hmac_test_hmac_vectors.2912172588
Short name	T198
Test name
Test status
Simulation time	54750988 ps
CPU time	1.17 seconds
Started	Jun 21 06:04:41 PM PDT 24
Finished	Jun 21 06:04:43 PM PDT 24
Peak memory	200064 kb
Host	smart-00ddc23c-a123-4dac-8bb5-3e6ba8c7e5e1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912172588 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_hmac_vectors.2912172588
Directory	/workspace/48.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/48.hmac_test_sha256_vectors.3761835547
Short name	T309
Test name
Test status
Simulation time	143022237587 ps
CPU time	529.3 seconds
Started	Jun 21 06:04:41 PM PDT 24
Finished	Jun 21 06:13:31 PM PDT 24
Peak memory	200112 kb
Host	smart-3045e4b2-6153-4a4e-a961-de9b038c2fbd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3761835547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha256_vectors.3761835547
Directory	/workspace/48.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/48.hmac_test_sha384_vectors.3706295433
Short name	T478
Test name
Test status
Simulation time	605405637610 ps
CPU time	1877.15 seconds
Started	Jun 21 06:04:41 PM PDT 24
Finished	Jun 21 06:35:59 PM PDT 24
Peak memory	216492 kb
Host	smart-0a5d31ab-4876-4f5e-8e4e-c83905157e95
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3706295433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha384_vectors.3706295433
Directory	/workspace/48.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/48.hmac_test_sha512_vectors.370927431
Short name	T329
Test name
Test status
Simulation time	520500868496 ps
CPU time	2064.13 seconds
Started	Jun 21 06:04:43 PM PDT 24
Finished	Jun 21 06:39:08 PM PDT 24
Peak memory	215544 kb
Host	smart-4ce0e332-8966-46f0-8aff-415bea34baf4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=370927431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha512_vectors.370927431
Directory	/workspace/48.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/48.hmac_wipe_secret.3672904151
Short name	T245
Test name
Test status
Simulation time	97242349466 ps
CPU time	124.41 seconds
Started	Jun 21 06:04:41 PM PDT 24
Finished	Jun 21 06:06:46 PM PDT 24
Peak memory	200156 kb
Host	smart-bb5acf54-46bc-4c77-be28-e41f49eeca76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3672904151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3672904151
Directory	/workspace/48.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/49.hmac_alert_test.1998438140
Short name	T45
Test name
Test status
Simulation time	61716863 ps
CPU time	0.62 seconds
Started	Jun 21 06:04:56 PM PDT 24
Finished	Jun 21 06:04:57 PM PDT 24
Peak memory	196040 kb
Host	smart-e0ab463c-c386-4046-b128-e4f9792512ac
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998438140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1998438140
Directory	/workspace/49.hmac_alert_test/latest

Test location	/workspace/coverage/default/49.hmac_back_pressure.612791542
Short name	T279
Test name
Test status
Simulation time	1003912293 ps
CPU time	30.85 seconds
Started	Jun 21 06:04:49 PM PDT 24
Finished	Jun 21 06:05:21 PM PDT 24
Peak memory	200024 kb
Host	smart-cfab155e-0966-4a83-823b-7cebb1062de3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=612791542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.612791542
Directory	/workspace/49.hmac_back_pressure/latest

Test location	/workspace/coverage/default/49.hmac_burst_wr.1106294113
Short name	T132
Test name
Test status
Simulation time	8762981635 ps
CPU time	59.68 seconds
Started	Jun 21 06:04:51 PM PDT 24
Finished	Jun 21 06:05:51 PM PDT 24
Peak memory	200176 kb
Host	smart-b0a5adbe-2a9c-408f-9810-08bec6c29026
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1106294113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1106294113
Directory	/workspace/49.hmac_burst_wr/latest

Test location	/workspace/coverage/default/49.hmac_datapath_stress.2985687944
Short name	T222
Test name
Test status
Simulation time	2505668847 ps
CPU time	711.88 seconds
Started	Jun 21 06:04:49 PM PDT 24
Finished	Jun 21 06:16:42 PM PDT 24
Peak memory	704288 kb
Host	smart-0440af51-5a5c-4e1f-bc7a-84ec3f8915c5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2985687944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2985687944
Directory	/workspace/49.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/49.hmac_error.1182546467
Short name	T489
Test name
Test status
Simulation time	43786299321 ps
CPU time	137.34 seconds
Started	Jun 21 06:04:49 PM PDT 24
Finished	Jun 21 06:07:07 PM PDT 24
Peak memory	200072 kb
Host	smart-53ef228e-1114-424a-bbcf-06e28c0f5aa7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182546467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1182546467
Directory	/workspace/49.hmac_error/latest

Test location	/workspace/coverage/default/49.hmac_long_msg.1038266921
Short name	T187
Test name
Test status
Simulation time	17982295110 ps
CPU time	67.95 seconds
Started	Jun 21 06:04:49 PM PDT 24
Finished	Jun 21 06:05:58 PM PDT 24
Peak memory	200120 kb
Host	smart-a7111b17-e17e-4435-ae6e-7f6a7f8d943d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1038266921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1038266921
Directory	/workspace/49.hmac_long_msg/latest

Test location	/workspace/coverage/default/49.hmac_smoke.48784222
Short name	T161
Test name
Test status
Simulation time	2822544442 ps
CPU time	13 seconds
Started	Jun 21 06:04:49 PM PDT 24
Finished	Jun 21 06:05:03 PM PDT 24
Peak memory	200136 kb
Host	smart-18b20982-eee3-4ccd-9eda-75ee5589881d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48784222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.48784222
Directory	/workspace/49.hmac_smoke/latest

Test location	/workspace/coverage/default/49.hmac_test_hmac_vectors.2898911374
Short name	T185
Test name
Test status
Simulation time	98238117 ps
CPU time	1.2 seconds
Started	Jun 21 06:04:57 PM PDT 24
Finished	Jun 21 06:04:59 PM PDT 24
Peak memory	199824 kb
Host	smart-83c90df1-c593-48b6-a8f3-f2d9fd9205a7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898911374 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_hmac_vectors.2898911374
Directory	/workspace/49.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/49.hmac_test_sha256_vectors.2348927996
Short name	T411
Test name
Test status
Simulation time	57201269949 ps
CPU time	517.91 seconds
Started	Jun 21 06:04:48 PM PDT 24
Finished	Jun 21 06:13:27 PM PDT 24
Peak memory	200080 kb
Host	smart-ef230393-0c64-442a-b21a-07a381429f04
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2348927996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha256_vectors.2348927996
Directory	/workspace/49.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/49.hmac_test_sha384_vectors.2503861932
Short name	T334
Test name
Test status
Simulation time	304928503384 ps
CPU time	1932.82 seconds
Started	Jun 21 06:04:49 PM PDT 24
Finished	Jun 21 06:37:03 PM PDT 24
Peak memory	216524 kb
Host	smart-784b6494-aee4-4220-a336-0a458d4eeb10
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2503861932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha384_vectors.2503861932
Directory	/workspace/49.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/49.hmac_test_sha512_vectors.3930580390
Short name	T621
Test name
Test status
Simulation time	578980757595 ps
CPU time	2109.7 seconds
Started	Jun 21 06:04:50 PM PDT 24
Finished	Jun 21 06:40:01 PM PDT 24
Peak memory	215660 kb
Host	smart-516d791e-6961-4470-a0b6-b8e1e7b42bc8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3930580390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha512_vectors.3930580390
Directory	/workspace/49.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/5.hmac_alert_test.3979090764
Short name	T580
Test name
Test status
Simulation time	42428282 ps
CPU time	0.59 seconds
Started	Jun 21 06:01:17 PM PDT 24
Finished	Jun 21 06:01:19 PM PDT 24
Peak memory	195904 kb
Host	smart-e89f1b56-b9f9-4d74-aa51-a2da426f5112
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979090764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3979090764
Directory	/workspace/5.hmac_alert_test/latest

Test location	/workspace/coverage/default/5.hmac_back_pressure.3520231801
Short name	T552
Test name
Test status
Simulation time	992677263 ps
CPU time	11.06 seconds
Started	Jun 21 06:01:15 PM PDT 24
Finished	Jun 21 06:01:27 PM PDT 24
Peak memory	200024 kb
Host	smart-9eb22f8d-b8e6-4f5d-b175-fa9e29f3e2da
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3520231801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3520231801
Directory	/workspace/5.hmac_back_pressure/latest

Test location	/workspace/coverage/default/5.hmac_burst_wr.271129616
Short name	T437
Test name
Test status
Simulation time	74120498 ps
CPU time	3.89 seconds
Started	Jun 21 06:01:15 PM PDT 24
Finished	Jun 21 06:01:20 PM PDT 24
Peak memory	199968 kb
Host	smart-b0329d7f-083e-4a47-9a67-dfced09ade56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=271129616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.271129616
Directory	/workspace/5.hmac_burst_wr/latest

Test location	/workspace/coverage/default/5.hmac_datapath_stress.1961601269
Short name	T374
Test name
Test status
Simulation time	13524211973 ps
CPU time	1116.77 seconds
Started	Jun 21 06:01:15 PM PDT 24
Finished	Jun 21 06:19:54 PM PDT 24
Peak memory	748336 kb
Host	smart-b740af44-fa5d-493d-9985-d4910d93856e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1961601269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1961601269
Directory	/workspace/5.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/5.hmac_long_msg.345116983
Short name	T221
Test name
Test status
Simulation time	11301608608 ps
CPU time	78.89 seconds
Started	Jun 21 06:01:16 PM PDT 24
Finished	Jun 21 06:02:36 PM PDT 24
Peak memory	200336 kb
Host	smart-87efe416-7318-483b-93b3-41dbc927e46d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=345116983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.345116983
Directory	/workspace/5.hmac_long_msg/latest

Test location	/workspace/coverage/default/5.hmac_smoke.1022570210
Short name	T597
Test name
Test status
Simulation time	3744374747 ps
CPU time	21.98 seconds
Started	Jun 21 06:01:15 PM PDT 24
Finished	Jun 21 06:01:38 PM PDT 24
Peak memory	200180 kb
Host	smart-5822fb89-6920-4b85-9cfd-fe5aeee35ec7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1022570210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1022570210
Directory	/workspace/5.hmac_smoke/latest

Test location	/workspace/coverage/default/5.hmac_test_hmac_vectors.914047229
Short name	T174
Test name
Test status
Simulation time	62801600 ps
CPU time	1.35 seconds
Started	Jun 21 06:01:15 PM PDT 24
Finished	Jun 21 06:01:17 PM PDT 24
Peak memory	200060 kb
Host	smart-817323e0-ddcd-42bf-8dd4-3e6304d228df
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914047229 -assert nopostpr oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_hmac_vectors.914047229
Directory	/workspace/5.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/5.hmac_test_sha256_vectors.2237967269
Short name	T509
Test name
Test status
Simulation time	27069217949 ps
CPU time	378.22 seconds
Started	Jun 21 06:01:15 PM PDT 24
Finished	Jun 21 06:07:34 PM PDT 24
Peak memory	200124 kb
Host	smart-74c9d7c4-0fe7-41ad-9bd6-a41bbb573dbf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2237967269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha256_vectors.2237967269
Directory	/workspace/5.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/5.hmac_test_sha384_vectors.1684582888
Short name	T362
Test name
Test status
Simulation time	650101734093 ps
CPU time	1911.91 seconds
Started	Jun 21 06:01:16 PM PDT 24
Finished	Jun 21 06:33:09 PM PDT 24
Peak memory	215884 kb
Host	smart-3df26b49-1c63-45de-9f64-3cd2408736d3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1684582888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha384_vectors.1684582888
Directory	/workspace/5.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/5.hmac_test_sha512_vectors.1634960004
Short name	T480
Test name
Test status
Simulation time	124765795745 ps
CPU time	1812.33 seconds
Started	Jun 21 06:01:14 PM PDT 24
Finished	Jun 21 06:31:27 PM PDT 24
Peak memory	215516 kb
Host	smart-8bfdc674-05ab-41b5-b40b-1e5ad620a976
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1634960004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha512_vectors.1634960004
Directory	/workspace/5.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/5.hmac_wipe_secret.1800907376
Short name	T441
Test name
Test status
Simulation time	5058472719 ps
CPU time	95.88 seconds
Started	Jun 21 06:01:16 PM PDT 24
Finished	Jun 21 06:02:53 PM PDT 24
Peak memory	200100 kb
Host	smart-f02a234b-ecaf-439c-bbfe-02111d09066a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1800907376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1800907376
Directory	/workspace/5.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/6.hmac_alert_test.1668671749
Short name	T529
Test name
Test status
Simulation time	23270488 ps
CPU time	0.63 seconds
Started	Jun 21 06:01:14 PM PDT 24
Finished	Jun 21 06:01:15 PM PDT 24
Peak memory	195620 kb
Host	smart-f3ce3941-6482-4a2d-98bd-c00a24d7e5ea
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668671749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1668671749
Directory	/workspace/6.hmac_alert_test/latest

Test location	/workspace/coverage/default/6.hmac_back_pressure.563450558
Short name	T370
Test name
Test status
Simulation time	464952549 ps
CPU time	11.06 seconds
Started	Jun 21 06:01:14 PM PDT 24
Finished	Jun 21 06:01:27 PM PDT 24
Peak memory	199884 kb
Host	smart-75a4cbd7-0946-401b-9b62-7f8232a175c9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=563450558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.563450558
Directory	/workspace/6.hmac_back_pressure/latest

Test location	/workspace/coverage/default/6.hmac_burst_wr.2685312681
Short name	T481
Test name
Test status
Simulation time	5102378398 ps
CPU time	72.69 seconds
Started	Jun 21 06:01:14 PM PDT 24
Finished	Jun 21 06:02:28 PM PDT 24
Peak memory	200252 kb
Host	smart-34171972-57c1-4312-930d-190cd9c14551
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2685312681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2685312681
Directory	/workspace/6.hmac_burst_wr/latest

Test location	/workspace/coverage/default/6.hmac_error.1551586656
Short name	T125
Test name
Test status
Simulation time	534467422 ps
CPU time	17.55 seconds
Started	Jun 21 06:01:15 PM PDT 24
Finished	Jun 21 06:01:34 PM PDT 24
Peak memory	199980 kb
Host	smart-1604b0b0-33eb-4d0f-9c26-fb8dd9a6962e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551586656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1551586656
Directory	/workspace/6.hmac_error/latest

Test location	/workspace/coverage/default/6.hmac_long_msg.355271672
Short name	T424
Test name
Test status
Simulation time	16921999475 ps
CPU time	118.61 seconds
Started	Jun 21 06:01:17 PM PDT 24
Finished	Jun 21 06:03:16 PM PDT 24
Peak memory	216384 kb
Host	smart-7dcd12c8-3fff-4252-9f0e-c22a8fc8b8fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=355271672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.355271672
Directory	/workspace/6.hmac_long_msg/latest

Test location	/workspace/coverage/default/6.hmac_smoke.934199458
Short name	T398
Test name
Test status
Simulation time	2889932301 ps
CPU time	16.74 seconds
Started	Jun 21 06:01:12 PM PDT 24
Finished	Jun 21 06:01:30 PM PDT 24
Peak memory	200112 kb
Host	smart-d516ef9f-a9fd-42b9-8fad-04ed10eed77d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=934199458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.934199458
Directory	/workspace/6.hmac_smoke/latest

Test location	/workspace/coverage/default/6.hmac_stress_all.1280427820
Short name	T36
Test name
Test status
Simulation time	6048750886 ps
CPU time	161.06 seconds
Started	Jun 21 06:01:17 PM PDT 24
Finished	Jun 21 06:03:59 PM PDT 24
Peak memory	200020 kb
Host	smart-fb880139-e77b-496c-9e17-c7eb66e957a6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280427820 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1280427820
Directory	/workspace/6.hmac_stress_all/latest

Test location	/workspace/coverage/default/6.hmac_test_hmac_vectors.1648186344
Short name	T197
Test name
Test status
Simulation time	64332160 ps
CPU time	1.32 seconds
Started	Jun 21 06:01:13 PM PDT 24
Finished	Jun 21 06:01:15 PM PDT 24
Peak memory	199980 kb
Host	smart-b8913072-d3be-4d7e-a118-5afed51dc575
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648186344 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_hmac_vectors.1648186344
Directory	/workspace/6.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/6.hmac_test_sha256_vectors.979090740
Short name	T203
Test name
Test status
Simulation time	7611750340 ps
CPU time	451.04 seconds
Started	Jun 21 06:01:13 PM PDT 24
Finished	Jun 21 06:08:45 PM PDT 24
Peak memory	200116 kb
Host	smart-f3dc17bd-0c56-4b20-9b7d-23c9da39eb41
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=979090740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha256_vectors.979090740
Directory	/workspace/6.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/6.hmac_test_sha384_vectors.69054442
Short name	T628
Test name
Test status
Simulation time	117372021149 ps
CPU time	1656.77 seconds
Started	Jun 21 06:01:11 PM PDT 24
Finished	Jun 21 06:28:49 PM PDT 24
Peak memory	216004 kb
Host	smart-18382a39-4000-453e-a826-fdcf5e4224b4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=69054442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha384_vectors.69054442
Directory	/workspace/6.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/6.hmac_test_sha512_vectors.1881734300
Short name	T295
Test name
Test status
Simulation time	114776206031 ps
CPU time	2129.92 seconds
Started	Jun 21 06:01:15 PM PDT 24
Finished	Jun 21 06:36:47 PM PDT 24
Peak memory	215644 kb
Host	smart-66d3a155-d70d-41b8-b750-a48fb304f167
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1881734300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha512_vectors.1881734300
Directory	/workspace/6.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/6.hmac_wipe_secret.3308849580
Short name	T639
Test name
Test status
Simulation time	15457028342 ps
CPU time	63.09 seconds
Started	Jun 21 06:01:13 PM PDT 24
Finished	Jun 21 06:02:17 PM PDT 24
Peak memory	200264 kb
Host	smart-375d2228-2a89-43f2-b013-023b866a1807
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3308849580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3308849580
Directory	/workspace/6.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/7.hmac_alert_test.4029142204
Short name	T553
Test name
Test status
Simulation time	18779385 ps
CPU time	0.59 seconds
Started	Jun 21 06:01:24 PM PDT 24
Finished	Jun 21 06:01:25 PM PDT 24
Peak memory	196000 kb
Host	smart-562fac2a-85a5-4df6-9b59-4aa9d1904d62
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029142204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.4029142204
Directory	/workspace/7.hmac_alert_test/latest

Test location	/workspace/coverage/default/7.hmac_back_pressure.2072636958
Short name	T493
Test name
Test status
Simulation time	1418898215 ps
CPU time	36.07 seconds
Started	Jun 21 06:01:14 PM PDT 24
Finished	Jun 21 06:01:51 PM PDT 24
Peak memory	200120 kb
Host	smart-4e3c679e-85b9-4cd7-9d3f-7673c6078eeb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2072636958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2072636958
Directory	/workspace/7.hmac_back_pressure/latest

Test location	/workspace/coverage/default/7.hmac_burst_wr.1001344038
Short name	T306
Test name
Test status
Simulation time	4162434704 ps
CPU time	56.79 seconds
Started	Jun 21 06:01:13 PM PDT 24
Finished	Jun 21 06:02:11 PM PDT 24
Peak memory	200092 kb
Host	smart-ad2ff1b6-b659-4901-a195-eb9ec0cf1f60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1001344038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1001344038
Directory	/workspace/7.hmac_burst_wr/latest

Test location	/workspace/coverage/default/7.hmac_datapath_stress.1774442717
Short name	T406
Test name
Test status
Simulation time	587522137 ps
CPU time	38.17 seconds
Started	Jun 21 06:01:14 PM PDT 24
Finished	Jun 21 06:01:53 PM PDT 24
Peak memory	316360 kb
Host	smart-4c3b688b-7afc-46a6-b8e1-3dae73f3bd70
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1774442717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1774442717
Directory	/workspace/7.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/7.hmac_error.1086446383
Short name	T123
Test name
Test status
Simulation time	22239260569 ps
CPU time	71.57 seconds
Started	Jun 21 06:01:13 PM PDT 24
Finished	Jun 21 06:02:25 PM PDT 24
Peak memory	200132 kb
Host	smart-2a61d75d-76a7-4a4a-b6b2-568d882e2aad
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086446383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1086446383
Directory	/workspace/7.hmac_error/latest

Test location	/workspace/coverage/default/7.hmac_smoke.545758307
Short name	T455
Test name
Test status
Simulation time	1152035476 ps
CPU time	12.42 seconds
Started	Jun 21 06:01:14 PM PDT 24
Finished	Jun 21 06:01:28 PM PDT 24
Peak memory	200084 kb
Host	smart-48d08d3a-e3b5-4020-9809-e0fd69daa956
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=545758307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.545758307
Directory	/workspace/7.hmac_smoke/latest

Test location	/workspace/coverage/default/7.hmac_test_hmac_vectors.2268153069
Short name	T460
Test name
Test status
Simulation time	113657036 ps
CPU time	1.35 seconds
Started	Jun 21 06:01:25 PM PDT 24
Finished	Jun 21 06:01:27 PM PDT 24
Peak memory	200084 kb
Host	smart-5b77a133-3294-4900-a9a0-1473153e9133
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268153069 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_hmac_vectors.2268153069
Directory	/workspace/7.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/7.hmac_test_sha256_vectors.2376815756
Short name	T594
Test name
Test status
Simulation time	16035641039 ps
CPU time	458.85 seconds
Started	Jun 21 06:01:19 PM PDT 24
Finished	Jun 21 06:08:58 PM PDT 24
Peak memory	200112 kb
Host	smart-b344b0d2-81df-42e1-a172-6d3d70875bdd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2376815756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha256_vectors.2376815756
Directory	/workspace/7.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/7.hmac_test_sha384_vectors.3351219532
Short name	T444
Test name
Test status
Simulation time	147281688550 ps
CPU time	1991.73 seconds
Started	Jun 21 06:01:22 PM PDT 24
Finished	Jun 21 06:34:34 PM PDT 24
Peak memory	216172 kb
Host	smart-7b3abb33-fa5e-4082-844d-e3a466425b2c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3351219532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha384_vectors.3351219532
Directory	/workspace/7.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/7.hmac_test_sha512_vectors.3119058124
Short name	T155
Test name
Test status
Simulation time	114663035949 ps
CPU time	1701.35 seconds
Started	Jun 21 06:01:25 PM PDT 24
Finished	Jun 21 06:29:47 PM PDT 24
Peak memory	216536 kb
Host	smart-d85a01c2-90ca-47b9-b16a-c8040deffff0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3119058124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha512_vectors.3119058124
Directory	/workspace/7.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/7.hmac_wipe_secret.2828921060
Short name	T557
Test name
Test status
Simulation time	20701477235 ps
CPU time	77.3 seconds
Started	Jun 21 06:01:24 PM PDT 24
Finished	Jun 21 06:02:42 PM PDT 24
Peak memory	200120 kb
Host	smart-aef17efa-bf77-476d-b885-d460d3e99456
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2828921060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2828921060
Directory	/workspace/7.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/8.hmac_alert_test.3183489273
Short name	T535
Test name
Test status
Simulation time	11396466 ps
CPU time	0.6 seconds
Started	Jun 21 06:01:23 PM PDT 24
Finished	Jun 21 06:01:25 PM PDT 24
Peak memory	194912 kb
Host	smart-1d9f2593-c76c-4021-89a4-067fdb378704
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183489273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3183489273
Directory	/workspace/8.hmac_alert_test/latest

Test location	/workspace/coverage/default/8.hmac_back_pressure.3367055556
Short name	T27
Test name
Test status
Simulation time	482128979 ps
CPU time	6.91 seconds
Started	Jun 21 06:01:20 PM PDT 24
Finished	Jun 21 06:01:28 PM PDT 24
Peak memory	200052 kb
Host	smart-294db45f-6d6e-46a6-a5f4-3730bc642e25
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3367055556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3367055556
Directory	/workspace/8.hmac_back_pressure/latest

Test location	/workspace/coverage/default/8.hmac_burst_wr.2097154295
Short name	T167
Test name
Test status
Simulation time	253821358 ps
CPU time	1.63 seconds
Started	Jun 21 06:01:26 PM PDT 24
Finished	Jun 21 06:01:28 PM PDT 24
Peak memory	200076 kb
Host	smart-cba83d87-00f0-4490-8002-30493a5adbc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2097154295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2097154295
Directory	/workspace/8.hmac_burst_wr/latest

Test location	/workspace/coverage/default/8.hmac_datapath_stress.1118881448
Short name	T319
Test name
Test status
Simulation time	5148500856 ps
CPU time	234.52 seconds
Started	Jun 21 06:01:25 PM PDT 24
Finished	Jun 21 06:05:20 PM PDT 24
Peak memory	642980 kb
Host	smart-34f64c38-37ea-49db-9a1d-874a367ea137
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1118881448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1118881448
Directory	/workspace/8.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/8.hmac_error.2064666767
Short name	T438
Test name
Test status
Simulation time	1335496166 ps
CPU time	23.99 seconds
Started	Jun 21 06:01:24 PM PDT 24
Finished	Jun 21 06:01:49 PM PDT 24
Peak memory	200056 kb
Host	smart-79150e16-1d02-496e-a7da-6475696cd6ae
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064666767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2064666767
Directory	/workspace/8.hmac_error/latest

Test location	/workspace/coverage/default/8.hmac_long_msg.2986931700
Short name	T589
Test name
Test status
Simulation time	1183626174 ps
CPU time	22.1 seconds
Started	Jun 21 06:01:26 PM PDT 24
Finished	Jun 21 06:01:49 PM PDT 24
Peak memory	200088 kb
Host	smart-a893ad2b-3e46-497f-a926-46c46e095e3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2986931700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2986931700
Directory	/workspace/8.hmac_long_msg/latest

Test location	/workspace/coverage/default/8.hmac_smoke.3832474497
Short name	T160
Test name
Test status
Simulation time	251327791 ps
CPU time	11.18 seconds
Started	Jun 21 06:01:22 PM PDT 24
Finished	Jun 21 06:01:34 PM PDT 24
Peak memory	200112 kb
Host	smart-98d142af-f0ee-4df8-9574-39a9c9070167
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3832474497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3832474497
Directory	/workspace/8.hmac_smoke/latest

Test location	/workspace/coverage/default/8.hmac_test_hmac_vectors.4290240563
Short name	T378
Test name
Test status
Simulation time	59494476 ps
CPU time	1.38 seconds
Started	Jun 21 06:01:23 PM PDT 24
Finished	Jun 21 06:01:25 PM PDT 24
Peak memory	200048 kb
Host	smart-0a8dcf00-8421-44f4-aa7b-0790a6a1f34a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290240563 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_hmac_vectors.4290240563
Directory	/workspace/8.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/8.hmac_test_sha256_vectors.2996183186
Short name	T230
Test name
Test status
Simulation time	140448576637 ps
CPU time	514.06 seconds
Started	Jun 21 06:01:22 PM PDT 24
Finished	Jun 21 06:09:57 PM PDT 24
Peak memory	200140 kb
Host	smart-adb1d01c-940a-477e-935b-7cd31aedefe4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2996183186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha256_vectors.2996183186
Directory	/workspace/8.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/8.hmac_test_sha512_vectors.4032383465
Short name	T525
Test name
Test status
Simulation time	282612436460 ps
CPU time	2025.28 seconds
Started	Jun 21 06:01:25 PM PDT 24
Finished	Jun 21 06:35:11 PM PDT 24
Peak memory	215652 kb
Host	smart-1aa8917b-28ed-4bee-ab02-7530728e0e48
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=4032383465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha512_vectors.4032383465
Directory	/workspace/8.hmac_test_sha512_vectors/latest

Test location	/workspace/coverage/default/8.hmac_wipe_secret.786696401
Short name	T369
Test name
Test status
Simulation time	5984523622 ps
CPU time	74.28 seconds
Started	Jun 21 06:01:25 PM PDT 24
Finished	Jun 21 06:02:40 PM PDT 24
Peak memory	200084 kb
Host	smart-101d6c11-e5f0-4ace-aa1c-d3470e9e15d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=786696401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.786696401
Directory	/workspace/8.hmac_wipe_secret/latest

Test location	/workspace/coverage/default/9.hmac_alert_test.2783718466
Short name	T390
Test name
Test status
Simulation time	50394011 ps
CPU time	0.61 seconds
Started	Jun 21 06:01:29 PM PDT 24
Finished	Jun 21 06:01:31 PM PDT 24
Peak memory	195960 kb
Host	smart-96e50824-9335-446c-ac8d-10e0fa919fd4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783718466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2783718466
Directory	/workspace/9.hmac_alert_test/latest

Test location	/workspace/coverage/default/9.hmac_back_pressure.294423915
Short name	T623
Test name
Test status
Simulation time	450208256 ps
CPU time	20.75 seconds
Started	Jun 21 06:01:22 PM PDT 24
Finished	Jun 21 06:01:43 PM PDT 24
Peak memory	200044 kb
Host	smart-6137d038-20f3-48c6-ad90-35181d9b9c8e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=294423915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.294423915
Directory	/workspace/9.hmac_back_pressure/latest

Test location	/workspace/coverage/default/9.hmac_burst_wr.1021241172
Short name	T646
Test name
Test status
Simulation time	265428103 ps
CPU time	7.32 seconds
Started	Jun 21 06:01:18 PM PDT 24
Finished	Jun 21 06:01:26 PM PDT 24
Peak memory	200024 kb
Host	smart-e08c1f94-283c-4529-9a84-f1253a774e87
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1021241172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1021241172
Directory	/workspace/9.hmac_burst_wr/latest

Test location	/workspace/coverage/default/9.hmac_datapath_stress.3300569811
Short name	T356
Test name
Test status
Simulation time	12609023293 ps
CPU time	437.81 seconds
Started	Jun 21 06:01:25 PM PDT 24
Finished	Jun 21 06:08:44 PM PDT 24
Peak memory	648260 kb
Host	smart-29a69a83-508c-4601-bce4-4c5d5639e460
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3300569811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3300569811
Directory	/workspace/9.hmac_datapath_stress/latest

Test location	/workspace/coverage/default/9.hmac_error.181156667
Short name	T335
Test name
Test status
Simulation time	26348410403 ps
CPU time	54.42 seconds
Started	Jun 21 06:01:21 PM PDT 24
Finished	Jun 21 06:02:17 PM PDT 24
Peak memory	200100 kb
Host	smart-48403960-9f98-49a7-a439-c07fb890c5c2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181156667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.181156667
Directory	/workspace/9.hmac_error/latest

Test location	/workspace/coverage/default/9.hmac_long_msg.3630302608
Short name	T440
Test name
Test status
Simulation time	1464636340 ps
CPU time	8.3 seconds
Started	Jun 21 06:01:20 PM PDT 24
Finished	Jun 21 06:01:29 PM PDT 24
Peak memory	200028 kb
Host	smart-8e524561-1ce3-481e-819d-0407080f6f13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3630302608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3630302608
Directory	/workspace/9.hmac_long_msg/latest

Test location	/workspace/coverage/default/9.hmac_smoke.2864299458
Short name	T468
Test name
Test status
Simulation time	608783608 ps
CPU time	10.04 seconds
Started	Jun 21 06:01:22 PM PDT 24
Finished	Jun 21 06:01:33 PM PDT 24
Peak memory	200088 kb
Host	smart-e63aa9ef-48e7-41eb-b44c-7ad95a90adf8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2864299458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2864299458
Directory	/workspace/9.hmac_smoke/latest

Test location	/workspace/coverage/default/9.hmac_test_hmac_vectors.3493354174
Short name	T458
Test name
Test status
Simulation time	52909690 ps
CPU time	1.13 seconds
Started	Jun 21 06:01:28 PM PDT 24
Finished	Jun 21 06:01:31 PM PDT 24
Peak memory	199920 kb
Host	smart-81a719e1-b22f-475f-80f9-98a8d397174b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493354174 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_hmac_vectors.3493354174
Directory	/workspace/9.hmac_test_hmac_vectors/latest

Test location	/workspace/coverage/default/9.hmac_test_sha256_vectors.1042774498
Short name	T332
Test name
Test status
Simulation time	35959348249 ps
CPU time	487.41 seconds
Started	Jun 21 06:01:21 PM PDT 24
Finished	Jun 21 06:09:29 PM PDT 24
Peak memory	200108 kb
Host	smart-ac5484ae-4c1c-41e8-88c7-8f537895882e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1042774498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha256_vectors.1042774498
Directory	/workspace/9.hmac_test_sha256_vectors/latest

Test location	/workspace/coverage/default/9.hmac_test_sha384_vectors.995377631
Short name	T15
Test name
Test status
Simulation time	139198109894 ps
CPU time	1763.35 seconds
Started	Jun 21 06:01:28 PM PDT 24
Finished	Jun 21 06:30:52 PM PDT 24
Peak memory	216088 kb
Host	smart-a3a43a15-f3ca-4796-b332-7a35ae5e3827
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=995377631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha384_vectors.995377631
Directory	/workspace/9.hmac_test_sha384_vectors/latest

Test location	/workspace/coverage/default/9.hmac_wipe_secret.1962481471
Short name	T456
Test name
Test status
Simulation time	1217341305 ps
CPU time	53.01 seconds
Started	Jun 21 06:01:22 PM PDT 24
Finished	Jun 21 06:02:16 PM PDT 24
Peak memory	200064 kb
Host	smart-312db593-bc74-49ef-9f4a-d06a417b5c4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1962481471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1962481471
Directory	/workspace/9.hmac_wipe_secret/latest

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