Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	35218221	1			T1	267778		T2	12457		T4	60
all_values[1]	35218221	1			T1	267778		T2	12457		T4	60
all_values[2]	35218221	1			T1	267778		T2	12457		T4	60

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86341

1

T2

5

T4

60

T11

1115

auto[1]

105568322

1

T1

803334

T2

37366

T4

120

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87648042

1

T1

682966

T2

29689

T4

155

auto[1]

18006621

1

T1

120368

T2

7682

T4

25

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	27344	1			T2	5		T5	176		T18	2
all_values[0]	auto[0]	auto[1]	195	1			T5	3		T53	2		T122	2
all_values[0]	auto[1]	auto[0]	35137882	1			T1	267392		T2	12430		T4	59
all_values[0]	auto[1]	auto[1]	52800	1			T1	386		T2	22		T4	1
all_values[1]	auto[0]	auto[0]	23443	1			T14	318		T53	4		T38	1511
all_values[1]	auto[0]	auto[1]	176	1			T68	4		T69	5		T121	42
all_values[1]	auto[1]	auto[0]	35191646	1			T1	267778		T2	12457		T4	60
all_values[1]	auto[1]	auto[1]	2956	1			T5	84		T7	118		T17	42
all_values[2]	auto[0]	auto[0]	13419	1			T4	36		T11	1		T5	177
all_values[2]	auto[0]	auto[1]	21764	1			T4	24		T11	1114		T55	27
all_values[2]	auto[1]	auto[0]	17254308	1			T1	147796		T2	4797		T8	166
all_values[2]	auto[1]	auto[1]	17928730	1			T1	119982		T2	7660		T8	335