Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33
Crosses	32	9	23	71.88

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	2	13	86.67	100	1	1	0
msg_len_upper_cp	1	1	0	0.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	7	23	76.67	100	1	1	0
msg_len_upper_cross	2	2	0	0.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

99112

1

T1

364

T2

28

T4

4

auto[1]

54562

1

T2

26

T8

20

T11

12

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	2	13	86.67

User Defined Bins for msg_len_lower_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_1023	0	1	1
len_511	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	24682	1			T1	54		T2	8		T9	23
len_1026_2046	17482	1			T1	4		T2	6		T9	5
len_514_1022	4893	1			T1	3		T2	1		T9	3
len_2_510	23977	1			T1	120		T2	8		T4	2
len_2049	4	1			T123	4		-	-		-	-
len_2048	22	1			T14	1		T124	2		T35	1
len_2047	1	1			T125	1		-	-		-	-
len_1025	5	1			T68	3		T126	1		T127	1
len_1024	60	1			T14	2		T124	1		T35	3
len_513	2	1			T45	2		-	-		-	-
len_512	59	1			T14	1		T124	2		T35	3
len_1	587	1			T9	1		T15	2		T65	1
len_0	5063	1			T1	1		T2	4		T9	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for msg_len_upper_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_upper	0	1	1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	7	23	76.67	7

Automatically Generated Cross Bins for msg_len_lower_cross

Uncovered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[len_2049]	0	1	1
[auto[0]]	[len_1023 , len_513]	--	--	2
[auto[0]]	[len_511]	0	1	1
[auto[1]]	[len_2047]	0	1	1
[auto[1]]	[len_1023]	0	1	1
[auto[1]]	[len_511]	0	1	1

Covered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	14794	1			T1	54		T2	5		T9	23
auto[0]	len_1026_2046	8938	1			T1	4		T2	5		T9	5
auto[0]	len_514_1022	3198	1			T1	3		T9	3		T10	4
auto[0]	len_2_510	20638	1			T1	120		T2	3		T4	2
auto[0]	len_2048	15	1			T14	1		T124	2		T35	1
auto[0]	len_2047	1	1			T125	1		-	-		-	-
auto[0]	len_1025	1	1			T126	1		-	-		-	-
auto[0]	len_1024	37	1			T14	2		T124	1		T35	2
auto[0]	len_512	40	1			T14	1		T124	1		T35	2
auto[0]	len_1	153	1			T9	1		T15	2		T65	1
auto[0]	len_0	1741	1			T1	1		T2	1		T9	1
auto[1]	len_2050_plus	9888	1			T2	3		T11	2		T16	1
auto[1]	len_1026_2046	8544	1			T2	1		T11	1		T16	4
auto[1]	len_514_1022	1695	1			T2	1		T14	10		T42	2
auto[1]	len_2_510	3339	1			T2	5		T8	10		T12	1
auto[1]	len_2049	4	1			T123	4		-	-		-	-
auto[1]	len_2048	7	1			T128	1		T129	1		T130	1
auto[1]	len_1025	4	1			T68	3		T127	1		-	-
auto[1]	len_1024	23	1			T35	1		T131	1		T129	1
auto[1]	len_513	2	1			T45	2		-	-		-	-
auto[1]	len_512	19	1			T124	1		T35	1		T132	1
auto[1]	len_1	434	1			T30	2		T18	5		T133	10
auto[1]	len_0	3322	1			T2	3		T11	3		T13	2

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	2	0	0.00	2

Automatically Generated Cross Bins for msg_len_upper_cross

Uncovered bins

hmac_en	msg_len_upper_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	2