Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::save_and_restore_cg

Group : hmac_env_pkg::hmac_env_cov::save_and_restore_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

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Summary for Group hmac_env_pkg::hmac_env_cov::save_and_restore_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	9	0	9	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::save_and_restore_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size_cp	3	0	3	100.00	100	1	1	0
save_and_restore_cp	3	0	3	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::save_and_restore_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sar_type_x_digest_size	9	0	9	100.00	100	1	1	0

Summary for Variable digest_size_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for digest_size_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_512	128	1			T2	1		T34	1		T17	1
sha2_384	152	1			T2	2		T5	2		T14	1
sha2_256	145	1			T7	1		T34	4		T124	1

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Summary for Variable save_and_restore_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for save_and_restore_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
stop_and_continue	142	1			T2	2		T5	1		T34	3
different_context	151	1			T14	1		T7	2		T34	2
same_context	132	1			T2	1		T5	1		T7	1

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Summary for Cross sar_type_x_digest_size

Samples crossed: save_and_restore_cp digest_size_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	9	0	9	100.00

Automatically Generated Cross Bins for sar_type_x_digest_size

Bins

save_and_restore_cp	digest_size_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
stop_and_continue	sha2_512	44	1			T37	2		T35	2		T149	1
stop_and_continue	sha2_384	49	1			T2	2		T5	1		T37	1
stop_and_continue	sha2_256	49	1			T34	3		T124	1		T36	1
different_context	sha2_512	47	1			T34	1		T17	1		T150	1
different_context	sha2_384	48	1			T14	1		T7	1		T124	1
different_context	sha2_256	56	1			T7	1		T34	1		T35	1
same_context	sha2_512	37	1			T2	1		T35	2		T23	1
same_context	sha2_384	55	1			T5	1		T7	1		T35	1
same_context	sha2_256	40	1			T35	1		T23	1		T151	1