Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17336445

1

T1

147409

T2

8859

T8

194

auto[1]

1220017

1

T2

3502

T4

57

T8

259

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1240333

1

T2

6583

T4

57

T8

288

auto[1]

17316129

1

T1

147409

T2

5778

T8

165

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16780584

1

T1

147409

T2

7405

T4

57

auto[1]

1775878

1

T2

4956

T8

249

T11

733

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	16284638	1			T1	112928		T2	12120		T4	57
fifo_depth[1]	482736	1			T1	4988		T2	134		T8	2
fifo_depth[2]	359014	1			T1	5013		T2	78		T8	2
fifo_depth[3]	283713	1			T1	4631		T2	19		T8	8
fifo_depth[4]	220917	1			T1	3958		T2	9		T8	1
fifo_depth[5]	173731	1			T1	3314		T2	1		T8	5
fifo_depth[6]	150946	1			T1	2923		T8	3		T9	1
fifo_depth[7]	134655	1			T1	2663		T8	3		T15	998

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2271824

1

T1

34481

T2

241

T8

40

auto[1]

16284638

1

T1

112928

T2

12120

T4

57

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18552736

1

T1

147409

T2

12361

T4

57

auto[1]

3726

1

T5

1

T6

1

T7

4

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

29093

1

T2

58

T8

21

T11

8

auto[0]

auto[0]

auto[0]

auto[1]

30365

1

T2

54

T16

9

T20

233

auto[0]

auto[0]

auto[1]

auto[0]

1920710

1

T1

34481

T2

42

T9

2275

auto[0]

auto[0]

auto[1]

auto[1]

33730

1

T2

16

T16

81

T20

317

auto[0]

auto[1]

auto[0]

auto[0]

67039

1

T2

24

T19

8

T16

88

auto[0]

auto[1]

auto[0]

auto[1]

49685

1

T2

5

T11

2

T19

1

auto[0]

auto[1]

auto[1]

auto[0]

67768

1

T8

7

T11

6

T12

3

auto[0]

auto[1]

auto[1]

auto[1]

73434

1

T2

42

T8

12

T19

12

auto[1]

auto[0]

auto[0]

auto[0]

145629

1

T2

2516

T8

55

T11

600

auto[1]

auto[0]

auto[0]

auto[1]

152132

1

T2

896

T4

57

T8

35

auto[1]

auto[0]

auto[1]

auto[0]

14310075

1

T1

112928

T2

2740

T8

70

auto[1]

auto[0]

auto[1]

auto[1]

158850

1

T2

1083

T8

23

T11

20

auto[1]

auto[1]

auto[0]

auto[0]

421694

1

T2

2486

T8

25

T11

6

auto[1]

auto[1]

auto[0]

auto[1]

344696

1

T2

544

T8

152

T11

216

auto[1]

auto[1]

auto[1]

auto[0]

374437

1

T2

993

T8

16

T11

502

auto[1]

auto[1]

auto[1]

auto[1]

377125

1

T2

862

T8

37

T11

1

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

174564

1

T2

2574

T8

76

T11

608

auto[0]

auto[0]

auto[0]

auto[1]

181705

1

T2

950

T4

57

T8

35

auto[0]

auto[0]

auto[1]

auto[0]

16230180

1

T1

147409

T2

2782

T8

70

auto[0]

auto[0]

auto[1]

auto[1]

192055

1

T2

1099

T8

23

T11

20

auto[0]

auto[1]

auto[0]

auto[0]

487990

1

T2

2510

T8

25

T11

6

auto[0]

auto[1]

auto[0]

auto[1]

394228

1

T2

549

T8

152

T11

218

auto[0]

auto[1]

auto[1]

auto[0]

441645

1

T2

993

T8

23

T11

508

auto[0]

auto[1]

auto[1]

auto[1]

450369

1

T2

904

T8

49

T11

1

auto[1]

auto[0]

auto[0]

auto[0]

158

1

T6

1

T130

7

T68

4

auto[1]

auto[0]

auto[0]

auto[1]

792

1

T132

151

T130

3

T68

330

auto[1]

auto[0]

auto[1]

auto[0]

605

1

T124

238

T152

1

T130

216

auto[1]

auto[0]

auto[1]

auto[1]

525

1

T7

1

T124

69

T150

6

auto[1]

auto[1]

auto[0]

auto[0]

743

1

T7

2

T153

36

T23

1

auto[1]

auto[1]

auto[0]

auto[1]

153

1

T5

1

T124

14

T154

4

auto[1]

auto[1]

auto[1]

auto[0]

560

1

T7

1

T155

1

T156

54

auto[1]

auto[1]

auto[1]

auto[1]

190

1

T124

41

T33

1

T155

70

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	145629	1			T2	2516		T8	55		T11	600
fifo_depth[0]	auto[0]	auto[0]	auto[1]	152132	1			T2	896		T4	57		T8	35
fifo_depth[0]	auto[0]	auto[1]	auto[0]	14310075	1			T1	112928		T2	2740		T8	70
fifo_depth[0]	auto[0]	auto[1]	auto[1]	158850	1			T2	1083		T8	23		T11	20
fifo_depth[0]	auto[1]	auto[0]	auto[0]	421694	1			T2	2486		T8	25		T11	6
fifo_depth[0]	auto[1]	auto[0]	auto[1]	344696	1			T2	544		T8	152		T11	216
fifo_depth[0]	auto[1]	auto[1]	auto[0]	374437	1			T2	993		T8	16		T11	502
fifo_depth[0]	auto[1]	auto[1]	auto[1]	377125	1			T2	862		T8	37		T11	1
fifo_depth[1]	auto[0]	auto[0]	auto[0]	3462	1			T2	31		T8	1		T11	8
fifo_depth[1]	auto[0]	auto[0]	auto[1]	3695	1			T2	36		T20	21		T31	29
fifo_depth[1]	auto[0]	auto[1]	auto[0]	444909	1			T1	4988		T2	22		T9	1367
fifo_depth[1]	auto[0]	auto[1]	auto[1]	3955	1			T2	6		T16	8		T20	35
fifo_depth[1]	auto[1]	auto[0]	auto[0]	6656	1			T2	12		T19	6		T16	7
fifo_depth[1]	auto[1]	auto[0]	auto[1]	5331	1			T2	3		T11	2		T18	50
fifo_depth[1]	auto[1]	auto[1]	auto[0]	7439	1			T11	5		T12	3		T19	2
fifo_depth[1]	auto[1]	auto[1]	auto[1]	7289	1			T2	24		T8	1		T19	6
fifo_depth[2]	auto[0]	auto[0]	auto[0]	3003	1			T2	20		T8	2		T19	1
fifo_depth[2]	auto[0]	auto[0]	auto[1]	2843	1			T2	15		T16	2		T20	25
fifo_depth[2]	auto[0]	auto[1]	auto[0]	325049	1			T1	5013		T2	13		T9	568
fifo_depth[2]	auto[0]	auto[1]	auto[1]	3611	1			T2	7		T16	8		T20	38
fifo_depth[2]	auto[1]	auto[0]	auto[0]	6105	1			T2	10		T19	1		T16	10
fifo_depth[2]	auto[1]	auto[0]	auto[1]	4910	1			T2	1		T18	45		T42	1
fifo_depth[2]	auto[1]	auto[1]	auto[0]	6632	1			T11	1		T19	1		T16	7
fifo_depth[2]	auto[1]	auto[1]	auto[1]	6861	1			T2	12		T19	4		T20	20
fifo_depth[3]	auto[0]	auto[0]	auto[0]	2205	1			T2	5		T8	5		T16	16
fifo_depth[3]	auto[0]	auto[0]	auto[1]	2050	1			T2	1		T20	20		T31	9
fifo_depth[3]	auto[0]	auto[1]	auto[0]	254584	1			T1	4631		T2	7		T9	247
fifo_depth[3]	auto[0]	auto[1]	auto[1]	2685	1			T2	2		T16	8		T20	32
fifo_depth[3]	auto[1]	auto[0]	auto[0]	5483	1			T19	1		T16	7		T20	30
fifo_depth[3]	auto[1]	auto[0]	auto[1]	4302	1			T2	1		T19	1		T18	49
fifo_depth[3]	auto[1]	auto[1]	auto[0]	5898	1			T8	1		T16	7		T21	13
fifo_depth[3]	auto[1]	auto[1]	auto[1]	6506	1			T2	3		T8	2		T19	1
fifo_depth[4]	auto[0]	auto[0]	auto[0]	2060	1			T2	2		T8	1		T16	11
fifo_depth[4]	auto[0]	auto[0]	auto[1]	1983	1			T2	2		T16	3		T20	19
fifo_depth[4]	auto[0]	auto[1]	auto[0]	193041	1			T1	3958		T9	79		T10	46
fifo_depth[4]	auto[0]	auto[1]	auto[1]	2912	1			T2	1		T16	9		T20	37
fifo_depth[4]	auto[1]	auto[0]	auto[0]	5154	1			T2	1		T16	9		T20	23
fifo_depth[4]	auto[1]	auto[0]	auto[1]	3982	1			T18	54		T56	40		T57	3
fifo_depth[4]	auto[1]	auto[1]	auto[0]	5766	1			T16	10		T14	4		T21	8
fifo_depth[4]	auto[1]	auto[1]	auto[1]	6019	1			T2	3		T20	23		T18	73
fifo_depth[5]	auto[0]	auto[0]	auto[0]	1653	1			T8	3		T16	14		T14	3
fifo_depth[5]	auto[0]	auto[0]	auto[1]	1609	1			T16	1		T20	15		T31	1
fifo_depth[5]	auto[0]	auto[1]	auto[0]	148565	1			T1	3314		T9	13		T10	11
fifo_depth[5]	auto[0]	auto[1]	auto[1]	2193	1			T16	10		T20	41		T42	3
fifo_depth[5]	auto[1]	auto[0]	auto[0]	4832	1			T2	1		T16	6		T20	29
fifo_depth[5]	auto[1]	auto[0]	auto[1]	3763	1			T18	49		T56	35		T57	4
fifo_depth[5]	auto[1]	auto[1]	auto[0]	5331	1			T8	2		T16	10		T14	1
fifo_depth[5]	auto[1]	auto[1]	auto[1]	5785	1			T19	1		T20	28		T18	76
fifo_depth[6]	auto[0]	auto[0]	auto[0]	1731	1			T8	2		T16	14		T14	2
fifo_depth[6]	auto[0]	auto[0]	auto[1]	1600	1			T16	1		T20	21		T31	1
fifo_depth[6]	auto[0]	auto[1]	auto[0]	125859	1			T1	2923		T9	1		T10	1
fifo_depth[6]	auto[0]	auto[1]	auto[1]	2305	1			T16	3		T20	23		T56	45
fifo_depth[6]	auto[1]	auto[0]	auto[0]	4633	1			T16	6		T20	18		T18	160
fifo_depth[6]	auto[1]	auto[0]	auto[1]	3634	1			T18	50		T56	31		T57	3
fifo_depth[6]	auto[1]	auto[1]	auto[0]	5367	1			T16	6		T14	3		T56	12
fifo_depth[6]	auto[1]	auto[1]	auto[1]	5817	1			T8	1		T20	18		T18	75
fifo_depth[7]	auto[0]	auto[0]	auto[0]	1510	1			T8	2		T16	17		T56	38
fifo_depth[7]	auto[0]	auto[0]	auto[1]	1433	1			T20	17		T31	1		T58	1
fifo_depth[7]	auto[0]	auto[1]	auto[0]	110792	1			T1	2663		T15	998		T65	3
fifo_depth[7]	auto[0]	auto[1]	auto[1]	1979	1			T16	7		T20	26		T56	48
fifo_depth[7]	auto[1]	auto[0]	auto[0]	4567	1			T16	3		T20	27		T18	153
fifo_depth[7]	auto[1]	auto[0]	auto[1]	3565	1			T18	52		T56	23		T57	5
fifo_depth[7]	auto[1]	auto[1]	auto[0]	5227	1			T16	2		T14	1		T56	16
fifo_depth[7]	auto[1]	auto[1]	auto[1]	5582	1			T8	1		T20	23		T18	60