Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	35218221	1			T1	267778		T2	12457		T4	60
all_pins[1]	35218221	1			T1	267778		T2	12457		T4	60
all_pins[2]	35218221	1			T1	267778		T2	12457		T4	60

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	87669615	1			T1	682966		T2	29687		T4	179
values[0x1]	17985048	1			T1	120368		T2	7684		T4	1
transitions[0x0=>0x1]	17984873	1			T1	120368		T2	7684		T4	1
transitions[0x1=>0x0]	17984885	1			T1	120368		T2	7684		T4	1

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	35164937	1			T1	267392		T2	12433		T4	59
all_pins[0]	values[0x1]	53284	1			T1	386		T2	24		T4	1
all_pins[0]	transitions[0x0=>0x1]	53250	1			T1	386		T2	24		T4	1
all_pins[0]	transitions[0x1=>0x0]	17928708	1			T1	119982		T2	7660		T8	335
all_pins[1]	values[0x0]	35215187	1			T1	267778		T2	12457		T4	60
all_pins[1]	values[0x1]	3034	1			T5	86		T7	121		T17	43
all_pins[1]	transitions[0x0=>0x1]	2911	1			T5	85		T7	116		T17	42
all_pins[1]	transitions[0x1=>0x0]	53161	1			T1	386		T2	24		T4	1
all_pins[2]	values[0x0]	17289491	1			T1	147796		T2	4797		T4	60
all_pins[2]	values[0x1]	17928730	1			T1	119982		T2	7660		T8	335
all_pins[2]	transitions[0x0=>0x1]	17928712	1			T1	119982		T2	7660		T8	335
all_pins[2]	transitions[0x1=>0x0]	3016	1			T5	86		T7	121		T17	43