Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 395 1 T68 21 T69 14 T70 4
all_values[1] 395 1 T68 21 T69 14 T70 4
all_values[2] 395 1 T68 21 T69 14 T70 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 653 1 T68 25 T69 20 T70 7
auto[1] 532 1 T68 38 T69 22 T70 5


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 385 1 T68 25 T69 11 T70 3
auto[1] 800 1 T68 38 T69 31 T70 9


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 639 1 T68 37 T69 20 T70 6
auto[1] 546 1 T68 26 T69 22 T70 6


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 70 1 T68 2 T69 3 T79 1
all_values[0] auto[0] auto[0] auto[1] 40 1 T68 1 T69 1 T70 2
all_values[0] auto[0] auto[1] auto[0] 53 1 T68 7 T79 3 T141 3
all_values[0] auto[0] auto[1] auto[1] 38 1 T68 4 T69 1 T141 3
all_values[0] auto[1] auto[0] auto[1] 102 1 T68 5 T69 5 T70 2
all_values[0] auto[1] auto[1] auto[1] 92 1 T68 2 T69 4 T141 3
all_values[1] auto[0] auto[0] auto[0] 69 1 T68 4 T70 1 T79 1
all_values[1] auto[0] auto[0] auto[1] 57 1 T68 2 T69 2 T70 1
all_values[1] auto[0] auto[1] auto[0] 43 1 T68 4 T69 4 T141 2
all_values[1] auto[0] auto[1] auto[1] 50 1 T68 3 T69 1 T79 2
all_values[1] auto[1] auto[0] auto[1] 100 1 T68 5 T69 4 T70 1
all_values[1] auto[1] auto[1] auto[1] 76 1 T68 3 T69 3 T70 1
all_values[2] auto[0] auto[0] auto[0] 87 1 T68 4 T69 2 T79 4
all_values[2] auto[0] auto[0] auto[1] 33 1 T141 1 T142 1 T143 2
all_values[2] auto[0] auto[1] auto[0] 63 1 T68 4 T69 2 T70 2
all_values[2] auto[0] auto[1] auto[1] 36 1 T68 2 T69 4 T141 3
all_values[2] auto[1] auto[0] auto[1] 95 1 T68 2 T69 3 T141 7
all_values[2] auto[1] auto[1] auto[1] 81 1 T68 9 T69 3 T70 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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