Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.47	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	2	18	90.00
Crosses	82	22	60	73.17

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	1	4	80.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	1	6	85.71	100	1	1	0
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	8	0	8	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	11	24	68.57	100	1	1	0
key_length_x_digest_size	35	11	24	68.57	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	1	4	80.00

User Defined Bins for digest_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
sha2_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_none	84	1			T11	5		T39	1		T40	3
sha2_512	20397	1			T2	5		T8	1		T11	3
sha2_384	20235	1			T1	386		T2	8		T4	1
sha2_256	11635	1			T2	3		T8	2		T9	194

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49662

1

T1

386

T2

7

T8

5

auto[1]

2689

1

T2

9

T4

1

T8

3

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2651

1

T2

9

T4

1

T8

4

auto[1]

49700

1

T1

386

T2

7

T8

4

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

2598

1

T2

6

T8

2

T11

6

disabled

49753

1

T1

386

T2

10

T4

1

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for key_length

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
key_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	1008	1			T2	4		T4	1		T8	2
key_1024	718	1			T2	1		T8	3		T11	1
key_512	874	1			T8	2		T11	1		T19	5
key_384	923	1			T2	2		T8	1		T11	9
key_256	47899	1			T1	386		T2	3		T9	194
key_128	929	1			T2	6		T11	1		T19	6

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

52157

1

T1

386

T2

16

T4

1

disabled

194

1

T11

6

T38

2

T39

4

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
enabled	auto[0]	auto[0]	592	1			T2	2		T11	3		T19	3
enabled	auto[0]	auto[1]	590	1			T2	2		T11	2		T19	2
enabled	auto[1]	auto[0]	861	1			T8	1		T11	1		T12	4
enabled	auto[1]	auto[1]	555	1			T2	2		T8	1		T19	5
disabled	auto[0]	auto[0]	687	1			T2	3		T8	2		T11	9
disabled	auto[0]	auto[1]	782	1			T2	2		T4	1		T8	2
disabled	auto[1]	auto[0]	47522	1			T1	386		T2	2		T8	2
disabled	auto[1]	auto[1]	762	1			T2	3		T11	2		T19	2

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

2503

1

T2

6

T8

2

T11

3

enabled

disabled

95

1

T11

3

T38

1

T39

1

disabled

disabled

99

1

T11

3

T38

1

T39

3

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

49654

1

T1

386

T2

10

T4

1

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	11	24	68.57	11
Automatically Generated Cross Bins	34	11	23	67.65	11
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid]	--	--	6

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_none	24	1			T11	1		T40	2		T134	1
key_none	sha2_512	373	1			T2	1		T11	1		T20	1
key_none	sha2_384	308	1			T2	2		T4	1		T11	4
key_none	sha2_256	303	1			T2	1		T8	2		T19	2
key_1024	sha2_none	11	1			T11	1		T135	2		T134	1
key_1024	sha2_512	300	1			T2	1		T19	1		T16	1
key_1024	sha2_384	263	1			T8	3		T19	2		T16	1
key_512	sha2_none	14	1			T11	1		T40	1		T136	1
key_512	sha2_512	277	1			T8	1		T19	2		T18	2
key_512	sha2_384	277	1			T8	1		T19	1		T16	1
key_512	sha2_256	306	1			T19	2		T5	1		T6	1
key_384	sha2_none	11	1			T11	1		T39	1		T137	1
key_384	sha2_512	320	1			T2	1		T19	1		T21	1
key_384	sha2_384	279	1			T2	1		T8	1		T11	8
key_384	sha2_256	313	1			T19	2		T16	1		T14	1
key_256	sha2_none	11	1			T138	1		T139	1		T140	1
key_256	sha2_512	18839	1			T11	2		T19	1		T20	1
key_256	sha2_384	18824	1			T1	386		T2	2		T10	386
key_256	sha2_256	10225	1			T2	1		T9	194		T12	4
key_128	sha2_none	13	1			T11	1		T138	2		T134	1
key_128	sha2_512	288	1			T2	2		T16	1		T21	1
key_128	sha2_384	284	1			T2	3		T19	4		T20	1
key_128	sha2_256	344	1			T2	1		T19	2		T21	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

144

1

T6

1

T42

1

T57

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	11	24	68.57	11

Automatically Generated Cross Bins for key_length_x_digest_size

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid]	--	--	6

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_none	24	1			T11	1		T40	2		T134	1
key_none	sha2_512	373	1			T2	1		T11	1		T20	1
key_none	sha2_384	308	1			T2	2		T4	1		T11	4
key_none	sha2_256	303	1			T2	1		T8	2		T19	2
key_1024	sha2_none	11	1			T11	1		T135	2		T134	1
key_1024	sha2_512	300	1			T2	1		T19	1		T16	1
key_1024	sha2_384	263	1			T8	3		T19	2		T16	1
key_1024	sha2_256	144	1			T6	1		T42	1		T57	1
key_512	sha2_none	14	1			T11	1		T40	1		T136	1
key_512	sha2_512	277	1			T8	1		T19	2		T18	2
key_512	sha2_384	277	1			T8	1		T19	1		T16	1
key_512	sha2_256	306	1			T19	2		T5	1		T6	1
key_384	sha2_none	11	1			T11	1		T39	1		T137	1
key_384	sha2_512	320	1			T2	1		T19	1		T21	1
key_384	sha2_384	279	1			T2	1		T8	1		T11	8
key_384	sha2_256	313	1			T19	2		T16	1		T14	1
key_256	sha2_none	11	1			T138	1		T139	1		T140	1
key_256	sha2_512	18839	1			T11	2		T19	1		T20	1
key_256	sha2_384	18824	1			T1	386		T2	2		T10	386
key_256	sha2_256	10225	1			T2	1		T9	194		T12	4
key_128	sha2_none	13	1			T11	1		T138	2		T134	1
key_128	sha2_512	288	1			T2	2		T16	1		T21	1
key_128	sha2_384	284	1			T2	3		T19	4		T20	1
key_128	sha2_256	344	1			T2	1		T19	2		T21	1