Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.54 95.85 92.99 100.00 74.36 91.89 99.49 93.23


Total test records in report: 775
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T752 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3759149764 Jun 22 04:44:19 PM PDT 24 Jun 22 04:44:23 PM PDT 24 141176467 ps
T753 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3646508312 Jun 22 04:44:11 PM PDT 24 Jun 22 04:44:13 PM PDT 24 100120537 ps
T754 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3225407778 Jun 22 04:44:16 PM PDT 24 Jun 22 04:44:17 PM PDT 24 19435255 ps
T755 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.602689035 Jun 22 04:44:02 PM PDT 24 Jun 22 04:44:04 PM PDT 24 86446940 ps
T756 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3596927216 Jun 22 04:44:23 PM PDT 24 Jun 22 04:44:26 PM PDT 24 42082348 ps
T757 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3314983836 Jun 22 04:44:16 PM PDT 24 Jun 22 04:44:18 PM PDT 24 62201575 ps
T758 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.10066337 Jun 22 04:44:09 PM PDT 24 Jun 22 04:44:13 PM PDT 24 182463458 ps
T759 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1093122452 Jun 22 04:44:24 PM PDT 24 Jun 22 04:44:25 PM PDT 24 22275416 ps
T760 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3425350754 Jun 22 04:44:25 PM PDT 24 Jun 22 04:44:27 PM PDT 24 89175893 ps
T761 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1866483292 Jun 22 04:44:03 PM PDT 24 Jun 22 04:44:07 PM PDT 24 96220306 ps
T762 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1192213974 Jun 22 04:44:39 PM PDT 24 Jun 22 04:44:40 PM PDT 24 12470357 ps
T763 /workspace/coverage/cover_reg_top/10.hmac_intr_test.208895664 Jun 22 04:44:13 PM PDT 24 Jun 22 04:44:14 PM PDT 24 34646232 ps
T764 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1571548797 Jun 22 04:44:00 PM PDT 24 Jun 22 04:44:02 PM PDT 24 31633985 ps
T148 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3779283629 Jun 22 04:44:18 PM PDT 24 Jun 22 04:44:20 PM PDT 24 139055464 ps
T765 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1414749693 Jun 22 04:44:09 PM PDT 24 Jun 22 04:44:11 PM PDT 24 114393897 ps
T766 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1892938134 Jun 22 04:44:17 PM PDT 24 Jun 22 04:44:22 PM PDT 24 397736088 ps
T767 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3695744398 Jun 22 04:44:07 PM PDT 24 Jun 22 04:44:10 PM PDT 24 272597438 ps
T768 /workspace/coverage/cover_reg_top/27.hmac_intr_test.179093202 Jun 22 04:44:32 PM PDT 24 Jun 22 04:44:33 PM PDT 24 33131300 ps
T769 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1436472799 Jun 22 04:44:17 PM PDT 24 Jun 22 04:44:19 PM PDT 24 61776608 ps
T770 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2694753502 Jun 22 04:44:01 PM PDT 24 Jun 22 04:44:02 PM PDT 24 253632982 ps
T771 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2771191848 Jun 22 04:44:02 PM PDT 24 Jun 22 04:44:04 PM PDT 24 53971191 ps
T772 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3791134560 Jun 22 04:44:08 PM PDT 24 Jun 22 04:44:10 PM PDT 24 17583949 ps
T773 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3993650973 Jun 22 04:44:08 PM PDT 24 Jun 22 04:44:10 PM PDT 24 64308510 ps
T774 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.10381391 Jun 22 04:44:22 PM PDT 24 Jun 22 04:44:24 PM PDT 24 44704511 ps
T775 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3624405085 Jun 22 04:44:02 PM PDT 24 Jun 22 04:44:09 PM PDT 24 2224645741 ps

Test location /workspace/coverage/default/42.hmac_long_msg.3101027320
Short name T2
Test name
Test status
Simulation time 13929411452 ps
CPU time 102.87 seconds
Started Jun 22 06:01:23 PM PDT 24
Finished Jun 22 06:03:06 PM PDT 24
Peak memory 200116 kb
Host smart-284d0edc-fe06-4045-a93b-a92059e006f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101027320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3101027320
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2920321695
Short name T14
Test name
Test status
Simulation time 2291904428 ps
CPU time 20.42 seconds
Started Jun 22 05:58:53 PM PDT 24
Finished Jun 22 05:59:14 PM PDT 24
Peak memory 200112 kb
Host smart-640c138d-fef9-4d6d-8ce9-2a7cfc52bb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920321695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2920321695
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3056864713
Short name T63
Test name
Test status
Simulation time 1312267654 ps
CPU time 2.71 seconds
Started Jun 22 04:44:00 PM PDT 24
Finished Jun 22 04:44:03 PM PDT 24
Peak memory 199612 kb
Host smart-83f7369d-ac38-4813-874d-abb665e5b4bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056864713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3056864713
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/default/29.hmac_stress_all.634625298
Short name T68
Test name
Test status
Simulation time 59912506689 ps
CPU time 2951.26 seconds
Started Jun 22 05:59:58 PM PDT 24
Finished Jun 22 06:49:10 PM PDT 24
Peak memory 830276 kb
Host smart-809137c5-cb41-4544-b7bd-dfffbea2bdcb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634625298 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.634625298
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1667840162
Short name T7
Test name
Test status
Simulation time 6093813119 ps
CPU time 41.29 seconds
Started Jun 22 06:00:34 PM PDT 24
Finished Jun 22 06:01:16 PM PDT 24
Peak memory 200124 kb
Host smart-b156ef25-b2f6-41df-889f-5960082fbadc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1667840162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1667840162
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3456127194
Short name T77
Test name
Test status
Simulation time 129423625 ps
CPU time 4.12 seconds
Started Jun 22 04:44:04 PM PDT 24
Finished Jun 22 04:44:09 PM PDT 24
Peak memory 199572 kb
Host smart-59b318a2-3735-44c2-9886-a768409cf988
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456127194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3456127194
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1224095327
Short name T16
Test name
Test status
Simulation time 668570728 ps
CPU time 29.81 seconds
Started Jun 22 06:00:42 PM PDT 24
Finished Jun 22 06:01:13 PM PDT 24
Peak memory 200076 kb
Host smart-22ef8dbe-e6e5-4d91-9c14-a9374fe6fd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224095327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1224095327
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_error.2001455510
Short name T11
Test name
Test status
Simulation time 18709671284 ps
CPU time 74.76 seconds
Started Jun 22 06:02:02 PM PDT 24
Finished Jun 22 06:03:17 PM PDT 24
Peak memory 200136 kb
Host smart-12097306-a2db-4e31-881b-d72367c0d72f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001455510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2001455510
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1414837689
Short name T43
Test name
Test status
Simulation time 222549056 ps
CPU time 0.87 seconds
Started Jun 22 05:56:36 PM PDT 24
Finished Jun 22 05:56:37 PM PDT 24
Peak memory 218212 kb
Host smart-b747b7c7-44ca-45d1-b0b0-9b8858fc500a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414837689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1414837689
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1674091562
Short name T80
Test name
Test status
Simulation time 122345117 ps
CPU time 0.95 seconds
Started Jun 22 04:44:09 PM PDT 24
Finished Jun 22 04:44:11 PM PDT 24
Peak memory 199336 kb
Host smart-e3dbaeaf-1bfc-49c8-ab6e-ad86d1479290
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674091562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1674091562
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/default/5.hmac_long_msg.2442586181
Short name T149
Test name
Test status
Simulation time 4527831732 ps
CPU time 123 seconds
Started Jun 22 05:56:56 PM PDT 24
Finished Jun 22 05:58:59 PM PDT 24
Peak memory 208356 kb
Host smart-da8d2e4e-bd42-4a9b-a701-2cb03f5a78b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442586181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2442586181
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3041677107
Short name T715
Test name
Test status
Simulation time 827838343 ps
CPU time 4.28 seconds
Started Jun 22 04:44:02 PM PDT 24
Finished Jun 22 04:44:08 PM PDT 24
Peak memory 199592 kb
Host smart-09daf28c-4cf8-4abb-b9ad-51e7234ffa71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041677107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3041677107
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/default/3.hmac_stress_all.4078017929
Short name T45
Test name
Test status
Simulation time 115737947181 ps
CPU time 1622.77 seconds
Started Jun 22 05:56:42 PM PDT 24
Finished Jun 22 06:23:46 PM PDT 24
Peak memory 796064 kb
Host smart-78d102d5-7239-4a47-937e-5b839a176ede
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078017929 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.4078017929
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_error.136675313
Short name T138
Test name
Test status
Simulation time 42469232575 ps
CPU time 152.16 seconds
Started Jun 22 05:59:45 PM PDT 24
Finished Jun 22 06:02:17 PM PDT 24
Peak memory 200108 kb
Host smart-1d97e523-026a-4ca4-999d-75f67223c8a9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136675313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.136675313
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2314986687
Short name T144
Test name
Test status
Simulation time 410164471 ps
CPU time 3.75 seconds
Started Jun 22 04:44:18 PM PDT 24
Finished Jun 22 04:44:22 PM PDT 24
Peak memory 199512 kb
Host smart-8c640585-60ae-4177-9610-8a1595738d8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314986687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2314986687
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/26.hmac_test_sha256_vectors.2372787510
Short name T9
Test name
Test status
Simulation time 28899387189 ps
CPU time 511.47 seconds
Started Jun 22 05:59:36 PM PDT 24
Finished Jun 22 06:08:08 PM PDT 24
Peak memory 200020 kb
Host smart-c2e0839d-281a-4cf6-91aa-bb8a9197d8af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2372787510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha256_vectors.2372787510
Directory /workspace/26.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1353513044
Short name T28
Test name
Test status
Simulation time 18859355 ps
CPU time 0.61 seconds
Started Jun 22 05:58:05 PM PDT 24
Finished Jun 22 05:58:07 PM PDT 24
Peak memory 196068 kb
Host smart-3ae96c82-6d05-47c7-b9d4-a31196d4b425
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353513044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1353513044
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1109913698
Short name T5
Test name
Test status
Simulation time 315249209 ps
CPU time 16.07 seconds
Started Jun 22 06:01:02 PM PDT 24
Finished Jun 22 06:01:19 PM PDT 24
Peak memory 200036 kb
Host smart-cf467b33-5d66-45a4-9431-4ac41d034753
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1109913698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1109913698
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_long_msg.4149273152
Short name T248
Test name
Test status
Simulation time 7028917535 ps
CPU time 94.03 seconds
Started Jun 22 05:59:00 PM PDT 24
Finished Jun 22 06:00:34 PM PDT 24
Peak memory 200088 kb
Host smart-5fb23535-d1ce-4e33-b17c-44c9f866643b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149273152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.4149273152
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1205272491
Short name T125
Test name
Test status
Simulation time 3374483070 ps
CPU time 47.86 seconds
Started Jun 22 06:00:51 PM PDT 24
Finished Jun 22 06:01:39 PM PDT 24
Peak memory 200160 kb
Host smart-8ea1f420-d353-43e3-bb80-b92d9e7f337d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205272491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1205272491
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2549251543
Short name T123
Test name
Test status
Simulation time 4454573438 ps
CPU time 1305.57 seconds
Started Jun 22 06:01:23 PM PDT 24
Finished Jun 22 06:23:09 PM PDT 24
Peak memory 750524 kb
Host smart-c96d801b-8535-4856-a7e8-3361530145e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2549251543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2549251543
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2372031668
Short name T75
Test name
Test status
Simulation time 160498855 ps
CPU time 1.9 seconds
Started Jun 22 04:44:04 PM PDT 24
Finished Jun 22 04:44:06 PM PDT 24
Peak memory 199628 kb
Host smart-12865cd6-2887-427f-85af-7b23199c2d96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372031668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2372031668
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1915692871
Short name T142
Test name
Test status
Simulation time 29073378 ps
CPU time 0.63 seconds
Started Jun 22 04:44:25 PM PDT 24
Finished Jun 22 04:44:26 PM PDT 24
Peak memory 194568 kb
Host smart-296a4d4c-1a2f-4586-b041-a8e76e41b2e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915692871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1915692871
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3776016898
Short name T128
Test name
Test status
Simulation time 22419049869 ps
CPU time 69.17 seconds
Started Jun 22 05:57:36 PM PDT 24
Finished Jun 22 05:58:46 PM PDT 24
Peak memory 200136 kb
Host smart-eea4141f-f255-4033-88a4-527b72c8c2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776016898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3776016898
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1162005129
Short name T126
Test name
Test status
Simulation time 2627278199 ps
CPU time 46.98 seconds
Started Jun 22 05:56:56 PM PDT 24
Finished Jun 22 05:57:44 PM PDT 24
Peak memory 200088 kb
Host smart-4267549a-6303-4784-af69-66a7d6c74751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162005129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1162005129
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3976691787
Short name T736
Test name
Test status
Simulation time 59905448 ps
CPU time 2.97 seconds
Started Jun 22 04:44:05 PM PDT 24
Finished Jun 22 04:44:08 PM PDT 24
Peak memory 199228 kb
Host smart-8e6488e3-ffbf-4ace-abd1-e46f34d8c61d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976691787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3976691787
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3702180307
Short name T723
Test name
Test status
Simulation time 3175745340 ps
CPU time 10.63 seconds
Started Jun 22 04:44:04 PM PDT 24
Finished Jun 22 04:44:16 PM PDT 24
Peak memory 198964 kb
Host smart-df155fae-3995-40a7-9ed4-9268d4224ee0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702180307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3702180307
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3580755866
Short name T108
Test name
Test status
Simulation time 78625246 ps
CPU time 1.01 seconds
Started Jun 22 04:43:55 PM PDT 24
Finished Jun 22 04:43:56 PM PDT 24
Peak memory 199376 kb
Host smart-0a2c8559-efcb-4da5-8fc6-69a9817951be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580755866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3580755866
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3628717896
Short name T722
Test name
Test status
Simulation time 366854668 ps
CPU time 2.25 seconds
Started Jun 22 04:44:00 PM PDT 24
Finished Jun 22 04:44:03 PM PDT 24
Peak memory 199524 kb
Host smart-74b86e8a-ef48-4494-bd41-dddffa80a7a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628717896 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.3628717896
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3710171015
Short name T737
Test name
Test status
Simulation time 16232144 ps
CPU time 0.7 seconds
Started Jun 22 04:44:01 PM PDT 24
Finished Jun 22 04:44:02 PM PDT 24
Peak memory 197628 kb
Host smart-ddf1f9d6-506a-49ea-83b0-586f9ec74f78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710171015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3710171015
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1964201732
Short name T725
Test name
Test status
Simulation time 13829480 ps
CPU time 0.58 seconds
Started Jun 22 04:43:54 PM PDT 24
Finished Jun 22 04:43:55 PM PDT 24
Peak memory 194384 kb
Host smart-f9af0b1b-f4b6-4030-a647-5339dca04cf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964201732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1964201732
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1293008049
Short name T113
Test name
Test status
Simulation time 78534471 ps
CPU time 1.69 seconds
Started Jun 22 04:44:01 PM PDT 24
Finished Jun 22 04:44:03 PM PDT 24
Peak memory 198988 kb
Host smart-28c554da-3e37-4f46-9e5b-972db8549452
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293008049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.1293008049
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.937066232
Short name T693
Test name
Test status
Simulation time 45605363 ps
CPU time 1.4 seconds
Started Jun 22 04:43:55 PM PDT 24
Finished Jun 22 04:43:57 PM PDT 24
Peak memory 199532 kb
Host smart-bf0b60f8-ff16-4bcc-a0b3-7f6e1f847f2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937066232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.937066232
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1467437062
Short name T145
Test name
Test status
Simulation time 131180104 ps
CPU time 3.88 seconds
Started Jun 22 04:43:55 PM PDT 24
Finished Jun 22 04:43:59 PM PDT 24
Peak memory 199648 kb
Host smart-2082fbef-4710-480c-b85e-1ce3e459fbbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467437062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1467437062
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2838871468
Short name T716
Test name
Test status
Simulation time 437523965 ps
CPU time 3.6 seconds
Started Jun 22 04:44:02 PM PDT 24
Finished Jun 22 04:44:07 PM PDT 24
Peak memory 199612 kb
Host smart-94c11a76-62d3-40fc-9eb4-d178f22a1497
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838871468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.2838871468
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.500820174
Short name T98
Test name
Test status
Simulation time 218214537 ps
CPU time 9.89 seconds
Started Jun 22 04:44:02 PM PDT 24
Finished Jun 22 04:44:13 PM PDT 24
Peak memory 199584 kb
Host smart-eb9fb28b-6db2-4a53-b4a7-01cf9ef8125b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500820174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.500820174
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.4162331
Short name T106
Test name
Test status
Simulation time 156225729 ps
CPU time 1.06 seconds
Started Jun 22 04:44:02 PM PDT 24
Finished Jun 22 04:44:04 PM PDT 24
Peak memory 199408 kb
Host smart-434ebc7c-5017-460e-92d4-708e28b3120b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.4162331
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.554707329
Short name T60
Test name
Test status
Simulation time 151169946 ps
CPU time 1.25 seconds
Started Jun 22 04:44:00 PM PDT 24
Finished Jun 22 04:44:02 PM PDT 24
Peak memory 199636 kb
Host smart-dbf69a40-ee31-4ba8-aa64-01608c31b954
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554707329 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.554707329
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1974920962
Short name T103
Test name
Test status
Simulation time 36481240 ps
CPU time 0.97 seconds
Started Jun 22 04:44:00 PM PDT 24
Finished Jun 22 04:44:01 PM PDT 24
Peak memory 199336 kb
Host smart-c65e6922-04c0-45f8-8b00-2b793d2142dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974920962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1974920962
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2771191848
Short name T771
Test name
Test status
Simulation time 53971191 ps
CPU time 0.64 seconds
Started Jun 22 04:44:02 PM PDT 24
Finished Jun 22 04:44:04 PM PDT 24
Peak memory 194336 kb
Host smart-9fd21355-297e-4c90-9da4-913ddcfc5b17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771191848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2771191848
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.4068971301
Short name T674
Test name
Test status
Simulation time 608980420 ps
CPU time 2.6 seconds
Started Jun 22 04:44:04 PM PDT 24
Finished Jun 22 04:44:08 PM PDT 24
Peak memory 199144 kb
Host smart-ca0313e0-cf5d-4e64-80ca-35b0a511f32b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068971301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.4068971301
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.720085047
Short name T66
Test name
Test status
Simulation time 510496582 ps
CPU time 2.72 seconds
Started Jun 22 04:44:02 PM PDT 24
Finished Jun 22 04:44:05 PM PDT 24
Peak memory 199628 kb
Host smart-289044f2-55bb-43a5-8540-4476253aa764
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720085047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.720085047
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1435040356
Short name T739
Test name
Test status
Simulation time 205784907 ps
CPU time 1.86 seconds
Started Jun 22 04:44:01 PM PDT 24
Finished Jun 22 04:44:04 PM PDT 24
Peak memory 199532 kb
Host smart-1f98ab90-5112-40f6-8675-617b32a47dcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435040356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1435040356
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1671340990
Short name T708
Test name
Test status
Simulation time 52558130 ps
CPU time 3.16 seconds
Started Jun 22 04:44:19 PM PDT 24
Finished Jun 22 04:44:23 PM PDT 24
Peak memory 215232 kb
Host smart-a64606b2-532a-49e6-ab8f-78fb21fcadea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671340990 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1671340990
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3791134560
Short name T772
Test name
Test status
Simulation time 17583949 ps
CPU time 0.89 seconds
Started Jun 22 04:44:08 PM PDT 24
Finished Jun 22 04:44:10 PM PDT 24
Peak memory 199232 kb
Host smart-5d9d899f-21e3-4fb5-aa38-47b60e4efad4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791134560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3791134560
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.208895664
Short name T763
Test name
Test status
Simulation time 34646232 ps
CPU time 0.64 seconds
Started Jun 22 04:44:13 PM PDT 24
Finished Jun 22 04:44:14 PM PDT 24
Peak memory 194276 kb
Host smart-1d9babfa-a0e2-4ac8-a200-cb8f980842e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208895664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.208895664
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.148805843
Short name T671
Test name
Test status
Simulation time 24496957 ps
CPU time 1.12 seconds
Started Jun 22 04:44:11 PM PDT 24
Finished Jun 22 04:44:12 PM PDT 24
Peak memory 199580 kb
Host smart-85678ca8-8d76-4f4c-badf-21953572385f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148805843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr
_outstanding.148805843
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1391531655
Short name T74
Test name
Test status
Simulation time 53362245 ps
CPU time 2.55 seconds
Started Jun 22 04:44:08 PM PDT 24
Finished Jun 22 04:44:11 PM PDT 24
Peak memory 199696 kb
Host smart-0b746082-7515-4846-b8e0-b25499b5d892
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391531655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1391531655
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3694451698
Short name T735
Test name
Test status
Simulation time 570294027 ps
CPU time 3.23 seconds
Started Jun 22 04:44:08 PM PDT 24
Finished Jun 22 04:44:13 PM PDT 24
Peak memory 199640 kb
Host smart-3064b252-025d-4de7-ae0b-ad972f056ac6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694451698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3694451698
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3299667499
Short name T678
Test name
Test status
Simulation time 37034590 ps
CPU time 2.22 seconds
Started Jun 22 04:44:17 PM PDT 24
Finished Jun 22 04:44:20 PM PDT 24
Peak memory 199788 kb
Host smart-f6c9e2b3-f250-4ad0-85ab-f684b14d2b38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299667499 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3299667499
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3225407778
Short name T754
Test name
Test status
Simulation time 19435255 ps
CPU time 0.71 seconds
Started Jun 22 04:44:16 PM PDT 24
Finished Jun 22 04:44:17 PM PDT 24
Peak memory 197684 kb
Host smart-20103d53-9c07-4b82-9cb2-1afcc6b177e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225407778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3225407778
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2245584377
Short name T720
Test name
Test status
Simulation time 89429069 ps
CPU time 0.59 seconds
Started Jun 22 04:44:19 PM PDT 24
Finished Jun 22 04:44:21 PM PDT 24
Peak memory 194504 kb
Host smart-9969f3b3-6496-490c-a462-6b4e1b81f664
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245584377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2245584377
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.548018908
Short name T111
Test name
Test status
Simulation time 155576108 ps
CPU time 1.66 seconds
Started Jun 22 04:44:18 PM PDT 24
Finished Jun 22 04:44:20 PM PDT 24
Peak memory 199560 kb
Host smart-6d25b8e7-fb3a-41d3-8b5f-998292031d16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548018908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.548018908
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3068049041
Short name T71
Test name
Test status
Simulation time 119168648 ps
CPU time 3.31 seconds
Started Jun 22 04:44:16 PM PDT 24
Finished Jun 22 04:44:20 PM PDT 24
Peak memory 199516 kb
Host smart-955e96ba-e923-4fd8-919f-ab9559fc3d7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068049041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3068049041
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2852876356
Short name T48
Test name
Test status
Simulation time 179287707 ps
CPU time 1.73 seconds
Started Jun 22 04:44:21 PM PDT 24
Finished Jun 22 04:44:23 PM PDT 24
Peak memory 199696 kb
Host smart-dd3b3b95-7853-4613-88fe-ee09dfb8536c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852876356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2852876356
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2943758958
Short name T704
Test name
Test status
Simulation time 424246441 ps
CPU time 2.46 seconds
Started Jun 22 04:44:18 PM PDT 24
Finished Jun 22 04:44:21 PM PDT 24
Peak memory 199760 kb
Host smart-1a3bf173-9fcb-43b2-9f30-fb670bbeffac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943758958 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2943758958
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1448558065
Short name T102
Test name
Test status
Simulation time 87835747 ps
CPU time 0.82 seconds
Started Jun 22 04:44:15 PM PDT 24
Finished Jun 22 04:44:16 PM PDT 24
Peak memory 199232 kb
Host smart-00f2b358-1443-4050-97dd-fce3630e3389
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448558065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1448558065
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3082135921
Short name T751
Test name
Test status
Simulation time 62848566 ps
CPU time 0.59 seconds
Started Jun 22 04:44:17 PM PDT 24
Finished Jun 22 04:44:19 PM PDT 24
Peak memory 194316 kb
Host smart-acdb2dac-f742-4a77-a0df-4b812d4be48f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082135921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3082135921
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3885720
Short name T731
Test name
Test status
Simulation time 24193649 ps
CPU time 1.09 seconds
Started Jun 22 04:44:19 PM PDT 24
Finished Jun 22 04:44:20 PM PDT 24
Peak memory 199308 kb
Host smart-7c06a9a9-3e08-401d-887e-0903771e930c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr_o
utstanding.3885720
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1546429120
Short name T47
Test name
Test status
Simulation time 109658986 ps
CPU time 2.31 seconds
Started Jun 22 04:44:19 PM PDT 24
Finished Jun 22 04:44:22 PM PDT 24
Peak memory 199592 kb
Host smart-fe7acc36-a2c1-431c-8800-f325406590c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546429120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1546429120
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2941302105
Short name T713
Test name
Test status
Simulation time 380033807 ps
CPU time 3.09 seconds
Started Jun 22 04:44:17 PM PDT 24
Finished Jun 22 04:44:20 PM PDT 24
Peak memory 199676 kb
Host smart-56322486-6a34-4f77-bc46-7c637dd0e72e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941302105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2941302105
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2756996569
Short name T679
Test name
Test status
Simulation time 80579442 ps
CPU time 1.76 seconds
Started Jun 22 04:44:22 PM PDT 24
Finished Jun 22 04:44:25 PM PDT 24
Peak memory 199536 kb
Host smart-ca706c96-4693-42b1-bb92-e56f88311e42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756996569 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2756996569
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2083626297
Short name T104
Test name
Test status
Simulation time 25133532 ps
CPU time 0.81 seconds
Started Jun 22 04:44:16 PM PDT 24
Finished Jun 22 04:44:17 PM PDT 24
Peak memory 198808 kb
Host smart-d3946217-952f-4dd8-88e8-01802ba8b391
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083626297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2083626297
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.660990361
Short name T661
Test name
Test status
Simulation time 18551848 ps
CPU time 0.61 seconds
Started Jun 22 04:44:18 PM PDT 24
Finished Jun 22 04:44:20 PM PDT 24
Peak memory 194316 kb
Host smart-0bd44c7e-40c2-403a-b952-aa1bb107286d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660990361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.660990361
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3234752807
Short name T83
Test name
Test status
Simulation time 57302021 ps
CPU time 1.2 seconds
Started Jun 22 04:44:17 PM PDT 24
Finished Jun 22 04:44:19 PM PDT 24
Peak memory 198088 kb
Host smart-a612d7bd-554e-46fc-9bd1-40c752379b10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234752807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3234752807
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1892938134
Short name T766
Test name
Test status
Simulation time 397736088 ps
CPU time 4.2 seconds
Started Jun 22 04:44:17 PM PDT 24
Finished Jun 22 04:44:22 PM PDT 24
Peak memory 199628 kb
Host smart-b0ada80b-3351-4d32-981a-7d84139ef7ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892938134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1892938134
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.396330048
Short name T698
Test name
Test status
Simulation time 138845373 ps
CPU time 2.22 seconds
Started Jun 22 04:44:21 PM PDT 24
Finished Jun 22 04:44:24 PM PDT 24
Peak memory 207876 kb
Host smart-823b393d-b958-4786-8388-86c8ffd6705d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396330048 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.396330048
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1436472799
Short name T769
Test name
Test status
Simulation time 61776608 ps
CPU time 0.68 seconds
Started Jun 22 04:44:17 PM PDT 24
Finished Jun 22 04:44:19 PM PDT 24
Peak memory 197888 kb
Host smart-241b20db-0937-4f73-9f02-5f8a9e015c4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436472799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1436472799
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.3500914504
Short name T701
Test name
Test status
Simulation time 19739384 ps
CPU time 0.59 seconds
Started Jun 22 04:44:19 PM PDT 24
Finished Jun 22 04:44:20 PM PDT 24
Peak memory 194516 kb
Host smart-5869eb37-10ee-4986-98e3-8ab90ae3661e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500914504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3500914504
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3508864702
Short name T721
Test name
Test status
Simulation time 124686992 ps
CPU time 1.69 seconds
Started Jun 22 04:44:18 PM PDT 24
Finished Jun 22 04:44:20 PM PDT 24
Peak memory 199604 kb
Host smart-d724b18c-4387-4c6d-80e9-3aebc456a678
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508864702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3508864702
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3759149764
Short name T752
Test name
Test status
Simulation time 141176467 ps
CPU time 3.71 seconds
Started Jun 22 04:44:19 PM PDT 24
Finished Jun 22 04:44:23 PM PDT 24
Peak memory 199568 kb
Host smart-da88165b-6c2b-4c74-8502-5c3de644f6a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759149764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3759149764
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3779283629
Short name T148
Test name
Test status
Simulation time 139055464 ps
CPU time 2 seconds
Started Jun 22 04:44:18 PM PDT 24
Finished Jun 22 04:44:20 PM PDT 24
Peak memory 199604 kb
Host smart-5710944f-0035-4c89-a41a-5bbad46906de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779283629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3779283629
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.10381391
Short name T774
Test name
Test status
Simulation time 44704511 ps
CPU time 1.31 seconds
Started Jun 22 04:44:22 PM PDT 24
Finished Jun 22 04:44:24 PM PDT 24
Peak memory 199716 kb
Host smart-7bd657d7-8097-49d6-a82f-4a813fc18ff7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10381391 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.10381391
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3877815529
Short name T747
Test name
Test status
Simulation time 71472815 ps
CPU time 0.69 seconds
Started Jun 22 04:44:23 PM PDT 24
Finished Jun 22 04:44:24 PM PDT 24
Peak memory 197364 kb
Host smart-16f1ba1b-73c7-42da-b87a-9609ee66e45c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877815529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3877815529
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3843249067
Short name T695
Test name
Test status
Simulation time 107686057 ps
CPU time 1.9 seconds
Started Jun 22 04:44:30 PM PDT 24
Finished Jun 22 04:44:32 PM PDT 24
Peak memory 199428 kb
Host smart-38932f7b-0e16-487c-9342-8b3432755cb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843249067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3843249067
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3314983836
Short name T757
Test name
Test status
Simulation time 62201575 ps
CPU time 1.56 seconds
Started Jun 22 04:44:16 PM PDT 24
Finished Jun 22 04:44:18 PM PDT 24
Peak memory 199836 kb
Host smart-21c67bc4-0592-42e2-ac74-517fa99529e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314983836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3314983836
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.728796384
Short name T78
Test name
Test status
Simulation time 97216630 ps
CPU time 1.69 seconds
Started Jun 22 04:44:17 PM PDT 24
Finished Jun 22 04:44:20 PM PDT 24
Peak memory 199664 kb
Host smart-a577ab8c-bafb-47c2-9f17-8fb5f3aecc5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728796384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.728796384
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4089737595
Short name T673
Test name
Test status
Simulation time 530236500 ps
CPU time 1.8 seconds
Started Jun 22 04:44:25 PM PDT 24
Finished Jun 22 04:44:28 PM PDT 24
Peak memory 199508 kb
Host smart-235a66d9-dc41-47a7-94a3-cc456ef2a1ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089737595 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.4089737595
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2905519842
Short name T86
Test name
Test status
Simulation time 63101545 ps
CPU time 0.77 seconds
Started Jun 22 04:44:24 PM PDT 24
Finished Jun 22 04:44:26 PM PDT 24
Peak memory 197472 kb
Host smart-e8a9141b-6e4b-4485-be63-8920dbbd6413
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905519842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2905519842
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.333229316
Short name T663
Test name
Test status
Simulation time 40111998 ps
CPU time 0.6 seconds
Started Jun 22 04:44:28 PM PDT 24
Finished Jun 22 04:44:29 PM PDT 24
Peak memory 194340 kb
Host smart-4486fedd-edcc-46fd-a6f8-06bca098e335
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333229316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.333229316
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1118575339
Short name T681
Test name
Test status
Simulation time 46788297 ps
CPU time 2.26 seconds
Started Jun 22 04:44:33 PM PDT 24
Finished Jun 22 04:44:36 PM PDT 24
Peak memory 199344 kb
Host smart-7cc059d6-d760-44a6-af6e-032dbb47c69b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118575339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1118575339
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3484109395
Short name T687
Test name
Test status
Simulation time 299843543 ps
CPU time 1.32 seconds
Started Jun 22 04:44:29 PM PDT 24
Finished Jun 22 04:44:30 PM PDT 24
Peak memory 199500 kb
Host smart-b80730db-78fd-4b81-a782-8acafbca516f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484109395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3484109395
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1210571721
Short name T146
Test name
Test status
Simulation time 183857209 ps
CPU time 3.14 seconds
Started Jun 22 04:44:24 PM PDT 24
Finished Jun 22 04:44:28 PM PDT 24
Peak memory 199544 kb
Host smart-56ccb2c1-d792-4ee7-af5f-a022312cd6e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210571721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1210571721
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1866971675
Short name T676
Test name
Test status
Simulation time 113655704 ps
CPU time 1.09 seconds
Started Jun 22 04:44:25 PM PDT 24
Finished Jun 22 04:44:27 PM PDT 24
Peak memory 199460 kb
Host smart-f8fb6db1-1ced-4f67-9c35-e13ff4507344
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866971675 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1866971675
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3425350754
Short name T760
Test name
Test status
Simulation time 89175893 ps
CPU time 0.84 seconds
Started Jun 22 04:44:25 PM PDT 24
Finished Jun 22 04:44:27 PM PDT 24
Peak memory 199320 kb
Host smart-44e5a26a-8dd3-486d-b17b-276a2cd11a52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425350754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3425350754
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1573918318
Short name T699
Test name
Test status
Simulation time 33476635 ps
CPU time 0.61 seconds
Started Jun 22 04:44:23 PM PDT 24
Finished Jun 22 04:44:24 PM PDT 24
Peak memory 194556 kb
Host smart-af141e05-8bfe-436b-8bb1-7c1970008c0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573918318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1573918318
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3188719805
Short name T677
Test name
Test status
Simulation time 46330605 ps
CPU time 2.05 seconds
Started Jun 22 04:44:25 PM PDT 24
Finished Jun 22 04:44:28 PM PDT 24
Peak memory 199512 kb
Host smart-01b96541-ff81-4297-a1aa-9a886c2d287c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188719805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3188719805
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1489617627
Short name T683
Test name
Test status
Simulation time 915604837 ps
CPU time 2.81 seconds
Started Jun 22 04:44:24 PM PDT 24
Finished Jun 22 04:44:27 PM PDT 24
Peak memory 199516 kb
Host smart-fdcdf72b-9886-4fb5-b3e7-f5d40bd300dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489617627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1489617627
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3132179999
Short name T96
Test name
Test status
Simulation time 214736588 ps
CPU time 1.68 seconds
Started Jun 22 04:44:23 PM PDT 24
Finished Jun 22 04:44:26 PM PDT 24
Peak memory 199540 kb
Host smart-7d399433-89ea-4f62-ab86-247b26d502eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132179999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3132179999
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3596927216
Short name T756
Test name
Test status
Simulation time 42082348 ps
CPU time 2.46 seconds
Started Jun 22 04:44:23 PM PDT 24
Finished Jun 22 04:44:26 PM PDT 24
Peak memory 207848 kb
Host smart-2959fe19-6fba-4b03-bfb7-e6158701de70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596927216 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3596927216
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3025908923
Short name T101
Test name
Test status
Simulation time 350087540 ps
CPU time 0.88 seconds
Started Jun 22 04:44:23 PM PDT 24
Finished Jun 22 04:44:25 PM PDT 24
Peak memory 199368 kb
Host smart-0663378e-0136-415f-8391-bbe2605085f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025908923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3025908923
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1582924237
Short name T717
Test name
Test status
Simulation time 11034622 ps
CPU time 0.6 seconds
Started Jun 22 04:44:26 PM PDT 24
Finished Jun 22 04:44:27 PM PDT 24
Peak memory 194448 kb
Host smart-eb8fc89c-f5d0-4e76-96bc-60ceeafae8e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582924237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1582924237
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1222295932
Short name T743
Test name
Test status
Simulation time 35623995 ps
CPU time 1.74 seconds
Started Jun 22 04:44:23 PM PDT 24
Finished Jun 22 04:44:26 PM PDT 24
Peak memory 199452 kb
Host smart-e25985a0-49b9-4438-97b1-b26ece123247
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222295932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1222295932
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2840787655
Short name T64
Test name
Test status
Simulation time 31130276 ps
CPU time 1.4 seconds
Started Jun 22 04:44:24 PM PDT 24
Finished Jun 22 04:44:26 PM PDT 24
Peak memory 199604 kb
Host smart-e74c999e-aa79-4a67-96f2-d3c5a21ec2d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840787655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2840787655
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2082329257
Short name T750
Test name
Test status
Simulation time 155867699 ps
CPU time 3.12 seconds
Started Jun 22 04:44:26 PM PDT 24
Finished Jun 22 04:44:29 PM PDT 24
Peak memory 199548 kb
Host smart-c073a7ef-cd12-4e00-8b6b-9fcecf534ac3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082329257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2082329257
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3205030224
Short name T690
Test name
Test status
Simulation time 137031537 ps
CPU time 1.25 seconds
Started Jun 22 04:44:29 PM PDT 24
Finished Jun 22 04:44:31 PM PDT 24
Peak memory 199500 kb
Host smart-862addf7-d23e-49e6-adec-cba147ef7b0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205030224 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3205030224
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3671792195
Short name T749
Test name
Test status
Simulation time 18217060 ps
CPU time 0.71 seconds
Started Jun 22 04:44:26 PM PDT 24
Finished Jun 22 04:44:27 PM PDT 24
Peak memory 197024 kb
Host smart-3c98b0d7-6a83-43bc-b1fc-84a2ac3e179a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671792195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3671792195
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2717045208
Short name T718
Test name
Test status
Simulation time 25810095 ps
CPU time 0.57 seconds
Started Jun 22 04:44:29 PM PDT 24
Finished Jun 22 04:44:30 PM PDT 24
Peak memory 194364 kb
Host smart-b56cb71f-865a-4a8c-8d3b-5967a9ff853f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717045208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2717045208
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3299986473
Short name T110
Test name
Test status
Simulation time 90866364 ps
CPU time 1.61 seconds
Started Jun 22 04:44:23 PM PDT 24
Finished Jun 22 04:44:26 PM PDT 24
Peak memory 199696 kb
Host smart-338e8b7d-6560-4d3d-9de1-ebc74b1679bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299986473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3299986473
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.575078549
Short name T724
Test name
Test status
Simulation time 48952475 ps
CPU time 2.22 seconds
Started Jun 22 04:44:27 PM PDT 24
Finished Jun 22 04:44:30 PM PDT 24
Peak memory 199608 kb
Host smart-8aac9fe8-28f6-4a9a-a7b4-4fd4fcb11f9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575078549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.575078549
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.845671059
Short name T46
Test name
Test status
Simulation time 95058070 ps
CPU time 2.74 seconds
Started Jun 22 04:44:25 PM PDT 24
Finished Jun 22 04:44:28 PM PDT 24
Peak memory 199640 kb
Host smart-e6954c91-f90b-4dfb-9f24-1a327d16caef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845671059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.845671059
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2638150346
Short name T105
Test name
Test status
Simulation time 2439849696 ps
CPU time 9.06 seconds
Started Jun 22 04:44:02 PM PDT 24
Finished Jun 22 04:44:12 PM PDT 24
Peak memory 199760 kb
Host smart-d9331032-09ef-4aa6-af05-845420d89553
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638150346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2638150346
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2214997240
Short name T82
Test name
Test status
Simulation time 957769527 ps
CPU time 11 seconds
Started Jun 22 04:44:01 PM PDT 24
Finished Jun 22 04:44:12 PM PDT 24
Peak memory 198588 kb
Host smart-3cef2ea5-528f-4ae6-96e6-29d12bfb8a4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214997240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2214997240
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2276816932
Short name T666
Test name
Test status
Simulation time 69458070 ps
CPU time 0.73 seconds
Started Jun 22 04:44:02 PM PDT 24
Finished Jun 22 04:44:04 PM PDT 24
Peak memory 197832 kb
Host smart-e6c91e37-1685-436e-8703-295320086e6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276816932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2276816932
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1866483292
Short name T761
Test name
Test status
Simulation time 96220306 ps
CPU time 2.54 seconds
Started Jun 22 04:44:03 PM PDT 24
Finished Jun 22 04:44:07 PM PDT 24
Peak memory 199612 kb
Host smart-7db5433f-54f7-4589-be1b-5ea18ac73746
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866483292 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1866483292
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2879016621
Short name T748
Test name
Test status
Simulation time 11946404 ps
CPU time 0.69 seconds
Started Jun 22 04:44:07 PM PDT 24
Finished Jun 22 04:44:08 PM PDT 24
Peak memory 197576 kb
Host smart-9d0de7ce-e070-4312-accc-787aeb9f5ece
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879016621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2879016621
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.25338414
Short name T732
Test name
Test status
Simulation time 17042858 ps
CPU time 0.64 seconds
Started Jun 22 04:44:03 PM PDT 24
Finished Jun 22 04:44:05 PM PDT 24
Peak memory 194444 kb
Host smart-a465f52e-d577-43c7-96de-b156baefb7df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25338414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.25338414
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3900628848
Short name T742
Test name
Test status
Simulation time 186976948 ps
CPU time 1.64 seconds
Started Jun 22 04:44:02 PM PDT 24
Finished Jun 22 04:44:04 PM PDT 24
Peak memory 199460 kb
Host smart-c513cab4-79e5-44b3-adbe-24fd0562602b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900628848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3900628848
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.821722771
Short name T67
Test name
Test status
Simulation time 74618654 ps
CPU time 3.84 seconds
Started Jun 22 04:44:04 PM PDT 24
Finished Jun 22 04:44:08 PM PDT 24
Peak memory 199528 kb
Host smart-096e8083-cfbb-4668-9076-da106f2a1f58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821722771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.821722771
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2986977366
Short name T696
Test name
Test status
Simulation time 84342043 ps
CPU time 1.79 seconds
Started Jun 22 04:44:00 PM PDT 24
Finished Jun 22 04:44:02 PM PDT 24
Peak memory 199568 kb
Host smart-a7c1077d-469d-4f95-8fae-678d99443cea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986977366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2986977366
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.100348499
Short name T684
Test name
Test status
Simulation time 14833747 ps
CPU time 0.6 seconds
Started Jun 22 04:44:24 PM PDT 24
Finished Jun 22 04:44:26 PM PDT 24
Peak memory 194424 kb
Host smart-fbe49923-feeb-45d7-a720-6ee4cc025f4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100348499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.100348499
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1093122452
Short name T759
Test name
Test status
Simulation time 22275416 ps
CPU time 0.64 seconds
Started Jun 22 04:44:24 PM PDT 24
Finished Jun 22 04:44:25 PM PDT 24
Peak memory 194520 kb
Host smart-6d5ba8b8-ad1d-4b22-b1da-ebf10ff36a58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093122452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1093122452
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.806062780
Short name T665
Test name
Test status
Simulation time 21070651 ps
CPU time 0.58 seconds
Started Jun 22 04:44:25 PM PDT 24
Finished Jun 22 04:44:26 PM PDT 24
Peak memory 194260 kb
Host smart-6691ac35-170a-4d89-b6a2-9501b7497abf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806062780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.806062780
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2747215186
Short name T682
Test name
Test status
Simulation time 55152551 ps
CPU time 0.61 seconds
Started Jun 22 04:44:26 PM PDT 24
Finished Jun 22 04:44:27 PM PDT 24
Peak memory 194332 kb
Host smart-d2622d99-123b-450f-af15-e72218a53210
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747215186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2747215186
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2259563006
Short name T741
Test name
Test status
Simulation time 17046300 ps
CPU time 0.59 seconds
Started Jun 22 04:44:30 PM PDT 24
Finished Jun 22 04:44:31 PM PDT 24
Peak memory 194340 kb
Host smart-0b12b5be-7c5d-4a67-941b-a7471dc2155c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259563006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2259563006
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3879505513
Short name T709
Test name
Test status
Simulation time 11873026 ps
CPU time 0.59 seconds
Started Jun 22 04:44:24 PM PDT 24
Finished Jun 22 04:44:25 PM PDT 24
Peak memory 194444 kb
Host smart-b611a81a-1f96-46e2-9901-02dbf55305b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879505513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3879505513
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3717088560
Short name T668
Test name
Test status
Simulation time 12281948 ps
CPU time 0.59 seconds
Started Jun 22 04:44:26 PM PDT 24
Finished Jun 22 04:44:27 PM PDT 24
Peak memory 194484 kb
Host smart-1c1b8816-b9e5-4928-98cd-d044c1560696
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717088560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3717088560
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.179093202
Short name T768
Test name
Test status
Simulation time 33131300 ps
CPU time 0.58 seconds
Started Jun 22 04:44:32 PM PDT 24
Finished Jun 22 04:44:33 PM PDT 24
Peak memory 194416 kb
Host smart-f8fd5afd-b61c-4e9f-a969-cf43793e7163
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179093202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.179093202
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.101778085
Short name T702
Test name
Test status
Simulation time 19733843 ps
CPU time 0.63 seconds
Started Jun 22 04:44:31 PM PDT 24
Finished Jun 22 04:44:32 PM PDT 24
Peak memory 194420 kb
Host smart-92a6a8c3-461b-4a7f-b33e-8f3337655826
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101778085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.101778085
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3344025547
Short name T143
Test name
Test status
Simulation time 13705398 ps
CPU time 0.64 seconds
Started Jun 22 04:44:32 PM PDT 24
Finished Jun 22 04:44:33 PM PDT 24
Peak memory 194512 kb
Host smart-6d2fe360-3d54-412c-872d-dfb1b31b9231
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344025547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3344025547
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.401186215
Short name T99
Test name
Test status
Simulation time 445886637 ps
CPU time 8.92 seconds
Started Jun 22 04:44:04 PM PDT 24
Finished Jun 22 04:44:14 PM PDT 24
Peak memory 199308 kb
Host smart-8ab1b49f-d447-489a-a160-51b3373eda70
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401186215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.401186215
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3801979130
Short name T669
Test name
Test status
Simulation time 1061488981 ps
CPU time 6.09 seconds
Started Jun 22 04:44:02 PM PDT 24
Finished Jun 22 04:44:09 PM PDT 24
Peak memory 199596 kb
Host smart-333b2706-cd6c-440d-ad47-7bdcdd620ec4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801979130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3801979130
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.4146970152
Short name T733
Test name
Test status
Simulation time 29687076 ps
CPU time 0.9 seconds
Started Jun 22 04:44:04 PM PDT 24
Finished Jun 22 04:44:06 PM PDT 24
Peak memory 199032 kb
Host smart-fd9b12fb-3633-4af7-ab2f-e5c541d99163
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146970152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.4146970152
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.220596751
Short name T714
Test name
Test status
Simulation time 310363178 ps
CPU time 2.99 seconds
Started Jun 22 04:43:59 PM PDT 24
Finished Jun 22 04:44:03 PM PDT 24
Peak memory 207888 kb
Host smart-a1bf45ab-bceb-4206-89ae-397bdc03810f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220596751 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.220596751
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2514015679
Short name T109
Test name
Test status
Simulation time 49083864 ps
CPU time 0.78 seconds
Started Jun 22 04:44:00 PM PDT 24
Finished Jun 22 04:44:01 PM PDT 24
Peak memory 199264 kb
Host smart-4591f412-5d47-4bb3-9f19-2de201fa20ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514015679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2514015679
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3569556450
Short name T728
Test name
Test status
Simulation time 82030818 ps
CPU time 0.57 seconds
Started Jun 22 04:44:00 PM PDT 24
Finished Jun 22 04:44:01 PM PDT 24
Peak memory 194408 kb
Host smart-6ec6ecef-3655-48f3-9ed2-bee9b2312f00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569556450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3569556450
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.636391059
Short name T112
Test name
Test status
Simulation time 81683213 ps
CPU time 1.74 seconds
Started Jun 22 04:44:02 PM PDT 24
Finished Jun 22 04:44:04 PM PDT 24
Peak memory 199396 kb
Host smart-063c38e0-5966-4553-ba11-5e6994ea9131
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636391059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.636391059
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.4196032664
Short name T730
Test name
Test status
Simulation time 304595827 ps
CPU time 3.52 seconds
Started Jun 22 04:44:01 PM PDT 24
Finished Jun 22 04:44:06 PM PDT 24
Peak memory 199512 kb
Host smart-ce55a947-0d53-4f16-a159-905d5ab996a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196032664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.4196032664
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1785945458
Short name T62
Test name
Test status
Simulation time 370126664 ps
CPU time 2.02 seconds
Started Jun 22 04:44:00 PM PDT 24
Finished Jun 22 04:44:03 PM PDT 24
Peak memory 199624 kb
Host smart-d3cb53d9-d895-416e-9141-2740406540b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785945458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1785945458
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1643320367
Short name T660
Test name
Test status
Simulation time 11845174 ps
CPU time 0.59 seconds
Started Jun 22 04:44:31 PM PDT 24
Finished Jun 22 04:44:32 PM PDT 24
Peak memory 194556 kb
Host smart-0d7aafa8-e10f-4d80-b5c3-bd3203e942d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643320367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1643320367
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3520975328
Short name T746
Test name
Test status
Simulation time 22345612 ps
CPU time 0.6 seconds
Started Jun 22 04:44:33 PM PDT 24
Finished Jun 22 04:44:34 PM PDT 24
Peak memory 194488 kb
Host smart-b1ccc6a5-8ddd-4a2d-bd37-7a30d3450097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520975328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3520975328
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1680417547
Short name T697
Test name
Test status
Simulation time 17217567 ps
CPU time 0.6 seconds
Started Jun 22 04:44:34 PM PDT 24
Finished Jun 22 04:44:36 PM PDT 24
Peak memory 194348 kb
Host smart-291a7acc-8bed-4166-9762-45a81b5ec802
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680417547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1680417547
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1698906091
Short name T689
Test name
Test status
Simulation time 25143675 ps
CPU time 0.58 seconds
Started Jun 22 04:44:34 PM PDT 24
Finished Jun 22 04:44:35 PM PDT 24
Peak memory 194344 kb
Host smart-215ec78f-949a-442c-a0f6-a251ffa08a1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698906091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1698906091
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1618269544
Short name T727
Test name
Test status
Simulation time 60880097 ps
CPU time 0.6 seconds
Started Jun 22 04:44:34 PM PDT 24
Finished Jun 22 04:44:36 PM PDT 24
Peak memory 194400 kb
Host smart-620654a5-cb5a-45fb-af38-1b7b210474b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618269544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1618269544
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2834003654
Short name T711
Test name
Test status
Simulation time 43146655 ps
CPU time 0.6 seconds
Started Jun 22 04:44:30 PM PDT 24
Finished Jun 22 04:44:31 PM PDT 24
Peak memory 194476 kb
Host smart-d52ca38b-4045-4789-9bd9-3f5429fc486e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834003654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2834003654
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2476983441
Short name T675
Test name
Test status
Simulation time 13385338 ps
CPU time 0.6 seconds
Started Jun 22 04:44:34 PM PDT 24
Finished Jun 22 04:44:34 PM PDT 24
Peak memory 194248 kb
Host smart-90592728-86a9-48f9-a80d-022a1571b09a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476983441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2476983441
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1514173229
Short name T726
Test name
Test status
Simulation time 35660755 ps
CPU time 0.58 seconds
Started Jun 22 04:44:33 PM PDT 24
Finished Jun 22 04:44:34 PM PDT 24
Peak memory 194344 kb
Host smart-716a8f60-31a7-4013-9ae2-6d4126c62bb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514173229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1514173229
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.617749180
Short name T706
Test name
Test status
Simulation time 14092679 ps
CPU time 0.55 seconds
Started Jun 22 04:44:34 PM PDT 24
Finished Jun 22 04:44:35 PM PDT 24
Peak memory 194440 kb
Host smart-376b1d8a-3cbb-415d-a908-ee065ebc49e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617749180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.617749180
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.629184773
Short name T688
Test name
Test status
Simulation time 29341123 ps
CPU time 0.66 seconds
Started Jun 22 04:44:34 PM PDT 24
Finished Jun 22 04:44:35 PM PDT 24
Peak memory 194420 kb
Host smart-6701116b-e024-470e-9ec7-e30dff6549d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629184773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.629184773
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2123778277
Short name T107
Test name
Test status
Simulation time 376535544 ps
CPU time 5.68 seconds
Started Jun 22 04:44:04 PM PDT 24
Finished Jun 22 04:44:10 PM PDT 24
Peak memory 199680 kb
Host smart-076c428b-841b-4cfd-b020-6be429e457bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123778277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2123778277
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3624405085
Short name T775
Test name
Test status
Simulation time 2224645741 ps
CPU time 5.82 seconds
Started Jun 22 04:44:02 PM PDT 24
Finished Jun 22 04:44:09 PM PDT 24
Peak memory 199092 kb
Host smart-3d42b243-f72d-4c14-91a2-891e1b4564bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624405085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3624405085
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3144021067
Short name T685
Test name
Test status
Simulation time 35799778 ps
CPU time 1.02 seconds
Started Jun 22 04:44:04 PM PDT 24
Finished Jun 22 04:44:06 PM PDT 24
Peak memory 199404 kb
Host smart-e317e005-9546-47bf-b1a1-654dca68048a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144021067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3144021067
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1508877327
Short name T61
Test name
Test status
Simulation time 35048124 ps
CPU time 2.06 seconds
Started Jun 22 04:44:04 PM PDT 24
Finished Jun 22 04:44:07 PM PDT 24
Peak memory 199244 kb
Host smart-5f9580a2-e664-4107-a37b-bb28123e6839
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508877327 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1508877327
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1571548797
Short name T764
Test name
Test status
Simulation time 31633985 ps
CPU time 0.94 seconds
Started Jun 22 04:44:00 PM PDT 24
Finished Jun 22 04:44:02 PM PDT 24
Peak memory 198480 kb
Host smart-f375f248-05aa-4d4f-b710-ac75f1b7d4de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571548797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1571548797
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1217665424
Short name T694
Test name
Test status
Simulation time 19935070 ps
CPU time 0.65 seconds
Started Jun 22 04:44:06 PM PDT 24
Finished Jun 22 04:44:07 PM PDT 24
Peak memory 194400 kb
Host smart-70b303f0-fb47-4193-bb09-44771d78f2a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217665424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1217665424
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.430271217
Short name T680
Test name
Test status
Simulation time 216414938 ps
CPU time 1.86 seconds
Started Jun 22 04:44:00 PM PDT 24
Finished Jun 22 04:44:03 PM PDT 24
Peak memory 199640 kb
Host smart-085815f7-57c0-449c-a5da-28fa9920f9d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430271217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_
outstanding.430271217
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.4134427889
Short name T712
Test name
Test status
Simulation time 29186630 ps
CPU time 0.59 seconds
Started Jun 22 04:44:34 PM PDT 24
Finished Jun 22 04:44:35 PM PDT 24
Peak memory 194428 kb
Host smart-0abb38f6-5646-4968-94eb-8d4a86c8c5ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134427889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.4134427889
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2312921542
Short name T692
Test name
Test status
Simulation time 11525759 ps
CPU time 0.62 seconds
Started Jun 22 04:44:35 PM PDT 24
Finished Jun 22 04:44:36 PM PDT 24
Peak memory 194320 kb
Host smart-21e17281-cbcb-4199-8802-2ec6900f12f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312921542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2312921542
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1076475714
Short name T667
Test name
Test status
Simulation time 21773383 ps
CPU time 0.62 seconds
Started Jun 22 04:44:32 PM PDT 24
Finished Jun 22 04:44:33 PM PDT 24
Peak memory 194440 kb
Host smart-f9778b60-a4a8-4e66-bb85-c1a48a0a87cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076475714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1076475714
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.272160364
Short name T744
Test name
Test status
Simulation time 14682349 ps
CPU time 0.61 seconds
Started Jun 22 04:44:40 PM PDT 24
Finished Jun 22 04:44:41 PM PDT 24
Peak memory 194644 kb
Host smart-eb7d71f8-b478-4fc1-9eec-2b8506d847a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272160364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.272160364
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2212737442
Short name T686
Test name
Test status
Simulation time 54543495 ps
CPU time 0.61 seconds
Started Jun 22 04:44:41 PM PDT 24
Finished Jun 22 04:44:42 PM PDT 24
Peak memory 194380 kb
Host smart-d7b888ae-9fbb-49fb-a66a-c0cdd5a2df32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212737442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2212737442
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2681957941
Short name T664
Test name
Test status
Simulation time 37427122 ps
CPU time 0.57 seconds
Started Jun 22 04:44:41 PM PDT 24
Finished Jun 22 04:44:42 PM PDT 24
Peak memory 194388 kb
Host smart-1738d85d-5192-4020-b6bc-d47c1ddcf362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681957941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2681957941
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1192213974
Short name T762
Test name
Test status
Simulation time 12470357 ps
CPU time 0.6 seconds
Started Jun 22 04:44:39 PM PDT 24
Finished Jun 22 04:44:40 PM PDT 24
Peak memory 194496 kb
Host smart-4cab3994-d0a2-49ef-b6b5-6ced9f368621
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192213974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1192213974
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.1912853775
Short name T707
Test name
Test status
Simulation time 65328013 ps
CPU time 0.59 seconds
Started Jun 22 04:44:40 PM PDT 24
Finished Jun 22 04:44:42 PM PDT 24
Peak memory 194348 kb
Host smart-950b7921-0076-491f-b1f4-67298560aa3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912853775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1912853775
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.931011159
Short name T734
Test name
Test status
Simulation time 27288913 ps
CPU time 0.61 seconds
Started Jun 22 04:44:39 PM PDT 24
Finished Jun 22 04:44:41 PM PDT 24
Peak memory 194464 kb
Host smart-9822b4d3-dc1a-4da2-8b86-45786de9a476
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931011159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.931011159
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1075502978
Short name T672
Test name
Test status
Simulation time 31233727 ps
CPU time 0.58 seconds
Started Jun 22 04:44:40 PM PDT 24
Finished Jun 22 04:44:41 PM PDT 24
Peak memory 194348 kb
Host smart-189ab3f0-22ff-4922-a06d-3593b9e902c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075502978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1075502978
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1934761320
Short name T700
Test name
Test status
Simulation time 42558563 ps
CPU time 1.28 seconds
Started Jun 22 04:44:01 PM PDT 24
Finished Jun 22 04:44:03 PM PDT 24
Peak memory 199448 kb
Host smart-b7cfd12b-e70d-40e1-9d18-9c700ecffb40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934761320 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1934761320
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.602689035
Short name T755
Test name
Test status
Simulation time 86446940 ps
CPU time 0.79 seconds
Started Jun 22 04:44:02 PM PDT 24
Finished Jun 22 04:44:04 PM PDT 24
Peak memory 199340 kb
Host smart-b5855b29-f72f-46f9-a877-c9e688fb6216
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602689035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.602689035
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.535055528
Short name T662
Test name
Test status
Simulation time 44819274 ps
CPU time 0.6 seconds
Started Jun 22 04:44:02 PM PDT 24
Finished Jun 22 04:44:04 PM PDT 24
Peak memory 194624 kb
Host smart-94f06775-72d7-4163-90c7-bb6d161debc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535055528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.535055528
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4256939188
Short name T85
Test name
Test status
Simulation time 796211037 ps
CPU time 2.43 seconds
Started Jun 22 04:44:04 PM PDT 24
Finished Jun 22 04:44:07 PM PDT 24
Peak memory 199484 kb
Host smart-a48ceff5-5552-4838-a8e3-6b587c66b1ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256939188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.4256939188
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1706007836
Short name T147
Test name
Test status
Simulation time 139873662 ps
CPU time 3.84 seconds
Started Jun 22 04:44:05 PM PDT 24
Finished Jun 22 04:44:10 PM PDT 24
Peak memory 199412 kb
Host smart-e4ab2ee2-cb8b-47b5-abef-acc3b85b9a68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706007836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1706007836
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.999318453
Short name T73
Test name
Test status
Simulation time 182223058 ps
CPU time 2.99 seconds
Started Jun 22 04:44:13 PM PDT 24
Finished Jun 22 04:44:16 PM PDT 24
Peak memory 207784 kb
Host smart-8ae40652-bcc9-424e-b8b3-152ce1309add
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999318453 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.999318453
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4269198723
Short name T100
Test name
Test status
Simulation time 48866269 ps
CPU time 0.86 seconds
Started Jun 22 04:44:08 PM PDT 24
Finished Jun 22 04:44:10 PM PDT 24
Peak memory 199284 kb
Host smart-13958b38-2bd3-4b5e-ba49-b189ee7f6017
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269198723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.4269198723
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2694753502
Short name T770
Test name
Test status
Simulation time 253632982 ps
CPU time 0.58 seconds
Started Jun 22 04:44:01 PM PDT 24
Finished Jun 22 04:44:02 PM PDT 24
Peak memory 194516 kb
Host smart-da07e255-d0dc-4aca-924c-2ee28901d33b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694753502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2694753502
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3753319147
Short name T710
Test name
Test status
Simulation time 44297900 ps
CPU time 2.14 seconds
Started Jun 22 04:44:10 PM PDT 24
Finished Jun 22 04:44:13 PM PDT 24
Peak memory 199460 kb
Host smart-97261c40-3188-46d5-9efa-4b4f72bfc1e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753319147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3753319147
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3695744398
Short name T767
Test name
Test status
Simulation time 272597438 ps
CPU time 1.62 seconds
Started Jun 22 04:44:07 PM PDT 24
Finished Jun 22 04:44:10 PM PDT 24
Peak memory 199616 kb
Host smart-f20c6d4d-1f08-407b-a5fb-9953e1ccb632
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695744398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3695744398
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1352302898
Short name T72
Test name
Test status
Simulation time 57552117973 ps
CPU time 554.29 seconds
Started Jun 22 04:44:08 PM PDT 24
Finished Jun 22 04:53:24 PM PDT 24
Peak memory 214932 kb
Host smart-57ecc7c6-0b8f-4b62-bc21-3ac822935ca6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352302898 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1352302898
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3993650973
Short name T773
Test name
Test status
Simulation time 64308510 ps
CPU time 0.9 seconds
Started Jun 22 04:44:08 PM PDT 24
Finished Jun 22 04:44:10 PM PDT 24
Peak memory 199336 kb
Host smart-87db25ee-e61d-4e82-a06c-5e09fc11c4a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993650973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3993650973
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.3065203361
Short name T705
Test name
Test status
Simulation time 53279870 ps
CPU time 0.57 seconds
Started Jun 22 04:44:08 PM PDT 24
Finished Jun 22 04:44:10 PM PDT 24
Peak memory 194364 kb
Host smart-826cfb39-cc49-48c7-9e33-432aab4f5122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065203361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3065203361
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2641548667
Short name T84
Test name
Test status
Simulation time 203653839 ps
CPU time 1.15 seconds
Started Jun 22 04:44:09 PM PDT 24
Finished Jun 22 04:44:12 PM PDT 24
Peak memory 197888 kb
Host smart-f4425b0e-ce2a-4904-9935-50effa01d797
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641548667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2641548667
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.10066337
Short name T758
Test name
Test status
Simulation time 182463458 ps
CPU time 2.32 seconds
Started Jun 22 04:44:09 PM PDT 24
Finished Jun 22 04:44:13 PM PDT 24
Peak memory 199668 kb
Host smart-56376d01-cf64-4ab5-88c5-5999256e8a7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10066337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.10066337
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3832872601
Short name T738
Test name
Test status
Simulation time 325448392 ps
CPU time 2.77 seconds
Started Jun 22 04:44:09 PM PDT 24
Finished Jun 22 04:44:13 PM PDT 24
Peak memory 199604 kb
Host smart-5210e469-4f16-4de5-89f4-52c4c195b97d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832872601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3832872601
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1539490628
Short name T729
Test name
Test status
Simulation time 19217286 ps
CPU time 1.08 seconds
Started Jun 22 04:44:11 PM PDT 24
Finished Jun 22 04:44:13 PM PDT 24
Peak memory 199452 kb
Host smart-0788692f-2d24-472d-a7bf-b5b689d1525b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539490628 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.1539490628
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1414749693
Short name T765
Test name
Test status
Simulation time 114393897 ps
CPU time 0.71 seconds
Started Jun 22 04:44:09 PM PDT 24
Finished Jun 22 04:44:11 PM PDT 24
Peak memory 197456 kb
Host smart-26dc1228-c03d-485c-9799-2a09285db8a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414749693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1414749693
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3099130476
Short name T703
Test name
Test status
Simulation time 42938253 ps
CPU time 0.62 seconds
Started Jun 22 04:44:09 PM PDT 24
Finished Jun 22 04:44:11 PM PDT 24
Peak memory 194412 kb
Host smart-9561bf79-4cc7-4bc7-9fbc-6cb69fe2453d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099130476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3099130476
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1591098681
Short name T81
Test name
Test status
Simulation time 101630712 ps
CPU time 1.79 seconds
Started Jun 22 04:44:10 PM PDT 24
Finished Jun 22 04:44:13 PM PDT 24
Peak memory 199520 kb
Host smart-45e09c42-a124-4033-aaff-846b051fdeea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591098681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1591098681
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3203188594
Short name T740
Test name
Test status
Simulation time 208670442 ps
CPU time 3.5 seconds
Started Jun 22 04:44:09 PM PDT 24
Finished Jun 22 04:44:14 PM PDT 24
Peak memory 199604 kb
Host smart-3351b541-5c87-4778-9126-1db256790e22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203188594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3203188594
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3017394915
Short name T76
Test name
Test status
Simulation time 914144990 ps
CPU time 4.27 seconds
Started Jun 22 04:44:07 PM PDT 24
Finished Jun 22 04:44:12 PM PDT 24
Peak memory 199480 kb
Host smart-e1887f26-1929-4e37-a083-696fbe7150d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017394915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3017394915
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1424849974
Short name T670
Test name
Test status
Simulation time 161314659 ps
CPU time 2.29 seconds
Started Jun 22 04:44:11 PM PDT 24
Finished Jun 22 04:44:14 PM PDT 24
Peak memory 199660 kb
Host smart-bcc35a58-eb39-43d5-aeb1-b7d2d56af85f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424849974 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1424849974
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.3102450737
Short name T691
Test name
Test status
Simulation time 86223616 ps
CPU time 0.58 seconds
Started Jun 22 04:44:07 PM PDT 24
Finished Jun 22 04:44:08 PM PDT 24
Peak memory 194488 kb
Host smart-b6a90093-5017-4d19-b99a-5691323b4313
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102450737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3102450737
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3646508312
Short name T753
Test name
Test status
Simulation time 100120537 ps
CPU time 1.11 seconds
Started Jun 22 04:44:11 PM PDT 24
Finished Jun 22 04:44:13 PM PDT 24
Peak memory 199592 kb
Host smart-fa8adb1e-6e76-4f9d-ad31-37cc98ad5b05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646508312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3646508312
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1155639235
Short name T745
Test name
Test status
Simulation time 73820530 ps
CPU time 3.78 seconds
Started Jun 22 04:44:08 PM PDT 24
Finished Jun 22 04:44:12 PM PDT 24
Peak memory 199612 kb
Host smart-37394495-a996-4f74-932b-7936113ebbab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155639235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1155639235
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.972195328
Short name T719
Test name
Test status
Simulation time 368020613 ps
CPU time 3.25 seconds
Started Jun 22 04:44:08 PM PDT 24
Finished Jun 22 04:44:13 PM PDT 24
Peak memory 199648 kb
Host smart-a963b7f3-8372-4bc1-a5ab-0269b9ed473d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972195328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.972195328
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1295400614
Short name T620
Test name
Test status
Simulation time 14555732 ps
CPU time 0.57 seconds
Started Jun 22 05:56:14 PM PDT 24
Finished Jun 22 05:56:15 PM PDT 24
Peak memory 195996 kb
Host smart-8ad32c7c-187e-4a13-8ce2-540dfdf00d71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295400614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1295400614
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.935520834
Short name T396
Test name
Test status
Simulation time 1004875976 ps
CPU time 40.54 seconds
Started Jun 22 05:56:04 PM PDT 24
Finished Jun 22 05:56:45 PM PDT 24
Peak memory 200024 kb
Host smart-7fe82db1-d550-4cc5-bd91-d045ac72cdcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=935520834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.935520834
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1048555343
Short name T413
Test name
Test status
Simulation time 1675768715 ps
CPU time 46.64 seconds
Started Jun 22 05:56:09 PM PDT 24
Finished Jun 22 05:56:56 PM PDT 24
Peak memory 200120 kb
Host smart-bbc3a930-08ea-45b9-b51b-091a81cf5a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048555343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1048555343
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3622266451
Short name T18
Test name
Test status
Simulation time 860462401 ps
CPU time 140.78 seconds
Started Jun 22 05:56:07 PM PDT 24
Finished Jun 22 05:58:28 PM PDT 24
Peak memory 340572 kb
Host smart-9e90f9a9-4a9e-443b-b963-f8679082d187
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3622266451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3622266451
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2926520161
Short name T637
Test name
Test status
Simulation time 9409387279 ps
CPU time 132.89 seconds
Started Jun 22 05:56:07 PM PDT 24
Finished Jun 22 05:58:21 PM PDT 24
Peak memory 200004 kb
Host smart-1c6084b6-aabb-44cd-913a-224e6ca84edc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926520161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2926520161
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.2979003248
Short name T233
Test name
Test status
Simulation time 74278788835 ps
CPU time 123.98 seconds
Started Jun 22 05:56:02 PM PDT 24
Finished Jun 22 05:58:06 PM PDT 24
Peak memory 208292 kb
Host smart-b4ba29bc-6c75-4088-b5d1-ae98572eb14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979003248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.2979003248
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.199165063
Short name T49
Test name
Test status
Simulation time 34336590 ps
CPU time 0.78 seconds
Started Jun 22 05:56:14 PM PDT 24
Finished Jun 22 05:56:16 PM PDT 24
Peak memory 218160 kb
Host smart-244f4587-0752-4fbf-9360-ff218076c76e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199165063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.199165063
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.744977859
Short name T598
Test name
Test status
Simulation time 2880689768 ps
CPU time 13.54 seconds
Started Jun 22 05:56:02 PM PDT 24
Finished Jun 22 05:56:16 PM PDT 24
Peak memory 200104 kb
Host smart-d876ea70-1b6a-4136-b0f5-d41a0d79bdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744977859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.744977859
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1399392876
Short name T319
Test name
Test status
Simulation time 238147093 ps
CPU time 1.35 seconds
Started Jun 22 05:56:16 PM PDT 24
Finished Jun 22 05:56:17 PM PDT 24
Peak memory 200088 kb
Host smart-88dfe70b-6e18-469b-af2a-07dc824d882f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399392876 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac_vectors.1399392876
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.3756141142
Short name T466
Test name
Test status
Simulation time 100919559913 ps
CPU time 462.12 seconds
Started Jun 22 05:56:08 PM PDT 24
Finished Jun 22 06:03:51 PM PDT 24
Peak memory 200124 kb
Host smart-ef93db82-8755-45df-85d4-0c15b927cd64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3756141142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3756141142
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.3161715036
Short name T163
Test name
Test status
Simulation time 44109376267 ps
CPU time 1726.25 seconds
Started Jun 22 05:56:08 PM PDT 24
Finished Jun 22 06:24:55 PM PDT 24
Peak memory 215676 kb
Host smart-58f897d9-7c9d-4ed3-9091-bf7cf7c263f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3161715036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.3161715036
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.3041271419
Short name T434
Test name
Test status
Simulation time 132560381800 ps
CPU time 1639.2 seconds
Started Jun 22 05:56:07 PM PDT 24
Finished Jun 22 06:23:27 PM PDT 24
Peak memory 215504 kb
Host smart-eecde0fc-3a61-44a0-8b74-b49f90e81cb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3041271419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.3041271419
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1583101786
Short name T116
Test name
Test status
Simulation time 6565599113 ps
CPU time 55.73 seconds
Started Jun 22 05:56:07 PM PDT 24
Finished Jun 22 05:57:03 PM PDT 24
Peak memory 200164 kb
Host smart-fd6618c1-7e27-463d-98a5-a8bb421cf6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583101786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1583101786
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3419344972
Short name T618
Test name
Test status
Simulation time 12397817 ps
CPU time 0.56 seconds
Started Jun 22 05:56:22 PM PDT 24
Finished Jun 22 05:56:22 PM PDT 24
Peak memory 195640 kb
Host smart-339222f7-925b-4dec-a21c-0413d2a33b23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419344972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3419344972
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3668329791
Short name T26
Test name
Test status
Simulation time 681622636 ps
CPU time 11.35 seconds
Started Jun 22 05:56:14 PM PDT 24
Finished Jun 22 05:56:26 PM PDT 24
Peak memory 200000 kb
Host smart-3cab469f-4d6e-4977-9b03-333e8547fa02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3668329791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3668329791
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2261190737
Short name T173
Test name
Test status
Simulation time 836284016 ps
CPU time 12.24 seconds
Started Jun 22 05:56:13 PM PDT 24
Finished Jun 22 05:56:26 PM PDT 24
Peak memory 200100 kb
Host smart-38fb73c8-c26e-46c2-89a6-dc76021e6435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261190737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2261190737
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3915808616
Short name T284
Test name
Test status
Simulation time 10739625453 ps
CPU time 641.71 seconds
Started Jun 22 05:56:15 PM PDT 24
Finished Jun 22 06:06:57 PM PDT 24
Peak memory 712096 kb
Host smart-62d9c26d-f19a-423d-8343-6fd004245e7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3915808616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3915808616
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.341791756
Short name T374
Test name
Test status
Simulation time 71460138282 ps
CPU time 124.25 seconds
Started Jun 22 05:56:13 PM PDT 24
Finished Jun 22 05:58:18 PM PDT 24
Peak memory 200008 kb
Host smart-a13172dd-9de3-4b68-b567-67696c01082d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341791756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.341791756
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.745571667
Short name T379
Test name
Test status
Simulation time 392236410 ps
CPU time 22.69 seconds
Started Jun 22 05:56:13 PM PDT 24
Finished Jun 22 05:56:36 PM PDT 24
Peak memory 200068 kb
Host smart-c01c517b-e592-4838-98a8-773bbcb795f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745571667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.745571667
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2302350828
Short name T51
Test name
Test status
Simulation time 235849692 ps
CPU time 0.87 seconds
Started Jun 22 05:56:20 PM PDT 24
Finished Jun 22 05:56:21 PM PDT 24
Peak memory 218144 kb
Host smart-225cc6fa-211c-4c93-969b-5cba97cf4a7a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302350828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2302350828
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3801320611
Short name T348
Test name
Test status
Simulation time 740484890 ps
CPU time 11.24 seconds
Started Jun 22 05:56:14 PM PDT 24
Finished Jun 22 05:56:26 PM PDT 24
Peak memory 200092 kb
Host smart-a044dec3-7e17-4e9d-b20b-2e234fedcb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801320611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3801320611
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.213203316
Short name T586
Test name
Test status
Simulation time 99997480 ps
CPU time 1.02 seconds
Started Jun 22 05:56:19 PM PDT 24
Finished Jun 22 05:56:21 PM PDT 24
Peak memory 199800 kb
Host smart-d9cfd655-cab2-4599-b8d3-5eb7b6c38998
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213203316 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac_vectors.213203316
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.860190198
Short name T476
Test name
Test status
Simulation time 74408347466 ps
CPU time 481.06 seconds
Started Jun 22 05:56:15 PM PDT 24
Finished Jun 22 06:04:16 PM PDT 24
Peak memory 200124 kb
Host smart-0853bbc3-c881-4a6c-97e6-d73777c8c4ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=860190198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.860190198
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.3035580430
Short name T239
Test name
Test status
Simulation time 216049749779 ps
CPU time 2007.59 seconds
Started Jun 22 05:56:23 PM PDT 24
Finished Jun 22 06:29:51 PM PDT 24
Peak memory 215424 kb
Host smart-acf41615-88c3-4a73-ac4c-af35de592e81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3035580430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.3035580430
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.4125580727
Short name T29
Test name
Test status
Simulation time 109016371903 ps
CPU time 1528.57 seconds
Started Jun 22 05:56:21 PM PDT 24
Finished Jun 22 06:21:50 PM PDT 24
Peak memory 216032 kb
Host smart-652feb96-85b5-48f3-b892-8ea289989309
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4125580727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.4125580727
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3350050086
Short name T236
Test name
Test status
Simulation time 1326876735 ps
CPU time 21.33 seconds
Started Jun 22 05:56:14 PM PDT 24
Finished Jun 22 05:56:36 PM PDT 24
Peak memory 200100 kb
Host smart-e457ec43-c216-4bac-8023-a5a3f5f8311d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350050086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3350050086
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1079898326
Short name T367
Test name
Test status
Simulation time 13766381 ps
CPU time 0.6 seconds
Started Jun 22 05:57:45 PM PDT 24
Finished Jun 22 05:57:46 PM PDT 24
Peak memory 196276 kb
Host smart-47579df0-1421-4ab7-a0e6-88403238c8f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079898326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1079898326
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.2359092694
Short name T530
Test name
Test status
Simulation time 1251800479 ps
CPU time 31.43 seconds
Started Jun 22 05:57:37 PM PDT 24
Finished Jun 22 05:58:09 PM PDT 24
Peak memory 200036 kb
Host smart-2ce852e4-aa38-4f9c-823d-7877257628f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2359092694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2359092694
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3021680953
Short name T464
Test name
Test status
Simulation time 24783991450 ps
CPU time 36.98 seconds
Started Jun 22 05:57:37 PM PDT 24
Finished Jun 22 05:58:15 PM PDT 24
Peak memory 200068 kb
Host smart-50e4d20f-bedc-49cf-b2be-5cc1ca5c31ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021680953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3021680953
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.3543278859
Short name T334
Test name
Test status
Simulation time 6584843281 ps
CPU time 903.15 seconds
Started Jun 22 05:57:40 PM PDT 24
Finished Jun 22 06:12:44 PM PDT 24
Peak memory 768548 kb
Host smart-a26f5bb5-0553-4e1d-a36b-8421d5ef708f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3543278859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3543278859
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3573962439
Short name T38
Test name
Test status
Simulation time 6301871567 ps
CPU time 80.91 seconds
Started Jun 22 05:57:40 PM PDT 24
Finished Jun 22 05:59:01 PM PDT 24
Peak memory 200136 kb
Host smart-3336484b-31b6-4c76-99ba-0117c8ba23a2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573962439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3573962439
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_smoke.3219963815
Short name T19
Test name
Test status
Simulation time 952687801 ps
CPU time 12.74 seconds
Started Jun 22 05:57:40 PM PDT 24
Finished Jun 22 05:57:53 PM PDT 24
Peak memory 200072 kb
Host smart-1fdfc4ed-b89c-4896-bf35-0ec35576025a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219963815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3219963815
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.2629787153
Short name T141
Test name
Test status
Simulation time 15601756371 ps
CPU time 1984.78 seconds
Started Jun 22 05:57:46 PM PDT 24
Finished Jun 22 06:30:51 PM PDT 24
Peak memory 788816 kb
Host smart-9ea90a3d-278e-4442-ba5a-9e0ccc38f5e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629787153 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2629787153
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.264837910
Short name T212
Test name
Test status
Simulation time 65776135 ps
CPU time 1.29 seconds
Started Jun 22 05:57:43 PM PDT 24
Finished Jun 22 05:57:45 PM PDT 24
Peak memory 200068 kb
Host smart-08767233-4ebf-4bfc-b087-e4e1bd59b722
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264837910 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_hmac_vectors.264837910
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha256_vectors.4226818932
Short name T370
Test name
Test status
Simulation time 37246549180 ps
CPU time 477.47 seconds
Started Jun 22 05:57:44 PM PDT 24
Finished Jun 22 06:05:42 PM PDT 24
Peak memory 200120 kb
Host smart-9e253449-2e17-44b8-8608-b6f87065ec2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4226818932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha256_vectors.4226818932
Directory /workspace/10.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha384_vectors.1962582668
Short name T160
Test name
Test status
Simulation time 32572330089 ps
CPU time 1818.51 seconds
Started Jun 22 05:57:43 PM PDT 24
Finished Jun 22 06:28:02 PM PDT 24
Peak memory 215692 kb
Host smart-30528d34-bc82-4f9a-abb1-bb80546199ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1962582668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha384_vectors.1962582668
Directory /workspace/10.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha512_vectors.3604044720
Short name T218
Test name
Test status
Simulation time 340878884661 ps
CPU time 2151.36 seconds
Started Jun 22 05:57:44 PM PDT 24
Finished Jun 22 06:33:36 PM PDT 24
Peak memory 216504 kb
Host smart-daa59511-45f5-468e-8b2b-d55ca7448074
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3604044720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha512_vectors.3604044720
Directory /workspace/10.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.3451207370
Short name T573
Test name
Test status
Simulation time 4898810150 ps
CPU time 23.68 seconds
Started Jun 22 05:57:46 PM PDT 24
Finished Jun 22 05:58:10 PM PDT 24
Peak memory 199968 kb
Host smart-72bffffd-4f41-4034-af29-503407ed59c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451207370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.3451207370
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3262877104
Short name T290
Test name
Test status
Simulation time 26072042 ps
CPU time 0.6 seconds
Started Jun 22 05:57:52 PM PDT 24
Finished Jun 22 05:57:53 PM PDT 24
Peak memory 196068 kb
Host smart-a77f387e-25d5-4631-8967-d649afa9ace4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262877104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3262877104
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2688718706
Short name T23
Test name
Test status
Simulation time 2642825524 ps
CPU time 31.42 seconds
Started Jun 22 05:57:44 PM PDT 24
Finished Jun 22 05:58:16 PM PDT 24
Peak memory 200148 kb
Host smart-df05529e-7b1b-4403-a7d7-41269610de17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2688718706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2688718706
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.2364562211
Short name T320
Test name
Test status
Simulation time 7529756739 ps
CPU time 24.62 seconds
Started Jun 22 05:57:54 PM PDT 24
Finished Jun 22 05:58:19 PM PDT 24
Peak memory 199952 kb
Host smart-6ea5ad6b-b50e-4e7d-b1bb-846bd93b2bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364562211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2364562211
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3013044323
Short name T451
Test name
Test status
Simulation time 11743306448 ps
CPU time 871.87 seconds
Started Jun 22 05:57:45 PM PDT 24
Finished Jun 22 06:12:17 PM PDT 24
Peak memory 714256 kb
Host smart-86833835-f639-4dab-9db4-103a7fbd4f0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3013044323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3013044323
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2669082287
Short name T215
Test name
Test status
Simulation time 949873409 ps
CPU time 56.65 seconds
Started Jun 22 05:57:52 PM PDT 24
Finished Jun 22 05:58:49 PM PDT 24
Peak memory 200076 kb
Host smart-f6b82070-a33d-4e7b-bf26-0d3bc1b63bb5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669082287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2669082287
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1825562674
Short name T416
Test name
Test status
Simulation time 1128404670 ps
CPU time 33.32 seconds
Started Jun 22 05:57:45 PM PDT 24
Finished Jun 22 05:58:18 PM PDT 24
Peak memory 200108 kb
Host smart-c5eea093-b120-42c8-938b-97209530b624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825562674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1825562674
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2569003153
Short name T256
Test name
Test status
Simulation time 255848504 ps
CPU time 4.5 seconds
Started Jun 22 05:57:44 PM PDT 24
Finished Jun 22 05:57:49 PM PDT 24
Peak memory 200068 kb
Host smart-258623bf-e768-4b6a-93d7-fa1bcfa6a122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569003153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2569003153
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.1718924704
Short name T412
Test name
Test status
Simulation time 31141903 ps
CPU time 1.26 seconds
Started Jun 22 05:57:53 PM PDT 24
Finished Jun 22 05:57:54 PM PDT 24
Peak memory 199936 kb
Host smart-365ec3a7-f2f8-465c-8678-e4e666e8d529
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718924704 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_hmac_vectors.1718924704
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha256_vectors.4046890649
Short name T503
Test name
Test status
Simulation time 7684273855 ps
CPU time 414.92 seconds
Started Jun 22 05:57:55 PM PDT 24
Finished Jun 22 06:04:50 PM PDT 24
Peak memory 200148 kb
Host smart-9c03515e-52a8-4ccf-9026-f6bb9ec4614e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4046890649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha256_vectors.4046890649
Directory /workspace/11.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha384_vectors.699749417
Short name T317
Test name
Test status
Simulation time 127521225361 ps
CPU time 1988.42 seconds
Started Jun 22 05:57:54 PM PDT 24
Finished Jun 22 06:31:03 PM PDT 24
Peak memory 215480 kb
Host smart-66cc142f-5c59-43d3-afcc-b98c3ca3f6ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=699749417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha384_vectors.699749417
Directory /workspace/11.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha512_vectors.266479590
Short name T32
Test name
Test status
Simulation time 164728244114 ps
CPU time 2104.59 seconds
Started Jun 22 05:57:53 PM PDT 24
Finished Jun 22 06:32:58 PM PDT 24
Peak memory 215532 kb
Host smart-0064e3e8-06a8-4bc0-930e-1fb6567ec4f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=266479590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha512_vectors.266479590
Directory /workspace/11.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2270440103
Short name T564
Test name
Test status
Simulation time 2109300801 ps
CPU time 30.92 seconds
Started Jun 22 05:57:52 PM PDT 24
Finished Jun 22 05:58:23 PM PDT 24
Peak memory 200084 kb
Host smart-2fb91811-c41c-4cfd-941e-b8910ed08561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270440103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2270440103
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1535136323
Short name T365
Test name
Test status
Simulation time 36200086 ps
CPU time 0.58 seconds
Started Jun 22 05:58:05 PM PDT 24
Finished Jun 22 05:58:06 PM PDT 24
Peak memory 194968 kb
Host smart-568ae779-f761-4fe0-a6ad-2f9cffbd1f09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535136323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1535136323
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1411760510
Short name T533
Test name
Test status
Simulation time 520371585 ps
CPU time 12.72 seconds
Started Jun 22 05:57:58 PM PDT 24
Finished Jun 22 05:58:11 PM PDT 24
Peak memory 200064 kb
Host smart-273c0be9-5637-4702-baed-74544875ed27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1411760510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1411760510
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.3800280431
Short name T124
Test name
Test status
Simulation time 1627837145 ps
CPU time 44.37 seconds
Started Jun 22 05:57:56 PM PDT 24
Finished Jun 22 05:58:41 PM PDT 24
Peak memory 200044 kb
Host smart-e956d1d9-2f33-4618-a318-af84dd65af40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800280431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.3800280431
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.442843698
Short name T133
Test name
Test status
Simulation time 10939468489 ps
CPU time 854.02 seconds
Started Jun 22 05:57:56 PM PDT 24
Finished Jun 22 06:12:10 PM PDT 24
Peak memory 696124 kb
Host smart-972a22e7-eef9-48aa-b95e-52f641bf1617
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=442843698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.442843698
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.4055258033
Short name T277
Test name
Test status
Simulation time 15180403172 ps
CPU time 69.72 seconds
Started Jun 22 05:57:59 PM PDT 24
Finished Jun 22 05:59:09 PM PDT 24
Peak memory 200132 kb
Host smart-ba486440-5d50-4e92-bed2-1c6a35fe8dcf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055258033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.4055258033
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.4229874528
Short name T440
Test name
Test status
Simulation time 5487227682 ps
CPU time 102.73 seconds
Started Jun 22 05:57:52 PM PDT 24
Finished Jun 22 05:59:35 PM PDT 24
Peak memory 200140 kb
Host smart-10b83dd2-c341-4712-9807-184ff3c63262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229874528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.4229874528
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1596707766
Short name T560
Test name
Test status
Simulation time 150554161 ps
CPU time 5.66 seconds
Started Jun 22 05:57:51 PM PDT 24
Finished Jun 22 05:57:57 PM PDT 24
Peak memory 199932 kb
Host smart-f227035a-16c1-4d4e-ae67-061d417229e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596707766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1596707766
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.4015603018
Short name T406
Test name
Test status
Simulation time 140362798 ps
CPU time 1.35 seconds
Started Jun 22 05:58:05 PM PDT 24
Finished Jun 22 05:58:07 PM PDT 24
Peak memory 200068 kb
Host smart-812494f0-a0ab-4cdb-9f74-390044ccd300
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015603018 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_hmac_vectors.4015603018
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha256_vectors.87403043
Short name T608
Test name
Test status
Simulation time 74270165323 ps
CPU time 459.08 seconds
Started Jun 22 05:57:56 PM PDT 24
Finished Jun 22 06:05:36 PM PDT 24
Peak memory 200120 kb
Host smart-3d303d8c-319e-402d-989f-056792ec1d52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=87403043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha256_vectors.87403043
Directory /workspace/12.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha384_vectors.2193297196
Short name T252
Test name
Test status
Simulation time 603051523849 ps
CPU time 1778.04 seconds
Started Jun 22 05:57:57 PM PDT 24
Finished Jun 22 06:27:36 PM PDT 24
Peak memory 216676 kb
Host smart-2f3b8041-50ac-43b4-b538-2f52ab2e3e39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2193297196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha384_vectors.2193297196
Directory /workspace/12.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha512_vectors.1982374384
Short name T176
Test name
Test status
Simulation time 549299105088 ps
CPU time 1977.81 seconds
Started Jun 22 05:57:59 PM PDT 24
Finished Jun 22 06:30:57 PM PDT 24
Peak memory 215544 kb
Host smart-a6edd9f6-2ee8-478b-9cbb-1adb25fabc6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1982374384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha512_vectors.1982374384
Directory /workspace/12.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2705183923
Short name T539
Test name
Test status
Simulation time 32820072008 ps
CPU time 95 seconds
Started Jun 22 05:57:59 PM PDT 24
Finished Jun 22 05:59:34 PM PDT 24
Peak memory 200140 kb
Host smart-06ed5fde-f064-4d87-b9cd-c92d733036ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705183923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2705183923
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2743696769
Short name T422
Test name
Test status
Simulation time 148370822 ps
CPU time 2.68 seconds
Started Jun 22 05:58:08 PM PDT 24
Finished Jun 22 05:58:11 PM PDT 24
Peak memory 199996 kb
Host smart-b0b81a1e-d1fb-4b0d-b017-b541d621a3cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2743696769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2743696769
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.3565334424
Short name T329
Test name
Test status
Simulation time 8021127065 ps
CPU time 29.91 seconds
Started Jun 22 05:58:05 PM PDT 24
Finished Jun 22 05:58:35 PM PDT 24
Peak memory 200100 kb
Host smart-8c3f04f6-3e87-401b-884d-cbba8a168e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565334424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3565334424
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2646811629
Short name T397
Test name
Test status
Simulation time 1166891475 ps
CPU time 74.31 seconds
Started Jun 22 05:58:04 PM PDT 24
Finished Jun 22 05:59:19 PM PDT 24
Peak memory 448632 kb
Host smart-835d9c29-740d-446c-9b4d-276c56389f89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2646811629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2646811629
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2724261245
Short name T272
Test name
Test status
Simulation time 1403370763 ps
CPU time 84.01 seconds
Started Jun 22 05:58:05 PM PDT 24
Finished Jun 22 05:59:30 PM PDT 24
Peak memory 200048 kb
Host smart-3e9d0fa4-1537-4b33-b7ea-98c66d37e3c1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724261245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2724261245
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2350920693
Short name T192
Test name
Test status
Simulation time 298088390 ps
CPU time 16.84 seconds
Started Jun 22 05:58:05 PM PDT 24
Finished Jun 22 05:58:23 PM PDT 24
Peak memory 200016 kb
Host smart-94605e4d-850f-48ea-a5b0-4faacd5f11e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350920693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2350920693
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1180302891
Short name T581
Test name
Test status
Simulation time 1118191089 ps
CPU time 12.84 seconds
Started Jun 22 05:58:05 PM PDT 24
Finished Jun 22 05:58:19 PM PDT 24
Peak memory 200060 kb
Host smart-6cdde52a-71c8-4118-b32b-d340b258bd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180302891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1180302891
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.882455689
Short name T359
Test name
Test status
Simulation time 229709942 ps
CPU time 1.33 seconds
Started Jun 22 05:58:05 PM PDT 24
Finished Jun 22 05:58:08 PM PDT 24
Peak memory 200200 kb
Host smart-0ffd1add-a8c5-4766-ac77-59c57a8e7837
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882455689 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_hmac_vectors.882455689
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha256_vectors.1357981793
Short name T182
Test name
Test status
Simulation time 23218392850 ps
CPU time 423.9 seconds
Started Jun 22 05:58:05 PM PDT 24
Finished Jun 22 06:05:10 PM PDT 24
Peak memory 200128 kb
Host smart-d370afbb-eae4-4a39-b890-27091fa82a71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1357981793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha256_vectors.1357981793
Directory /workspace/13.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha384_vectors.2663304299
Short name T456
Test name
Test status
Simulation time 31433167985 ps
CPU time 1771.96 seconds
Started Jun 22 05:58:06 PM PDT 24
Finished Jun 22 06:27:39 PM PDT 24
Peak memory 215608 kb
Host smart-6bb1c5eb-b9d2-4632-84e5-a2dceed6b0e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2663304299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha384_vectors.2663304299
Directory /workspace/13.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha512_vectors.1138923780
Short name T259
Test name
Test status
Simulation time 31861453352 ps
CPU time 1785.41 seconds
Started Jun 22 05:58:05 PM PDT 24
Finished Jun 22 06:27:52 PM PDT 24
Peak memory 215640 kb
Host smart-aecee545-8a8d-4899-8afd-239655d33ef4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1138923780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha512_vectors.1138923780
Directory /workspace/13.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2008847684
Short name T314
Test name
Test status
Simulation time 1206641657 ps
CPU time 49.48 seconds
Started Jun 22 05:58:05 PM PDT 24
Finished Jun 22 05:58:55 PM PDT 24
Peak memory 200084 kb
Host smart-62cab5b6-2289-466d-8d7c-a832ef959c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008847684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2008847684
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2007443408
Short name T355
Test name
Test status
Simulation time 14154926 ps
CPU time 0.58 seconds
Started Jun 22 05:58:11 PM PDT 24
Finished Jun 22 05:58:12 PM PDT 24
Peak memory 195640 kb
Host smart-5ba6a514-54af-4b5d-bb8f-140e5ec04d8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007443408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2007443408
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3094121313
Short name T582
Test name
Test status
Simulation time 315845370 ps
CPU time 16.28 seconds
Started Jun 22 05:58:04 PM PDT 24
Finished Jun 22 05:58:20 PM PDT 24
Peak memory 200092 kb
Host smart-655daf2d-2e0f-47d7-ae7c-c8521a8157f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3094121313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3094121313
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2716547130
Short name T201
Test name
Test status
Simulation time 7969026203 ps
CPU time 53.22 seconds
Started Jun 22 05:58:13 PM PDT 24
Finished Jun 22 05:59:06 PM PDT 24
Peak memory 200144 kb
Host smart-6ddd530b-be97-41b5-a21d-bbd7971fde9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716547130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2716547130
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3916769339
Short name T557
Test name
Test status
Simulation time 7515065889 ps
CPU time 454.12 seconds
Started Jun 22 05:58:11 PM PDT 24
Finished Jun 22 06:05:46 PM PDT 24
Peak memory 676476 kb
Host smart-c1b1d0bf-b67c-4307-8042-daf9ece92626
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3916769339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3916769339
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3159252311
Short name T471
Test name
Test status
Simulation time 10223194135 ps
CPU time 127.6 seconds
Started Jun 22 05:58:11 PM PDT 24
Finished Jun 22 06:00:19 PM PDT 24
Peak memory 200108 kb
Host smart-ac429951-9989-46e2-a453-b7275d874979
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159252311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3159252311
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.373611607
Short name T237
Test name
Test status
Simulation time 25387647069 ps
CPU time 91.25 seconds
Started Jun 22 05:58:06 PM PDT 24
Finished Jun 22 05:59:38 PM PDT 24
Peak memory 200308 kb
Host smart-70891c09-9e55-4229-93df-6507d31f09d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373611607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.373611607
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3188527345
Short name T649
Test name
Test status
Simulation time 965127315 ps
CPU time 11.94 seconds
Started Jun 22 05:58:05 PM PDT 24
Finished Jun 22 05:58:17 PM PDT 24
Peak memory 200072 kb
Host smart-c9e932c3-f928-4732-bef1-307df6e345c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188527345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3188527345
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.99351728
Short name T79
Test name
Test status
Simulation time 22659392 ps
CPU time 0.62 seconds
Started Jun 22 05:58:11 PM PDT 24
Finished Jun 22 05:58:12 PM PDT 24
Peak memory 195820 kb
Host smart-61a8b992-8bbc-46cb-968a-97a6e557b9dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99351728 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.99351728
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.1934868769
Short name T270
Test name
Test status
Simulation time 32944859 ps
CPU time 1.29 seconds
Started Jun 22 05:58:13 PM PDT 24
Finished Jun 22 05:58:14 PM PDT 24
Peak memory 200040 kb
Host smart-2d2b73bd-cca3-4fe4-98d8-6891b482ba93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934868769 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_hmac_vectors.1934868769
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha256_vectors.103215748
Short name T335
Test name
Test status
Simulation time 85212917244 ps
CPU time 588.11 seconds
Started Jun 22 05:58:13 PM PDT 24
Finished Jun 22 06:08:01 PM PDT 24
Peak memory 200120 kb
Host smart-b9c4b291-a0ad-4db9-805a-341ab8618445
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=103215748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha256_vectors.103215748
Directory /workspace/14.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha384_vectors.2499017371
Short name T431
Test name
Test status
Simulation time 369646706956 ps
CPU time 2440.32 seconds
Started Jun 22 05:58:14 PM PDT 24
Finished Jun 22 06:38:55 PM PDT 24
Peak memory 216500 kb
Host smart-55539f1a-61d9-488c-b527-46b7fa3a080c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2499017371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha384_vectors.2499017371
Directory /workspace/14.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha512_vectors.2049574477
Short name T177
Test name
Test status
Simulation time 411948925399 ps
CPU time 1907.05 seconds
Started Jun 22 05:58:13 PM PDT 24
Finished Jun 22 06:30:00 PM PDT 24
Peak memory 216536 kb
Host smart-79fd89b8-5a53-45e4-a087-e7f8dd7ab75a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2049574477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha512_vectors.2049574477
Directory /workspace/14.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.157707059
Short name T119
Test name
Test status
Simulation time 2448305795 ps
CPU time 38.36 seconds
Started Jun 22 05:58:11 PM PDT 24
Finished Jun 22 05:58:50 PM PDT 24
Peak memory 200132 kb
Host smart-3b283059-b0c9-4a98-8858-11124ab1be32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157707059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.157707059
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.661058997
Short name T231
Test name
Test status
Simulation time 49313522 ps
CPU time 0.59 seconds
Started Jun 22 05:58:18 PM PDT 24
Finished Jun 22 05:58:19 PM PDT 24
Peak memory 196972 kb
Host smart-11b38ef6-f6a6-479e-8dcc-f7fdaf46a082
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661058997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.661058997
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2151300815
Short name T347
Test name
Test status
Simulation time 2218137545 ps
CPU time 27.23 seconds
Started Jun 22 05:58:10 PM PDT 24
Finished Jun 22 05:58:38 PM PDT 24
Peak memory 200068 kb
Host smart-486ae84b-cb54-4cb8-9926-4e6932a81d0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2151300815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2151300815
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2602444193
Short name T260
Test name
Test status
Simulation time 8185609521 ps
CPU time 40.02 seconds
Started Jun 22 05:58:17 PM PDT 24
Finished Jun 22 05:58:57 PM PDT 24
Peak memory 200136 kb
Host smart-a8956cdb-ef9c-4644-9dff-436d2bcc53c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602444193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2602444193
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3770426159
Short name T654
Test name
Test status
Simulation time 6722987674 ps
CPU time 499.31 seconds
Started Jun 22 05:58:28 PM PDT 24
Finished Jun 22 06:06:49 PM PDT 24
Peak memory 737612 kb
Host smart-aa42f193-696e-4fad-9860-1bb074bf0af5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3770426159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3770426159
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.116615306
Short name T596
Test name
Test status
Simulation time 6026073587 ps
CPU time 54.73 seconds
Started Jun 22 05:58:17 PM PDT 24
Finished Jun 22 05:59:12 PM PDT 24
Peak memory 200080 kb
Host smart-4aab3a91-5bae-4d4f-8ff4-e83fe3cb40b9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116615306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.116615306
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2616177552
Short name T432
Test name
Test status
Simulation time 35606817217 ps
CPU time 91.16 seconds
Started Jun 22 05:58:10 PM PDT 24
Finished Jun 22 05:59:42 PM PDT 24
Peak memory 200312 kb
Host smart-7b9244a6-0503-4399-a126-86b4a5af2a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616177552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2616177552
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1020395227
Short name T570
Test name
Test status
Simulation time 2762475432 ps
CPU time 14.25 seconds
Started Jun 22 05:58:13 PM PDT 24
Finished Jun 22 05:58:28 PM PDT 24
Peak memory 200144 kb
Host smart-73a2871d-1113-4e6d-865e-375351695c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020395227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1020395227
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.1790485936
Short name T164
Test name
Test status
Simulation time 110964989 ps
CPU time 1.14 seconds
Started Jun 22 05:58:18 PM PDT 24
Finished Jun 22 05:58:20 PM PDT 24
Peak memory 199988 kb
Host smart-11fae63c-2bb4-4d5c-a79f-ecbbe1852a60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790485936 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_hmac_vectors.1790485936
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha256_vectors.1915982429
Short name T593
Test name
Test status
Simulation time 6905697711 ps
CPU time 403.9 seconds
Started Jun 22 05:58:21 PM PDT 24
Finished Jun 22 06:05:06 PM PDT 24
Peak memory 199996 kb
Host smart-caec2fa5-34f6-4961-810c-8fe9a417d984
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1915982429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha256_vectors.1915982429
Directory /workspace/15.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha384_vectors.3368739583
Short name T630
Test name
Test status
Simulation time 29250555729 ps
CPU time 1719.18 seconds
Started Jun 22 05:58:17 PM PDT 24
Finished Jun 22 06:26:57 PM PDT 24
Peak memory 215508 kb
Host smart-019231ec-ed34-4cb0-9ee3-8d6d1d45d0bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3368739583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha384_vectors.3368739583
Directory /workspace/15.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha512_vectors.3681694447
Short name T276
Test name
Test status
Simulation time 645006814814 ps
CPU time 2117.27 seconds
Started Jun 22 05:58:17 PM PDT 24
Finished Jun 22 06:33:35 PM PDT 24
Peak memory 216024 kb
Host smart-42805309-2e1e-4ffd-8e41-8a3d142d63c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3681694447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha512_vectors.3681694447
Directory /workspace/15.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3342750499
Short name T521
Test name
Test status
Simulation time 1335480670 ps
CPU time 9.08 seconds
Started Jun 22 05:58:17 PM PDT 24
Finished Jun 22 05:58:26 PM PDT 24
Peak memory 200108 kb
Host smart-24888102-5c10-44bb-aa5e-a04dfc1f6d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342750499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3342750499
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.1672389699
Short name T306
Test name
Test status
Simulation time 74932170 ps
CPU time 0.58 seconds
Started Jun 22 05:58:31 PM PDT 24
Finished Jun 22 05:58:32 PM PDT 24
Peak memory 196740 kb
Host smart-59a39cc4-c84e-4a2e-a73b-fc984cc338b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672389699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1672389699
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.479414982
Short name T509
Test name
Test status
Simulation time 8648923393 ps
CPU time 42.17 seconds
Started Jun 22 05:58:28 PM PDT 24
Finished Jun 22 05:59:11 PM PDT 24
Peak memory 208332 kb
Host smart-e4025f0c-09e4-4d0c-a6da-cd5967ea2cce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=479414982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.479414982
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2062122044
Short name T563
Test name
Test status
Simulation time 54988164 ps
CPU time 2.58 seconds
Started Jun 22 05:58:24 PM PDT 24
Finished Jun 22 05:58:27 PM PDT 24
Peak memory 200100 kb
Host smart-fab0faf5-1d2c-4add-81e3-f6f63999e191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062122044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2062122044
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.164965044
Short name T548
Test name
Test status
Simulation time 3362128352 ps
CPU time 806.86 seconds
Started Jun 22 05:58:25 PM PDT 24
Finished Jun 22 06:11:53 PM PDT 24
Peak memory 692432 kb
Host smart-824e3dff-46ed-44d1-93cb-131326082fcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=164965044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.164965044
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.3229161619
Short name T136
Test name
Test status
Simulation time 4964338695 ps
CPU time 118.77 seconds
Started Jun 22 05:58:28 PM PDT 24
Finished Jun 22 06:00:28 PM PDT 24
Peak memory 200228 kb
Host smart-ce27818d-dd5c-487d-acca-9d9f592ccc95
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229161619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3229161619
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.386882053
Short name T595
Test name
Test status
Simulation time 4881866652 ps
CPU time 73.6 seconds
Started Jun 22 05:58:25 PM PDT 24
Finished Jun 22 05:59:39 PM PDT 24
Peak memory 200168 kb
Host smart-e1cb4c6a-f77e-4196-9219-9466ba303eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386882053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.386882053
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.622238147
Short name T376
Test name
Test status
Simulation time 37758631 ps
CPU time 2.06 seconds
Started Jun 22 05:58:28 PM PDT 24
Finished Jun 22 05:58:30 PM PDT 24
Peak memory 200096 kb
Host smart-cf4a3831-e1f6-4593-982c-c9d23bbd1bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622238147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.622238147
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.641746930
Short name T594
Test name
Test status
Simulation time 118085859 ps
CPU time 1.32 seconds
Started Jun 22 05:58:26 PM PDT 24
Finished Jun 22 05:58:28 PM PDT 24
Peak memory 200060 kb
Host smart-dc6f81ed-a07c-45f5-8763-7e55f912472c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641746930 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_hmac_vectors.641746930
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha256_vectors.2902667190
Short name T639
Test name
Test status
Simulation time 178987436095 ps
CPU time 590.21 seconds
Started Jun 22 05:58:28 PM PDT 24
Finished Jun 22 06:08:19 PM PDT 24
Peak memory 200252 kb
Host smart-d8cd823e-a937-4f47-8527-4cb033e0636e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2902667190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha256_vectors.2902667190
Directory /workspace/16.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha384_vectors.3562946727
Short name T526
Test name
Test status
Simulation time 219837098434 ps
CPU time 1899.23 seconds
Started Jun 22 05:58:26 PM PDT 24
Finished Jun 22 06:30:05 PM PDT 24
Peak memory 216012 kb
Host smart-7e096384-0c4e-4b33-8662-a1f41f730944
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3562946727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha384_vectors.3562946727
Directory /workspace/16.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha512_vectors.1978786671
Short name T402
Test name
Test status
Simulation time 414073894895 ps
CPU time 2186.59 seconds
Started Jun 22 05:58:25 PM PDT 24
Finished Jun 22 06:34:52 PM PDT 24
Peak memory 215592 kb
Host smart-7faf79ee-d4c8-4932-b8f0-6e49cb5fb9f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1978786671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha512_vectors.1978786671
Directory /workspace/16.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1048384105
Short name T346
Test name
Test status
Simulation time 8710662396 ps
CPU time 81.39 seconds
Started Jun 22 05:58:25 PM PDT 24
Finished Jun 22 05:59:47 PM PDT 24
Peak memory 200112 kb
Host smart-e7008a06-d0f5-404c-9321-056e5dcc0f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048384105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1048384105
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1932546980
Short name T502
Test name
Test status
Simulation time 12777665 ps
CPU time 0.61 seconds
Started Jun 22 05:58:35 PM PDT 24
Finished Jun 22 05:58:36 PM PDT 24
Peak memory 196000 kb
Host smart-f1f645f4-b265-4846-9449-abf50afcc2c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932546980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1932546980
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2070747386
Short name T417
Test name
Test status
Simulation time 997325880 ps
CPU time 23.92 seconds
Started Jun 22 05:58:32 PM PDT 24
Finished Jun 22 05:58:56 PM PDT 24
Peak memory 200040 kb
Host smart-4db9c0f5-11b8-4ded-82a8-fd9776dc61de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2070747386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2070747386
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1627060665
Short name T493
Test name
Test status
Simulation time 2360555339 ps
CPU time 16.92 seconds
Started Jun 22 05:58:31 PM PDT 24
Finished Jun 22 05:58:48 PM PDT 24
Peak memory 200120 kb
Host smart-1f651d41-7401-4ee5-bcf5-0248ab21cd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627060665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1627060665
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2656033117
Short name T318
Test name
Test status
Simulation time 6022243424 ps
CPU time 353.17 seconds
Started Jun 22 05:58:32 PM PDT 24
Finished Jun 22 06:04:25 PM PDT 24
Peak memory 629396 kb
Host smart-f92576f7-22fd-48a0-bf7e-e3140d4302fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2656033117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2656033117
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.4154487342
Short name T140
Test name
Test status
Simulation time 5835756976 ps
CPU time 100.58 seconds
Started Jun 22 05:58:30 PM PDT 24
Finished Jun 22 06:00:12 PM PDT 24
Peak memory 200136 kb
Host smart-1eb48bb7-cea2-45ae-a7bc-c1f8ebf9ef6f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154487342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.4154487342
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3329063482
Short name T188
Test name
Test status
Simulation time 1609401805 ps
CPU time 96.35 seconds
Started Jun 22 05:58:36 PM PDT 24
Finished Jun 22 06:00:12 PM PDT 24
Peak memory 199952 kb
Host smart-57912872-90a9-4fab-919e-e87ab0fc6cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329063482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3329063482
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.1469835405
Short name T302
Test name
Test status
Simulation time 7382378518 ps
CPU time 23.26 seconds
Started Jun 22 05:58:33 PM PDT 24
Finished Jun 22 05:58:56 PM PDT 24
Peak memory 200128 kb
Host smart-4507d8b7-46d5-47cc-834a-174deeb72c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469835405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1469835405
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.65304587
Short name T243
Test name
Test status
Simulation time 299471857 ps
CPU time 1.4 seconds
Started Jun 22 05:58:33 PM PDT 24
Finished Jun 22 05:58:35 PM PDT 24
Peak memory 200068 kb
Host smart-8ea9abac-2692-46df-947d-ccea5663249e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65304587 -assert nopostpro
c +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_hmac_vectors.65304587
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha256_vectors.3450946389
Short name T645
Test name
Test status
Simulation time 16346685936 ps
CPU time 474.04 seconds
Started Jun 22 05:58:31 PM PDT 24
Finished Jun 22 06:06:25 PM PDT 24
Peak memory 200020 kb
Host smart-9fce2619-1ed5-4a3a-9d3f-02702f793898
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3450946389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha256_vectors.3450946389
Directory /workspace/17.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha384_vectors.751842629
Short name T647
Test name
Test status
Simulation time 138076421707 ps
CPU time 1860.22 seconds
Started Jun 22 05:58:32 PM PDT 24
Finished Jun 22 06:29:33 PM PDT 24
Peak memory 215492 kb
Host smart-225e6eb5-ed70-4ed4-a6de-fe6edf7ffc07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=751842629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha384_vectors.751842629
Directory /workspace/17.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha512_vectors.694257905
Short name T442
Test name
Test status
Simulation time 323433329875 ps
CPU time 1553.01 seconds
Started Jun 22 05:58:34 PM PDT 24
Finished Jun 22 06:24:28 PM PDT 24
Peak memory 216540 kb
Host smart-1a04b3ad-392e-4bf5-9a4e-ee7e2d7d4d5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=694257905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha512_vectors.694257905
Directory /workspace/17.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3361885000
Short name T31
Test name
Test status
Simulation time 3888942902 ps
CPU time 27.73 seconds
Started Jun 22 05:58:33 PM PDT 24
Finished Jun 22 05:59:01 PM PDT 24
Peak memory 200136 kb
Host smart-97bafc75-6693-4157-b098-172aac7f94e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361885000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3361885000
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.76597158
Short name T537
Test name
Test status
Simulation time 95853768 ps
CPU time 0.59 seconds
Started Jun 22 05:58:45 PM PDT 24
Finished Jun 22 05:58:46 PM PDT 24
Peak memory 196004 kb
Host smart-9119e9ca-4342-4209-b7ae-ec44dcfa501d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76597158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.76597158
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.534373384
Short name T578
Test name
Test status
Simulation time 1457924381 ps
CPU time 33.42 seconds
Started Jun 22 05:58:42 PM PDT 24
Finished Jun 22 05:59:16 PM PDT 24
Peak memory 200040 kb
Host smart-68d7c912-f002-45ba-8220-73cfbe85f2b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=534373384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.534373384
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1965706589
Short name T240
Test name
Test status
Simulation time 106858851 ps
CPU time 3.15 seconds
Started Jun 22 05:58:40 PM PDT 24
Finished Jun 22 05:58:43 PM PDT 24
Peak memory 199964 kb
Host smart-cee99024-a974-40de-915d-7335174d134d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965706589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1965706589
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1951053873
Short name T408
Test name
Test status
Simulation time 981102286 ps
CPU time 219.94 seconds
Started Jun 22 05:58:39 PM PDT 24
Finished Jun 22 06:02:19 PM PDT 24
Peak memory 618008 kb
Host smart-f09d0404-8257-4093-a0b3-4e24bb48dcbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1951053873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1951053873
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2691967481
Short name T13
Test name
Test status
Simulation time 13232450 ps
CPU time 0.72 seconds
Started Jun 22 05:58:42 PM PDT 24
Finished Jun 22 05:58:43 PM PDT 24
Peak memory 196496 kb
Host smart-4be6e600-1c35-4665-9da3-ce8c313c032e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691967481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2691967481
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1580034616
Short name T297
Test name
Test status
Simulation time 2249800007 ps
CPU time 33.17 seconds
Started Jun 22 05:58:43 PM PDT 24
Finished Jun 22 05:59:17 PM PDT 24
Peak memory 200140 kb
Host smart-0342d8d5-0485-4a49-8b9b-2f3f43ee09ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580034616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1580034616
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1097444917
Short name T458
Test name
Test status
Simulation time 764451720 ps
CPU time 11.29 seconds
Started Jun 22 05:58:40 PM PDT 24
Finished Jun 22 05:58:51 PM PDT 24
Peak memory 200108 kb
Host smart-ff4b9a86-71c8-4f33-a9e1-9908e1937c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097444917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1097444917
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.2178440207
Short name T514
Test name
Test status
Simulation time 46167890 ps
CPU time 1.09 seconds
Started Jun 22 05:58:44 PM PDT 24
Finished Jun 22 05:58:46 PM PDT 24
Peak memory 199584 kb
Host smart-c21f3adc-203d-4299-b280-45aff324c983
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178440207 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_hmac_vectors.2178440207
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha256_vectors.1909524139
Short name T501
Test name
Test status
Simulation time 138335134986 ps
CPU time 459.98 seconds
Started Jun 22 05:58:43 PM PDT 24
Finished Jun 22 06:06:23 PM PDT 24
Peak memory 200124 kb
Host smart-8fff0370-6bb4-4533-9206-a20aa01514de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1909524139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha256_vectors.1909524139
Directory /workspace/18.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha384_vectors.3838592940
Short name T525
Test name
Test status
Simulation time 158374835960 ps
CPU time 1904.93 seconds
Started Jun 22 05:58:39 PM PDT 24
Finished Jun 22 06:30:24 PM PDT 24
Peak memory 216400 kb
Host smart-1af8db03-a5f1-4885-941e-0cb25910a181
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3838592940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha384_vectors.3838592940
Directory /workspace/18.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha512_vectors.4151027686
Short name T90
Test name
Test status
Simulation time 55399972259 ps
CPU time 1544.26 seconds
Started Jun 22 05:58:47 PM PDT 24
Finished Jun 22 06:24:31 PM PDT 24
Peak memory 215700 kb
Host smart-65dc9a7c-bb74-41b9-a49c-59b13e5250d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4151027686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha512_vectors.4151027686
Directory /workspace/18.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2234463994
Short name T273
Test name
Test status
Simulation time 42615934128 ps
CPU time 39.4 seconds
Started Jun 22 05:58:39 PM PDT 24
Finished Jun 22 05:59:19 PM PDT 24
Peak memory 200060 kb
Host smart-7ff61b7b-7010-4eb4-aefd-11936f43825f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234463994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2234463994
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1117856006
Short name T378
Test name
Test status
Simulation time 19364406 ps
CPU time 0.58 seconds
Started Jun 22 05:58:48 PM PDT 24
Finished Jun 22 05:58:49 PM PDT 24
Peak memory 194972 kb
Host smart-7049e839-ab52-4c35-aa2f-af10494b6585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117856006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1117856006
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.1086781593
Short name T336
Test name
Test status
Simulation time 1854741151 ps
CPU time 10.74 seconds
Started Jun 22 05:58:44 PM PDT 24
Finished Jun 22 05:58:55 PM PDT 24
Peak memory 200056 kb
Host smart-42e7413c-abc2-4361-bd06-dd274e286831
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1086781593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1086781593
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.4121845134
Short name T35
Test name
Test status
Simulation time 4179690941 ps
CPU time 72.93 seconds
Started Jun 22 05:58:47 PM PDT 24
Finished Jun 22 06:00:00 PM PDT 24
Peak memory 200112 kb
Host smart-01524498-211a-48ee-8025-cadcf8b138f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121845134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.4121845134
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2980019269
Short name T603
Test name
Test status
Simulation time 1313971017 ps
CPU time 285.95 seconds
Started Jun 22 05:58:48 PM PDT 24
Finished Jun 22 06:03:35 PM PDT 24
Peak memory 462764 kb
Host smart-1abae589-dc95-4e1e-88cd-d5cc2ce346b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2980019269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2980019269
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.1599197192
Short name T600
Test name
Test status
Simulation time 29071241330 ps
CPU time 102.28 seconds
Started Jun 22 05:58:47 PM PDT 24
Finished Jun 22 06:00:30 PM PDT 24
Peak memory 200096 kb
Host smart-d345885d-8b50-4abc-aec0-b711552f4674
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599197192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.1599197192
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1536201183
Short name T651
Test name
Test status
Simulation time 4232401818 ps
CPU time 64.06 seconds
Started Jun 22 05:58:45 PM PDT 24
Finished Jun 22 05:59:49 PM PDT 24
Peak memory 200176 kb
Host smart-25afb5e1-3027-4092-bda0-198b1a1181e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536201183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1536201183
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1609919909
Short name T191
Test name
Test status
Simulation time 92639372 ps
CPU time 3.96 seconds
Started Jun 22 05:58:46 PM PDT 24
Finished Jun 22 05:58:51 PM PDT 24
Peak memory 200096 kb
Host smart-26b31b33-1a96-43ff-81fd-b15132ead604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609919909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1609919909
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.2260104459
Short name T543
Test name
Test status
Simulation time 233887495 ps
CPU time 1.11 seconds
Started Jun 22 05:58:45 PM PDT 24
Finished Jun 22 05:58:46 PM PDT 24
Peak memory 200096 kb
Host smart-3139a378-ca94-43d7-844a-a833ef7d566d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260104459 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_hmac_vectors.2260104459
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha256_vectors.605159772
Short name T326
Test name
Test status
Simulation time 41175183229 ps
CPU time 497.21 seconds
Started Jun 22 05:58:46 PM PDT 24
Finished Jun 22 06:07:04 PM PDT 24
Peak memory 200108 kb
Host smart-f0367167-b23f-4578-8a82-79a71f46f041
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=605159772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha256_vectors.605159772
Directory /workspace/19.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha384_vectors.2277274543
Short name T587
Test name
Test status
Simulation time 437492771479 ps
CPU time 1903.28 seconds
Started Jun 22 05:58:47 PM PDT 24
Finished Jun 22 06:30:31 PM PDT 24
Peak memory 215552 kb
Host smart-227c68b3-8493-4df4-9e96-2461a4386e20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2277274543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha384_vectors.2277274543
Directory /workspace/19.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha512_vectors.303595964
Short name T166
Test name
Test status
Simulation time 337299650672 ps
CPU time 1979.63 seconds
Started Jun 22 05:58:48 PM PDT 24
Finished Jun 22 06:31:48 PM PDT 24
Peak memory 216044 kb
Host smart-1fd0cab7-959d-477c-8806-08bb34cd7490
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=303595964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha512_vectors.303595964
Directory /workspace/19.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.160416533
Short name T480
Test name
Test status
Simulation time 2191388466 ps
CPU time 41.05 seconds
Started Jun 22 05:58:46 PM PDT 24
Finished Jun 22 05:59:27 PM PDT 24
Peak memory 200104 kb
Host smart-6bdec685-533b-40a7-9f95-457a1b3c687f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160416533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.160416533
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3389711946
Short name T293
Test name
Test status
Simulation time 11917455 ps
CPU time 0.56 seconds
Started Jun 22 05:56:39 PM PDT 24
Finished Jun 22 05:56:40 PM PDT 24
Peak memory 195632 kb
Host smart-9f9e82d6-9bbc-49ca-9fe3-3aa46e6fc9df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389711946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3389711946
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3099752661
Short name T33
Test name
Test status
Simulation time 903791289 ps
CPU time 33.91 seconds
Started Jun 22 05:56:20 PM PDT 24
Finished Jun 22 05:56:54 PM PDT 24
Peak memory 200068 kb
Host smart-268a2606-bade-4067-8d00-863938f7d789
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3099752661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3099752661
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1344582164
Short name T612
Test name
Test status
Simulation time 5721925665 ps
CPU time 25.52 seconds
Started Jun 22 05:56:28 PM PDT 24
Finished Jun 22 05:56:54 PM PDT 24
Peak memory 200180 kb
Host smart-73b3c687-83d1-4d9c-8320-56ffc8f9e875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344582164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1344582164
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1190096206
Short name T655
Test name
Test status
Simulation time 293594028 ps
CPU time 5.88 seconds
Started Jun 22 05:56:21 PM PDT 24
Finished Jun 22 05:56:27 PM PDT 24
Peak memory 200132 kb
Host smart-14522745-974a-4ca9-b46b-f397e5541539
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1190096206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1190096206
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.873517273
Short name T394
Test name
Test status
Simulation time 4003614408 ps
CPU time 132.1 seconds
Started Jun 22 05:56:27 PM PDT 24
Finished Jun 22 05:58:40 PM PDT 24
Peak memory 200136 kb
Host smart-f689ae46-ea30-444d-8b48-fc79cbce0856
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873517273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.873517273
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3585447116
Short name T249
Test name
Test status
Simulation time 1028336167 ps
CPU time 59.59 seconds
Started Jun 22 05:56:21 PM PDT 24
Finished Jun 22 05:57:21 PM PDT 24
Peak memory 200088 kb
Host smart-5dfe5ce7-2854-49f1-83c7-97960335f58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585447116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3585447116
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_smoke.1423551305
Short name T607
Test name
Test status
Simulation time 616149047 ps
CPU time 5.71 seconds
Started Jun 22 05:56:21 PM PDT 24
Finished Jun 22 05:56:27 PM PDT 24
Peak memory 200192 kb
Host smart-717da6f7-a484-4d99-aa15-42a02e737384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423551305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1423551305
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.3896402724
Short name T558
Test name
Test status
Simulation time 133547688 ps
CPU time 1.3 seconds
Started Jun 22 05:56:36 PM PDT 24
Finished Jun 22 05:56:38 PM PDT 24
Peak memory 200036 kb
Host smart-a3fc88c8-3379-4273-ab0c-9ce33df01af4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896402724 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac_vectors.3896402724
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.1726916383
Short name T209
Test name
Test status
Simulation time 116674851008 ps
CPU time 470.57 seconds
Started Jun 22 05:56:28 PM PDT 24
Finished Jun 22 06:04:19 PM PDT 24
Peak memory 200120 kb
Host smart-e0629e01-f1b2-4ec5-91f9-2c21a280c201
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1726916383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.1726916383
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.3582025044
Short name T1
Test name
Test status
Simulation time 167167462728 ps
CPU time 1646.64 seconds
Started Jun 22 05:56:27 PM PDT 24
Finished Jun 22 06:23:54 PM PDT 24
Peak memory 216244 kb
Host smart-f93a176a-ca66-4548-ad37-53e699c1bae1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3582025044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.3582025044
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.272839677
Short name T472
Test name
Test status
Simulation time 124037335009 ps
CPU time 1809.33 seconds
Started Jun 22 05:56:28 PM PDT 24
Finished Jun 22 06:26:38 PM PDT 24
Peak memory 215632 kb
Host smart-74442b64-547b-49b0-8999-d073c7d82396
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=272839677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.272839677
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3901986005
Short name T56
Test name
Test status
Simulation time 1733996643 ps
CPU time 82.02 seconds
Started Jun 22 05:56:31 PM PDT 24
Finished Jun 22 05:57:53 PM PDT 24
Peak memory 200044 kb
Host smart-7f3f6789-03f8-46b2-b81b-9e457e5035d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901986005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3901986005
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.300986704
Short name T95
Test name
Test status
Simulation time 14362903 ps
CPU time 0.62 seconds
Started Jun 22 05:58:53 PM PDT 24
Finished Jun 22 05:58:55 PM PDT 24
Peak memory 195972 kb
Host smart-5604c703-cdcb-4262-9150-2851b83e3cc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300986704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.300986704
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1862806739
Short name T541
Test name
Test status
Simulation time 1040337669 ps
CPU time 44.06 seconds
Started Jun 22 05:58:47 PM PDT 24
Finished Jun 22 05:59:32 PM PDT 24
Peak memory 200032 kb
Host smart-7d53231b-325f-4e25-be2f-fad946d9d9c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1862806739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1862806739
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.158574160
Short name T153
Test name
Test status
Simulation time 4195301583 ps
CPU time 16.25 seconds
Started Jun 22 05:58:47 PM PDT 24
Finished Jun 22 05:59:03 PM PDT 24
Peak memory 200140 kb
Host smart-d510ea1f-926b-419f-aa47-2231c4d5226a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158574160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.158574160
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2107637790
Short name T487
Test name
Test status
Simulation time 713061744 ps
CPU time 35.31 seconds
Started Jun 22 05:58:45 PM PDT 24
Finished Jun 22 05:59:21 PM PDT 24
Peak memory 310380 kb
Host smart-141aaa98-ee91-4541-b51f-7d593e0cec1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2107637790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2107637790
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1390913435
Short name T40
Test name
Test status
Simulation time 10616499304 ps
CPU time 124.99 seconds
Started Jun 22 05:58:46 PM PDT 24
Finished Jun 22 06:00:52 PM PDT 24
Peak memory 200268 kb
Host smart-a40cbefe-cfd8-4ff5-bb26-93cecb965365
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390913435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1390913435
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2197145864
Short name T591
Test name
Test status
Simulation time 2510725560 ps
CPU time 18.29 seconds
Started Jun 22 05:58:45 PM PDT 24
Finished Jun 22 05:59:03 PM PDT 24
Peak memory 200136 kb
Host smart-8707d923-609b-4ff6-b015-b6e4bdc404dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197145864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2197145864
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.4206193854
Short name T638
Test name
Test status
Simulation time 163041904 ps
CPU time 7.03 seconds
Started Jun 22 05:58:44 PM PDT 24
Finished Jun 22 05:58:51 PM PDT 24
Peak memory 200072 kb
Host smart-d7c03829-ec60-42ba-8dd7-67bb345d4fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206193854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.4206193854
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.3259162686
Short name T304
Test name
Test status
Simulation time 58593852 ps
CPU time 1.3 seconds
Started Jun 22 05:58:51 PM PDT 24
Finished Jun 22 05:58:53 PM PDT 24
Peak memory 200068 kb
Host smart-0499e13c-bc3a-494f-aeb9-86c9de90526b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259162686 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_hmac_vectors.3259162686
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha256_vectors.3433173362
Short name T546
Test name
Test status
Simulation time 213816861546 ps
CPU time 584.58 seconds
Started Jun 22 05:58:52 PM PDT 24
Finished Jun 22 06:08:37 PM PDT 24
Peak memory 200124 kb
Host smart-6f7e9545-e218-4719-a474-d47a3cf9c5af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3433173362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha256_vectors.3433173362
Directory /workspace/20.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha384_vectors.4116048060
Short name T634
Test name
Test status
Simulation time 29694404985 ps
CPU time 1763.5 seconds
Started Jun 22 05:58:53 PM PDT 24
Finished Jun 22 06:28:18 PM PDT 24
Peak memory 215860 kb
Host smart-c15afc6d-853a-4a29-9ec7-e31b2019d316
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4116048060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha384_vectors.4116048060
Directory /workspace/20.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha512_vectors.1620701930
Short name T524
Test name
Test status
Simulation time 77335332529 ps
CPU time 1684.89 seconds
Started Jun 22 05:58:54 PM PDT 24
Finished Jun 22 06:27:00 PM PDT 24
Peak memory 216020 kb
Host smart-57818c74-ed2e-4a9b-b9d2-90991b49faaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1620701930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha512_vectors.1620701930
Directory /workspace/20.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2901376875
Short name T88
Test name
Test status
Simulation time 1080040967 ps
CPU time 9.38 seconds
Started Jun 22 05:58:53 PM PDT 24
Finished Jun 22 05:59:03 PM PDT 24
Peak memory 199992 kb
Host smart-cefadc2c-5fc2-498e-912c-3af478c2ff7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901376875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2901376875
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3680590348
Short name T278
Test name
Test status
Simulation time 43388415 ps
CPU time 0.56 seconds
Started Jun 22 05:58:58 PM PDT 24
Finished Jun 22 05:58:59 PM PDT 24
Peak memory 194892 kb
Host smart-aa0b7c0c-dd56-4ea0-8c7b-8a6773e4762b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680590348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3680590348
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1049502194
Short name T372
Test name
Test status
Simulation time 577009856 ps
CPU time 12.06 seconds
Started Jun 22 05:58:51 PM PDT 24
Finished Jun 22 05:59:03 PM PDT 24
Peak memory 199956 kb
Host smart-ee257d4e-30c2-41d1-8e63-e2dd6923aaf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1049502194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1049502194
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.81255172
Short name T460
Test name
Test status
Simulation time 3745588463 ps
CPU time 169.89 seconds
Started Jun 22 05:58:54 PM PDT 24
Finished Jun 22 06:01:44 PM PDT 24
Peak memory 612244 kb
Host smart-e1cd809d-9c30-4832-81d3-ad61b596962a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=81255172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.81255172
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.688773029
Short name T475
Test name
Test status
Simulation time 44881866417 ps
CPU time 83.26 seconds
Started Jun 22 05:58:53 PM PDT 24
Finished Jun 22 06:00:17 PM PDT 24
Peak memory 200112 kb
Host smart-c5c4561d-511f-4dae-b667-fa9d8fb56658
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688773029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.688773029
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.813323585
Short name T576
Test name
Test status
Simulation time 48809142779 ps
CPU time 185.51 seconds
Started Jun 22 05:58:54 PM PDT 24
Finished Jun 22 06:02:00 PM PDT 24
Peak memory 216532 kb
Host smart-ec1ad18c-b973-414d-bbcd-eaad78da4273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813323585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.813323585
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.849219621
Short name T8
Test name
Test status
Simulation time 498824288 ps
CPU time 5.83 seconds
Started Jun 22 05:58:54 PM PDT 24
Finished Jun 22 05:59:00 PM PDT 24
Peak memory 200040 kb
Host smart-4ded0820-9234-475a-b783-ef70097e9149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849219621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.849219621
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.3088920973
Short name T419
Test name
Test status
Simulation time 32971592 ps
CPU time 1.24 seconds
Started Jun 22 05:58:58 PM PDT 24
Finished Jun 22 05:58:59 PM PDT 24
Peak memory 200064 kb
Host smart-942f73bb-b3eb-44ad-8527-3bd6aa2d5476
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088920973 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_hmac_vectors.3088920973
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha256_vectors.2771219448
Short name T257
Test name
Test status
Simulation time 29278652278 ps
CPU time 514.63 seconds
Started Jun 22 05:58:51 PM PDT 24
Finished Jun 22 06:07:26 PM PDT 24
Peak memory 200124 kb
Host smart-c3eb72b9-3b3d-482a-9eb1-8509c07bc3f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2771219448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha256_vectors.2771219448
Directory /workspace/21.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha384_vectors.1993313232
Short name T559
Test name
Test status
Simulation time 75741568992 ps
CPU time 1966.04 seconds
Started Jun 22 05:58:53 PM PDT 24
Finished Jun 22 06:31:40 PM PDT 24
Peak memory 216048 kb
Host smart-972a6c0e-61ff-47fe-af16-b7571168dc5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1993313232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha384_vectors.1993313232
Directory /workspace/21.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha512_vectors.2499220104
Short name T282
Test name
Test status
Simulation time 324446117511 ps
CPU time 2078.04 seconds
Started Jun 22 05:58:59 PM PDT 24
Finished Jun 22 06:33:38 PM PDT 24
Peak memory 216224 kb
Host smart-2b6e1839-07e7-4491-a15e-414ad55c5848
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2499220104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha512_vectors.2499220104
Directory /workspace/21.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1753548071
Short name T389
Test name
Test status
Simulation time 2110651843 ps
CPU time 31.89 seconds
Started Jun 22 05:58:52 PM PDT 24
Finished Jun 22 05:59:24 PM PDT 24
Peak memory 200060 kb
Host smart-572652b2-0c11-452b-9373-483ff2784fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753548071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1753548071
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2310287393
Short name T479
Test name
Test status
Simulation time 38036140 ps
CPU time 0.59 seconds
Started Jun 22 05:59:05 PM PDT 24
Finished Jun 22 05:59:06 PM PDT 24
Peak memory 196068 kb
Host smart-75ff9199-b50d-4107-b338-16190e8f0415
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310287393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2310287393
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2142608511
Short name T420
Test name
Test status
Simulation time 2232397947 ps
CPU time 22.9 seconds
Started Jun 22 05:58:59 PM PDT 24
Finished Jun 22 05:59:23 PM PDT 24
Peak memory 200148 kb
Host smart-50c1071e-5739-41a4-ba4c-901621077c96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2142608511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2142608511
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.727339272
Short name T358
Test name
Test status
Simulation time 13822382856 ps
CPU time 44.17 seconds
Started Jun 22 05:59:07 PM PDT 24
Finished Jun 22 05:59:52 PM PDT 24
Peak memory 200376 kb
Host smart-cce66b50-f276-4bad-a4e6-d54c8d1d6627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727339272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.727339272
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2080599500
Short name T127
Test name
Test status
Simulation time 4961748139 ps
CPU time 1035.02 seconds
Started Jun 22 05:59:07 PM PDT 24
Finished Jun 22 06:16:22 PM PDT 24
Peak memory 766584 kb
Host smart-73338724-21b4-4c2b-88fe-79e37c716351
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2080599500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2080599500
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.4289674970
Short name T400
Test name
Test status
Simulation time 1026429194 ps
CPU time 18.4 seconds
Started Jun 22 05:59:08 PM PDT 24
Finished Jun 22 05:59:26 PM PDT 24
Peak memory 200044 kb
Host smart-9a10a90b-7a0c-4099-99de-81e4a2c3370e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289674970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.4289674970
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_smoke.173117533
Short name T245
Test name
Test status
Simulation time 196412845 ps
CPU time 2.23 seconds
Started Jun 22 05:59:02 PM PDT 24
Finished Jun 22 05:59:04 PM PDT 24
Peak memory 199980 kb
Host smart-34442d88-4218-41be-ba09-74c623b0af92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173117533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.173117533
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.3258870545
Short name T307
Test name
Test status
Simulation time 55626684 ps
CPU time 1.07 seconds
Started Jun 22 05:59:07 PM PDT 24
Finished Jun 22 05:59:08 PM PDT 24
Peak memory 199800 kb
Host smart-159054b5-8d86-48a9-860e-da9afc94747d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258870545 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_hmac_vectors.3258870545
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha256_vectors.2512001503
Short name T207
Test name
Test status
Simulation time 30216845142 ps
CPU time 402.89 seconds
Started Jun 22 05:59:08 PM PDT 24
Finished Jun 22 06:05:51 PM PDT 24
Peak memory 200144 kb
Host smart-1e06f383-a593-4259-8d5b-7460d9c1aea7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2512001503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha256_vectors.2512001503
Directory /workspace/22.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha384_vectors.1426245025
Short name T59
Test name
Test status
Simulation time 32390536170 ps
CPU time 1738.8 seconds
Started Jun 22 05:59:09 PM PDT 24
Finished Jun 22 06:28:09 PM PDT 24
Peak memory 208328 kb
Host smart-2ee86c6c-05a1-4475-9946-069cf11acde2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1426245025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha384_vectors.1426245025
Directory /workspace/22.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha512_vectors.1914905594
Short name T203
Test name
Test status
Simulation time 183339226655 ps
CPU time 1839.71 seconds
Started Jun 22 05:59:06 PM PDT 24
Finished Jun 22 06:29:46 PM PDT 24
Peak memory 215584 kb
Host smart-f297ba7d-b1b8-4b79-951c-dcffa136db76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1914905594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha512_vectors.1914905594
Directory /workspace/22.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1485003578
Short name T426
Test name
Test status
Simulation time 18788167125 ps
CPU time 69.94 seconds
Started Jun 22 05:59:09 PM PDT 24
Finished Jun 22 06:00:19 PM PDT 24
Peak memory 200140 kb
Host smart-e22153c2-4741-42f9-b388-e6d2177f526b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485003578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1485003578
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3022748530
Short name T478
Test name
Test status
Simulation time 13212949 ps
CPU time 0.58 seconds
Started Jun 22 05:59:12 PM PDT 24
Finished Jun 22 05:59:13 PM PDT 24
Peak memory 196012 kb
Host smart-6f94776a-1207-4bc0-8c89-ec537fddd6ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022748530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3022748530
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1217476115
Short name T17
Test name
Test status
Simulation time 272691793 ps
CPU time 12.98 seconds
Started Jun 22 05:59:14 PM PDT 24
Finished Jun 22 05:59:27 PM PDT 24
Peak memory 200068 kb
Host smart-79098a37-0af0-4057-8ac9-4f27e441d8e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1217476115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1217476115
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.157524789
Short name T611
Test name
Test status
Simulation time 1585945522 ps
CPU time 11.45 seconds
Started Jun 22 05:59:14 PM PDT 24
Finished Jun 22 05:59:26 PM PDT 24
Peak memory 200060 kb
Host smart-bfa083c0-0587-4396-8a62-93744b420d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157524789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.157524789
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.3645565540
Short name T230
Test name
Test status
Simulation time 2239449662 ps
CPU time 457.85 seconds
Started Jun 22 05:59:16 PM PDT 24
Finished Jun 22 06:06:54 PM PDT 24
Peak memory 474264 kb
Host smart-19fb0abc-987d-4038-b129-068daf2caf41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3645565540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.3645565540
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3424985578
Short name T544
Test name
Test status
Simulation time 2184818684 ps
CPU time 93.92 seconds
Started Jun 22 05:59:12 PM PDT 24
Finished Jun 22 06:00:47 PM PDT 24
Peak memory 200132 kb
Host smart-8e632f04-974b-4ca7-9813-bf79d1d12868
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424985578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3424985578
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1172594662
Short name T251
Test name
Test status
Simulation time 1608522885 ps
CPU time 54.24 seconds
Started Jun 22 05:59:07 PM PDT 24
Finished Jun 22 06:00:01 PM PDT 24
Peak memory 200076 kb
Host smart-3e6a41fa-fb11-4900-9cdb-769333458fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172594662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1172594662
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2601571116
Short name T528
Test name
Test status
Simulation time 132003997 ps
CPU time 0.83 seconds
Started Jun 22 05:59:05 PM PDT 24
Finished Jun 22 05:59:06 PM PDT 24
Peak memory 198696 kb
Host smart-4f3b0ac0-7030-47f3-b41a-25300b567b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601571116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2601571116
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.632597417
Short name T159
Test name
Test status
Simulation time 218754553 ps
CPU time 1.27 seconds
Started Jun 22 05:59:12 PM PDT 24
Finished Jun 22 05:59:14 PM PDT 24
Peak memory 200004 kb
Host smart-d8983707-8a8e-4308-a45f-2e60de94bfc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632597417 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_hmac_vectors.632597417
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha256_vectors.2943987742
Short name T342
Test name
Test status
Simulation time 163825083823 ps
CPU time 425.1 seconds
Started Jun 22 05:59:13 PM PDT 24
Finished Jun 22 06:06:19 PM PDT 24
Peak memory 200120 kb
Host smart-62f2a795-6f74-4840-9dfc-4209df34ba58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2943987742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha256_vectors.2943987742
Directory /workspace/23.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha384_vectors.1848685909
Short name T623
Test name
Test status
Simulation time 31480383348 ps
CPU time 1588.67 seconds
Started Jun 22 05:59:13 PM PDT 24
Finished Jun 22 06:25:43 PM PDT 24
Peak memory 216340 kb
Host smart-72d1a91b-516d-44d8-81b1-6310e416a7d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1848685909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha384_vectors.1848685909
Directory /workspace/23.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha512_vectors.1143452273
Short name T360
Test name
Test status
Simulation time 114944877977 ps
CPU time 2048.76 seconds
Started Jun 22 05:59:12 PM PDT 24
Finished Jun 22 06:33:22 PM PDT 24
Peak memory 214856 kb
Host smart-1b8e8c29-e0d9-4324-b34f-8801d18bbbbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1143452273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha512_vectors.1143452273
Directory /workspace/23.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1453509804
Short name T114
Test name
Test status
Simulation time 7732996344 ps
CPU time 76.78 seconds
Started Jun 22 05:59:14 PM PDT 24
Finished Jun 22 06:00:32 PM PDT 24
Peak memory 200116 kb
Host smart-874655ef-0fc3-40f3-ba25-9fd3109e586a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453509804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1453509804
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.4220790525
Short name T93
Test name
Test status
Simulation time 21767971 ps
CPU time 0.59 seconds
Started Jun 22 05:59:31 PM PDT 24
Finished Jun 22 05:59:31 PM PDT 24
Peak memory 195720 kb
Host smart-b84d2d27-6ac6-40bf-9ce1-31b9960fe1da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220790525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.4220790525
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3967473966
Short name T94
Test name
Test status
Simulation time 551633744 ps
CPU time 14.58 seconds
Started Jun 22 05:59:14 PM PDT 24
Finished Jun 22 05:59:29 PM PDT 24
Peak memory 200060 kb
Host smart-b74512bc-d69e-43df-9edf-ed360ad3c030
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3967473966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3967473966
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1408533317
Short name T189
Test name
Test status
Simulation time 4006663585 ps
CPU time 53.13 seconds
Started Jun 22 05:59:20 PM PDT 24
Finished Jun 22 06:00:14 PM PDT 24
Peak memory 200116 kb
Host smart-edfc6cff-d1f7-4397-a819-f99a0ac65596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408533317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1408533317
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2414133178
Short name T436
Test name
Test status
Simulation time 1047827220 ps
CPU time 279.12 seconds
Started Jun 22 05:59:20 PM PDT 24
Finished Jun 22 06:03:59 PM PDT 24
Peak memory 640556 kb
Host smart-24cb8242-4e04-4cfa-8f24-073878ae53ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2414133178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2414133178
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2216547176
Short name T92
Test name
Test status
Simulation time 10722049692 ps
CPU time 133.72 seconds
Started Jun 22 05:59:20 PM PDT 24
Finished Jun 22 06:01:34 PM PDT 24
Peak memory 200084 kb
Host smart-1d30ff44-ea9e-4df9-b9b1-4cee64d3b9b0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216547176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2216547176
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2963137596
Short name T172
Test name
Test status
Simulation time 3888715310 ps
CPU time 58.12 seconds
Started Jun 22 05:59:16 PM PDT 24
Finished Jun 22 06:00:14 PM PDT 24
Peak memory 200140 kb
Host smart-a9c7c4d0-fc7a-4619-8a6c-81f0a5ce0187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963137596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2963137596
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3466406256
Short name T375
Test name
Test status
Simulation time 1433679809 ps
CPU time 9.42 seconds
Started Jun 22 05:59:13 PM PDT 24
Finished Jun 22 05:59:23 PM PDT 24
Peak memory 200084 kb
Host smart-c674cb4b-3dfe-4e22-9508-5f85967622ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466406256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3466406256
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2884797184
Short name T446
Test name
Test status
Simulation time 1141171322 ps
CPU time 24.54 seconds
Started Jun 22 05:59:30 PM PDT 24
Finished Jun 22 05:59:55 PM PDT 24
Peak memory 200072 kb
Host smart-273563ae-637d-43d1-84ba-1449c6e84408
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884797184 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2884797184
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.3829899988
Short name T457
Test name
Test status
Simulation time 62417982 ps
CPU time 1.32 seconds
Started Jun 22 05:59:19 PM PDT 24
Finished Jun 22 05:59:21 PM PDT 24
Peak memory 200016 kb
Host smart-daafa785-1740-4153-ba34-2a0725191ce0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829899988 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_hmac_vectors.3829899988
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha256_vectors.1386134362
Short name T226
Test name
Test status
Simulation time 109920345981 ps
CPU time 498.64 seconds
Started Jun 22 05:59:20 PM PDT 24
Finished Jun 22 06:07:40 PM PDT 24
Peak memory 200108 kb
Host smart-38130bd1-dc7d-400e-86c0-09e2332815ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1386134362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha256_vectors.1386134362
Directory /workspace/24.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha512_vectors.3478005026
Short name T197
Test name
Test status
Simulation time 137234997433 ps
CPU time 1989.2 seconds
Started Jun 22 05:59:20 PM PDT 24
Finished Jun 22 06:32:30 PM PDT 24
Peak memory 216500 kb
Host smart-84636148-14be-41bb-9ecf-396cc2322d76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3478005026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha512_vectors.3478005026
Directory /workspace/24.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2930390349
Short name T454
Test name
Test status
Simulation time 83617700 ps
CPU time 2.32 seconds
Started Jun 22 05:59:20 PM PDT 24
Finished Jun 22 05:59:22 PM PDT 24
Peak memory 200076 kb
Host smart-104e41b8-bb77-4e88-9f2a-f446480e3605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930390349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2930390349
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.108298049
Short name T167
Test name
Test status
Simulation time 14527316 ps
CPU time 0.59 seconds
Started Jun 22 05:59:26 PM PDT 24
Finished Jun 22 05:59:27 PM PDT 24
Peak memory 194872 kb
Host smart-06ee9958-07aa-4b10-803a-908c62f7248c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108298049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.108298049
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3251277241
Short name T333
Test name
Test status
Simulation time 1991512997 ps
CPU time 52.09 seconds
Started Jun 22 05:59:32 PM PDT 24
Finished Jun 22 06:00:24 PM PDT 24
Peak memory 200064 kb
Host smart-c914c091-6254-4da5-ae54-4a289bf7542a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3251277241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3251277241
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1871829104
Short name T122
Test name
Test status
Simulation time 107947308 ps
CPU time 5.71 seconds
Started Jun 22 05:59:28 PM PDT 24
Finished Jun 22 05:59:34 PM PDT 24
Peak memory 200076 kb
Host smart-28a5312a-c5de-42fc-96a8-ba3148ff9886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871829104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1871829104
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.654951307
Short name T174
Test name
Test status
Simulation time 2079960152 ps
CPU time 700.53 seconds
Started Jun 22 05:59:26 PM PDT 24
Finished Jun 22 06:11:07 PM PDT 24
Peak memory 690284 kb
Host smart-c8b14e89-2186-4418-b8e6-025229058c43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=654951307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.654951307
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.1628708730
Short name T383
Test name
Test status
Simulation time 6494549722 ps
CPU time 169.92 seconds
Started Jun 22 05:59:28 PM PDT 24
Finished Jun 22 06:02:18 PM PDT 24
Peak memory 200132 kb
Host smart-cce5f233-f09f-41d5-b94e-0cd5d3f5a84c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628708730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.1628708730
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2109592053
Short name T229
Test name
Test status
Simulation time 4283450394 ps
CPU time 30.61 seconds
Started Jun 22 05:59:28 PM PDT 24
Finished Jun 22 05:59:59 PM PDT 24
Peak memory 200136 kb
Host smart-c8a858e5-b55a-43b1-a370-cc44af5fbda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109592053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2109592053
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1304480530
Short name T453
Test name
Test status
Simulation time 4004000074 ps
CPU time 21.31 seconds
Started Jun 22 05:59:28 PM PDT 24
Finished Jun 22 05:59:50 PM PDT 24
Peak memory 200132 kb
Host smart-a2bf0b3f-86a7-445b-a5d6-c07cb9141bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304480530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1304480530
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.488030766
Short name T57
Test name
Test status
Simulation time 464907278 ps
CPU time 16.24 seconds
Started Jun 22 05:59:29 PM PDT 24
Finished Jun 22 05:59:46 PM PDT 24
Peak memory 200092 kb
Host smart-4844d123-f11f-429f-8527-575c2627bc65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488030766 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.488030766
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.1887178020
Short name T281
Test name
Test status
Simulation time 67133825 ps
CPU time 1.46 seconds
Started Jun 22 05:59:30 PM PDT 24
Finished Jun 22 05:59:32 PM PDT 24
Peak memory 200060 kb
Host smart-1e52bfe6-d4be-49e6-a748-b62276e41146
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887178020 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_hmac_vectors.1887178020
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha256_vectors.4136850878
Short name T199
Test name
Test status
Simulation time 387720590004 ps
CPU time 496.74 seconds
Started Jun 22 05:59:28 PM PDT 24
Finished Jun 22 06:07:45 PM PDT 24
Peak memory 200148 kb
Host smart-b442b5d8-535d-42e1-ba9a-8714cd149a5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4136850878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha256_vectors.4136850878
Directory /workspace/25.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha384_vectors.28135012
Short name T223
Test name
Test status
Simulation time 139823582826 ps
CPU time 1969.33 seconds
Started Jun 22 05:59:29 PM PDT 24
Finished Jun 22 06:32:19 PM PDT 24
Peak memory 215680 kb
Host smart-3ecfd7e2-1f26-445b-9146-8e6ac59abd59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=28135012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha384_vectors.28135012
Directory /workspace/25.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha512_vectors.2115230202
Short name T617
Test name
Test status
Simulation time 149110013628 ps
CPU time 1678.88 seconds
Started Jun 22 05:59:28 PM PDT 24
Finished Jun 22 06:27:28 PM PDT 24
Peak memory 215616 kb
Host smart-e9c18f50-8554-41d7-8b49-acc3bc5119d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2115230202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha512_vectors.2115230202
Directory /workspace/25.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3582038127
Short name T580
Test name
Test status
Simulation time 12148027139 ps
CPU time 48.19 seconds
Started Jun 22 05:59:27 PM PDT 24
Finished Jun 22 06:00:15 PM PDT 24
Peak memory 200124 kb
Host smart-fc398b18-8d33-4682-860c-913759e4b95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582038127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3582038127
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2132115176
Short name T635
Test name
Test status
Simulation time 23038385 ps
CPU time 0.62 seconds
Started Jun 22 05:59:39 PM PDT 24
Finished Jun 22 05:59:40 PM PDT 24
Peak memory 194848 kb
Host smart-444cff9e-42f8-46e1-8667-8ff9e69aacef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132115176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2132115176
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3983758195
Short name T24
Test name
Test status
Simulation time 1380495408 ps
CPU time 31.46 seconds
Started Jun 22 05:59:37 PM PDT 24
Finished Jun 22 06:00:09 PM PDT 24
Peak memory 200068 kb
Host smart-ab70b847-2bdd-4cd7-ad60-18b7a5009cde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3983758195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3983758195
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.244783759
Short name T150
Test name
Test status
Simulation time 2115535231 ps
CPU time 13.9 seconds
Started Jun 22 05:59:38 PM PDT 24
Finished Jun 22 05:59:52 PM PDT 24
Peak memory 200048 kb
Host smart-1f1f2a95-bd54-4346-a3ff-777d44921582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244783759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.244783759
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3134982538
Short name T633
Test name
Test status
Simulation time 1681998564 ps
CPU time 410.23 seconds
Started Jun 22 05:59:37 PM PDT 24
Finished Jun 22 06:06:27 PM PDT 24
Peak memory 719696 kb
Host smart-5d0e679d-1cb9-4aa3-9295-278423cc0e81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3134982538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3134982538
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3744342004
Short name T305
Test name
Test status
Simulation time 17994767832 ps
CPU time 75.86 seconds
Started Jun 22 05:59:39 PM PDT 24
Finished Jun 22 06:00:55 PM PDT 24
Peak memory 200108 kb
Host smart-3c88984d-757a-4405-9353-1dbcf1d97f7a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744342004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3744342004
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3490917158
Short name T404
Test name
Test status
Simulation time 90248682041 ps
CPU time 151.38 seconds
Started Jun 22 05:59:29 PM PDT 24
Finished Jun 22 06:02:01 PM PDT 24
Peak memory 200344 kb
Host smart-08972860-3218-45fe-9542-641ee0904d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490917158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3490917158
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.1165066596
Short name T250
Test name
Test status
Simulation time 2026588052 ps
CPU time 12.09 seconds
Started Jun 22 05:59:27 PM PDT 24
Finished Jun 22 05:59:39 PM PDT 24
Peak memory 200100 kb
Host smart-abf0a4f1-bb80-48dc-896e-49227b4d0c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165066596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1165066596
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.3050903875
Short name T181
Test name
Test status
Simulation time 182573430 ps
CPU time 1.22 seconds
Started Jun 22 05:59:38 PM PDT 24
Finished Jun 22 05:59:39 PM PDT 24
Peak memory 200008 kb
Host smart-0d51c0b9-cd43-4749-a3b2-f4d56f38ee60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050903875 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_hmac_vectors.3050903875
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha384_vectors.447256795
Short name T473
Test name
Test status
Simulation time 230362286874 ps
CPU time 2016.55 seconds
Started Jun 22 05:59:38 PM PDT 24
Finished Jun 22 06:33:15 PM PDT 24
Peak memory 216004 kb
Host smart-e72a902b-5947-4860-8461-b432e05345e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=447256795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha384_vectors.447256795
Directory /workspace/26.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha512_vectors.29773469
Short name T515
Test name
Test status
Simulation time 124938844487 ps
CPU time 1682.48 seconds
Started Jun 22 05:59:37 PM PDT 24
Finished Jun 22 06:27:40 PM PDT 24
Peak memory 216016 kb
Host smart-f730e564-b460-41fe-a08c-411cfa1eb915
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=29773469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha512_vectors.29773469
Directory /workspace/26.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.280356615
Short name T20
Test name
Test status
Simulation time 1627316648 ps
CPU time 20.07 seconds
Started Jun 22 05:59:38 PM PDT 24
Finished Jun 22 05:59:58 PM PDT 24
Peak memory 200068 kb
Host smart-7ad66ed5-35e5-408b-9f47-8aad63aa9f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280356615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.280356615
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3627115152
Short name T287
Test name
Test status
Simulation time 44938832 ps
CPU time 0.58 seconds
Started Jun 22 05:59:43 PM PDT 24
Finished Jun 22 05:59:44 PM PDT 24
Peak memory 196756 kb
Host smart-f886b886-127c-4fb3-8268-b86e1279c56a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627115152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3627115152
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1858074677
Short name T152
Test name
Test status
Simulation time 1559095270 ps
CPU time 20.6 seconds
Started Jun 22 05:59:38 PM PDT 24
Finished Jun 22 05:59:59 PM PDT 24
Peak memory 200080 kb
Host smart-4f8de7c8-b96a-4feb-8364-98562428d851
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1858074677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1858074677
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2566395998
Short name T155
Test name
Test status
Simulation time 154147402 ps
CPU time 7.46 seconds
Started Jun 22 05:59:38 PM PDT 24
Finished Jun 22 05:59:46 PM PDT 24
Peak memory 200124 kb
Host smart-5f99b988-275f-424a-aa84-b153071bea8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566395998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2566395998
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.407287688
Short name T485
Test name
Test status
Simulation time 78766485412 ps
CPU time 1160.97 seconds
Started Jun 22 05:59:39 PM PDT 24
Finished Jun 22 06:19:01 PM PDT 24
Peak memory 785208 kb
Host smart-e194f87d-7884-4a0a-bf8a-c6376ceabff4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=407287688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.407287688
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3759394673
Short name T39
Test name
Test status
Simulation time 8052285734 ps
CPU time 116.53 seconds
Started Jun 22 05:59:39 PM PDT 24
Finished Jun 22 06:01:36 PM PDT 24
Peak memory 200108 kb
Host smart-6a427051-2487-4aec-af02-5e9aa25f0154
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759394673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3759394673
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2308003716
Short name T340
Test name
Test status
Simulation time 12564976833 ps
CPU time 132.13 seconds
Started Jun 22 05:59:39 PM PDT 24
Finished Jun 22 06:01:52 PM PDT 24
Peak memory 200104 kb
Host smart-c06034e3-17c4-4016-b5ac-d7c81db11e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308003716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2308003716
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2892767699
Short name T219
Test name
Test status
Simulation time 634551103 ps
CPU time 8.08 seconds
Started Jun 22 05:59:36 PM PDT 24
Finished Jun 22 05:59:45 PM PDT 24
Peak memory 200100 kb
Host smart-9e5f41d7-ea3d-4f77-b75b-18204e1b5ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892767699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2892767699
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.4021775947
Short name T625
Test name
Test status
Simulation time 53179895 ps
CPU time 1 seconds
Started Jun 22 05:59:39 PM PDT 24
Finished Jun 22 05:59:40 PM PDT 24
Peak memory 199744 kb
Host smart-0e36072c-eca5-493b-b1d5-f73eb2c7a733
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021775947 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_hmac_vectors.4021775947
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha256_vectors.2132014768
Short name T577
Test name
Test status
Simulation time 8127651939 ps
CPU time 429.73 seconds
Started Jun 22 05:59:39 PM PDT 24
Finished Jun 22 06:06:49 PM PDT 24
Peak memory 200124 kb
Host smart-a8333355-4a26-44c3-b9cd-ca28b116a4d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2132014768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha256_vectors.2132014768
Directory /workspace/27.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha384_vectors.1750004716
Short name T373
Test name
Test status
Simulation time 122630165335 ps
CPU time 1767.35 seconds
Started Jun 22 05:59:37 PM PDT 24
Finished Jun 22 06:29:05 PM PDT 24
Peak memory 215992 kb
Host smart-805606ac-67e7-43c7-a55f-f7a1f8a46408
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1750004716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha384_vectors.1750004716
Directory /workspace/27.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha512_vectors.1917518159
Short name T534
Test name
Test status
Simulation time 109429663378 ps
CPU time 2019.19 seconds
Started Jun 22 05:59:37 PM PDT 24
Finished Jun 22 06:33:17 PM PDT 24
Peak memory 215936 kb
Host smart-c37707b6-c537-4efb-9633-27443e159e12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1917518159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha512_vectors.1917518159
Directory /workspace/27.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3387436402
Short name T21
Test name
Test status
Simulation time 3125785284 ps
CPU time 27.67 seconds
Started Jun 22 05:59:37 PM PDT 24
Finished Jun 22 06:00:05 PM PDT 24
Peak memory 200164 kb
Host smart-5a5f09dc-5271-43ac-833d-37c44f4c302f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387436402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3387436402
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2623067108
Short name T202
Test name
Test status
Simulation time 33583401 ps
CPU time 0.57 seconds
Started Jun 22 05:59:53 PM PDT 24
Finished Jun 22 05:59:54 PM PDT 24
Peak memory 194828 kb
Host smart-3aad1faf-7555-49ba-bcd9-740e962930d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623067108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2623067108
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1847324636
Short name T438
Test name
Test status
Simulation time 301980346 ps
CPU time 8.25 seconds
Started Jun 22 05:59:45 PM PDT 24
Finished Jun 22 05:59:53 PM PDT 24
Peak memory 199944 kb
Host smart-0a7ab389-2a6d-4266-b0d3-7e44b8bceaf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1847324636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1847324636
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.817653876
Short name T410
Test name
Test status
Simulation time 2030861382 ps
CPU time 33.61 seconds
Started Jun 22 05:59:42 PM PDT 24
Finished Jun 22 06:00:16 PM PDT 24
Peak memory 200056 kb
Host smart-5080f157-e993-47b0-9727-6f46f909a2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817653876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.817653876
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2122189152
Short name T87
Test name
Test status
Simulation time 3359652273 ps
CPU time 539.91 seconds
Started Jun 22 05:59:48 PM PDT 24
Finished Jun 22 06:08:48 PM PDT 24
Peak memory 506900 kb
Host smart-1a343fa5-6c14-4f99-8ae6-6986ee82d001
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2122189152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2122189152
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3387344509
Short name T602
Test name
Test status
Simulation time 3943232169 ps
CPU time 26.17 seconds
Started Jun 22 05:59:42 PM PDT 24
Finished Jun 22 06:00:08 PM PDT 24
Peak memory 200132 kb
Host smart-ca530d4b-6244-4d92-a5f4-cb3de298e999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387344509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3387344509
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.34752498
Short name T339
Test name
Test status
Simulation time 898288996 ps
CPU time 12.48 seconds
Started Jun 22 05:59:47 PM PDT 24
Finished Jun 22 06:00:00 PM PDT 24
Peak memory 200068 kb
Host smart-33ad70ac-fb2f-44bc-9ee2-fc4ff4fcb194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34752498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.34752498
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.3469389847
Short name T437
Test name
Test status
Simulation time 108062965 ps
CPU time 1.27 seconds
Started Jun 22 05:59:47 PM PDT 24
Finished Jun 22 05:59:49 PM PDT 24
Peak memory 200060 kb
Host smart-87a7be1f-c677-4854-bf04-17788ddedcec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469389847 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_hmac_vectors.3469389847
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha256_vectors.4138759129
Short name T275
Test name
Test status
Simulation time 7134011244 ps
CPU time 424.58 seconds
Started Jun 22 05:59:43 PM PDT 24
Finished Jun 22 06:06:48 PM PDT 24
Peak memory 200120 kb
Host smart-af4f9798-88de-413a-80fd-46e56542c23d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4138759129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha256_vectors.4138759129
Directory /workspace/28.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha384_vectors.2022961718
Short name T627
Test name
Test status
Simulation time 100582640144 ps
CPU time 1712.06 seconds
Started Jun 22 05:59:47 PM PDT 24
Finished Jun 22 06:28:20 PM PDT 24
Peak memory 215952 kb
Host smart-41bcb5c6-85d7-423c-9bdf-86eb7685548e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2022961718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha384_vectors.2022961718
Directory /workspace/28.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha512_vectors.3470718843
Short name T364
Test name
Test status
Simulation time 113408317032 ps
CPU time 2079.91 seconds
Started Jun 22 05:59:44 PM PDT 24
Finished Jun 22 06:34:24 PM PDT 24
Peak memory 215640 kb
Host smart-4d5516af-a566-49ab-8c64-a96cec377302
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3470718843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha512_vectors.3470718843
Directory /workspace/28.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3487813204
Short name T641
Test name
Test status
Simulation time 1240014235 ps
CPU time 23.8 seconds
Started Jun 22 05:59:45 PM PDT 24
Finished Jun 22 06:00:09 PM PDT 24
Peak memory 200056 kb
Host smart-5b593cb4-fcec-4263-95b6-c62264fd580a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487813204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3487813204
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3651317501
Short name T609
Test name
Test status
Simulation time 73057281 ps
CPU time 0.56 seconds
Started Jun 22 05:59:57 PM PDT 24
Finished Jun 22 05:59:58 PM PDT 24
Peak memory 194972 kb
Host smart-b5d478c0-66db-40ea-9990-b2f9c2c6a314
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651317501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3651317501
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3533635242
Short name T224
Test name
Test status
Simulation time 1362652763 ps
CPU time 32.65 seconds
Started Jun 22 05:59:51 PM PDT 24
Finished Jun 22 06:00:24 PM PDT 24
Peak memory 200036 kb
Host smart-3f24eefd-ccbc-46ae-8ae2-557e7c0dec27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3533635242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3533635242
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.775940170
Short name T129
Test name
Test status
Simulation time 49428591734 ps
CPU time 74.72 seconds
Started Jun 22 05:59:51 PM PDT 24
Finished Jun 22 06:01:06 PM PDT 24
Peak memory 200156 kb
Host smart-7ab8f4b5-7c10-40e5-b274-e115f1cdc1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775940170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.775940170
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1261171590
Short name T488
Test name
Test status
Simulation time 19701137794 ps
CPU time 863 seconds
Started Jun 22 05:59:52 PM PDT 24
Finished Jun 22 06:14:15 PM PDT 24
Peak memory 730924 kb
Host smart-06ab53db-e8dc-4c70-ab2e-85352c029fbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1261171590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1261171590
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2315458405
Short name T439
Test name
Test status
Simulation time 3421894741 ps
CPU time 75.35 seconds
Started Jun 22 05:59:52 PM PDT 24
Finished Jun 22 06:01:07 PM PDT 24
Peak memory 200120 kb
Host smart-9e74e5d4-4c14-4e9d-ab1b-c4ec99254bbf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315458405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2315458405
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3286645323
Short name T195
Test name
Test status
Simulation time 22086452618 ps
CPU time 123.87 seconds
Started Jun 22 05:59:54 PM PDT 24
Finished Jun 22 06:01:58 PM PDT 24
Peak memory 216532 kb
Host smart-90ebca3f-3819-4609-8333-82e8740fbc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286645323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3286645323
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.252379370
Short name T151
Test name
Test status
Simulation time 208716875 ps
CPU time 9.27 seconds
Started Jun 22 05:59:52 PM PDT 24
Finished Jun 22 06:00:02 PM PDT 24
Peak memory 200060 kb
Host smart-6f9c4cdc-3d6d-4ff4-9164-f3092a07e5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252379370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.252379370
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.3543842227
Short name T216
Test name
Test status
Simulation time 48561540 ps
CPU time 1.09 seconds
Started Jun 22 05:59:52 PM PDT 24
Finished Jun 22 05:59:54 PM PDT 24
Peak memory 200008 kb
Host smart-dac288d6-d868-4fd7-8ed1-1ee42dba474a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543842227 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_hmac_vectors.3543842227
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha256_vectors.1653326646
Short name T495
Test name
Test status
Simulation time 32728546592 ps
CPU time 460.23 seconds
Started Jun 22 05:59:50 PM PDT 24
Finished Jun 22 06:07:31 PM PDT 24
Peak memory 200088 kb
Host smart-eea77089-57d5-4bd9-b6c5-e2b50bc4a893
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1653326646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha256_vectors.1653326646
Directory /workspace/29.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha384_vectors.2492921290
Short name T184
Test name
Test status
Simulation time 114916841584 ps
CPU time 1660.93 seconds
Started Jun 22 05:59:51 PM PDT 24
Finished Jun 22 06:27:32 PM PDT 24
Peak memory 215900 kb
Host smart-39280115-7fe6-4ba3-bb6f-518b48fb367f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2492921290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha384_vectors.2492921290
Directory /workspace/29.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha512_vectors.2846898411
Short name T455
Test name
Test status
Simulation time 581460289041 ps
CPU time 2057.56 seconds
Started Jun 22 05:59:52 PM PDT 24
Finished Jun 22 06:34:11 PM PDT 24
Peak memory 216444 kb
Host smart-30e74156-8a07-4c14-b56e-5e0aeefb382d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2846898411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha512_vectors.2846898411
Directory /workspace/29.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3266458174
Short name T283
Test name
Test status
Simulation time 233868423 ps
CPU time 3.7 seconds
Started Jun 22 05:59:52 PM PDT 24
Finished Jun 22 05:59:57 PM PDT 24
Peak memory 200108 kb
Host smart-d238d049-aab4-44c0-b06a-7a8b43951730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266458174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3266458174
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.4080006157
Short name T504
Test name
Test status
Simulation time 23194085 ps
CPU time 0.59 seconds
Started Jun 22 05:56:41 PM PDT 24
Finished Jun 22 05:56:42 PM PDT 24
Peak memory 196008 kb
Host smart-e444339a-c0df-458b-b6d2-5653276fc979
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080006157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.4080006157
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.978029609
Short name T371
Test name
Test status
Simulation time 99641416 ps
CPU time 1.68 seconds
Started Jun 22 05:56:36 PM PDT 24
Finished Jun 22 05:56:38 PM PDT 24
Peak memory 199960 kb
Host smart-b11a568c-b3cc-4974-bfe2-11342dee5fa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=978029609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.978029609
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.988373912
Short name T269
Test name
Test status
Simulation time 2435506618 ps
CPU time 43.17 seconds
Started Jun 22 05:56:44 PM PDT 24
Finished Jun 22 05:57:28 PM PDT 24
Peak memory 200012 kb
Host smart-90646bac-c843-4740-aba8-852bfdf3fbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988373912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.988373912
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1964367711
Short name T30
Test name
Test status
Simulation time 19376083 ps
CPU time 0.68 seconds
Started Jun 22 05:56:35 PM PDT 24
Finished Jun 22 05:56:36 PM PDT 24
Peak memory 199288 kb
Host smart-177e6e78-d523-4159-a65d-07f51d784fa7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1964367711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1964367711
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1379219278
Short name T205
Test name
Test status
Simulation time 566090197 ps
CPU time 6.61 seconds
Started Jun 22 05:56:42 PM PDT 24
Finished Jun 22 05:56:49 PM PDT 24
Peak memory 200020 kb
Host smart-1661fd9e-02ea-45cf-b357-16b341519ed3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379219278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1379219278
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3995392329
Short name T196
Test name
Test status
Simulation time 11026007300 ps
CPU time 54.21 seconds
Started Jun 22 05:56:36 PM PDT 24
Finished Jun 22 05:57:30 PM PDT 24
Peak memory 200112 kb
Host smart-d3249c82-e28a-4bcc-82ba-0162998f9c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995392329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3995392329
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.267403286
Short name T50
Test name
Test status
Simulation time 106872951 ps
CPU time 0.86 seconds
Started Jun 22 05:56:46 PM PDT 24
Finished Jun 22 05:56:47 PM PDT 24
Peak memory 218164 kb
Host smart-5ec84cc6-0be6-4191-8c09-6d3f6b0ec045
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267403286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.267403286
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1083013099
Short name T657
Test name
Test status
Simulation time 739817501 ps
CPU time 8.29 seconds
Started Jun 22 05:56:35 PM PDT 24
Finished Jun 22 05:56:44 PM PDT 24
Peak memory 200104 kb
Host smart-f40fd9e6-fb47-484f-b7f5-79b95f9b1077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083013099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1083013099
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.3874874963
Short name T321
Test name
Test status
Simulation time 51567095 ps
CPU time 1.17 seconds
Started Jun 22 05:56:42 PM PDT 24
Finished Jun 22 05:56:44 PM PDT 24
Peak memory 199764 kb
Host smart-a92825e2-a655-47ef-857c-c27b65c479f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874874963 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac_vectors.3874874963
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.3371333646
Short name T234
Test name
Test status
Simulation time 157235613335 ps
CPU time 487.57 seconds
Started Jun 22 05:56:42 PM PDT 24
Finished Jun 22 06:04:50 PM PDT 24
Peak memory 200144 kb
Host smart-2bc7a4cc-f6d2-4275-83a4-619254cd0540
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3371333646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.3371333646
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.4157854323
Short name T592
Test name
Test status
Simulation time 30503817124 ps
CPU time 1712.87 seconds
Started Jun 22 05:56:45 PM PDT 24
Finished Jun 22 06:25:18 PM PDT 24
Peak memory 216056 kb
Host smart-df6b3b6d-ad76-48ec-9b03-6500743e6ec2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4157854323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.4157854323
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.1281969358
Short name T644
Test name
Test status
Simulation time 519857439901 ps
CPU time 1865.93 seconds
Started Jun 22 05:56:43 PM PDT 24
Finished Jun 22 06:27:50 PM PDT 24
Peak memory 215580 kb
Host smart-e0685365-3835-4eed-9f27-5f7ae4025ed2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1281969358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.1281969358
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.416203229
Short name T474
Test name
Test status
Simulation time 1322517941 ps
CPU time 49.47 seconds
Started Jun 22 05:56:44 PM PDT 24
Finished Jun 22 05:57:33 PM PDT 24
Peak memory 200024 kb
Host smart-5d2f49ba-1a6c-4315-a847-30cf73d8ef27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416203229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.416203229
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1195530650
Short name T211
Test name
Test status
Simulation time 45727906 ps
CPU time 0.64 seconds
Started Jun 22 06:00:00 PM PDT 24
Finished Jun 22 06:00:01 PM PDT 24
Peak memory 195724 kb
Host smart-9b2dce2a-4dd3-4bec-8ada-6a36fe46d586
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195530650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1195530650
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1057243985
Short name T604
Test name
Test status
Simulation time 879395719 ps
CPU time 39.61 seconds
Started Jun 22 05:59:57 PM PDT 24
Finished Jun 22 06:00:37 PM PDT 24
Peak memory 200064 kb
Host smart-63b11610-4bbe-468e-a9d7-8694213b148d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1057243985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1057243985
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1788856353
Short name T91
Test name
Test status
Simulation time 4583799813 ps
CPU time 33.75 seconds
Started Jun 22 06:00:03 PM PDT 24
Finished Jun 22 06:00:37 PM PDT 24
Peak memory 200008 kb
Host smart-7439c6a4-ea61-4a13-83b2-09f3b2ee7b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788856353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1788856353
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3688148523
Short name T268
Test name
Test status
Simulation time 2904104366 ps
CPU time 718.63 seconds
Started Jun 22 05:59:57 PM PDT 24
Finished Jun 22 06:11:56 PM PDT 24
Peak memory 659280 kb
Host smart-25fcce56-6df8-41d6-b6a5-8c9b5c6f3785
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3688148523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3688148523
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.226165930
Short name T134
Test name
Test status
Simulation time 1518193614 ps
CPU time 83.28 seconds
Started Jun 22 05:59:59 PM PDT 24
Finished Jun 22 06:01:23 PM PDT 24
Peak memory 200052 kb
Host smart-85cbd46d-d8d4-411a-9975-d4bc27075959
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226165930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.226165930
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3247992982
Short name T308
Test name
Test status
Simulation time 15455568029 ps
CPU time 83.39 seconds
Started Jun 22 06:00:02 PM PDT 24
Finished Jun 22 06:01:26 PM PDT 24
Peak memory 200152 kb
Host smart-0bd04670-2108-4f84-9437-fb5607f479a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247992982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3247992982
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2165759838
Short name T332
Test name
Test status
Simulation time 233414182 ps
CPU time 5.62 seconds
Started Jun 22 05:59:59 PM PDT 24
Finished Jun 22 06:00:05 PM PDT 24
Peak memory 200072 kb
Host smart-a7dc4400-71e7-4c58-a733-707658ee5b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165759838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2165759838
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.3394289629
Short name T516
Test name
Test status
Simulation time 32058789 ps
CPU time 1.06 seconds
Started Jun 22 05:59:59 PM PDT 24
Finished Jun 22 06:00:00 PM PDT 24
Peak memory 199988 kb
Host smart-f4becbab-bfe2-4af2-bc10-152cb6bab1cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394289629 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_hmac_vectors.3394289629
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha256_vectors.3602255450
Short name T15
Test name
Test status
Simulation time 8032305815 ps
CPU time 439.64 seconds
Started Jun 22 05:59:59 PM PDT 24
Finished Jun 22 06:07:19 PM PDT 24
Peak memory 200120 kb
Host smart-99ac277a-c9dd-410a-b3fc-2fec05a52fc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3602255450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha256_vectors.3602255450
Directory /workspace/30.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha384_vectors.1053407653
Short name T200
Test name
Test status
Simulation time 415238008704 ps
CPU time 1879.56 seconds
Started Jun 22 05:59:59 PM PDT 24
Finished Jun 22 06:31:19 PM PDT 24
Peak memory 216456 kb
Host smart-6354bd9e-0e1d-4474-91e9-9abb7e086dfd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1053407653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha384_vectors.1053407653
Directory /workspace/30.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha512_vectors.2489527655
Short name T291
Test name
Test status
Simulation time 626394229465 ps
CPU time 1919.81 seconds
Started Jun 22 05:59:58 PM PDT 24
Finished Jun 22 06:31:58 PM PDT 24
Peak memory 215576 kb
Host smart-2c9530e8-f563-475e-9a39-aaa6aa340b0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2489527655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha512_vectors.2489527655
Directory /workspace/30.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.1652608977
Short name T117
Test name
Test status
Simulation time 1553568183 ps
CPU time 73.56 seconds
Started Jun 22 05:59:59 PM PDT 24
Finished Jun 22 06:01:13 PM PDT 24
Peak memory 200028 kb
Host smart-2212e0ba-ff64-451f-b17a-e7876f0ad94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652608977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1652608977
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1207773082
Short name T357
Test name
Test status
Simulation time 41892210 ps
CPU time 0.56 seconds
Started Jun 22 06:00:13 PM PDT 24
Finished Jun 22 06:00:14 PM PDT 24
Peak memory 194972 kb
Host smart-2434c85c-71da-49f4-b248-a83927ecec7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207773082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1207773082
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.973359665
Short name T632
Test name
Test status
Simulation time 2896172907 ps
CPU time 36.43 seconds
Started Jun 22 06:00:06 PM PDT 24
Finished Jun 22 06:00:43 PM PDT 24
Peak memory 200124 kb
Host smart-7d839feb-24e6-45a8-9c8e-accb06ba272e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=973359665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.973359665
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3417433882
Short name T345
Test name
Test status
Simulation time 3577673879 ps
CPU time 50.82 seconds
Started Jun 22 06:00:08 PM PDT 24
Finished Jun 22 06:00:59 PM PDT 24
Peak memory 200168 kb
Host smart-84762b6f-0c8c-434d-82e3-e8b2a42cf0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417433882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3417433882
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2951557229
Short name T433
Test name
Test status
Simulation time 7216219493 ps
CPU time 1102.1 seconds
Started Jun 22 06:00:05 PM PDT 24
Finished Jun 22 06:18:28 PM PDT 24
Peak memory 785468 kb
Host smart-00ccc665-755a-4426-b60d-d7550c42d451
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2951557229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2951557229
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1181495819
Short name T369
Test name
Test status
Simulation time 5844591678 ps
CPU time 100.92 seconds
Started Jun 22 06:00:12 PM PDT 24
Finished Jun 22 06:01:53 PM PDT 24
Peak memory 200140 kb
Host smart-4d3d5a57-bc89-4ca4-a5b3-8566af726e5b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181495819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1181495819
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1625299705
Short name T325
Test name
Test status
Simulation time 5215960526 ps
CPU time 53.18 seconds
Started Jun 22 06:00:07 PM PDT 24
Finished Jun 22 06:01:00 PM PDT 24
Peak memory 200136 kb
Host smart-55b5b670-7a31-4b5a-8f23-8546f385bb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625299705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1625299705
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1884260093
Short name T4
Test name
Test status
Simulation time 58900730 ps
CPU time 1.45 seconds
Started Jun 22 05:59:59 PM PDT 24
Finished Jun 22 06:00:01 PM PDT 24
Peak memory 199992 kb
Host smart-4b0b0521-cad5-4243-bb07-236e07137fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884260093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1884260093
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.2913215304
Short name T157
Test name
Test status
Simulation time 147401139 ps
CPU time 1.36 seconds
Started Jun 22 06:00:05 PM PDT 24
Finished Jun 22 06:00:07 PM PDT 24
Peak memory 200000 kb
Host smart-e46538c1-912c-4205-b37f-5af9ba4b5baf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913215304 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_hmac_vectors.2913215304
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha256_vectors.1217510485
Short name T444
Test name
Test status
Simulation time 31618405479 ps
CPU time 530.31 seconds
Started Jun 22 06:00:05 PM PDT 24
Finished Jun 22 06:08:56 PM PDT 24
Peak memory 200124 kb
Host smart-2f1dd157-7209-4dba-8647-df179fc08d43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1217510485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha256_vectors.1217510485
Directory /workspace/31.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha384_vectors.507745758
Short name T377
Test name
Test status
Simulation time 148759943215 ps
CPU time 1825.97 seconds
Started Jun 22 06:00:05 PM PDT 24
Finished Jun 22 06:30:32 PM PDT 24
Peak memory 216128 kb
Host smart-9784783e-5d96-4b80-8e03-40ba8da85277
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=507745758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha384_vectors.507745758
Directory /workspace/31.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha512_vectors.3085274081
Short name T535
Test name
Test status
Simulation time 591804023941 ps
CPU time 1881.45 seconds
Started Jun 22 06:00:07 PM PDT 24
Finished Jun 22 06:31:29 PM PDT 24
Peak memory 215452 kb
Host smart-14d94c28-0a1e-4f9e-9024-686dd1974982
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3085274081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha512_vectors.3085274081
Directory /workspace/31.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.4265628634
Short name T97
Test name
Test status
Simulation time 8624385762 ps
CPU time 41.18 seconds
Started Jun 22 06:00:08 PM PDT 24
Finished Jun 22 06:00:49 PM PDT 24
Peak memory 200140 kb
Host smart-a99ac9b7-6897-42c1-97e1-dae451caf668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265628634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.4265628634
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.936982741
Short name T356
Test name
Test status
Simulation time 19020939 ps
CPU time 0.59 seconds
Started Jun 22 06:00:21 PM PDT 24
Finished Jun 22 06:00:22 PM PDT 24
Peak memory 194972 kb
Host smart-18905dbe-868a-4cac-8f94-c207ba47f873
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936982741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.936982741
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3724986453
Short name T27
Test name
Test status
Simulation time 83449474 ps
CPU time 4.51 seconds
Started Jun 22 06:00:13 PM PDT 24
Finished Jun 22 06:00:18 PM PDT 24
Peak memory 200052 kb
Host smart-6b19d989-2013-49bd-927a-a9f2f032c23b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3724986453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3724986453
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.270757076
Short name T204
Test name
Test status
Simulation time 14476531828 ps
CPU time 39.18 seconds
Started Jun 22 06:00:14 PM PDT 24
Finished Jun 22 06:00:54 PM PDT 24
Peak memory 200128 kb
Host smart-6bca3839-4feb-4a68-bd76-68324859b6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270757076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.270757076
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2419041917
Short name T441
Test name
Test status
Simulation time 5864255273 ps
CPU time 305.09 seconds
Started Jun 22 06:00:13 PM PDT 24
Finished Jun 22 06:05:19 PM PDT 24
Peak memory 492420 kb
Host smart-e580c88b-0509-415d-b327-60c56cad3175
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2419041917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2419041917
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.113346006
Short name T274
Test name
Test status
Simulation time 7753298858 ps
CPU time 66.82 seconds
Started Jun 22 06:00:13 PM PDT 24
Finished Jun 22 06:01:20 PM PDT 24
Peak memory 200112 kb
Host smart-7ce749ed-3d2e-437f-aac6-ef39bab8cd68
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113346006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.113346006
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3414112706
Short name T264
Test name
Test status
Simulation time 9396744465 ps
CPU time 133.79 seconds
Started Jun 22 06:00:14 PM PDT 24
Finished Jun 22 06:02:28 PM PDT 24
Peak memory 200140 kb
Host smart-3088e687-1d6d-48d2-9a8e-00be1b40ce8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414112706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3414112706
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1724966728
Short name T316
Test name
Test status
Simulation time 2537663686 ps
CPU time 18.72 seconds
Started Jun 22 06:00:15 PM PDT 24
Finished Jun 22 06:00:34 PM PDT 24
Peak memory 200104 kb
Host smart-10baec1e-7f6c-4b2f-b720-125ed6503a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724966728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1724966728
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.3935385417
Short name T217
Test name
Test status
Simulation time 230813508 ps
CPU time 1.35 seconds
Started Jun 22 06:00:13 PM PDT 24
Finished Jun 22 06:00:15 PM PDT 24
Peak memory 200036 kb
Host smart-40790ec9-6a90-4785-9cd7-0a53ab76112a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935385417 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_hmac_vectors.3935385417
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha256_vectors.1850484935
Short name T351
Test name
Test status
Simulation time 436949685254 ps
CPU time 477.9 seconds
Started Jun 22 06:00:13 PM PDT 24
Finished Jun 22 06:08:11 PM PDT 24
Peak memory 200152 kb
Host smart-f2d436be-fe71-4626-843d-251cb8ff8de8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1850484935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha256_vectors.1850484935
Directory /workspace/32.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha384_vectors.3077047118
Short name T241
Test name
Test status
Simulation time 492634597219 ps
CPU time 1784.83 seconds
Started Jun 22 06:00:12 PM PDT 24
Finished Jun 22 06:29:57 PM PDT 24
Peak memory 216144 kb
Host smart-4164bd66-5b6a-4d11-87bd-6901a44d85aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3077047118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha384_vectors.3077047118
Directory /workspace/32.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha512_vectors.1931218949
Short name T566
Test name
Test status
Simulation time 32304682344 ps
CPU time 1787.36 seconds
Started Jun 22 06:00:11 PM PDT 24
Finished Jun 22 06:29:58 PM PDT 24
Peak memory 216196 kb
Host smart-c9d9d36c-5621-4a62-af43-86336396f1ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1931218949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha512_vectors.1931218949
Directory /workspace/32.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1695967822
Short name T280
Test name
Test status
Simulation time 635320178 ps
CPU time 29.63 seconds
Started Jun 22 06:00:13 PM PDT 24
Finished Jun 22 06:00:43 PM PDT 24
Peak memory 200104 kb
Host smart-837ac0a1-0606-40da-a7ad-5e71ebb3fd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695967822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1695967822
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.561502068
Short name T552
Test name
Test status
Simulation time 12962904 ps
CPU time 0.59 seconds
Started Jun 22 06:00:21 PM PDT 24
Finished Jun 22 06:00:22 PM PDT 24
Peak memory 196132 kb
Host smart-7afa2a2b-e699-4c80-97b0-10c3a978dfe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561502068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.561502068
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.1360960090
Short name T286
Test name
Test status
Simulation time 9845508133 ps
CPU time 59.97 seconds
Started Jun 22 06:00:19 PM PDT 24
Finished Jun 22 06:01:19 PM PDT 24
Peak memory 208324 kb
Host smart-2838ba85-e457-4682-820e-d0c8b04ec4d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1360960090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1360960090
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.289709321
Short name T650
Test name
Test status
Simulation time 1683800122 ps
CPU time 22.91 seconds
Started Jun 22 06:00:20 PM PDT 24
Finished Jun 22 06:00:43 PM PDT 24
Peak memory 200076 kb
Host smart-78849d9f-4b5f-4ad0-b536-f2537eff83d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289709321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.289709321
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.326664240
Short name T179
Test name
Test status
Simulation time 21313144 ps
CPU time 1.04 seconds
Started Jun 22 06:00:19 PM PDT 24
Finished Jun 22 06:00:20 PM PDT 24
Peak memory 199920 kb
Host smart-6823a15a-b6e3-4634-be62-1b038c8be252
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=326664240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.326664240
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2052323384
Short name T427
Test name
Test status
Simulation time 40377006873 ps
CPU time 172.15 seconds
Started Jun 22 06:00:21 PM PDT 24
Finished Jun 22 06:03:14 PM PDT 24
Peak memory 200108 kb
Host smart-b53bb992-d851-4ee4-a0fa-84e65aedf4c5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052323384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2052323384
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1404797900
Short name T315
Test name
Test status
Simulation time 2462375735 ps
CPU time 16.98 seconds
Started Jun 22 06:00:22 PM PDT 24
Finished Jun 22 06:00:40 PM PDT 24
Peak memory 200040 kb
Host smart-7ecc67d1-df27-4618-8694-4f8afb676e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404797900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1404797900
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3678220101
Short name T187
Test name
Test status
Simulation time 457387211 ps
CPU time 8.76 seconds
Started Jun 22 06:00:20 PM PDT 24
Finished Jun 22 06:00:29 PM PDT 24
Peak memory 200084 kb
Host smart-d761d5d4-a598-436d-8800-56a6949811aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678220101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3678220101
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2085496601
Short name T70
Test name
Test status
Simulation time 31789572198 ps
CPU time 377.17 seconds
Started Jun 22 06:00:22 PM PDT 24
Finished Jun 22 06:06:39 PM PDT 24
Peak memory 200624 kb
Host smart-1bf5978d-fca7-4d94-92fe-4328f81e2108
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085496601 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2085496601
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.1170366965
Short name T170
Test name
Test status
Simulation time 294920605 ps
CPU time 1.45 seconds
Started Jun 22 06:00:26 PM PDT 24
Finished Jun 22 06:00:27 PM PDT 24
Peak memory 200092 kb
Host smart-a8f0856a-24f7-4b06-9897-b6476b129abc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170366965 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_hmac_vectors.1170366965
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha256_vectors.1044587730
Short name T183
Test name
Test status
Simulation time 30761345920 ps
CPU time 561.01 seconds
Started Jun 22 06:00:20 PM PDT 24
Finished Jun 22 06:09:41 PM PDT 24
Peak memory 200092 kb
Host smart-b9219026-48b6-4bcd-95d1-b457a5956190
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1044587730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha256_vectors.1044587730
Directory /workspace/33.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha384_vectors.1863692453
Short name T341
Test name
Test status
Simulation time 169604646241 ps
CPU time 2085.17 seconds
Started Jun 22 06:00:19 PM PDT 24
Finished Jun 22 06:35:05 PM PDT 24
Peak memory 216144 kb
Host smart-860313d2-1580-4c80-83dd-c9a875fa5d65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1863692453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha384_vectors.1863692453
Directory /workspace/33.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha512_vectors.2425596107
Short name T54
Test name
Test status
Simulation time 55049376737 ps
CPU time 1619.36 seconds
Started Jun 22 06:00:21 PM PDT 24
Finished Jun 22 06:27:21 PM PDT 24
Peak memory 215608 kb
Host smart-b9dc2933-079c-4302-a8a5-fb615897314a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2425596107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha512_vectors.2425596107
Directory /workspace/33.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3135073435
Short name T380
Test name
Test status
Simulation time 4428117244 ps
CPU time 16.91 seconds
Started Jun 22 06:00:26 PM PDT 24
Finished Jun 22 06:00:43 PM PDT 24
Peak memory 200112 kb
Host smart-b632b033-261d-4729-9896-c3ba357193b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135073435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3135073435
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1560734808
Short name T428
Test name
Test status
Simulation time 47398516 ps
CPU time 0.61 seconds
Started Jun 22 06:00:29 PM PDT 24
Finished Jun 22 06:00:30 PM PDT 24
Peak memory 196068 kb
Host smart-9ec564cc-6da2-47bf-b49c-a05613c18dbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560734808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1560734808
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1469919449
Short name T532
Test name
Test status
Simulation time 216632973 ps
CPU time 2.96 seconds
Started Jun 22 06:00:31 PM PDT 24
Finished Jun 22 06:00:34 PM PDT 24
Peak memory 200052 kb
Host smart-a425ca1e-0ca2-4f37-8fe7-15236ee0d1d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1469919449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1469919449
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2074964157
Short name T131
Test name
Test status
Simulation time 3575060176 ps
CPU time 53.77 seconds
Started Jun 22 06:00:29 PM PDT 24
Finished Jun 22 06:01:24 PM PDT 24
Peak memory 200060 kb
Host smart-4354c770-5fef-459c-b41c-7c118cf23504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074964157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2074964157
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.2742524297
Short name T584
Test name
Test status
Simulation time 11906912061 ps
CPU time 835.32 seconds
Started Jun 22 06:00:30 PM PDT 24
Finished Jun 22 06:14:26 PM PDT 24
Peak memory 752428 kb
Host smart-3c0bc8b8-bfe3-44bb-b606-080bd1ee3c22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2742524297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2742524297
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3058102138
Short name T614
Test name
Test status
Simulation time 10690515803 ps
CPU time 95.67 seconds
Started Jun 22 06:00:30 PM PDT 24
Finished Jun 22 06:02:06 PM PDT 24
Peak memory 200108 kb
Host smart-fc82ce3f-c0bf-4aea-8583-e461a3209d03
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058102138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3058102138
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1942275372
Short name T312
Test name
Test status
Simulation time 2446157425 ps
CPU time 37.58 seconds
Started Jun 22 06:00:30 PM PDT 24
Finished Jun 22 06:01:08 PM PDT 24
Peak memory 200136 kb
Host smart-5ae69a53-7218-4517-a4bc-d05cb1651bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942275372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1942275372
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.10884499
Short name T640
Test name
Test status
Simulation time 65176015 ps
CPU time 1.33 seconds
Started Jun 22 06:00:20 PM PDT 24
Finished Jun 22 06:00:22 PM PDT 24
Peak memory 196396 kb
Host smart-2a330e42-75e0-4565-8e47-92e8b2c4912c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10884499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.10884499
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.3718472549
Short name T490
Test name
Test status
Simulation time 62481828 ps
CPU time 1.16 seconds
Started Jun 22 06:00:30 PM PDT 24
Finished Jun 22 06:00:32 PM PDT 24
Peak memory 199808 kb
Host smart-450c6f1b-2435-4fb9-a42f-942796866156
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718472549 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_hmac_vectors.3718472549
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha256_vectors.1525233037
Short name T522
Test name
Test status
Simulation time 311260193927 ps
CPU time 543.27 seconds
Started Jun 22 06:00:28 PM PDT 24
Finished Jun 22 06:09:31 PM PDT 24
Peak memory 200380 kb
Host smart-a6cf6316-2335-4ac3-8924-c0b4e81f614d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1525233037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha256_vectors.1525233037
Directory /workspace/34.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha512_vectors.1442571451
Short name T463
Test name
Test status
Simulation time 677019789963 ps
CPU time 1975.9 seconds
Started Jun 22 06:00:26 PM PDT 24
Finished Jun 22 06:33:23 PM PDT 24
Peak memory 216516 kb
Host smart-a0868465-1308-4800-9436-865fb48a1d07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1442571451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha512_vectors.1442571451
Directory /workspace/34.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1344914159
Short name T327
Test name
Test status
Simulation time 8451627234 ps
CPU time 67.71 seconds
Started Jun 22 06:00:28 PM PDT 24
Finished Jun 22 06:01:36 PM PDT 24
Peak memory 200168 kb
Host smart-6288af7c-f3b7-4707-a6c8-a488959c8e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344914159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1344914159
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3764525110
Short name T89
Test name
Test status
Simulation time 50966548 ps
CPU time 0.59 seconds
Started Jun 22 06:00:42 PM PDT 24
Finished Jun 22 06:00:43 PM PDT 24
Peak memory 195708 kb
Host smart-71009231-1f44-47bf-97fd-894769aa1c20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764525110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3764525110
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1375306687
Short name T388
Test name
Test status
Simulation time 1806798835 ps
CPU time 49.39 seconds
Started Jun 22 06:00:35 PM PDT 24
Finished Jun 22 06:01:25 PM PDT 24
Peak memory 200072 kb
Host smart-5f4304ef-f153-4725-9fd7-dad2e1e63047
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1375306687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1375306687
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2240010363
Short name T606
Test name
Test status
Simulation time 1274107528 ps
CPU time 71.37 seconds
Started Jun 22 06:00:43 PM PDT 24
Finished Jun 22 06:01:55 PM PDT 24
Peak memory 200116 kb
Host smart-fff08f4a-0550-44aa-bf69-a0bda540a541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240010363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2240010363
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2912630525
Short name T407
Test name
Test status
Simulation time 718933430 ps
CPU time 129.28 seconds
Started Jun 22 06:00:43 PM PDT 24
Finished Jun 22 06:02:53 PM PDT 24
Peak memory 591148 kb
Host smart-ea400529-a2da-4c5c-84f6-fe4a55942b06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2912630525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2912630525
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.373285256
Short name T331
Test name
Test status
Simulation time 9503664941 ps
CPU time 40.74 seconds
Started Jun 22 06:00:39 PM PDT 24
Finished Jun 22 06:01:20 PM PDT 24
Peak memory 200136 kb
Host smart-52a73cf1-24de-4ddd-9232-23180c989004
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373285256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.373285256
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3232948748
Short name T298
Test name
Test status
Simulation time 3479129416 ps
CPU time 53.35 seconds
Started Jun 22 06:00:43 PM PDT 24
Finished Jun 22 06:01:37 PM PDT 24
Peak memory 200132 kb
Host smart-b81b05ec-8bef-4684-9ee2-2c21bde8e0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232948748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3232948748
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2546571432
Short name T310
Test name
Test status
Simulation time 1033451974 ps
CPU time 5.99 seconds
Started Jun 22 06:00:44 PM PDT 24
Finished Jun 22 06:00:50 PM PDT 24
Peak memory 200072 kb
Host smart-881de9d3-97ac-485a-a22f-338c6ef812e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546571432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2546571432
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.396252340
Short name T571
Test name
Test status
Simulation time 73189306 ps
CPU time 1.47 seconds
Started Jun 22 06:00:39 PM PDT 24
Finished Jun 22 06:00:41 PM PDT 24
Peak memory 199992 kb
Host smart-b88e2e52-cea8-45f5-ba35-bebab200e1b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396252340 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_hmac_vectors.396252340
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha256_vectors.2436925798
Short name T556
Test name
Test status
Simulation time 7610142327 ps
CPU time 434.67 seconds
Started Jun 22 06:00:37 PM PDT 24
Finished Jun 22 06:07:52 PM PDT 24
Peak memory 200124 kb
Host smart-52e5511f-9a8a-403f-9fe5-5deb0a054b99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2436925798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha256_vectors.2436925798
Directory /workspace/35.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha384_vectors.1276899153
Short name T631
Test name
Test status
Simulation time 638479539801 ps
CPU time 2107.83 seconds
Started Jun 22 06:00:44 PM PDT 24
Finished Jun 22 06:35:52 PM PDT 24
Peak memory 215476 kb
Host smart-d60f8b86-bf8d-4143-9619-dc451907571b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1276899153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha384_vectors.1276899153
Directory /workspace/35.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha512_vectors.3628764198
Short name T418
Test name
Test status
Simulation time 159907479101 ps
CPU time 2083.12 seconds
Started Jun 22 06:00:34 PM PDT 24
Finished Jun 22 06:35:18 PM PDT 24
Peak memory 215588 kb
Host smart-96131372-c297-456b-8fec-6a950a8bd6fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3628764198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha512_vectors.3628764198
Directory /workspace/35.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.733917257
Short name T459
Test name
Test status
Simulation time 2048072673 ps
CPU time 36.6 seconds
Started Jun 22 06:00:40 PM PDT 24
Finished Jun 22 06:01:17 PM PDT 24
Peak memory 200060 kb
Host smart-9ab17184-544d-4de6-a21d-f649e75ebe40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733917257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.733917257
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.458990507
Short name T186
Test name
Test status
Simulation time 44221568 ps
CPU time 0.64 seconds
Started Jun 22 06:00:45 PM PDT 24
Finished Jun 22 06:00:46 PM PDT 24
Peak memory 196744 kb
Host smart-2317d23c-9c25-40f9-b247-919f393145de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458990507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.458990507
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2400255518
Short name T443
Test name
Test status
Simulation time 3941405714 ps
CPU time 19.68 seconds
Started Jun 22 06:00:49 PM PDT 24
Finished Jun 22 06:01:09 PM PDT 24
Peak memory 200016 kb
Host smart-6597d02c-a882-4555-8ead-1e52453c055c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400255518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2400255518
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1910525490
Short name T395
Test name
Test status
Simulation time 859575662 ps
CPU time 229.73 seconds
Started Jun 22 06:00:42 PM PDT 24
Finished Jun 22 06:04:32 PM PDT 24
Peak memory 648352 kb
Host smart-e029e48f-603e-46e2-8afa-e0cbbb821533
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1910525490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1910525490
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2516618387
Short name T621
Test name
Test status
Simulation time 8899055588 ps
CPU time 116.59 seconds
Started Jun 22 06:00:42 PM PDT 24
Finished Jun 22 06:02:39 PM PDT 24
Peak memory 200080 kb
Host smart-c957fd75-ec62-415f-a702-79a4fca5bf9a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516618387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2516618387
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2822082980
Short name T221
Test name
Test status
Simulation time 2092572321 ps
CPU time 40.2 seconds
Started Jun 22 06:00:42 PM PDT 24
Finished Jun 22 06:01:22 PM PDT 24
Peak memory 200084 kb
Host smart-f314566f-35fc-4624-bb70-64b98eb04e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822082980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2822082980
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2078065111
Short name T518
Test name
Test status
Simulation time 258736775 ps
CPU time 3.75 seconds
Started Jun 22 06:00:34 PM PDT 24
Finished Jun 22 06:00:38 PM PDT 24
Peak memory 200072 kb
Host smart-9876f93e-ab3f-46e4-bcc0-749f74fd8796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078065111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2078065111
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.1637766031
Short name T311
Test name
Test status
Simulation time 43223775 ps
CPU time 1.04 seconds
Started Jun 22 06:00:49 PM PDT 24
Finished Jun 22 06:00:50 PM PDT 24
Peak memory 199720 kb
Host smart-491b07b6-7926-4ab4-a7f3-7225b2394859
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637766031 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_hmac_vectors.1637766031
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha256_vectors.2775099657
Short name T613
Test name
Test status
Simulation time 29660953004 ps
CPU time 528.54 seconds
Started Jun 22 06:00:46 PM PDT 24
Finished Jun 22 06:09:35 PM PDT 24
Peak memory 200144 kb
Host smart-b97aa670-4bbb-4eb8-8203-63686fc2b4fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2775099657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha256_vectors.2775099657
Directory /workspace/36.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha384_vectors.2976819758
Short name T349
Test name
Test status
Simulation time 421311217093 ps
CPU time 1920.38 seconds
Started Jun 22 06:00:42 PM PDT 24
Finished Jun 22 06:32:43 PM PDT 24
Peak memory 215644 kb
Host smart-d70ce17d-ea34-456b-a552-6fe0293fe900
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2976819758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha384_vectors.2976819758
Directory /workspace/36.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha512_vectors.3857288808
Short name T512
Test name
Test status
Simulation time 170275328764 ps
CPU time 1854.75 seconds
Started Jun 22 06:00:48 PM PDT 24
Finished Jun 22 06:31:43 PM PDT 24
Peak memory 216196 kb
Host smart-0b301e54-c916-4474-b23b-a3b26742bedd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3857288808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha512_vectors.3857288808
Directory /workspace/36.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/37.hmac_alert_test.668504264
Short name T292
Test name
Test status
Simulation time 40720414 ps
CPU time 0.6 seconds
Started Jun 22 06:00:49 PM PDT 24
Finished Jun 22 06:00:50 PM PDT 24
Peak memory 196064 kb
Host smart-6569423d-2444-4108-b9d6-d1ef36bc0554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668504264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.668504264
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1098900385
Short name T636
Test name
Test status
Simulation time 3359685837 ps
CPU time 40.58 seconds
Started Jun 22 06:00:49 PM PDT 24
Finished Jun 22 06:01:30 PM PDT 24
Peak memory 200032 kb
Host smart-0d56d8c2-1015-4f3b-9a52-59d55557c8d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1098900385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1098900385
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.4172644915
Short name T469
Test name
Test status
Simulation time 285902413 ps
CPU time 1.78 seconds
Started Jun 22 06:00:41 PM PDT 24
Finished Jun 22 06:00:43 PM PDT 24
Peak memory 200060 kb
Host smart-f98e0f44-63d5-4174-b628-e89382e6fd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172644915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.4172644915
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2824665099
Short name T368
Test name
Test status
Simulation time 1433774988 ps
CPU time 57.92 seconds
Started Jun 22 06:00:48 PM PDT 24
Finished Jun 22 06:01:47 PM PDT 24
Peak memory 328804 kb
Host smart-9ef31bb9-950c-4e80-a233-121a187ce4f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2824665099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2824665099
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3376911305
Short name T505
Test name
Test status
Simulation time 757138942 ps
CPU time 4.16 seconds
Started Jun 22 06:00:49 PM PDT 24
Finished Jun 22 06:00:54 PM PDT 24
Peak memory 199988 kb
Host smart-80509258-b6b3-4a8a-af37-4773db5236a9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376911305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3376911305
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3834964214
Short name T565
Test name
Test status
Simulation time 30663532516 ps
CPU time 112.39 seconds
Started Jun 22 06:00:42 PM PDT 24
Finished Jun 22 06:02:35 PM PDT 24
Peak memory 200352 kb
Host smart-79fcde67-5e4c-409e-9f35-7fffb7520037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834964214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3834964214
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1913465584
Short name T55
Test name
Test status
Simulation time 446048993 ps
CPU time 9.1 seconds
Started Jun 22 06:00:44 PM PDT 24
Finished Jun 22 06:00:53 PM PDT 24
Peak memory 200072 kb
Host smart-4b674fe9-9b3b-4938-a378-12cb29fb5594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913465584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1913465584
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.176523637
Short name T228
Test name
Test status
Simulation time 148868507 ps
CPU time 1.14 seconds
Started Jun 22 06:00:48 PM PDT 24
Finished Jun 22 06:00:49 PM PDT 24
Peak memory 200084 kb
Host smart-a7795d70-19ed-459f-aacd-49154d038df8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176523637 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_hmac_vectors.176523637
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha256_vectors.4059700909
Short name T628
Test name
Test status
Simulation time 289921584363 ps
CPU time 465.97 seconds
Started Jun 22 06:00:49 PM PDT 24
Finished Jun 22 06:08:35 PM PDT 24
Peak memory 200124 kb
Host smart-2bab6c2d-a0b6-4a94-981a-227f95b584c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4059700909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha256_vectors.4059700909
Directory /workspace/37.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha384_vectors.173852301
Short name T656
Test name
Test status
Simulation time 230351537902 ps
CPU time 2027.5 seconds
Started Jun 22 06:00:50 PM PDT 24
Finished Jun 22 06:34:38 PM PDT 24
Peak memory 215820 kb
Host smart-c0412c2c-19f4-4c7e-8e1d-036a79717cba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=173852301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha384_vectors.173852301
Directory /workspace/37.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha512_vectors.2661744228
Short name T555
Test name
Test status
Simulation time 31942076625 ps
CPU time 1860.75 seconds
Started Jun 22 06:00:48 PM PDT 24
Finished Jun 22 06:31:49 PM PDT 24
Peak memory 216328 kb
Host smart-48318b83-a2ad-42a9-9f5d-176d31c63015
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2661744228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha512_vectors.2661744228
Directory /workspace/37.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3556715120
Short name T238
Test name
Test status
Simulation time 38977995 ps
CPU time 0.6 seconds
Started Jun 22 06:00:58 PM PDT 24
Finished Jun 22 06:00:59 PM PDT 24
Peak memory 195944 kb
Host smart-32dedfe7-2ac7-4e91-96f5-8941e9647c05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556715120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3556715120
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3017736707
Short name T121
Test name
Test status
Simulation time 3592591848 ps
CPU time 38.45 seconds
Started Jun 22 06:00:56 PM PDT 24
Finished Jun 22 06:01:35 PM PDT 24
Peak memory 200132 kb
Host smart-4d227774-3381-4361-a827-a62bf26b8e53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3017736707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3017736707
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.43397388
Short name T508
Test name
Test status
Simulation time 1785607219 ps
CPU time 50.77 seconds
Started Jun 22 06:00:57 PM PDT 24
Finished Jun 22 06:01:48 PM PDT 24
Peak memory 200176 kb
Host smart-5b20cbeb-a216-4248-a314-4a4024b21897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43397388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.43397388
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.683173115
Short name T185
Test name
Test status
Simulation time 7713176053 ps
CPU time 475.42 seconds
Started Jun 22 06:00:55 PM PDT 24
Finished Jun 22 06:08:51 PM PDT 24
Peak memory 618820 kb
Host smart-840e4ee0-6652-4be6-a0d0-4c54dbab76bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=683173115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.683173115
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.192651184
Short name T381
Test name
Test status
Simulation time 3761713731 ps
CPU time 49.69 seconds
Started Jun 22 06:00:55 PM PDT 24
Finished Jun 22 06:01:45 PM PDT 24
Peak memory 200108 kb
Host smart-faacdc19-c74c-4e22-a701-283db906cabc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192651184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.192651184
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.892266231
Short name T550
Test name
Test status
Simulation time 126265694553 ps
CPU time 130.1 seconds
Started Jun 22 06:00:58 PM PDT 24
Finished Jun 22 06:03:08 PM PDT 24
Peak memory 200104 kb
Host smart-520f79a1-1e03-45ee-a685-017f6afe2ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892266231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.892266231
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2888756667
Short name T568
Test name
Test status
Simulation time 36602822 ps
CPU time 1.12 seconds
Started Jun 22 06:00:49 PM PDT 24
Finished Jun 22 06:00:51 PM PDT 24
Peak memory 199992 kb
Host smart-0e182ce5-9495-405c-911e-dd1860dc5849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888756667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2888756667
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.82562340
Short name T452
Test name
Test status
Simulation time 111740217 ps
CPU time 1.24 seconds
Started Jun 22 06:00:55 PM PDT 24
Finished Jun 22 06:00:57 PM PDT 24
Peak memory 200012 kb
Host smart-c594a177-0d49-413c-81fb-6a13a6165099
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82562340 -assert nopostpro
c +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_hmac_vectors.82562340
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha256_vectors.2806991654
Short name T585
Test name
Test status
Simulation time 8464756575 ps
CPU time 434.3 seconds
Started Jun 22 06:00:55 PM PDT 24
Finished Jun 22 06:08:10 PM PDT 24
Peak memory 200124 kb
Host smart-47df2cf0-8ebe-4328-bdb0-13e860925299
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2806991654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha256_vectors.2806991654
Directory /workspace/38.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha384_vectors.170332962
Short name T435
Test name
Test status
Simulation time 685632158217 ps
CPU time 1864.09 seconds
Started Jun 22 06:00:58 PM PDT 24
Finished Jun 22 06:32:02 PM PDT 24
Peak memory 215816 kb
Host smart-f658e0d3-fb6b-45c9-9921-d352900da380
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=170332962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha384_vectors.170332962
Directory /workspace/38.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha512_vectors.450044238
Short name T409
Test name
Test status
Simulation time 595699903400 ps
CPU time 2174.49 seconds
Started Jun 22 06:01:07 PM PDT 24
Finished Jun 22 06:37:22 PM PDT 24
Peak memory 215536 kb
Host smart-1680c7bc-6f5e-474d-9878-a84caad4ede5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=450044238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha512_vectors.450044238
Directory /workspace/38.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.25282562
Short name T120
Test name
Test status
Simulation time 4532075182 ps
CPU time 52.04 seconds
Started Jun 22 06:00:56 PM PDT 24
Finished Jun 22 06:01:48 PM PDT 24
Peak memory 200136 kb
Host smart-358b700e-ec08-4f10-9ab9-c9aa9c2631f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25282562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.25282562
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2620686896
Short name T246
Test name
Test status
Simulation time 44353779 ps
CPU time 0.62 seconds
Started Jun 22 06:01:01 PM PDT 24
Finished Jun 22 06:01:02 PM PDT 24
Peak memory 196012 kb
Host smart-ae7b03fe-90ac-4bb6-971d-65ecce1a803a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620686896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2620686896
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.836839120
Short name T629
Test name
Test status
Simulation time 3709524602 ps
CPU time 26.37 seconds
Started Jun 22 06:01:02 PM PDT 24
Finished Jun 22 06:01:28 PM PDT 24
Peak memory 208256 kb
Host smart-64d0359d-badb-4392-92f5-f4bb85799dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836839120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.836839120
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2463610194
Short name T421
Test name
Test status
Simulation time 2285746446 ps
CPU time 604.01 seconds
Started Jun 22 06:01:04 PM PDT 24
Finished Jun 22 06:11:08 PM PDT 24
Peak memory 717968 kb
Host smart-13f01f8b-a32b-4fcc-aa33-afe8dffb728c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2463610194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2463610194
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3958221469
Short name T567
Test name
Test status
Simulation time 9407083823 ps
CPU time 144.32 seconds
Started Jun 22 06:01:02 PM PDT 24
Finished Jun 22 06:03:27 PM PDT 24
Peak memory 200148 kb
Host smart-40bc38da-830a-48b9-a90d-7136f3d1b2ef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958221469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3958221469
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1602107724
Short name T449
Test name
Test status
Simulation time 31012381262 ps
CPU time 125.92 seconds
Started Jun 22 06:00:58 PM PDT 24
Finished Jun 22 06:03:04 PM PDT 24
Peak memory 200160 kb
Host smart-f1b43a9b-fbf7-4c0d-9f5f-6457a54ff224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602107724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1602107724
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2179564952
Short name T301
Test name
Test status
Simulation time 591067767 ps
CPU time 8.24 seconds
Started Jun 22 06:00:58 PM PDT 24
Finished Jun 22 06:01:07 PM PDT 24
Peak memory 200192 kb
Host smart-5f4d7c2d-8a75-49ff-96a0-64e74cff1c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179564952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2179564952
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.4235140260
Short name T517
Test name
Test status
Simulation time 252842937 ps
CPU time 1.22 seconds
Started Jun 22 06:01:03 PM PDT 24
Finished Jun 22 06:01:05 PM PDT 24
Peak memory 200004 kb
Host smart-415f3610-a4d1-484c-81a4-73cde04516d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235140260 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_hmac_vectors.4235140260
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha256_vectors.1755936117
Short name T520
Test name
Test status
Simulation time 9265469014 ps
CPU time 503.47 seconds
Started Jun 22 06:01:01 PM PDT 24
Finished Jun 22 06:09:25 PM PDT 24
Peak memory 200104 kb
Host smart-a585cecb-5684-4371-af2a-a6f41e45f7f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1755936117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha256_vectors.1755936117
Directory /workspace/39.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha384_vectors.1364355711
Short name T168
Test name
Test status
Simulation time 33301514828 ps
CPU time 1946.15 seconds
Started Jun 22 06:01:02 PM PDT 24
Finished Jun 22 06:33:29 PM PDT 24
Peak memory 216536 kb
Host smart-4396054d-1111-4d71-9dee-17533a40a24b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1364355711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha384_vectors.1364355711
Directory /workspace/39.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha512_vectors.2946220757
Short name T390
Test name
Test status
Simulation time 105293582690 ps
CPU time 1970.88 seconds
Started Jun 22 06:01:02 PM PDT 24
Finished Jun 22 06:33:53 PM PDT 24
Peak memory 216540 kb
Host smart-130d8a7c-f335-483f-9182-32f2df4efedf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2946220757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha512_vectors.2946220757
Directory /workspace/39.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.4058846626
Short name T500
Test name
Test status
Simulation time 6689564911 ps
CPU time 93.01 seconds
Started Jun 22 06:01:01 PM PDT 24
Finished Jun 22 06:02:35 PM PDT 24
Peak memory 200136 kb
Host smart-3d528f0f-d78b-44e3-850c-57827400ee44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058846626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.4058846626
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2834059208
Short name T165
Test name
Test status
Simulation time 23139347 ps
CPU time 0.57 seconds
Started Jun 22 05:56:56 PM PDT 24
Finished Jun 22 05:56:57 PM PDT 24
Peak memory 195992 kb
Host smart-daca0f08-239e-4710-b9b4-9d9b50cf7b4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834059208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2834059208
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3702956751
Short name T262
Test name
Test status
Simulation time 262410484 ps
CPU time 4.28 seconds
Started Jun 22 05:56:49 PM PDT 24
Finished Jun 22 05:56:54 PM PDT 24
Peak memory 200060 kb
Host smart-4120c84f-e18c-4fe5-9d1c-e5485d48d867
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3702956751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3702956751
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2463309121
Short name T461
Test name
Test status
Simulation time 534128179 ps
CPU time 28.79 seconds
Started Jun 22 05:56:49 PM PDT 24
Finished Jun 22 05:57:18 PM PDT 24
Peak memory 200016 kb
Host smart-eb319689-5615-48b9-9aac-681b61588ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463309121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2463309121
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1291135583
Short name T554
Test name
Test status
Simulation time 57989623815 ps
CPU time 861.05 seconds
Started Jun 22 05:56:53 PM PDT 24
Finished Jun 22 06:11:15 PM PDT 24
Peak memory 717780 kb
Host smart-d1a24151-f29f-4953-93d8-1dc3d4dd23d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1291135583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1291135583
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.757201382
Short name T648
Test name
Test status
Simulation time 7234927697 ps
CPU time 109.71 seconds
Started Jun 22 05:56:48 PM PDT 24
Finished Jun 22 05:58:39 PM PDT 24
Peak memory 200108 kb
Host smart-defcb6aa-404a-4406-be97-b3198ba48ed1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757201382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.757201382
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.2051574295
Short name T393
Test name
Test status
Simulation time 4523851717 ps
CPU time 23.26 seconds
Started Jun 22 05:56:51 PM PDT 24
Finished Jun 22 05:57:15 PM PDT 24
Peak memory 208244 kb
Host smart-17cef2ca-25bd-484b-ae9b-99d1e0b28d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051574295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2051574295
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.652631788
Short name T44
Test name
Test status
Simulation time 57420187 ps
CPU time 0.88 seconds
Started Jun 22 05:56:53 PM PDT 24
Finished Jun 22 05:56:55 PM PDT 24
Peak memory 218332 kb
Host smart-6db9f9b7-b90f-4e6a-b6c6-6c09f42b30a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652631788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.652631788
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1908359360
Short name T36
Test name
Test status
Simulation time 900200661 ps
CPU time 11.55 seconds
Started Jun 22 05:56:43 PM PDT 24
Finished Jun 22 05:56:54 PM PDT 24
Peak memory 200052 kb
Host smart-029912e3-ec70-4d8b-97ef-a67156831f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908359360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1908359360
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.1961780401
Short name T484
Test name
Test status
Simulation time 185585863 ps
CPU time 1.21 seconds
Started Jun 22 05:56:53 PM PDT 24
Finished Jun 22 05:56:55 PM PDT 24
Peak memory 200064 kb
Host smart-5cd0908a-ebf1-474c-8fd8-03dca1a0fedf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961780401 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac_vectors.1961780401
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.544122324
Short name T178
Test name
Test status
Simulation time 9016771134 ps
CPU time 491.32 seconds
Started Jun 22 05:56:49 PM PDT 24
Finished Jun 22 06:05:01 PM PDT 24
Peak memory 200180 kb
Host smart-8e2d8ab2-79cb-4589-bb80-f9390835efa2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=544122324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.544122324
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.1508379446
Short name T169
Test name
Test status
Simulation time 224918568288 ps
CPU time 2035.92 seconds
Started Jun 22 05:56:50 PM PDT 24
Finished Jun 22 06:30:46 PM PDT 24
Peak memory 215532 kb
Host smart-ca9e02d1-6d58-41ce-955a-a2bd4d060a41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1508379446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.1508379446
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.359687888
Short name T561
Test name
Test status
Simulation time 59497319879 ps
CPU time 1710.71 seconds
Started Jun 22 05:56:52 PM PDT 24
Finished Jun 22 06:25:23 PM PDT 24
Peak memory 216700 kb
Host smart-a8a9f163-c697-4ba4-9bf4-c7e200eea989
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=359687888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.359687888
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.581904579
Short name T255
Test name
Test status
Simulation time 4564199794 ps
CPU time 50.36 seconds
Started Jun 22 05:56:49 PM PDT 24
Finished Jun 22 05:57:40 PM PDT 24
Peak memory 200108 kb
Host smart-6a2a5a88-2a75-4690-ae00-77c779add738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581904579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.581904579
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2393341610
Short name T494
Test name
Test status
Simulation time 47295415 ps
CPU time 0.58 seconds
Started Jun 22 06:01:19 PM PDT 24
Finished Jun 22 06:01:20 PM PDT 24
Peak memory 195592 kb
Host smart-0ee32e77-ed55-462c-9cbf-bcbd5d966d1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393341610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2393341610
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.585533978
Short name T6
Test name
Test status
Simulation time 1475604672 ps
CPU time 7.07 seconds
Started Jun 22 06:01:09 PM PDT 24
Finished Jun 22 06:01:17 PM PDT 24
Peak memory 200068 kb
Host smart-299b25f4-f003-4f9a-8149-e3b765ce8b09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585533978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.585533978
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1687254811
Short name T523
Test name
Test status
Simulation time 4565370809 ps
CPU time 65.95 seconds
Started Jun 22 06:01:08 PM PDT 24
Finished Jun 22 06:02:15 PM PDT 24
Peak memory 200096 kb
Host smart-c0bbb6e8-5668-4d6c-974e-c0689b81045f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687254811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1687254811
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.558543365
Short name T499
Test name
Test status
Simulation time 2002693078 ps
CPU time 270.9 seconds
Started Jun 22 06:01:07 PM PDT 24
Finished Jun 22 06:05:39 PM PDT 24
Peak memory 689780 kb
Host smart-e9a554de-57a4-43b9-990e-b208869fe557
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=558543365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.558543365
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.61527136
Short name T646
Test name
Test status
Simulation time 6467865091 ps
CPU time 41.16 seconds
Started Jun 22 06:01:12 PM PDT 24
Finished Jun 22 06:01:54 PM PDT 24
Peak memory 200140 kb
Host smart-cc759371-202e-4bad-9aff-50784faa1449
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61527136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.61527136
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1628472142
Short name T235
Test name
Test status
Simulation time 2259396266 ps
CPU time 16.41 seconds
Started Jun 22 06:01:09 PM PDT 24
Finished Jun 22 06:01:26 PM PDT 24
Peak memory 200164 kb
Host smart-aa81fa82-0f9a-4bde-8564-9032e5a942da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628472142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1628472142
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1561660631
Short name T353
Test name
Test status
Simulation time 138748328 ps
CPU time 2.56 seconds
Started Jun 22 06:01:08 PM PDT 24
Finished Jun 22 06:01:10 PM PDT 24
Peak memory 200060 kb
Host smart-b1108f29-10c6-450c-bf7b-25cd6c09a27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561660631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1561660631
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.439623570
Short name T296
Test name
Test status
Simulation time 43791657 ps
CPU time 1.06 seconds
Started Jun 22 06:01:08 PM PDT 24
Finished Jun 22 06:01:10 PM PDT 24
Peak memory 199864 kb
Host smart-921c11c4-e7ab-4ada-bac5-f883eaad9c00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439623570 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_hmac_vectors.439623570
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha256_vectors.2612138866
Short name T498
Test name
Test status
Simulation time 14399987338 ps
CPU time 387.76 seconds
Started Jun 22 06:01:07 PM PDT 24
Finished Jun 22 06:07:35 PM PDT 24
Peak memory 200092 kb
Host smart-073856c3-1107-4904-a0cc-a56623f61fa1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2612138866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha256_vectors.2612138866
Directory /workspace/40.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha384_vectors.2278620324
Short name T385
Test name
Test status
Simulation time 30173345044 ps
CPU time 1766.67 seconds
Started Jun 22 06:01:08 PM PDT 24
Finished Jun 22 06:30:36 PM PDT 24
Peak memory 216384 kb
Host smart-216c93d2-c2de-47ac-9b4b-98963438a486
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2278620324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha384_vectors.2278620324
Directory /workspace/40.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha512_vectors.2771200950
Short name T415
Test name
Test status
Simulation time 34100174425 ps
CPU time 1934.81 seconds
Started Jun 22 06:01:10 PM PDT 24
Finished Jun 22 06:33:26 PM PDT 24
Peak memory 208348 kb
Host smart-a62291b6-d3a6-4fa9-b1ea-3669df4002a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2771200950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha512_vectors.2771200950
Directory /workspace/40.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.3817495813
Short name T392
Test name
Test status
Simulation time 426908330 ps
CPU time 6.6 seconds
Started Jun 22 06:01:10 PM PDT 24
Finished Jun 22 06:01:18 PM PDT 24
Peak memory 200056 kb
Host smart-bb940257-e372-4799-a367-629f96f44608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817495813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3817495813
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1475181168
Short name T411
Test name
Test status
Simulation time 51584853 ps
CPU time 0.61 seconds
Started Jun 22 06:01:22 PM PDT 24
Finished Jun 22 06:01:23 PM PDT 24
Peak memory 196004 kb
Host smart-0c3635e2-aca3-4823-a7f6-6c01cf083869
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475181168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1475181168
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1751312619
Short name T267
Test name
Test status
Simulation time 50269223 ps
CPU time 1.69 seconds
Started Jun 22 06:01:20 PM PDT 24
Finished Jun 22 06:01:22 PM PDT 24
Peak memory 199868 kb
Host smart-4d1d9403-b0a0-403d-97ce-e6a08c5cb707
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1751312619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1751312619
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3112952544
Short name T309
Test name
Test status
Simulation time 8279746173 ps
CPU time 55.85 seconds
Started Jun 22 06:01:16 PM PDT 24
Finished Jun 22 06:02:12 PM PDT 24
Peak memory 200148 kb
Host smart-c5262a57-28de-484c-b132-d70fce374c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112952544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3112952544
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.3798394304
Short name T619
Test name
Test status
Simulation time 1735752626 ps
CPU time 134.69 seconds
Started Jun 22 06:01:14 PM PDT 24
Finished Jun 22 06:03:29 PM PDT 24
Peak memory 559476 kb
Host smart-2aaddf95-a226-4068-b16b-e6b947c9a27a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3798394304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3798394304
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1431615475
Short name T53
Test name
Test status
Simulation time 31231598 ps
CPU time 0.71 seconds
Started Jun 22 06:01:15 PM PDT 24
Finished Jun 22 06:01:16 PM PDT 24
Peak memory 196408 kb
Host smart-971170f7-c8ae-4f2b-a7fe-d9212f1d83e4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431615475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1431615475
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.1835049572
Short name T258
Test name
Test status
Simulation time 40145331023 ps
CPU time 110.83 seconds
Started Jun 22 06:01:16 PM PDT 24
Finished Jun 22 06:03:07 PM PDT 24
Peak memory 208460 kb
Host smart-08342092-3448-4773-bcfb-312654a6dbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835049572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1835049572
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.4142084754
Short name T491
Test name
Test status
Simulation time 368064139 ps
CPU time 7.12 seconds
Started Jun 22 06:01:14 PM PDT 24
Finished Jun 22 06:01:22 PM PDT 24
Peak memory 200072 kb
Host smart-eff472c4-4336-4cc8-a1c2-e92aa196c18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142084754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.4142084754
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.1127333784
Short name T569
Test name
Test status
Simulation time 249995185 ps
CPU time 1.09 seconds
Started Jun 22 06:01:18 PM PDT 24
Finished Jun 22 06:01:19 PM PDT 24
Peak memory 199796 kb
Host smart-2cf46792-3c5d-46f2-88ae-86f066965236
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127333784 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_hmac_vectors.1127333784
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha256_vectors.1320639104
Short name T210
Test name
Test status
Simulation time 109591510003 ps
CPU time 456.35 seconds
Started Jun 22 06:01:17 PM PDT 24
Finished Jun 22 06:08:53 PM PDT 24
Peak memory 200124 kb
Host smart-b1bde4cf-86d2-4c44-abae-b77aebaa0829
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1320639104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha256_vectors.1320639104
Directory /workspace/41.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha384_vectors.591016350
Short name T330
Test name
Test status
Simulation time 348219044853 ps
CPU time 2123.78 seconds
Started Jun 22 06:01:15 PM PDT 24
Finished Jun 22 06:36:40 PM PDT 24
Peak memory 216432 kb
Host smart-40c2e3d3-aeac-4678-86bc-8145f12e0efe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=591016350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha384_vectors.591016350
Directory /workspace/41.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha512_vectors.1009338337
Short name T213
Test name
Test status
Simulation time 271587133902 ps
CPU time 1851.44 seconds
Started Jun 22 06:01:15 PM PDT 24
Finished Jun 22 06:32:08 PM PDT 24
Peak memory 216432 kb
Host smart-69bf651d-120e-48f5-aba7-91e5f769506d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1009338337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha512_vectors.1009338337
Directory /workspace/41.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.884091813
Short name T414
Test name
Test status
Simulation time 88664706 ps
CPU time 4.2 seconds
Started Jun 22 06:01:15 PM PDT 24
Finished Jun 22 06:01:20 PM PDT 24
Peak memory 200084 kb
Host smart-1d58b03a-c96f-4f47-aaaf-2aecf0e38097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884091813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.884091813
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.951271735
Short name T643
Test name
Test status
Simulation time 15294760 ps
CPU time 0.63 seconds
Started Jun 22 06:01:24 PM PDT 24
Finished Jun 22 06:01:25 PM PDT 24
Peak memory 196064 kb
Host smart-54c2d834-9894-4b02-af7b-9004af483889
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951271735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.951271735
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.4142401129
Short name T467
Test name
Test status
Simulation time 787198402 ps
CPU time 10.85 seconds
Started Jun 22 06:01:22 PM PDT 24
Finished Jun 22 06:01:34 PM PDT 24
Peak memory 200028 kb
Host smart-ba81411b-87ff-4ced-89e2-60a848fefc44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4142401129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.4142401129
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2719561448
Short name T154
Test name
Test status
Simulation time 353639135 ps
CPU time 2.97 seconds
Started Jun 22 06:01:22 PM PDT 24
Finished Jun 22 06:01:26 PM PDT 24
Peak memory 200080 kb
Host smart-17d232d9-6b96-4d33-bcee-8431fc20c1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719561448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2719561448
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_error.3802630925
Short name T324
Test name
Test status
Simulation time 3232654098 ps
CPU time 85.29 seconds
Started Jun 22 06:01:24 PM PDT 24
Finished Jun 22 06:02:50 PM PDT 24
Peak memory 200136 kb
Host smart-29a8ba7e-1d70-4f22-a28b-7e3053acb592
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802630925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3802630925
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_smoke.3769440610
Short name T489
Test name
Test status
Simulation time 106288965 ps
CPU time 5.27 seconds
Started Jun 22 06:01:22 PM PDT 24
Finished Jun 22 06:01:28 PM PDT 24
Peak memory 200100 kb
Host smart-a065e989-98ae-4e49-98eb-40c26be3cbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769440610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3769440610
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.649718027
Short name T622
Test name
Test status
Simulation time 74960429 ps
CPU time 1.34 seconds
Started Jun 22 06:01:24 PM PDT 24
Finished Jun 22 06:01:26 PM PDT 24
Peak memory 200064 kb
Host smart-bb781200-366a-4367-8e0f-64700289fa7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649718027 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_hmac_vectors.649718027
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha256_vectors.3192712976
Short name T507
Test name
Test status
Simulation time 193971996109 ps
CPU time 567.77 seconds
Started Jun 22 06:01:28 PM PDT 24
Finished Jun 22 06:10:56 PM PDT 24
Peak memory 200124 kb
Host smart-7578919c-4749-47df-8546-65ddcbfad241
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3192712976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha256_vectors.3192712976
Directory /workspace/42.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha384_vectors.2116325400
Short name T386
Test name
Test status
Simulation time 28976956200 ps
CPU time 1700.51 seconds
Started Jun 22 06:01:22 PM PDT 24
Finished Jun 22 06:29:43 PM PDT 24
Peak memory 216100 kb
Host smart-e77f694c-2cf2-440d-9108-ff70c95ba71d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2116325400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha384_vectors.2116325400
Directory /workspace/42.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha512_vectors.1502656894
Short name T597
Test name
Test status
Simulation time 29880668999 ps
CPU time 1709.83 seconds
Started Jun 22 06:01:36 PM PDT 24
Finished Jun 22 06:30:07 PM PDT 24
Peak memory 215532 kb
Host smart-d7984000-8a6a-4e93-8570-c7ed927031f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1502656894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha512_vectors.1502656894
Directory /workspace/42.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.363550686
Short name T323
Test name
Test status
Simulation time 1253235606 ps
CPU time 23.44 seconds
Started Jun 22 06:01:21 PM PDT 24
Finished Jun 22 06:01:45 PM PDT 24
Peak memory 200076 kb
Host smart-b4d3b807-b442-4ae8-b7da-69eaace67815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363550686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.363550686
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1988820757
Short name T382
Test name
Test status
Simulation time 30257895 ps
CPU time 0.59 seconds
Started Jun 22 06:01:31 PM PDT 24
Finished Jun 22 06:01:33 PM PDT 24
Peak memory 194972 kb
Host smart-49387166-9d18-4798-a1eb-38fa86a2a15f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988820757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1988820757
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1692600694
Short name T588
Test name
Test status
Simulation time 304335304 ps
CPU time 13.73 seconds
Started Jun 22 06:01:23 PM PDT 24
Finished Jun 22 06:01:37 PM PDT 24
Peak memory 200056 kb
Host smart-47354f62-5a11-4679-ac91-c0b8fbac8011
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1692600694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1692600694
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3554759557
Short name T156
Test name
Test status
Simulation time 13468088713 ps
CPU time 52.44 seconds
Started Jun 22 06:01:23 PM PDT 24
Finished Jun 22 06:02:16 PM PDT 24
Peak memory 200116 kb
Host smart-12e6fab9-a591-43a9-bfe7-544f27c2a409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554759557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3554759557
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.1771088645
Short name T328
Test name
Test status
Simulation time 13809547509 ps
CPU time 839.64 seconds
Started Jun 22 06:01:22 PM PDT 24
Finished Jun 22 06:15:23 PM PDT 24
Peak memory 728564 kb
Host smart-15f28ac0-ca0f-4702-b7f6-28635dcca769
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1771088645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1771088645
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.4179709927
Short name T139
Test name
Test status
Simulation time 2848187035 ps
CPU time 39.88 seconds
Started Jun 22 06:01:28 PM PDT 24
Finished Jun 22 06:02:08 PM PDT 24
Peak memory 200268 kb
Host smart-19217dc8-4f07-43de-b6b2-52bfafd71279
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179709927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.4179709927
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1565426500
Short name T398
Test name
Test status
Simulation time 372364923 ps
CPU time 21.77 seconds
Started Jun 22 06:01:28 PM PDT 24
Finished Jun 22 06:01:50 PM PDT 24
Peak memory 200048 kb
Host smart-43e56e53-d05c-42dd-b198-ad82ccc1d233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565426500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1565426500
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.694540614
Short name T391
Test name
Test status
Simulation time 700969917 ps
CPU time 11.21 seconds
Started Jun 22 06:01:26 PM PDT 24
Finished Jun 22 06:01:37 PM PDT 24
Peak memory 200076 kb
Host smart-9a628672-6cfd-45b8-8eee-77b5f30f2201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694540614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.694540614
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.271417868
Short name T615
Test name
Test status
Simulation time 32737478129 ps
CPU time 101.78 seconds
Started Jun 22 06:01:30 PM PDT 24
Finished Jun 22 06:03:12 PM PDT 24
Peak memory 216484 kb
Host smart-31dc99ca-58ad-433b-a78b-3274d95f37ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271417868 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.271417868
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.851371294
Short name T158
Test name
Test status
Simulation time 223131483 ps
CPU time 1.09 seconds
Started Jun 22 06:01:30 PM PDT 24
Finished Jun 22 06:01:32 PM PDT 24
Peak memory 199724 kb
Host smart-e73982e2-e1da-4031-8489-1c1782311643
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851371294 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_hmac_vectors.851371294
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha256_vectors.3079915375
Short name T448
Test name
Test status
Simulation time 40418782282 ps
CPU time 407.36 seconds
Started Jun 22 06:01:28 PM PDT 24
Finished Jun 22 06:08:16 PM PDT 24
Peak memory 200120 kb
Host smart-1887ee4c-a49e-43ea-b134-6cf7706635b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3079915375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha256_vectors.3079915375
Directory /workspace/43.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha384_vectors.4146829727
Short name T338
Test name
Test status
Simulation time 34432290280 ps
CPU time 1901.19 seconds
Started Jun 22 06:01:29 PM PDT 24
Finished Jun 22 06:33:11 PM PDT 24
Peak memory 216096 kb
Host smart-de43a09d-457f-414d-977f-2608dba1c138
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4146829727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha384_vectors.4146829727
Directory /workspace/43.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha512_vectors.410156052
Short name T208
Test name
Test status
Simulation time 306291405655 ps
CPU time 1932.85 seconds
Started Jun 22 06:01:29 PM PDT 24
Finished Jun 22 06:33:42 PM PDT 24
Peak memory 216048 kb
Host smart-387195a8-aec9-47f0-8340-c7eebd8fd92e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=410156052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha512_vectors.410156052
Directory /workspace/43.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.3636069206
Short name T605
Test name
Test status
Simulation time 1612638630 ps
CPU time 30.62 seconds
Started Jun 22 06:01:31 PM PDT 24
Finished Jun 22 06:02:02 PM PDT 24
Peak memory 200084 kb
Host smart-e5847e35-d0fa-4ca1-b508-32c23f2aa93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636069206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3636069206
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1238463308
Short name T214
Test name
Test status
Simulation time 42690331 ps
CPU time 0.61 seconds
Started Jun 22 06:01:37 PM PDT 24
Finished Jun 22 06:01:38 PM PDT 24
Peak memory 194972 kb
Host smart-6609b5d2-a62f-4e6c-9bcc-72324b26bd0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238463308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1238463308
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3938706824
Short name T483
Test name
Test status
Simulation time 4090611282 ps
CPU time 51.27 seconds
Started Jun 22 06:01:30 PM PDT 24
Finished Jun 22 06:02:22 PM PDT 24
Peak memory 208248 kb
Host smart-69d6d113-6aec-4e68-a2c6-10572a9c25a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3938706824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3938706824
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.4025109978
Short name T601
Test name
Test status
Simulation time 14541799780 ps
CPU time 55.62 seconds
Started Jun 22 06:01:28 PM PDT 24
Finished Jun 22 06:02:24 PM PDT 24
Peak memory 200128 kb
Host smart-94515a4c-cab8-4b5d-88cd-51ea91227a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025109978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.4025109978
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3254113205
Short name T322
Test name
Test status
Simulation time 5784556145 ps
CPU time 1027.03 seconds
Started Jun 22 06:01:31 PM PDT 24
Finished Jun 22 06:18:39 PM PDT 24
Peak memory 778716 kb
Host smart-06de6dab-2e47-433f-9291-2fe26775cb8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3254113205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3254113205
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1883238665
Short name T496
Test name
Test status
Simulation time 10260394645 ps
CPU time 45.1 seconds
Started Jun 22 06:01:30 PM PDT 24
Finished Jun 22 06:02:15 PM PDT 24
Peak memory 200004 kb
Host smart-17553f25-b6ae-4cc4-bda3-ce9d4fa2afa9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883238665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1883238665
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1653635606
Short name T482
Test name
Test status
Simulation time 8107199452 ps
CPU time 27.86 seconds
Started Jun 22 06:01:30 PM PDT 24
Finished Jun 22 06:01:58 PM PDT 24
Peak memory 200164 kb
Host smart-0d608586-5b2b-40a6-85f3-a7c5f15f2116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653635606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1653635606
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.790310701
Short name T337
Test name
Test status
Simulation time 329202103 ps
CPU time 8.29 seconds
Started Jun 22 06:01:28 PM PDT 24
Finished Jun 22 06:01:37 PM PDT 24
Peak memory 200080 kb
Host smart-6b9af164-ac68-4de6-bf1e-87fa64a20197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790310701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.790310701
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3981543315
Short name T69
Test name
Test status
Simulation time 175242116381 ps
CPU time 1372.06 seconds
Started Jun 22 06:01:37 PM PDT 24
Finished Jun 22 06:24:30 PM PDT 24
Peak memory 722928 kb
Host smart-a541519e-a04b-44ba-a4ef-52b1d6e7ef85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981543315 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3981543315
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.798949210
Short name T361
Test name
Test status
Simulation time 99939652 ps
CPU time 1.01 seconds
Started Jun 22 06:01:38 PM PDT 24
Finished Jun 22 06:01:40 PM PDT 24
Peak memory 199848 kb
Host smart-994b3548-3ab4-4cb5-b1e6-c029726f8b5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798949210 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_hmac_vectors.798949210
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha256_vectors.476754605
Short name T52
Test name
Test status
Simulation time 230773455047 ps
CPU time 599.94 seconds
Started Jun 22 06:01:30 PM PDT 24
Finished Jun 22 06:11:31 PM PDT 24
Peak memory 200124 kb
Host smart-35e918b9-7641-477a-9783-3b6a113f94fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=476754605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha256_vectors.476754605
Directory /workspace/44.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha384_vectors.1669869537
Short name T300
Test name
Test status
Simulation time 65132617768 ps
CPU time 1863.14 seconds
Started Jun 22 06:01:32 PM PDT 24
Finished Jun 22 06:32:36 PM PDT 24
Peak memory 216096 kb
Host smart-208d52b1-7d3f-4682-9c8b-4771bb515645
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1669869537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha384_vectors.1669869537
Directory /workspace/44.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha512_vectors.1348743691
Short name T506
Test name
Test status
Simulation time 629345371624 ps
CPU time 2010.63 seconds
Started Jun 22 06:01:36 PM PDT 24
Finished Jun 22 06:35:08 PM PDT 24
Peak memory 216208 kb
Host smart-acb92cd6-517d-454a-a95d-7c381f2e6dc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1348743691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha512_vectors.1348743691
Directory /workspace/44.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.3281448879
Short name T450
Test name
Test status
Simulation time 18284002663 ps
CPU time 70.21 seconds
Started Jun 22 06:01:29 PM PDT 24
Finished Jun 22 06:02:40 PM PDT 24
Peak memory 200068 kb
Host smart-ccb0b406-197c-459f-97b5-e7012d9445e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281448879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3281448879
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2307478860
Short name T574
Test name
Test status
Simulation time 31901311 ps
CPU time 0.58 seconds
Started Jun 22 06:01:45 PM PDT 24
Finished Jun 22 06:01:46 PM PDT 24
Peak memory 194972 kb
Host smart-261760eb-fa50-4c82-b15e-5defa5e2dc87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307478860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2307478860
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.189910058
Short name T313
Test name
Test status
Simulation time 974917973 ps
CPU time 10.86 seconds
Started Jun 22 06:01:54 PM PDT 24
Finished Jun 22 06:02:05 PM PDT 24
Peak memory 200052 kb
Host smart-2e23d0a4-8e98-4211-aad4-6f37d6c58d4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=189910058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.189910058
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.4283301080
Short name T193
Test name
Test status
Simulation time 3359731038 ps
CPU time 43.94 seconds
Started Jun 22 06:01:45 PM PDT 24
Finished Jun 22 06:02:30 PM PDT 24
Peak memory 200132 kb
Host smart-eec80648-21c7-4de9-bb1e-8acd7a6c9ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283301080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.4283301080
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.77214052
Short name T384
Test name
Test status
Simulation time 4048633188 ps
CPU time 438.28 seconds
Started Jun 22 06:01:46 PM PDT 24
Finished Jun 22 06:09:05 PM PDT 24
Peak memory 658956 kb
Host smart-7b037c3a-e6e0-409a-a5e3-494322a9688d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77214052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.77214052
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.4177368223
Short name T135
Test name
Test status
Simulation time 904723518 ps
CPU time 27.31 seconds
Started Jun 22 06:01:48 PM PDT 24
Finished Jun 22 06:02:16 PM PDT 24
Peak memory 200076 kb
Host smart-a899ef34-2044-4318-aefe-983a252b8f4b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177368223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.4177368223
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1078788402
Short name T531
Test name
Test status
Simulation time 7069526071 ps
CPU time 106.72 seconds
Started Jun 22 06:01:38 PM PDT 24
Finished Jun 22 06:03:25 PM PDT 24
Peak memory 200132 kb
Host smart-e395f515-b192-4970-8b7b-760a2aea328d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078788402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1078788402
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3455186326
Short name T549
Test name
Test status
Simulation time 504727250 ps
CPU time 5.12 seconds
Started Jun 22 06:01:36 PM PDT 24
Finished Jun 22 06:01:41 PM PDT 24
Peak memory 200072 kb
Host smart-4a292cc2-8c28-4f68-b3ab-9c01aadff9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455186326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3455186326
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.2900376210
Short name T162
Test name
Test status
Simulation time 323880352 ps
CPU time 1.39 seconds
Started Jun 22 06:01:45 PM PDT 24
Finished Jun 22 06:01:47 PM PDT 24
Peak memory 200092 kb
Host smart-01dc2ae8-3b73-44de-88b6-cca5322118a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900376210 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_hmac_vectors.2900376210
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha256_vectors.4150562026
Short name T232
Test name
Test status
Simulation time 35832845098 ps
CPU time 489.91 seconds
Started Jun 22 06:01:44 PM PDT 24
Finished Jun 22 06:09:55 PM PDT 24
Peak memory 200108 kb
Host smart-e8c42e61-96e1-48c3-88d9-7c87dc1e21d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4150562026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha256_vectors.4150562026
Directory /workspace/45.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha384_vectors.289541545
Short name T303
Test name
Test status
Simulation time 221313532644 ps
CPU time 2029.74 seconds
Started Jun 22 06:01:50 PM PDT 24
Finished Jun 22 06:35:41 PM PDT 24
Peak memory 216400 kb
Host smart-45f463e6-ff60-4a86-8c28-973809692f8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=289541545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha384_vectors.289541545
Directory /workspace/45.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha512_vectors.2890118538
Short name T624
Test name
Test status
Simulation time 278381575061 ps
CPU time 1853.69 seconds
Started Jun 22 06:01:47 PM PDT 24
Finished Jun 22 06:32:41 PM PDT 24
Peak memory 215584 kb
Host smart-ee40b679-7c14-45b6-a29a-697053748f87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2890118538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha512_vectors.2890118538
Directory /workspace/45.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2702723913
Short name T58
Test name
Test status
Simulation time 18450372677 ps
CPU time 95.6 seconds
Started Jun 22 06:01:52 PM PDT 24
Finished Jun 22 06:03:28 PM PDT 24
Peak memory 200140 kb
Host smart-13c38d7c-d23e-496f-a1bb-bd42a9de1b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702723913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2702723913
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3604967853
Short name T423
Test name
Test status
Simulation time 17088369 ps
CPU time 0.59 seconds
Started Jun 22 06:01:55 PM PDT 24
Finished Jun 22 06:01:56 PM PDT 24
Peak memory 194896 kb
Host smart-78542cbe-f7de-44a1-ac9c-60cad277fdc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604967853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3604967853
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.4137938623
Short name T510
Test name
Test status
Simulation time 1032886219 ps
CPU time 43.22 seconds
Started Jun 22 06:01:55 PM PDT 24
Finished Jun 22 06:02:39 PM PDT 24
Peak memory 200068 kb
Host smart-d7d8603f-3bac-47a9-abf3-f55bd62ea574
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4137938623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.4137938623
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.3136985178
Short name T513
Test name
Test status
Simulation time 1879060624 ps
CPU time 26.17 seconds
Started Jun 22 06:01:56 PM PDT 24
Finished Jun 22 06:02:22 PM PDT 24
Peak memory 200040 kb
Host smart-cf750fbc-3362-46f6-8e79-8b9a7be3110e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136985178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3136985178
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2846529382
Short name T424
Test name
Test status
Simulation time 12578701800 ps
CPU time 967.78 seconds
Started Jun 22 06:01:52 PM PDT 24
Finished Jun 22 06:18:01 PM PDT 24
Peak memory 709836 kb
Host smart-2ff3f41e-47e7-43ed-b86d-7959a098a0ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2846529382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2846529382
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.3386114531
Short name T468
Test name
Test status
Simulation time 1209996185 ps
CPU time 69.85 seconds
Started Jun 22 06:01:53 PM PDT 24
Finished Jun 22 06:03:03 PM PDT 24
Peak memory 200008 kb
Host smart-d65e7d0a-c57d-4823-834e-82a08ac6b668
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386114531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3386114531
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1591684146
Short name T599
Test name
Test status
Simulation time 10009572256 ps
CPU time 96.83 seconds
Started Jun 22 06:01:53 PM PDT 24
Finished Jun 22 06:03:30 PM PDT 24
Peak memory 200116 kb
Host smart-29c8d946-8432-44b0-93f8-bce6b088d883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591684146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1591684146
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3150134664
Short name T180
Test name
Test status
Simulation time 4074456247 ps
CPU time 19.51 seconds
Started Jun 22 06:01:45 PM PDT 24
Finished Jun 22 06:02:05 PM PDT 24
Peak memory 200076 kb
Host smart-9ebb77fd-c828-4bf8-9da1-461d0eab43fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150134664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3150134664
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.434266280
Short name T354
Test name
Test status
Simulation time 105799471 ps
CPU time 1 seconds
Started Jun 22 06:01:54 PM PDT 24
Finished Jun 22 06:01:56 PM PDT 24
Peak memory 199776 kb
Host smart-135a0b7f-6264-4f55-99c2-3c157ce5c204
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434266280 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_hmac_vectors.434266280
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha256_vectors.2131740953
Short name T253
Test name
Test status
Simulation time 13939648988 ps
CPU time 381.85 seconds
Started Jun 22 06:01:56 PM PDT 24
Finished Jun 22 06:08:18 PM PDT 24
Peak memory 199956 kb
Host smart-ff6b8546-7147-45bf-b4e5-54f570e5fc1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2131740953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha256_vectors.2131740953
Directory /workspace/46.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha384_vectors.2389757287
Short name T299
Test name
Test status
Simulation time 435167471895 ps
CPU time 1896.04 seconds
Started Jun 22 06:01:53 PM PDT 24
Finished Jun 22 06:33:29 PM PDT 24
Peak memory 215472 kb
Host smart-a9c4497f-a29c-4d57-876b-4db6413fc5fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2389757287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha384_vectors.2389757287
Directory /workspace/46.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha512_vectors.1014295159
Short name T244
Test name
Test status
Simulation time 103734145216 ps
CPU time 1916.66 seconds
Started Jun 22 06:01:52 PM PDT 24
Finished Jun 22 06:33:50 PM PDT 24
Peak memory 215568 kb
Host smart-eae47130-e2c7-4beb-93fa-cfce8ab6a345
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1014295159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha512_vectors.1014295159
Directory /workspace/46.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.4215371002
Short name T470
Test name
Test status
Simulation time 4305344102 ps
CPU time 38.6 seconds
Started Jun 22 06:01:55 PM PDT 24
Finished Jun 22 06:02:33 PM PDT 24
Peak memory 200136 kb
Host smart-a0fc83c5-207e-4ccf-a0dc-7f5535035b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215371002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.4215371002
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3212222931
Short name T447
Test name
Test status
Simulation time 35973328 ps
CPU time 0.62 seconds
Started Jun 22 06:02:02 PM PDT 24
Finished Jun 22 06:02:03 PM PDT 24
Peak memory 194584 kb
Host smart-ada7b2d0-940c-4748-a896-ca88a773d540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212222931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3212222931
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1039140309
Short name T652
Test name
Test status
Simulation time 314277547 ps
CPU time 15.4 seconds
Started Jun 22 06:01:52 PM PDT 24
Finished Jun 22 06:02:08 PM PDT 24
Peak memory 200060 kb
Host smart-49c2328f-21e3-48f5-a92d-8d261f13bd88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1039140309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1039140309
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3372734083
Short name T132
Test name
Test status
Simulation time 359236700 ps
CPU time 18.86 seconds
Started Jun 22 06:02:04 PM PDT 24
Finished Jun 22 06:02:23 PM PDT 24
Peak memory 200064 kb
Host smart-4a54b2b8-219f-4afa-8b2f-77d99ceb4c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372734083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3372734083
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.678327182
Short name T481
Test name
Test status
Simulation time 4118816830 ps
CPU time 173.17 seconds
Started Jun 22 06:02:00 PM PDT 24
Finished Jun 22 06:04:54 PM PDT 24
Peak memory 463064 kb
Host smart-ee1b09b4-c9ff-483e-a2a6-34d4e58ec2bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=678327182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.678327182
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3240137040
Short name T198
Test name
Test status
Simulation time 3318917040 ps
CPU time 41.78 seconds
Started Jun 22 06:01:54 PM PDT 24
Finished Jun 22 06:02:36 PM PDT 24
Peak memory 200252 kb
Host smart-0f03c4fb-76ba-4bee-a413-a79f1e9eeec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240137040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3240137040
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3483927349
Short name T545
Test name
Test status
Simulation time 4766018730 ps
CPU time 18.85 seconds
Started Jun 22 06:01:56 PM PDT 24
Finished Jun 22 06:02:15 PM PDT 24
Peak memory 199980 kb
Host smart-6b2e7700-78ff-46ba-a89e-09dcf6feb755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483927349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3483927349
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2413078141
Short name T12
Test name
Test status
Simulation time 111199703 ps
CPU time 1.46 seconds
Started Jun 22 06:02:01 PM PDT 24
Finished Jun 22 06:02:03 PM PDT 24
Peak memory 200036 kb
Host smart-3dc4b5bb-edc4-4cfc-b8dc-c3f7c1465aaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413078141 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_hmac_vectors.2413078141
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha256_vectors.3929783709
Short name T254
Test name
Test status
Simulation time 37336450413 ps
CPU time 465.3 seconds
Started Jun 22 06:02:06 PM PDT 24
Finished Jun 22 06:09:52 PM PDT 24
Peak memory 200120 kb
Host smart-cf324eb3-c4cc-4a3d-9719-18d4619620df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3929783709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha256_vectors.3929783709
Directory /workspace/47.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha384_vectors.396216055
Short name T10
Test name
Test status
Simulation time 195074055378 ps
CPU time 1999.29 seconds
Started Jun 22 06:02:00 PM PDT 24
Finished Jun 22 06:35:20 PM PDT 24
Peak memory 215532 kb
Host smart-92e0d4f0-d7ba-460a-839d-6e0ce00827b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=396216055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha384_vectors.396216055
Directory /workspace/47.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha512_vectors.2957806066
Short name T227
Test name
Test status
Simulation time 166149020836 ps
CPU time 1993.39 seconds
Started Jun 22 06:02:01 PM PDT 24
Finished Jun 22 06:35:15 PM PDT 24
Peak memory 216320 kb
Host smart-69e7ab52-40ef-4b7f-99b1-779b19716457
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2957806066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha512_vectors.2957806066
Directory /workspace/47.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.83986062
Short name T363
Test name
Test status
Simulation time 508090945 ps
CPU time 5.92 seconds
Started Jun 22 06:01:59 PM PDT 24
Finished Jun 22 06:02:06 PM PDT 24
Peak memory 200008 kb
Host smart-6182d005-08d1-4194-81bb-f61ab469832a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83986062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.83986062
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1972964468
Short name T289
Test name
Test status
Simulation time 14304624 ps
CPU time 0.61 seconds
Started Jun 22 06:02:10 PM PDT 24
Finished Jun 22 06:02:11 PM PDT 24
Peak memory 195628 kb
Host smart-588ecd2a-17d9-4eea-9a15-311e8ae56485
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972964468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1972964468
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.4052740397
Short name T583
Test name
Test status
Simulation time 318128499 ps
CPU time 15.8 seconds
Started Jun 22 06:02:04 PM PDT 24
Finished Jun 22 06:02:20 PM PDT 24
Peak memory 200064 kb
Host smart-9d88a632-7acc-43e9-9c96-1a9930c6021f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4052740397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.4052740397
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3282530043
Short name T547
Test name
Test status
Simulation time 765298268 ps
CPU time 9.72 seconds
Started Jun 22 06:01:59 PM PDT 24
Finished Jun 22 06:02:10 PM PDT 24
Peak memory 200044 kb
Host smart-2a2a0eb4-78bf-4426-8260-e688018957ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282530043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3282530043
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3817250971
Short name T497
Test name
Test status
Simulation time 17501913298 ps
CPU time 830.72 seconds
Started Jun 22 06:02:02 PM PDT 24
Finished Jun 22 06:15:53 PM PDT 24
Peak memory 732960 kb
Host smart-6371fb17-3e8c-45f9-93dc-a254af3e0a10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3817250971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3817250971
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1052325040
Short name T529
Test name
Test status
Simulation time 7575327761 ps
CPU time 130.41 seconds
Started Jun 22 06:02:02 PM PDT 24
Finished Jun 22 06:04:13 PM PDT 24
Peak memory 200100 kb
Host smart-3a1966c6-4858-469a-9705-b0681d15a0c4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052325040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1052325040
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3092779002
Short name T642
Test name
Test status
Simulation time 2537710722 ps
CPU time 151.56 seconds
Started Jun 22 06:02:02 PM PDT 24
Finished Jun 22 06:04:34 PM PDT 24
Peak memory 215868 kb
Host smart-e5e9b4c6-87ab-46e0-8155-4b12c83f2674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092779002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3092779002
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1937245994
Short name T171
Test name
Test status
Simulation time 831632570 ps
CPU time 8.77 seconds
Started Jun 22 06:02:01 PM PDT 24
Finished Jun 22 06:02:10 PM PDT 24
Peak memory 199956 kb
Host smart-a1d2a23e-3ecd-4d37-9866-07316199ad4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937245994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1937245994
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.3980883913
Short name T222
Test name
Test status
Simulation time 268988745 ps
CPU time 1.29 seconds
Started Jun 22 06:02:07 PM PDT 24
Finished Jun 22 06:02:09 PM PDT 24
Peak memory 199960 kb
Host smart-be1117fc-6fee-4808-a0ca-012476f17257
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980883913 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_hmac_vectors.3980883913
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha256_vectors.644533230
Short name T653
Test name
Test status
Simulation time 26697621234 ps
CPU time 480.8 seconds
Started Jun 22 06:02:00 PM PDT 24
Finished Jun 22 06:10:01 PM PDT 24
Peak memory 200124 kb
Host smart-b670f85f-56c6-4148-b527-2988bd2d04b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=644533230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha256_vectors.644533230
Directory /workspace/48.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha384_vectors.494396245
Short name T589
Test name
Test status
Simulation time 112076311776 ps
CPU time 2061.57 seconds
Started Jun 22 06:02:01 PM PDT 24
Finished Jun 22 06:36:23 PM PDT 24
Peak memory 215732 kb
Host smart-02900765-9b9c-4d23-98bd-1d718f7aa2b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=494396245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha384_vectors.494396245
Directory /workspace/48.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha512_vectors.1837436850
Short name T405
Test name
Test status
Simulation time 32478490359 ps
CPU time 1824.72 seconds
Started Jun 22 06:02:02 PM PDT 24
Finished Jun 22 06:32:27 PM PDT 24
Peak memory 215684 kb
Host smart-bdfd22c6-e99b-4669-9e35-8e74edfab558
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1837436850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha512_vectors.1837436850
Directory /workspace/48.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2830827721
Short name T42
Test name
Test status
Simulation time 26240124532 ps
CPU time 42.55 seconds
Started Jun 22 06:01:58 PM PDT 24
Finished Jun 22 06:02:40 PM PDT 24
Peak memory 200156 kb
Host smart-b819ffd4-1021-4016-b6f1-a9f439619dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830827721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2830827721
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1425666977
Short name T220
Test name
Test status
Simulation time 19942250 ps
CPU time 0.6 seconds
Started Jun 22 06:02:13 PM PDT 24
Finished Jun 22 06:02:14 PM PDT 24
Peak memory 196000 kb
Host smart-36f855dc-cf03-4b4f-9f12-c94d9d9daa76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425666977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1425666977
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.659664924
Short name T401
Test name
Test status
Simulation time 515256150 ps
CPU time 12.61 seconds
Started Jun 22 06:02:09 PM PDT 24
Finished Jun 22 06:02:22 PM PDT 24
Peak memory 200060 kb
Host smart-a70fc9aa-ab44-4113-bdc1-afb4d97ee85f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=659664924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.659664924
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1600931964
Short name T130
Test name
Test status
Simulation time 4328798863 ps
CPU time 59.7 seconds
Started Jun 22 06:02:09 PM PDT 24
Finished Jun 22 06:03:10 PM PDT 24
Peak memory 216536 kb
Host smart-ea95ee0b-0042-42d9-93f5-47f1261ac54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600931964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1600931964
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1132018079
Short name T271
Test name
Test status
Simulation time 6725308301 ps
CPU time 336.64 seconds
Started Jun 22 06:02:17 PM PDT 24
Finished Jun 22 06:07:54 PM PDT 24
Peak memory 608252 kb
Host smart-d8de7879-6e56-4a63-9518-38d9d65467d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1132018079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1132018079
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3541392413
Short name T519
Test name
Test status
Simulation time 6655745939 ps
CPU time 117.08 seconds
Started Jun 22 06:02:08 PM PDT 24
Finished Jun 22 06:04:05 PM PDT 24
Peak memory 200108 kb
Host smart-db33ab70-9168-4cc8-bedd-8dba09ffd402
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541392413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3541392413
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3229373076
Short name T34
Test name
Test status
Simulation time 5228008394 ps
CPU time 102.64 seconds
Started Jun 22 06:02:10 PM PDT 24
Finished Jun 22 06:03:53 PM PDT 24
Peak memory 200176 kb
Host smart-59e05f84-e47d-4211-bc89-c50042867eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229373076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3229373076
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.145773546
Short name T190
Test name
Test status
Simulation time 2372913054 ps
CPU time 8.82 seconds
Started Jun 22 06:02:11 PM PDT 24
Finished Jun 22 06:02:20 PM PDT 24
Peak memory 200160 kb
Host smart-d9e2d93c-7f14-43b7-82c2-cea1782c4db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145773546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.145773546
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.72859313
Short name T161
Test name
Test status
Simulation time 58221769 ps
CPU time 1 seconds
Started Jun 22 06:02:07 PM PDT 24
Finished Jun 22 06:02:08 PM PDT 24
Peak memory 199572 kb
Host smart-cbe846d6-81da-4ead-b8e9-c1e5e1fd60c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72859313 -assert nopostpro
c +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_hmac_vectors.72859313
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha256_vectors.572266610
Short name T266
Test name
Test status
Simulation time 28496703249 ps
CPU time 407.87 seconds
Started Jun 22 06:02:11 PM PDT 24
Finished Jun 22 06:08:59 PM PDT 24
Peak memory 200120 kb
Host smart-1a7f167b-a22f-4bf4-97ed-049adfa4d4f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=572266610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha256_vectors.572266610
Directory /workspace/49.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha384_vectors.3250031521
Short name T538
Test name
Test status
Simulation time 138285513796 ps
CPU time 2049.47 seconds
Started Jun 22 06:02:08 PM PDT 24
Finished Jun 22 06:36:18 PM PDT 24
Peak memory 215668 kb
Host smart-d57dc1dd-16eb-469b-85b1-fdfc02dc8246
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3250031521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha384_vectors.3250031521
Directory /workspace/49.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha512_vectors.3947568262
Short name T551
Test name
Test status
Simulation time 154627368929 ps
CPU time 2088.1 seconds
Started Jun 22 06:02:08 PM PDT 24
Finished Jun 22 06:36:57 PM PDT 24
Peak memory 215768 kb
Host smart-86ed398d-0d68-4be4-964d-89812ad33d42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3947568262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha512_vectors.3947568262
Directory /workspace/49.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3899540750
Short name T590
Test name
Test status
Simulation time 925760085 ps
CPU time 16.26 seconds
Started Jun 22 06:02:06 PM PDT 24
Finished Jun 22 06:02:22 PM PDT 24
Peak memory 200068 kb
Host smart-082c26ec-fb28-4914-9159-49a6216a2285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899540750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3899540750
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.751130467
Short name T362
Test name
Test status
Simulation time 24262861 ps
CPU time 0.61 seconds
Started Jun 22 05:57:02 PM PDT 24
Finished Jun 22 05:57:03 PM PDT 24
Peak memory 195988 kb
Host smart-bfa19140-323e-4004-a485-a0d8e19100a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751130467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.751130467
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1764398211
Short name T25
Test name
Test status
Simulation time 16822240959 ps
CPU time 52.78 seconds
Started Jun 22 05:56:56 PM PDT 24
Finished Jun 22 05:57:50 PM PDT 24
Peak memory 200148 kb
Host smart-d926078c-d208-4e65-b3d6-c7954dd83ee9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1764398211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1764398211
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.670031462
Short name T399
Test name
Test status
Simulation time 44112374 ps
CPU time 0.86 seconds
Started Jun 22 05:56:58 PM PDT 24
Finished Jun 22 05:57:00 PM PDT 24
Peak memory 209148 kb
Host smart-654a9f47-90ff-49d6-8977-64ef84f09f1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=670031462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.670031462
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1468199806
Short name T575
Test name
Test status
Simulation time 65086462936 ps
CPU time 133.36 seconds
Started Jun 22 05:56:58 PM PDT 24
Finished Jun 22 05:59:12 PM PDT 24
Peak memory 200144 kb
Host smart-d7f2d277-2a51-4324-80f5-35e5d90303a7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468199806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1468199806
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_smoke.153314146
Short name T527
Test name
Test status
Simulation time 696107925 ps
CPU time 4.29 seconds
Started Jun 22 05:56:55 PM PDT 24
Finished Jun 22 05:57:00 PM PDT 24
Peak memory 200068 kb
Host smart-f68cb96e-0ec8-488a-8fba-f6d5c3158725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153314146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.153314146
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.2603912317
Short name T206
Test name
Test status
Simulation time 106285841 ps
CPU time 1.26 seconds
Started Jun 22 05:57:03 PM PDT 24
Finished Jun 22 05:57:04 PM PDT 24
Peak memory 200088 kb
Host smart-b48737c6-452c-4510-aab0-7c71bdd2fe55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603912317 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_hmac_vectors.2603912317
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha256_vectors.3255516536
Short name T579
Test name
Test status
Simulation time 31067530611 ps
CPU time 453.54 seconds
Started Jun 22 05:56:58 PM PDT 24
Finished Jun 22 06:04:32 PM PDT 24
Peak memory 200148 kb
Host smart-d0a791a4-7953-4efc-9213-1f39e9773e9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3255516536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha256_vectors.3255516536
Directory /workspace/5.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha384_vectors.3914099785
Short name T486
Test name
Test status
Simulation time 62744177809 ps
CPU time 1744.41 seconds
Started Jun 22 05:56:55 PM PDT 24
Finished Jun 22 06:26:00 PM PDT 24
Peak memory 215832 kb
Host smart-809d41e8-0c45-4081-b885-d7d1ee8b9fde
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3914099785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha384_vectors.3914099785
Directory /workspace/5.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha512_vectors.761004742
Short name T626
Test name
Test status
Simulation time 321141751698 ps
CPU time 2036.62 seconds
Started Jun 22 05:57:02 PM PDT 24
Finished Jun 22 06:31:00 PM PDT 24
Peak memory 216452 kb
Host smart-308e37ba-6d1b-4ffc-93eb-4942e3674eea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=761004742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha512_vectors.761004742
Directory /workspace/5.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.1212088776
Short name T263
Test name
Test status
Simulation time 9156711978 ps
CPU time 59.42 seconds
Started Jun 22 05:56:57 PM PDT 24
Finished Jun 22 05:57:57 PM PDT 24
Peak memory 200048 kb
Host smart-6e8e832c-c756-4016-9821-07df3de52a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212088776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1212088776
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.440455771
Short name T225
Test name
Test status
Simulation time 35734978 ps
CPU time 0.57 seconds
Started Jun 22 05:57:11 PM PDT 24
Finished Jun 22 05:57:12 PM PDT 24
Peak memory 194972 kb
Host smart-8a54fc24-637f-43b7-9cfb-1a812804cef2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440455771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.440455771
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.1675317868
Short name T22
Test name
Test status
Simulation time 937237527 ps
CPU time 43.83 seconds
Started Jun 22 05:57:04 PM PDT 24
Finished Jun 22 05:57:48 PM PDT 24
Peak memory 200012 kb
Host smart-fde788a5-2012-4033-924c-9bf22b905507
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1675317868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.1675317868
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1606493891
Short name T387
Test name
Test status
Simulation time 1593210165 ps
CPU time 29.79 seconds
Started Jun 22 05:57:03 PM PDT 24
Finished Jun 22 05:57:33 PM PDT 24
Peak memory 200092 kb
Host smart-d0b0306a-c790-4379-a972-2b16f08f362c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606493891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1606493891
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1051661306
Short name T429
Test name
Test status
Simulation time 231553224 ps
CPU time 32.49 seconds
Started Jun 22 05:57:08 PM PDT 24
Finished Jun 22 05:57:42 PM PDT 24
Peak memory 312580 kb
Host smart-69fef94f-2e8a-4d00-9cc1-5239081e7079
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1051661306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1051661306
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.4080151517
Short name T403
Test name
Test status
Simulation time 4202382462 ps
CPU time 113.76 seconds
Started Jun 22 05:57:03 PM PDT 24
Finished Jun 22 05:58:57 PM PDT 24
Peak memory 200252 kb
Host smart-7a9e440d-b9cd-47ac-b805-caf07c2e57ec
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080151517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.4080151517
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.2423683609
Short name T572
Test name
Test status
Simulation time 7115222891 ps
CPU time 92.97 seconds
Started Jun 22 05:57:03 PM PDT 24
Finished Jun 22 05:58:37 PM PDT 24
Peak memory 200248 kb
Host smart-744445ad-90df-417e-9183-104533c794ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423683609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2423683609
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3591512867
Short name T492
Test name
Test status
Simulation time 479728054 ps
CPU time 6.85 seconds
Started Jun 22 05:57:03 PM PDT 24
Finished Jun 22 05:57:10 PM PDT 24
Peak memory 200032 kb
Host smart-19151c0c-6045-40d1-9d17-646c76d1f941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591512867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3591512867
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.4227323158
Short name T616
Test name
Test status
Simulation time 70941319 ps
CPU time 1.34 seconds
Started Jun 22 05:57:09 PM PDT 24
Finished Jun 22 05:57:11 PM PDT 24
Peak memory 200036 kb
Host smart-2f7357d1-8ebe-4bcd-aeba-25bfdf07bce3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227323158 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_hmac_vectors.4227323158
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha256_vectors.1782862584
Short name T261
Test name
Test status
Simulation time 7523024821 ps
CPU time 414.74 seconds
Started Jun 22 05:57:11 PM PDT 24
Finished Jun 22 06:04:07 PM PDT 24
Peak memory 200092 kb
Host smart-53d8d3c5-706c-4c2c-b85c-1f0f9d12b708
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1782862584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha256_vectors.1782862584
Directory /workspace/6.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha384_vectors.1223635374
Short name T343
Test name
Test status
Simulation time 127551850229 ps
CPU time 1776.81 seconds
Started Jun 22 05:57:10 PM PDT 24
Finished Jun 22 06:26:47 PM PDT 24
Peak memory 215456 kb
Host smart-31375b91-ce3c-464c-9c99-3da2c472203b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1223635374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha384_vectors.1223635374
Directory /workspace/6.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.426349795
Short name T553
Test name
Test status
Simulation time 33018860710 ps
CPU time 91.52 seconds
Started Jun 22 05:57:02 PM PDT 24
Finished Jun 22 05:58:34 PM PDT 24
Peak memory 200140 kb
Host smart-04e8a1ae-2868-4e86-9576-9bcd7904d452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426349795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.426349795
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2699170447
Short name T242
Test name
Test status
Simulation time 30250120 ps
CPU time 0.58 seconds
Started Jun 22 05:57:16 PM PDT 24
Finished Jun 22 05:57:17 PM PDT 24
Peak memory 196640 kb
Host smart-e3c3b2ec-3328-4d5f-acef-21f33a4c699d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699170447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2699170447
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.4197881119
Short name T445
Test name
Test status
Simulation time 3898448088 ps
CPU time 44.99 seconds
Started Jun 22 05:57:11 PM PDT 24
Finished Jun 22 05:57:57 PM PDT 24
Peak memory 200104 kb
Host smart-4575918b-8c75-41ee-b925-34e1f771c562
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4197881119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.4197881119
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.859970277
Short name T175
Test name
Test status
Simulation time 18730929869 ps
CPU time 53.01 seconds
Started Jun 22 05:57:12 PM PDT 24
Finished Jun 22 05:58:06 PM PDT 24
Peak memory 208312 kb
Host smart-4f8f1366-3d5a-40df-8b06-b716f86d9583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859970277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.859970277
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2642317125
Short name T295
Test name
Test status
Simulation time 3904423646 ps
CPU time 207.25 seconds
Started Jun 22 05:57:10 PM PDT 24
Finished Jun 22 06:00:38 PM PDT 24
Peak memory 602924 kb
Host smart-566fb54d-3611-47f2-9028-0d9cdb1724bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2642317125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2642317125
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.3753906066
Short name T137
Test name
Test status
Simulation time 109556936936 ps
CPU time 205.09 seconds
Started Jun 22 05:57:13 PM PDT 24
Finished Jun 22 06:00:39 PM PDT 24
Peak memory 200116 kb
Host smart-b6db0c63-2541-42b7-856f-41080b394d34
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753906066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3753906066
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2849629312
Short name T247
Test name
Test status
Simulation time 21145492427 ps
CPU time 110.82 seconds
Started Jun 22 05:57:10 PM PDT 24
Finished Jun 22 05:59:02 PM PDT 24
Peak memory 216444 kb
Host smart-ac9d680f-bcab-44ee-9165-55136f8f5288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849629312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2849629312
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3354242633
Short name T285
Test name
Test status
Simulation time 355635431 ps
CPU time 7.89 seconds
Started Jun 22 05:57:12 PM PDT 24
Finished Jun 22 05:57:20 PM PDT 24
Peak memory 200084 kb
Host smart-b9d8aa91-aaec-4150-aca8-40da40357bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354242633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3354242633
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.2491445677
Short name T477
Test name
Test status
Simulation time 56492255 ps
CPU time 1.06 seconds
Started Jun 22 05:57:18 PM PDT 24
Finished Jun 22 05:57:19 PM PDT 24
Peak memory 199800 kb
Host smart-3711c553-6c80-4aee-b942-eea91b0fd116
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491445677 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_hmac_vectors.2491445677
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha256_vectors.3496327661
Short name T194
Test name
Test status
Simulation time 31122438422 ps
CPU time 443.97 seconds
Started Jun 22 05:57:18 PM PDT 24
Finished Jun 22 06:04:43 PM PDT 24
Peak memory 200120 kb
Host smart-396d1b54-08b2-432d-8d99-c645dec2fd57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3496327661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha256_vectors.3496327661
Directory /workspace/7.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha384_vectors.1627940961
Short name T65
Test name
Test status
Simulation time 575499997855 ps
CPU time 1912.38 seconds
Started Jun 22 05:57:21 PM PDT 24
Finished Jun 22 06:29:14 PM PDT 24
Peak memory 215924 kb
Host smart-cda7202f-5523-4aa2-9360-943c8412453a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1627940961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha384_vectors.1627940961
Directory /workspace/7.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha512_vectors.3641251533
Short name T511
Test name
Test status
Simulation time 285030878634 ps
CPU time 2035.1 seconds
Started Jun 22 05:57:17 PM PDT 24
Finished Jun 22 06:31:13 PM PDT 24
Peak memory 215976 kb
Host smart-9eef637f-5a3b-44d3-9aa7-d31b2a012437
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3641251533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha512_vectors.3641251533
Directory /workspace/7.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.3743128453
Short name T115
Test name
Test status
Simulation time 723892305 ps
CPU time 35.45 seconds
Started Jun 22 05:57:16 PM PDT 24
Finished Jun 22 05:57:52 PM PDT 24
Peak memory 200100 kb
Host smart-8c8674c2-7826-4e79-bfe8-dcb3902667d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743128453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3743128453
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1638231491
Short name T41
Test name
Test status
Simulation time 12137608 ps
CPU time 0.59 seconds
Started Jun 22 05:57:32 PM PDT 24
Finished Jun 22 05:57:32 PM PDT 24
Peak memory 194964 kb
Host smart-14c8811d-31a9-46f4-9991-2a3da8d99f0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638231491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1638231491
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.4285838451
Short name T350
Test name
Test status
Simulation time 138047810 ps
CPU time 7.33 seconds
Started Jun 22 05:57:17 PM PDT 24
Finished Jun 22 05:57:26 PM PDT 24
Peak memory 200024 kb
Host smart-5f3b3348-7bd4-4295-a000-46a7e8d8cbf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4285838451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.4285838451
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.552472242
Short name T562
Test name
Test status
Simulation time 160800668 ps
CPU time 1.55 seconds
Started Jun 22 05:57:17 PM PDT 24
Finished Jun 22 05:57:19 PM PDT 24
Peak memory 200020 kb
Host smart-d6ee3a8c-1eb5-40b7-880a-54ea5ddcc21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552472242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.552472242
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.36831648
Short name T344
Test name
Test status
Simulation time 26269630 ps
CPU time 0.72 seconds
Started Jun 22 05:57:17 PM PDT 24
Finished Jun 22 05:57:18 PM PDT 24
Peak memory 199712 kb
Host smart-984499d5-d6dc-4207-bbf1-6bfa71dbf79e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=36831648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.36831648
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2416999509
Short name T288
Test name
Test status
Simulation time 12998418543 ps
CPU time 156.45 seconds
Started Jun 22 05:57:30 PM PDT 24
Finished Jun 22 06:00:07 PM PDT 24
Peak memory 200140 kb
Host smart-f8d5b211-9f8d-4203-8eb8-925fedffab32
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416999509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2416999509
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.767207207
Short name T279
Test name
Test status
Simulation time 14165167937 ps
CPU time 91.87 seconds
Started Jun 22 05:57:17 PM PDT 24
Finished Jun 22 05:58:49 PM PDT 24
Peak memory 200132 kb
Host smart-1de36dd7-7fff-4fbd-8582-a10bd908e3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767207207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.767207207
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3763088183
Short name T465
Test name
Test status
Simulation time 881986129 ps
CPU time 12.05 seconds
Started Jun 22 05:57:18 PM PDT 24
Finished Jun 22 05:57:31 PM PDT 24
Peak memory 200056 kb
Host smart-5e6a3f46-6ce6-45ad-b73f-068b0ece0315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763088183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3763088183
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.3773634502
Short name T430
Test name
Test status
Simulation time 104538372 ps
CPU time 1.04 seconds
Started Jun 22 05:57:28 PM PDT 24
Finished Jun 22 05:57:30 PM PDT 24
Peak memory 199096 kb
Host smart-ee5f21b4-0a39-4645-bea8-1ca8f73a5ea0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773634502 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_hmac_vectors.3773634502
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha256_vectors.2908981663
Short name T294
Test name
Test status
Simulation time 136318639688 ps
CPU time 491.68 seconds
Started Jun 22 05:57:28 PM PDT 24
Finished Jun 22 06:05:40 PM PDT 24
Peak memory 200124 kb
Host smart-1eaa33e9-b6d8-4c4b-89e7-4d878584dd55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2908981663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha256_vectors.2908981663
Directory /workspace/8.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha384_vectors.1259990418
Short name T352
Test name
Test status
Simulation time 734953554657 ps
CPU time 2123.62 seconds
Started Jun 22 05:57:30 PM PDT 24
Finished Jun 22 06:32:54 PM PDT 24
Peak memory 200380 kb
Host smart-ca1d49cb-8cb8-472b-abc0-be7254a403ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1259990418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha384_vectors.1259990418
Directory /workspace/8.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha512_vectors.282741031
Short name T366
Test name
Test status
Simulation time 174741972438 ps
CPU time 2287.31 seconds
Started Jun 22 05:57:30 PM PDT 24
Finished Jun 22 06:35:38 PM PDT 24
Peak memory 215976 kb
Host smart-fc978acf-b9f0-46c4-a58f-09262391c36e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=282741031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha512_vectors.282741031
Directory /workspace/8.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2746402771
Short name T536
Test name
Test status
Simulation time 6301586777 ps
CPU time 78.37 seconds
Started Jun 22 05:57:28 PM PDT 24
Finished Jun 22 05:58:47 PM PDT 24
Peak memory 200164 kb
Host smart-122a0bfa-dfdd-452d-8458-2a3ee078a3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746402771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2746402771
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2573564609
Short name T3
Test name
Test status
Simulation time 61097890 ps
CPU time 0.63 seconds
Started Jun 22 05:57:37 PM PDT 24
Finished Jun 22 05:57:38 PM PDT 24
Peak memory 196292 kb
Host smart-debdd80b-ef5c-4410-a8b1-d261d5b04f6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573564609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2573564609
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.3681785676
Short name T658
Test name
Test status
Simulation time 888415451 ps
CPU time 14.4 seconds
Started Jun 22 05:57:39 PM PDT 24
Finished Jun 22 05:57:53 PM PDT 24
Peak memory 200084 kb
Host smart-5b1b4c78-05cf-41fa-a254-d6b6b31c0a33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3681785676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.3681785676
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.351948563
Short name T462
Test name
Test status
Simulation time 1827580046 ps
CPU time 31.24 seconds
Started Jun 22 05:57:37 PM PDT 24
Finished Jun 22 05:58:09 PM PDT 24
Peak memory 200108 kb
Host smart-837f1583-52a7-4d49-ad91-1267cfee896f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351948563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.351948563
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1570037234
Short name T659
Test name
Test status
Simulation time 551875397 ps
CPU time 131.75 seconds
Started Jun 22 05:57:37 PM PDT 24
Finished Jun 22 05:59:49 PM PDT 24
Peak memory 470280 kb
Host smart-b7d0da95-98d0-4093-a16b-483a13a93eeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1570037234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1570037234
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3057228047
Short name T610
Test name
Test status
Simulation time 5628694202 ps
CPU time 33.39 seconds
Started Jun 22 05:57:40 PM PDT 24
Finished Jun 22 05:58:14 PM PDT 24
Peak memory 200116 kb
Host smart-090e2104-2768-40f2-9b0d-07af6555c6c6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057228047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3057228047
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3160130714
Short name T37
Test name
Test status
Simulation time 6325397655 ps
CPU time 109.64 seconds
Started Jun 22 05:57:40 PM PDT 24
Finished Jun 22 05:59:30 PM PDT 24
Peak memory 208324 kb
Host smart-36565395-7a69-413d-9bdd-0f147e91f72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160130714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3160130714
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2493365896
Short name T540
Test name
Test status
Simulation time 963732694 ps
CPU time 14.86 seconds
Started Jun 22 05:57:30 PM PDT 24
Finished Jun 22 05:57:46 PM PDT 24
Peak memory 200048 kb
Host smart-d3e742e9-a116-44dd-8fcf-99d979ada6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493365896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2493365896
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.2269212059
Short name T542
Test name
Test status
Simulation time 630586725 ps
CPU time 1.14 seconds
Started Jun 22 05:57:38 PM PDT 24
Finished Jun 22 05:57:40 PM PDT 24
Peak memory 199856 kb
Host smart-9bbc0043-c42d-4ad4-9e66-46719c3fe4d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269212059 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_hmac_vectors.2269212059
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha256_vectors.1278909462
Short name T265
Test name
Test status
Simulation time 30581173776 ps
CPU time 432.55 seconds
Started Jun 22 05:57:38 PM PDT 24
Finished Jun 22 06:04:51 PM PDT 24
Peak memory 200124 kb
Host smart-b273963a-f8df-4c86-8997-3f0db5964261
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1278909462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha256_vectors.1278909462
Directory /workspace/9.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha384_vectors.1057442913
Short name T425
Test name
Test status
Simulation time 27568581793 ps
CPU time 1602.36 seconds
Started Jun 22 05:57:40 PM PDT 24
Finished Jun 22 06:24:23 PM PDT 24
Peak memory 215708 kb
Host smart-691cfb4a-8cf6-433c-bf7b-b25c21e1af48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1057442913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha384_vectors.1057442913
Directory /workspace/9.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1485550887
Short name T118
Test name
Test status
Simulation time 1524386247 ps
CPU time 75.19 seconds
Started Jun 22 05:57:41 PM PDT 24
Finished Jun 22 05:58:57 PM PDT 24
Peak memory 200060 kb
Host smart-001b2236-643a-45a2-8cb5-82511acb5938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485550887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1485550887
Directory /workspace/9.hmac_wipe_secret/latest
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