Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	35307242	1			T1	633		T2	3074		T4	1765
all_values[1]	35307242	1			T1	633		T2	3074		T4	1765
all_values[2]	35307242	1			T1	633		T2	3074		T4	1765

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

96514

1

T1

23

T9

10

T16

498

auto[1]

105825212

1

T1

1876

T2

9222

T4

5295

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87922814

1

T1

1597

T2

7586

T4

4089

auto[1]

17998912

1

T1

302

T2

1636

T4

1206

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	29064	1			T1	1		T9	10		T18	47
all_values[0]	auto[0]	auto[1]	190	1			T1	2		T39	1		T115	2
all_values[0]	auto[1]	auto[0]	35225024	1			T1	613		T2	3068		T4	1760
all_values[0]	auto[1]	auto[1]	52964	1			T1	17		T2	6		T4	5
all_values[1]	auto[0]	auto[0]	33737	1			T1	20		T18	47		T31	457
all_values[1]	auto[0]	auto[1]	73	1			T39	1		T27	2		T64	4
all_values[1]	auto[1]	auto[0]	35269807	1			T1	613		T2	3074		T4	1765
all_values[1]	auto[1]	auto[1]	3625	1			T5	42		T6	84		T15	42
all_values[2]	auto[0]	auto[0]	16860	1			T16	1		T13	1257		T31	457
all_values[2]	auto[0]	auto[1]	16590	1			T16	497		T18	47		T39	3
all_values[2]	auto[1]	auto[0]	17348322	1			T1	350		T2	1444		T4	564
all_values[2]	auto[1]	auto[1]	17925470	1			T1	283		T2	1630		T4	1201