Group : hmac_env_pkg::hmac_env_cov::msg_len_cg
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Group : hmac_env_pkg::hmac_env_cov::msg_len_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
80.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv



Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 18 2 16 88.89
Crosses 32 8 24 75.00


Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
hmac_en 2 0 2 100.00 100 1 1 2
msg_len_lower_cp 15 1 14 93.33 100 1 1 0
msg_len_upper_cp 1 1 0 0.00 100 1 1 0


Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
msg_len_lower_cross 30 6 24 80.00 100 1 1 0
msg_len_upper_cross 2 2 0 0.00 100 1 1 0


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 105638 1 T1 22 T2 4 T4 8
auto[1] 50022 1 T1 14 T2 16 T4 2



Summary for Variable msg_len_lower_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 1 14 93.33


User Defined Bins for msg_len_lower_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
len_513 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
len_2050_plus 26287 1 T2 5 T8 19 T5 2
len_1026_2046 15487 1 T2 2 T4 2 T8 3
len_514_1022 6336 1 T8 2 T10 4 T12 4
len_2_510 24278 1 T1 14 T4 3 T8 66
len_2049 1 1 T119 1 - - - -
len_2048 37 1 T38 2 T26 3 T120 2
len_2047 2 1 T121 2 - - - -
len_1025 2 1 T122 2 - - - -
len_1024 66 1 T38 1 T26 6 T20 3
len_1023 8 1 T123 1 T124 2 T125 5
len_512 68 1 T38 2 T26 2 T126 1
len_511 1 1 T127 1 - - - -
len_1 559 1 T8 1 T10 2 T12 1
len_0 4698 1 T1 4 T2 3 T8 1



Summary for Variable msg_len_upper_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for msg_len_upper_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
len_upper 0 1 1



Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 30 6 24 80.00 6


Automatically Generated Cross Bins for msg_len_lower_cross

Uncovered bins
hmac_enmsg_len_lower_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [len_2049] 0 1 1
[auto[0]] [len_1025] 0 1 1
[auto[0]] [len_513] 0 1 1
[auto[0]] [len_511] 0 1 1
[auto[1]] [len_2047] 0 1 1
[auto[1]] [len_513] 0 1 1


Covered bins
hmac_enmsg_len_lower_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] len_2050_plus 16950 1 T2 2 T8 19 T5 1
auto[0] len_1026_2046 9026 1 T4 2 T8 3 T10 6
auto[0] len_514_1022 3483 1 T8 2 T10 4 T12 4
auto[0] len_2_510 20911 1 T1 10 T4 2 T8 66
auto[0] len_2048 25 1 T38 2 T26 2 T120 2
auto[0] len_2047 2 1 T121 2 - - - -
auto[0] len_1024 41 1 T26 3 T20 2 T120 1
auto[0] len_1023 6 1 T123 1 T124 2 T125 3
auto[0] len_512 34 1 T38 1 T26 1 T128 1
auto[0] len_1 153 1 T8 1 T10 2 T12 1
auto[0] len_0 2188 1 T1 1 T8 1 T12 1
auto[1] len_2050_plus 9337 1 T2 3 T5 1 T16 3
auto[1] len_1026_2046 6461 1 T2 2 T16 2 T13 1
auto[1] len_514_1022 2853 1 T16 1 T38 101 T39 3
auto[1] len_2_510 3367 1 T1 4 T4 1 T5 1
auto[1] len_2049 1 1 T119 1 - - - -
auto[1] len_2048 12 1 T26 1 T27 1 T72 1
auto[1] len_1025 2 1 T122 2 - - - -
auto[1] len_1024 25 1 T38 1 T26 3 T20 1
auto[1] len_1023 2 1 T125 2 - - - -
auto[1] len_512 34 1 T38 1 T26 1 T126 1
auto[1] len_511 1 1 T127 1 - - - -
auto[1] len_1 406 1 T129 2 T130 8 T131 2
auto[1] len_0 2510 1 T1 3 T2 3 T5 1



Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 2 0 0.00 2


Automatically Generated Cross Bins for msg_len_upper_cross

Uncovered bins
hmac_enmsg_len_upper_cpCOUNTAT LEASTNUMBERSTATUS
* * -- -- 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%