Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17489352

1

T1

303

T2

1840

T4

896

auto[1]

1202668

1

T1

262

T2

1219

T4

859

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1223401

1

T1

243

T2

658

T5

5

auto[1]

17468619

1

T1

322

T2

2401

T4

1755

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16984760

1

T1

319

T2

726

T4

328

auto[1]

1707260

1

T1

246

T2

2333

T4

1427

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	16517722	1			T1	465		T2	2887		T4	1409
fifo_depth[1]	481375	1			T1	12		T2	64		T4	33
fifo_depth[2]	351056	1			T1	6		T2	58		T4	42
fifo_depth[3]	270581	1			T1	9		T2	33		T4	40
fifo_depth[4]	208027	1			T1	8		T2	11		T4	34
fifo_depth[5]	161163	1			T1	8		T2	4		T4	34
fifo_depth[6]	138770	1			T1	6		T2	2		T4	42
fifo_depth[7]	122865	1			T1	5		T4	33		T10	1971

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2174298

1

T1

100

T2

172

T4

346

auto[1]

16517722

1

T1

465

T2

2887

T4

1409

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18687310

1

T1

565

T2

3059

T4

1755

auto[1]

4710

1

T15

3

T19

3

T20

2

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

29920

1

T1

16

T9

2

T16

73

auto[0]

auto[0]

auto[0]

auto[1]

35242

1

T1

8

T9

4

T13

249

auto[0]

auto[0]

auto[1]

auto[0]

1851905

1

T1

21

T2

57

T8

927

auto[0]

auto[0]

auto[1]

auto[1]

29900

1

T1

10

T4

203

T5

2

auto[0]

auto[1]

auto[0]

auto[0]

59656

1

T1

11

T2

29

T9

5

auto[0]

auto[1]

auto[0]

auto[1]

60755

1

T5

1

T9

4

T16

23

auto[0]

auto[1]

auto[1]

auto[0]

51100

1

T1

8

T4

143

T9

2

auto[0]

auto[1]

auto[1]

auto[1]

55820

1

T1

26

T2

86

T16

13

auto[1]

auto[0]

auto[0]

auto[0]

153591

1

T1

95

T2

1

T9

52

auto[1]

auto[0]

auto[0]

auto[1]

140195

1

T1

64

T5

1

T9

94

auto[1]

auto[0]

auto[1]

auto[0]

14621331

1

T1

30

T2

668

T4

9

auto[1]

auto[0]

auto[1]

auto[1]

122676

1

T1

75

T4

116

T16

431

auto[1]

auto[1]

auto[0]

auto[0]

359036

1

T1

24

T2

628

T5

1

auto[1]

auto[1]

auto[0]

auto[1]

385006

1

T1

25

T5

2

T9

107

auto[1]

auto[1]

auto[1]

auto[0]

362813

1

T1

98

T2

457

T4

744

auto[1]

auto[1]

auto[1]

auto[1]

373074

1

T1

54

T2

1133

T4

540

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

183141

1

T1

111

T2

1

T9

54

auto[0]

auto[0]

auto[0]

auto[1]

174581

1

T1

72

T5

1

T9

98

auto[0]

auto[0]

auto[1]

auto[0]

16472334

1

T1

51

T2

725

T4

9

auto[0]

auto[0]

auto[1]

auto[1]

151779

1

T1

85

T4

319

T5

2

auto[0]

auto[1]

auto[0]

auto[0]

418158

1

T1

35

T2

657

T5

1

auto[0]

auto[1]

auto[0]

auto[1]

445171

1

T1

25

T5

3

T9

111

auto[0]

auto[1]

auto[1]

auto[0]

413543

1

T1

106

T2

457

T4

887

auto[0]

auto[1]

auto[1]

auto[1]

428603

1

T1

80

T2

1219

T4

540

auto[1]

auto[0]

auto[0]

auto[0]

370

1

T22

2

T120

20

T82

1

auto[1]

auto[0]

auto[0]

auto[1]

856

1

T15

2

T19

2

T20

1

auto[1]

auto[0]

auto[1]

auto[0]

902

1

T19

1

T126

11

T120

2

auto[1]

auto[0]

auto[1]

auto[1]

797

1

T20

1

T126

1

T120

37

auto[1]

auto[1]

auto[0]

auto[0]

534

1

T144

22

T145

14

T83

20

auto[1]

auto[1]

auto[0]

auto[1]

590

1

T120

234

T24

1

T145

12

auto[1]

auto[1]

auto[1]

auto[0]

370

1

T15

1

T126

210

T83

2

auto[1]

auto[1]

auto[1]

auto[1]

291

1

T144

3

T146

1

T83

2

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	153591	1			T1	95		T2	1		T9	52
fifo_depth[0]	auto[0]	auto[0]	auto[1]	140195	1			T1	64		T5	1		T9	94
fifo_depth[0]	auto[0]	auto[1]	auto[0]	14621331	1			T1	30		T2	668		T4	9
fifo_depth[0]	auto[0]	auto[1]	auto[1]	122676	1			T1	75		T4	116		T16	431
fifo_depth[0]	auto[1]	auto[0]	auto[0]	359036	1			T1	24		T2	628		T5	1
fifo_depth[0]	auto[1]	auto[0]	auto[1]	385006	1			T1	25		T5	2		T9	107
fifo_depth[0]	auto[1]	auto[1]	auto[0]	362813	1			T1	98		T2	457		T4	744
fifo_depth[0]	auto[1]	auto[1]	auto[1]	373074	1			T1	54		T2	1133		T4	540
fifo_depth[1]	auto[0]	auto[0]	auto[0]	3814	1			T1	3		T16	45		T13	56
fifo_depth[1]	auto[0]	auto[0]	auto[1]	3264	1			T1	2		T9	2		T13	77
fifo_depth[1]	auto[0]	auto[1]	auto[0]	448078	1			T1	1		T2	29		T8	741
fifo_depth[1]	auto[0]	auto[1]	auto[1]	3138	1			T1	1		T4	16		T16	8
fifo_depth[1]	auto[1]	auto[0]	auto[0]	6032	1			T1	1		T2	13		T9	4
fifo_depth[1]	auto[1]	auto[0]	auto[1]	5782	1			T9	1		T16	9		T13	13
fifo_depth[1]	auto[1]	auto[1]	auto[0]	5213	1			T1	1		T4	17		T16	30
fifo_depth[1]	auto[1]	auto[1]	auto[1]	6054	1			T1	3		T2	22		T16	10
fifo_depth[2]	auto[0]	auto[0]	auto[0]	3050	1			T1	1		T9	1		T16	15
fifo_depth[2]	auto[0]	auto[0]	auto[1]	3082	1			T1	1		T13	75		T18	1
fifo_depth[2]	auto[0]	auto[1]	auto[0]	320724	1			T1	1		T2	19		T8	162
fifo_depth[2]	auto[0]	auto[1]	auto[1]	2714	1			T4	23		T16	4		T17	14
fifo_depth[2]	auto[1]	auto[0]	auto[0]	5631	1			T1	1		T2	8		T16	8
fifo_depth[2]	auto[1]	auto[0]	auto[1]	5503	1			T9	1		T16	6		T13	15
fifo_depth[2]	auto[1]	auto[1]	auto[0]	4864	1			T4	19		T9	2		T16	18
fifo_depth[2]	auto[1]	auto[1]	auto[1]	5488	1			T1	2		T2	31		T16	3
fifo_depth[3]	auto[0]	auto[0]	auto[0]	2198	1			T1	2		T9	1		T16	12
fifo_depth[3]	auto[0]	auto[0]	auto[1]	2334	1			T1	1		T9	2		T13	52
fifo_depth[3]	auto[0]	auto[1]	auto[0]	244782	1			T1	2		T2	7		T8	18
fifo_depth[3]	auto[0]	auto[1]	auto[1]	1853	1			T4	22		T16	3		T13	11
fifo_depth[3]	auto[1]	auto[0]	auto[0]	5096	1			T1	1		T2	8		T9	1
fifo_depth[3]	auto[1]	auto[0]	auto[1]	5017	1			T9	1		T16	5		T13	6
fifo_depth[3]	auto[1]	auto[1]	auto[0]	4388	1			T1	1		T4	18		T16	7
fifo_depth[3]	auto[1]	auto[1]	auto[1]	4913	1			T1	2		T2	18		T56	76
fifo_depth[4]	auto[0]	auto[0]	auto[0]	2069	1			T1	2		T16	1		T13	9
fifo_depth[4]	auto[0]	auto[0]	auto[1]	2189	1			T1	1		T13	30		T38	5
fifo_depth[4]	auto[0]	auto[1]	auto[0]	183340	1			T1	1		T2	1		T8	5
fifo_depth[4]	auto[0]	auto[1]	auto[1]	1760	1			T1	1		T4	21		T16	1
fifo_depth[4]	auto[1]	auto[0]	auto[0]	4805	1			T16	1		T13	4		T18	1
fifo_depth[4]	auto[1]	auto[0]	auto[1]	4901	1			T9	1		T16	3		T38	21
fifo_depth[4]	auto[1]	auto[1]	auto[0]	4298	1			T1	1		T4	13		T18	1
fifo_depth[4]	auto[1]	auto[1]	auto[1]	4665	1			T1	2		T2	10		T18	1
fifo_depth[5]	auto[0]	auto[0]	auto[0]	1398	1			T1	1		T13	1		T56	3
fifo_depth[5]	auto[0]	auto[0]	auto[1]	1891	1			T13	12		T38	5		T31	30
fifo_depth[5]	auto[0]	auto[1]	auto[0]	138841	1			T1	3		T2	1		T8	1
fifo_depth[5]	auto[0]	auto[1]	auto[1]	1431	1			T1	1		T4	17		T17	1
fifo_depth[5]	auto[1]	auto[0]	auto[0]	4795	1			T1	1		T38	4		T142	13
fifo_depth[5]	auto[1]	auto[0]	auto[1]	4653	1			T38	6		T31	41		T129	123
fifo_depth[5]	auto[1]	auto[1]	auto[0]	3966	1			T1	2		T4	17		T16	1
fifo_depth[5]	auto[1]	auto[1]	auto[1]	4188	1			T2	3		T56	95		T31	16
fifo_depth[6]	auto[0]	auto[0]	auto[0]	1415	1			T1	1		T13	1		T56	3
fifo_depth[6]	auto[0]	auto[0]	auto[1]	1673	1			T13	2		T38	4		T31	23
fifo_depth[6]	auto[0]	auto[1]	auto[0]	117017	1			T1	2		T10	2167		T12	2591
fifo_depth[6]	auto[0]	auto[1]	auto[1]	1368	1			T1	1		T4	24		T17	12
fifo_depth[6]	auto[1]	auto[0]	auto[0]	4708	1			T38	5		T142	23		T35	1
fifo_depth[6]	auto[1]	auto[0]	auto[1]	4505	1			T38	1		T31	41		T129	118
fifo_depth[6]	auto[1]	auto[1]	auto[0]	3870	1			T4	18		T38	6		T31	19
fifo_depth[6]	auto[1]	auto[1]	auto[1]	4214	1			T1	2		T2	2		T56	88
fifo_depth[7]	auto[0]	auto[0]	auto[0]	1282	1			T1	2		T13	1		T56	1
fifo_depth[7]	auto[0]	auto[0]	auto[1]	1528	1			T1	1		T13	1		T38	1
fifo_depth[7]	auto[0]	auto[1]	auto[0]	102196	1			T1	1		T10	1971		T12	2417
fifo_depth[7]	auto[0]	auto[1]	auto[1]	1259	1			T1	1		T4	21		T17	1
fifo_depth[7]	auto[1]	auto[0]	auto[0]	4379	1			T38	3		T142	11		T130	74
fifo_depth[7]	auto[1]	auto[0]	auto[1]	4444	1			T13	1		T38	1		T31	48
fifo_depth[7]	auto[1]	auto[1]	auto[0]	3749	1			T4	12		T56	1		T38	3
fifo_depth[7]	auto[1]	auto[1]	auto[1]	4028	1			T56	82		T31	15		T26	1