Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	35307242	1			T1	633		T2	3074		T4	1765
all_pins[1]	35307242	1			T1	633		T2	3074		T4	1765
all_pins[2]	35307242	1			T1	633		T2	3074		T4	1765

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	87939140	1			T1	1598		T2	7586		T4	4089
values[0x1]	17982586	1			T1	301		T2	1636		T4	1206
transitions[0x0=>0x1]	17982415	1			T1	301		T2	1636		T4	1206
transitions[0x1=>0x0]	17982432	1			T1	301		T2	1636		T4	1206

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	35253843	1			T1	615		T2	3068		T4	1760
all_pins[0]	values[0x1]	53399	1			T1	18		T2	6		T4	5
all_pins[0]	transitions[0x0=>0x1]	53368	1			T1	18		T2	6		T4	5
all_pins[0]	transitions[0x1=>0x0]	17925456	1			T1	283		T2	1630		T4	1201
all_pins[1]	values[0x0]	35303525	1			T1	633		T2	3074		T4	1765
all_pins[1]	values[0x1]	3717	1			T5	43		T6	86		T15	43
all_pins[1]	transitions[0x0=>0x1]	3592	1			T5	42		T6	84		T15	42
all_pins[1]	transitions[0x1=>0x0]	53274	1			T1	18		T2	6		T4	5
all_pins[2]	values[0x0]	17381772	1			T1	350		T2	1444		T4	564
all_pins[2]	values[0x1]	17925470	1			T1	283		T2	1630		T4	1201
all_pins[2]	transitions[0x0=>0x1]	17925455	1			T1	283		T2	1630		T4	1201
all_pins[2]	transitions[0x1=>0x0]	3702	1			T5	43		T6	86		T15	43