Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 379 1 T39 10 T27 7 T64 24
all_values[1] 379 1 T39 10 T27 7 T64 24
all_values[2] 379 1 T39 10 T27 7 T64 24


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 633 1 T39 17 T27 11 T64 50
auto[1] 504 1 T39 13 T27 10 T64 22


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 405 1 T39 14 T27 9 T64 30
auto[1] 732 1 T39 16 T27 12 T64 42


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 633 1 T39 19 T27 13 T64 45
auto[1] 504 1 T39 11 T27 8 T64 27


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 79 1 T39 6 T27 5 T64 8
all_values[0] auto[0] auto[0] auto[1] 44 1 T39 1 T64 4 T133 2
all_values[0] auto[0] auto[1] auto[0] 59 1 T64 1 T68 1 T133 5
all_values[0] auto[0] auto[1] auto[1] 26 1 T64 1 T68 1 T134 3
all_values[0] auto[1] auto[0] auto[1] 103 1 T39 2 T27 1 T64 6
all_values[0] auto[1] auto[1] auto[1] 68 1 T39 1 T27 1 T64 4
all_values[1] auto[0] auto[0] auto[0] 62 1 T39 2 T27 1 T64 7
all_values[1] auto[0] auto[0] auto[1] 40 1 T39 1 T27 1 T64 2
all_values[1] auto[0] auto[1] auto[0] 64 1 T39 4 T27 1 T64 6
all_values[1] auto[0] auto[1] auto[1] 45 1 T39 1 T27 1 T64 2
all_values[1] auto[1] auto[0] auto[1] 83 1 T39 2 T27 2 T64 5
all_values[1] auto[1] auto[1] auto[1] 85 1 T27 1 T64 2 T68 3
all_values[2] auto[0] auto[0] auto[0] 81 1 T39 2 T64 8 T68 3
all_values[2] auto[0] auto[0] auto[1] 44 1 T39 1 T27 1 T64 5
all_values[2] auto[0] auto[1] auto[0] 60 1 T27 2 T68 2 T134 3
all_values[2] auto[0] auto[1] auto[1] 29 1 T39 1 T27 1 T64 1
all_values[2] auto[1] auto[0] auto[1] 97 1 T64 5 T133 3 T70 1
all_values[2] auto[1] auto[1] auto[1] 68 1 T39 6 T27 3 T64 5


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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