Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.47	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	2	18	90.00
Crosses	82	22	60	73.17

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	1	4	80.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	1	6	85.71	100	1	1	0
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	8	0	8	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	11	24	68.57	100	1	1	0
key_length_x_digest_size	35	11	24	68.57	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	1	4	80.00

User Defined Bins for digest_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
sha2_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_none	82	1			T37	2		T32	1		T33	1
sha2_512	20515	1			T1	3		T2	1		T5	1
sha2_384	20549	1			T1	7		T2	2		T4	1
sha2_256	11269	1			T1	5		T2	3		T4	3

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49966

1

T1

10

T2

4

T4

2

auto[1]

2449

1

T1

5

T2

2

T4

2

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2423

1

T1

9

T2

2

T5

1

auto[1]

49992

1

T1

6

T2

4

T4

4

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

2379

1

T1

5

T2

4

T4

1

disabled

50036

1

T1

10

T2

2

T4

3

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for key_length

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
key_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	947	1			T1	4		T2	1		T4	1
key_1024	643	1			T1	1		T9	1		T16	1
key_512	816	1			T1	4		T2	2		T9	3
key_384	872	1			T1	4		T2	1		T4	2
key_256	48266	1			T1	1		T2	1		T8	194
key_128	871	1			T1	1		T2	1		T4	1

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

52240

1

T1

15

T2

6

T4

4

disabled

175

1

T37

2

T32

2

T33

3

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
enabled	auto[0]	auto[0]	499	1			T1	2		T2	1		T9	1
enabled	auto[0]	auto[1]	532	1			T5	1		T9	2		T16	1
enabled	auto[1]	auto[0]	747	1			T1	1		T2	1		T4	1
enabled	auto[1]	auto[1]	601	1			T1	2		T2	2		T16	1
disabled	auto[0]	auto[0]	694	1			T1	6		T2	1		T9	2
disabled	auto[0]	auto[1]	698	1			T1	1		T9	4		T13	5
disabled	auto[1]	auto[0]	48026	1			T1	1		T2	1		T4	1
disabled	auto[1]	auto[1]	618	1			T1	2		T4	2		T5	2

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

2280

1

T1

5

T2

4

T4

1

enabled

disabled

99

1

T37

1

T32

1

T34

4

disabled

disabled

76

1

T37

1

T32

1

T33

3

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

49960

1

T1

10

T2

2

T4

3

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	11	24	68.57	11
Automatically Generated Cross Bins	34	11	23	67.65	11
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid]	--	--	6

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_none	29	1			T37	1		T34	4		T116	1
key_none	sha2_512	290	1			T1	1		T5	1		T16	1
key_none	sha2_384	309	1			T1	2		T9	1		T13	3
key_none	sha2_256	319	1			T1	1		T2	1		T4	1
key_1024	sha2_none	5	1			T37	1		T83	1		T64	1
key_1024	sha2_512	269	1			T1	1		T9	1		T16	1
key_1024	sha2_384	263	1			T13	2		T6	1		T31	2
key_512	sha2_none	9	1			T32	1		T33	1		T34	1
key_512	sha2_512	255	1			T1	1		T9	2		T16	2
key_512	sha2_384	282	1			T1	2		T2	1		T9	1
key_512	sha2_256	270	1			T1	1		T2	1		T16	1
key_384	sha2_none	14	1			T117	1		T116	2		T118	1
key_384	sha2_512	276	1			T13	1		T18	1		T56	2
key_384	sha2_384	281	1			T1	2		T4	1		T9	1
key_384	sha2_256	301	1			T1	2		T2	1		T4	1
key_256	sha2_none	13	1			T116	1		T83	1		T64	1
key_256	sha2_512	19143	1			T10	386		T16	2		T13	2
key_256	sha2_384	19161	1			T1	1		T2	1		T5	1
key_256	sha2_256	9949	1			T8	194		T16	2		T14	194
key_128	sha2_none	12	1			T34	1		T117	1		T118	1
key_128	sha2_512	282	1			T2	1		T9	1		T18	3
key_128	sha2_384	253	1			T5	1		T9	1		T17	1
key_128	sha2_256	324	1			T1	1		T4	1		T9	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

106

1

T18

1

T38

2

T31

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	11	24	68.57	11

Automatically Generated Cross Bins for key_length_x_digest_size

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid]	--	--	6

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_none	29	1			T37	1		T34	4		T116	1
key_none	sha2_512	290	1			T1	1		T5	1		T16	1
key_none	sha2_384	309	1			T1	2		T9	1		T13	3
key_none	sha2_256	319	1			T1	1		T2	1		T4	1
key_1024	sha2_none	5	1			T37	1		T83	1		T64	1
key_1024	sha2_512	269	1			T1	1		T9	1		T16	1
key_1024	sha2_384	263	1			T13	2		T6	1		T31	2
key_1024	sha2_256	106	1			T18	1		T38	2		T31	2
key_512	sha2_none	9	1			T32	1		T33	1		T34	1
key_512	sha2_512	255	1			T1	1		T9	2		T16	2
key_512	sha2_384	282	1			T1	2		T2	1		T9	1
key_512	sha2_256	270	1			T1	1		T2	1		T16	1
key_384	sha2_none	14	1			T117	1		T116	2		T118	1
key_384	sha2_512	276	1			T13	1		T18	1		T56	2
key_384	sha2_384	281	1			T1	2		T4	1		T9	1
key_384	sha2_256	301	1			T1	2		T2	1		T4	1
key_256	sha2_none	13	1			T116	1		T83	1		T64	1
key_256	sha2_512	19143	1			T10	386		T16	2		T13	2
key_256	sha2_384	19161	1			T1	1		T2	1		T5	1
key_256	sha2_256	9949	1			T8	194		T16	2		T14	194
key_128	sha2_none	12	1			T34	1		T117	1		T118	1
key_128	sha2_512	282	1			T2	1		T9	1		T18	3
key_128	sha2_384	253	1			T5	1		T9	1		T17	1
key_128	sha2_256	324	1			T1	1		T4	1		T9	1