Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.58 95.85 92.94 100.00 74.36 91.89 99.49 93.58


Total test records in report: 775
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html
T753 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3069424176 Jun 23 06:01:46 PM PDT 24 Jun 23 06:01:55 PM PDT 24 218436812 ps
T138 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1621365073 Jun 23 06:02:07 PM PDT 24 Jun 23 06:02:10 PM PDT 24 156720630 ps
T754 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.362463723 Jun 23 06:02:05 PM PDT 24 Jun 23 06:02:10 PM PDT 24 732653914 ps
T755 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3988687311 Jun 23 06:01:53 PM PDT 24 Jun 23 06:01:55 PM PDT 24 45314520 ps
T756 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.4007126657 Jun 23 06:01:51 PM PDT 24 Jun 23 06:01:54 PM PDT 24 256698177 ps
T757 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2527147467 Jun 23 06:02:01 PM PDT 24 Jun 23 06:02:03 PM PDT 24 87178442 ps
T139 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4148493746 Jun 23 06:01:55 PM PDT 24 Jun 23 06:01:59 PM PDT 24 94788798 ps
T758 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.53861310 Jun 23 06:02:08 PM PDT 24 Jun 23 06:02:11 PM PDT 24 390108935 ps
T759 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.57680440 Jun 23 06:01:47 PM PDT 24 Jun 23 06:01:49 PM PDT 24 178323580 ps
T760 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3502611960 Jun 23 06:02:21 PM PDT 24 Jun 23 06:02:27 PM PDT 24 270614731 ps
T761 /workspace/coverage/cover_reg_top/34.hmac_intr_test.823957082 Jun 23 06:02:27 PM PDT 24 Jun 23 06:02:28 PM PDT 24 11963770 ps
T762 /workspace/coverage/cover_reg_top/30.hmac_intr_test.3179195364 Jun 23 06:02:23 PM PDT 24 Jun 23 06:02:24 PM PDT 24 31972321 ps
T763 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2700650301 Jun 23 06:01:53 PM PDT 24 Jun 23 06:01:55 PM PDT 24 150392688 ps
T764 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4123170339 Jun 23 06:02:05 PM PDT 24 Jun 23 06:02:10 PM PDT 24 268451481 ps
T765 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1073334760 Jun 23 06:02:02 PM PDT 24 Jun 23 06:02:07 PM PDT 24 1268117840 ps
T766 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4153679475 Jun 23 06:01:56 PM PDT 24 Jun 23 06:01:58 PM PDT 24 106256102 ps
T767 /workspace/coverage/cover_reg_top/38.hmac_intr_test.61704682 Jun 23 06:02:29 PM PDT 24 Jun 23 06:02:30 PM PDT 24 17719438 ps
T768 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1103378243 Jun 23 06:02:06 PM PDT 24 Jun 23 06:02:07 PM PDT 24 18198327 ps
T769 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3877474317 Jun 23 06:02:06 PM PDT 24 Jun 23 06:02:07 PM PDT 24 78627673 ps
T770 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1709349378 Jun 23 06:02:15 PM PDT 24 Jun 23 06:02:17 PM PDT 24 73190547 ps
T771 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.4066230211 Jun 23 06:02:14 PM PDT 24 Jun 23 06:02:18 PM PDT 24 579183987 ps
T772 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3862102086 Jun 23 06:01:48 PM PDT 24 Jun 23 06:01:50 PM PDT 24 147054607 ps
T773 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1533238630 Jun 23 06:02:12 PM PDT 24 Jun 23 06:02:16 PM PDT 24 82480211 ps
T774 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1800074237 Jun 23 06:02:07 PM PDT 24 Jun 23 06:02:08 PM PDT 24 15148270 ps
T775 /workspace/coverage/cover_reg_top/12.hmac_intr_test.541449138 Jun 23 06:02:09 PM PDT 24 Jun 23 06:02:10 PM PDT 24 25949576 ps

Test location /workspace/coverage/default/35.hmac_smoke.3378634287
Short name T1
Test name
Test status
Simulation time 907148525 ps
CPU time 8.68 seconds
Started Jun 23 05:12:30 PM PDT 24
Finished Jun 23 05:12:39 PM PDT 24
Peak memory 200260 kb
Host smart-b70213a9-e6f0-4b02-9df7-9af8a74b6101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378634287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3378634287
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.4111578845
Short name T26
Test name
Test status
Simulation time 9148095960 ps
CPU time 58.64 seconds
Started Jun 23 05:12:28 PM PDT 24
Finished Jun 23 05:13:27 PM PDT 24
Peak memory 200080 kb
Host smart-7b8ba3b2-31b3-433a-bc5f-0415543396a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111578845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.4111578845
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.830312069
Short name T62
Test name
Test status
Simulation time 150459883018 ps
CPU time 726.65 seconds
Started Jun 23 06:02:06 PM PDT 24
Finished Jun 23 06:14:13 PM PDT 24
Peak memory 216144 kb
Host smart-cd5ee7a6-3b60-4266-82aa-4085af7a46fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830312069 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.830312069
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2609004980
Short name T39
Test name
Test status
Simulation time 348232130 ps
CPU time 6.83 seconds
Started Jun 23 05:11:39 PM PDT 24
Finished Jun 23 05:11:46 PM PDT 24
Peak memory 200060 kb
Host smart-46440964-df08-4847-90e8-5d70a5679924
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609004980 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2609004980
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.666279020
Short name T20
Test name
Test status
Simulation time 1121955971 ps
CPU time 51.5 seconds
Started Jun 23 05:11:40 PM PDT 24
Finished Jun 23 05:12:31 PM PDT 24
Peak memory 200056 kb
Host smart-aa91791d-7cf7-4b5e-bc2c-55328eceecd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=666279020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.666279020
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.832809175
Short name T79
Test name
Test status
Simulation time 305643042 ps
CPU time 2.76 seconds
Started Jun 23 06:02:18 PM PDT 24
Finished Jun 23 06:02:21 PM PDT 24
Peak memory 199620 kb
Host smart-6d78c519-91b9-41d4-8e91-df67b11631ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832809175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.832809175
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1515072612
Short name T83
Test name
Test status
Simulation time 15839609106 ps
CPU time 883.5 seconds
Started Jun 23 05:11:14 PM PDT 24
Finished Jun 23 05:25:58 PM PDT 24
Peak memory 713696 kb
Host smart-60902ab7-dffe-4512-b157-d5a9d59c1c23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515072612 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1515072612
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.4259957522
Short name T16
Test name
Test status
Simulation time 15320234102 ps
CPU time 55.89 seconds
Started Jun 23 05:12:04 PM PDT 24
Finished Jun 23 05:13:00 PM PDT 24
Peak memory 200148 kb
Host smart-9242fd8c-3cf3-44f1-9e0d-6ee78d356278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259957522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.4259957522
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.222877480
Short name T40
Test name
Test status
Simulation time 70863310 ps
CPU time 0.92 seconds
Started Jun 23 05:11:06 PM PDT 24
Finished Jun 23 05:11:08 PM PDT 24
Peak memory 218000 kb
Host smart-aab0f0e2-9b21-4d97-8af4-c982f6209b18
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222877480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.222877480
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3469982286
Short name T88
Test name
Test status
Simulation time 61826676 ps
CPU time 0.8 seconds
Started Jun 23 06:02:03 PM PDT 24
Finished Jun 23 06:02:04 PM PDT 24
Peak memory 199168 kb
Host smart-80924322-624d-4ea7-8b35-fe1509c7525a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469982286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3469982286
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/default/36.hmac_error.4054706811
Short name T35
Test name
Test status
Simulation time 1265575092 ps
CPU time 72.12 seconds
Started Jun 23 05:12:37 PM PDT 24
Finished Jun 23 05:13:50 PM PDT 24
Peak memory 199968 kb
Host smart-de59f5d9-39e4-4e34-a128-f46533fa61fb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054706811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.4054706811
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.65513297
Short name T134
Test name
Test status
Simulation time 15231416 ps
CPU time 0.59 seconds
Started Jun 23 06:01:49 PM PDT 24
Finished Jun 23 06:01:50 PM PDT 24
Peak memory 194460 kb
Host smart-b016c642-ac00-4846-ae68-66f96a7a17ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65513297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.65513297
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/default/40.hmac_error.1614700921
Short name T34
Test name
Test status
Simulation time 2594934415 ps
CPU time 141.17 seconds
Started Jun 23 05:12:58 PM PDT 24
Finished Jun 23 05:15:19 PM PDT 24
Peak memory 200084 kb
Host smart-9607c0e7-c1fc-43f4-901e-94fc71827fc2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614700921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1614700921
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_alert_test.749240219
Short name T3
Test name
Test status
Simulation time 23485493 ps
CPU time 0.57 seconds
Started Jun 23 05:11:21 PM PDT 24
Finished Jun 23 05:11:22 PM PDT 24
Peak memory 196024 kb
Host smart-73dbc65d-cc2a-4ea2-89de-064e2dd3912f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749240219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.749240219
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4148493746
Short name T139
Test name
Test status
Simulation time 94788798 ps
CPU time 2.81 seconds
Started Jun 23 06:01:55 PM PDT 24
Finished Jun 23 06:01:59 PM PDT 24
Peak memory 199704 kb
Host smart-aeba96b5-a3c1-40e6-ba3f-b34c8c730a12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148493746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.4148493746
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1123416220
Short name T125
Test name
Test status
Simulation time 7488379921 ps
CPU time 102.95 seconds
Started Jun 23 05:12:17 PM PDT 24
Finished Jun 23 05:14:00 PM PDT 24
Peak memory 200140 kb
Host smart-525f75df-a7fb-4abe-98b1-a3e7986af95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123416220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1123416220
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.4215593058
Short name T129
Test name
Test status
Simulation time 1435844383 ps
CPU time 412.06 seconds
Started Jun 23 05:11:06 PM PDT 24
Finished Jun 23 05:17:58 PM PDT 24
Peak memory 676876 kb
Host smart-2e1b61b5-378e-41bd-a34e-27c159666ceb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4215593058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.4215593058
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.469783192
Short name T500
Test name
Test status
Simulation time 4305010776 ps
CPU time 58.81 seconds
Started Jun 23 05:11:06 PM PDT 24
Finished Jun 23 05:12:05 PM PDT 24
Peak memory 200092 kb
Host smart-29d67cd2-55f6-4573-a4a0-80d376064f33
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469783192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.469783192
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1086751616
Short name T127
Test name
Test status
Simulation time 1155525101 ps
CPU time 47.32 seconds
Started Jun 23 05:11:24 PM PDT 24
Finished Jun 23 05:12:11 PM PDT 24
Peak memory 200048 kb
Host smart-d96df2d9-270f-4c63-a8b7-751b7f8e657a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1086751616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1086751616
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.389351083
Short name T120
Test name
Test status
Simulation time 3939597052 ps
CPU time 52.46 seconds
Started Jun 23 05:11:10 PM PDT 24
Finished Jun 23 05:12:03 PM PDT 24
Peak memory 200140 kb
Host smart-2411fd50-2c8a-4dd2-b4e6-6f83973b8901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389351083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.389351083
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3377127291
Short name T119
Test name
Test status
Simulation time 10731247581 ps
CPU time 56.8 seconds
Started Jun 23 05:11:07 PM PDT 24
Finished Jun 23 05:12:05 PM PDT 24
Peak memory 200140 kb
Host smart-87a21af3-3a37-42bc-a6ae-f920dbcc9a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377127291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3377127291
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.774170993
Short name T122
Test name
Test status
Simulation time 31516777294 ps
CPU time 1313.78 seconds
Started Jun 23 05:12:54 PM PDT 24
Finished Jun 23 05:34:48 PM PDT 24
Peak memory 722992 kb
Host smart-f18b08fa-202d-43a0-b458-1b45caceef6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=774170993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.774170993
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3230070715
Short name T121
Test name
Test status
Simulation time 15006893474 ps
CPU time 107.72 seconds
Started Jun 23 05:11:18 PM PDT 24
Finished Jun 23 05:13:07 PM PDT 24
Peak memory 200156 kb
Host smart-4c85a094-f11e-4f7c-ae88-6166ce776dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230070715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3230070715
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1748068687
Short name T109
Test name
Test status
Simulation time 1930339079 ps
CPU time 41.95 seconds
Started Jun 23 05:11:01 PM PDT 24
Finished Jun 23 05:11:43 PM PDT 24
Peak memory 200020 kb
Host smart-b82332f9-28cd-4e57-b0d3-cb9ab048444b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748068687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1748068687
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3009815182
Short name T80
Test name
Test status
Simulation time 1907901291 ps
CPU time 4.34 seconds
Started Jun 23 06:02:08 PM PDT 24
Finished Jun 23 06:02:12 PM PDT 24
Peak memory 199604 kb
Host smart-3092c367-bc92-48cf-bf32-428d4b671b7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009815182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3009815182
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.23752320
Short name T10
Test name
Test status
Simulation time 131750913006 ps
CPU time 1800.61 seconds
Started Jun 23 05:11:07 PM PDT 24
Finished Jun 23 05:41:09 PM PDT 24
Peak memory 215636 kb
Host smart-c2595368-5d3c-4467-ac93-7b06a7099861
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=23752320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.23752320
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1838474083
Short name T666
Test name
Test status
Simulation time 730885745 ps
CPU time 3.22 seconds
Started Jun 23 06:01:44 PM PDT 24
Finished Jun 23 06:01:48 PM PDT 24
Peak memory 199532 kb
Host smart-b7cb1551-4bc4-4001-8ccd-96db71e3a295
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838474083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1838474083
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3069424176
Short name T753
Test name
Test status
Simulation time 218436812 ps
CPU time 9.59 seconds
Started Jun 23 06:01:46 PM PDT 24
Finished Jun 23 06:01:55 PM PDT 24
Peak memory 199588 kb
Host smart-6baa7b92-1538-4fc5-a1aa-64fbc6bae522
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069424176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3069424176
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.537282567
Short name T731
Test name
Test status
Simulation time 51706808 ps
CPU time 0.83 seconds
Started Jun 23 06:01:43 PM PDT 24
Finished Jun 23 06:01:44 PM PDT 24
Peak memory 199024 kb
Host smart-8a728358-8518-4264-ab2d-53f0133efc93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537282567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.537282567
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.542019235
Short name T63
Test name
Test status
Simulation time 543560674628 ps
CPU time 475.61 seconds
Started Jun 23 06:01:43 PM PDT 24
Finished Jun 23 06:09:39 PM PDT 24
Peak memory 215924 kb
Host smart-53ca7457-5aac-4f5a-95b3-526f782c6742
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542019235 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.542019235
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2646390949
Short name T103
Test name
Test status
Simulation time 39614952 ps
CPU time 0.7 seconds
Started Jun 23 06:01:44 PM PDT 24
Finished Jun 23 06:01:45 PM PDT 24
Peak memory 197396 kb
Host smart-bbe4fce0-d95a-4f1b-ba18-f82ecc234182
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646390949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2646390949
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1374225755
Short name T722
Test name
Test status
Simulation time 27554251 ps
CPU time 0.61 seconds
Started Jun 23 06:01:44 PM PDT 24
Finished Jun 23 06:01:45 PM PDT 24
Peak memory 194488 kb
Host smart-91cbc990-e8dd-4083-8af1-2f93d151b8be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374225755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1374225755
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.57680440
Short name T759
Test name
Test status
Simulation time 178323580 ps
CPU time 2.22 seconds
Started Jun 23 06:01:47 PM PDT 24
Finished Jun 23 06:01:49 PM PDT 24
Peak memory 199728 kb
Host smart-8e837f4c-a694-4baf-8910-3d6ba1bcbc0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57680440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_o
utstanding.57680440
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.815058926
Short name T750
Test name
Test status
Simulation time 340893114 ps
CPU time 3.14 seconds
Started Jun 23 06:01:46 PM PDT 24
Finished Jun 23 06:01:49 PM PDT 24
Peak memory 199600 kb
Host smart-0fc2e2db-0082-4ad7-bb4f-53475819c29e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815058926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.815058926
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2838783515
Short name T141
Test name
Test status
Simulation time 444090581 ps
CPU time 3.38 seconds
Started Jun 23 06:01:43 PM PDT 24
Finished Jun 23 06:01:47 PM PDT 24
Peak memory 199636 kb
Host smart-0342d27c-9c09-4a72-b01b-bb5fa162f47b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838783515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2838783515
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3700025345
Short name T86
Test name
Test status
Simulation time 4013299254 ps
CPU time 8.79 seconds
Started Jun 23 06:01:50 PM PDT 24
Finished Jun 23 06:02:00 PM PDT 24
Peak memory 199688 kb
Host smart-2aece74a-b0e5-4b38-9c9b-ef97fd1d93e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700025345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3700025345
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3106784698
Short name T661
Test name
Test status
Simulation time 438317105 ps
CPU time 5.2 seconds
Started Jun 23 06:01:48 PM PDT 24
Finished Jun 23 06:01:54 PM PDT 24
Peak memory 199580 kb
Host smart-052854cd-f224-49a5-b63b-4107211f09e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106784698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3106784698
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1658172315
Short name T721
Test name
Test status
Simulation time 66336295 ps
CPU time 0.83 seconds
Started Jun 23 06:01:50 PM PDT 24
Finished Jun 23 06:01:52 PM PDT 24
Peak memory 199104 kb
Host smart-ab27abc6-9931-42ee-bc93-090f54ba09bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658172315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1658172315
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3862102086
Short name T772
Test name
Test status
Simulation time 147054607 ps
CPU time 1.27 seconds
Started Jun 23 06:01:48 PM PDT 24
Finished Jun 23 06:01:50 PM PDT 24
Peak memory 199708 kb
Host smart-e61ec04a-14da-4078-ba0e-927b4c2ecd69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862102086 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.3862102086
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1239239500
Short name T69
Test name
Test status
Simulation time 93689620 ps
CPU time 0.81 seconds
Started Jun 23 06:01:46 PM PDT 24
Finished Jun 23 06:01:47 PM PDT 24
Peak memory 198996 kb
Host smart-a70a902e-6889-4bc7-b0bb-d596e78187dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239239500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1239239500
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3851825401
Short name T99
Test name
Test status
Simulation time 214221823 ps
CPU time 2.24 seconds
Started Jun 23 06:01:49 PM PDT 24
Finished Jun 23 06:01:52 PM PDT 24
Peak memory 199600 kb
Host smart-cd43b714-a5d9-47ce-93ae-3acbb77d7ed1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851825401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3851825401
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.4007126657
Short name T756
Test name
Test status
Simulation time 256698177 ps
CPU time 3.47 seconds
Started Jun 23 06:01:51 PM PDT 24
Finished Jun 23 06:01:54 PM PDT 24
Peak memory 199528 kb
Host smart-6d878f00-7bc7-454a-8ec9-8bca0ea4a58a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007126657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.4007126657
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.167189665
Short name T137
Test name
Test status
Simulation time 709394233 ps
CPU time 3.27 seconds
Started Jun 23 06:01:48 PM PDT 24
Finished Jun 23 06:01:52 PM PDT 24
Peak memory 199660 kb
Host smart-2122adb9-a385-4999-8206-335a9ab831b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167189665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.167189665
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3877474317
Short name T769
Test name
Test status
Simulation time 78627673 ps
CPU time 1.14 seconds
Started Jun 23 06:02:06 PM PDT 24
Finished Jun 23 06:02:07 PM PDT 24
Peak memory 199540 kb
Host smart-8fca4701-7164-43a3-9305-e6cd2c331830
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877474317 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3877474317
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3543674113
Short name T98
Test name
Test status
Simulation time 53725136 ps
CPU time 0.74 seconds
Started Jun 23 06:02:04 PM PDT 24
Finished Jun 23 06:02:05 PM PDT 24
Peak memory 197552 kb
Host smart-78cf283a-a1cc-4445-9668-fd584bb708b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543674113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3543674113
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1658452044
Short name T68
Test name
Test status
Simulation time 50217515 ps
CPU time 0.61 seconds
Started Jun 23 06:02:04 PM PDT 24
Finished Jun 23 06:02:05 PM PDT 24
Peak memory 194392 kb
Host smart-81400d3d-85af-4113-b892-dab1eee3d420
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658452044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1658452044
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2806308394
Short name T102
Test name
Test status
Simulation time 44167213 ps
CPU time 2.03 seconds
Started Jun 23 06:02:03 PM PDT 24
Finished Jun 23 06:02:05 PM PDT 24
Peak memory 199628 kb
Host smart-34c9cdf0-d22c-43c8-84db-4dcde2cb6361
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806308394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2806308394
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.53861310
Short name T758
Test name
Test status
Simulation time 390108935 ps
CPU time 2.33 seconds
Started Jun 23 06:02:08 PM PDT 24
Finished Jun 23 06:02:11 PM PDT 24
Peak memory 199640 kb
Host smart-806de3ae-7b53-41f9-9432-b00c3add9ae8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53861310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.53861310
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.715439741
Short name T140
Test name
Test status
Simulation time 311446826 ps
CPU time 1.75 seconds
Started Jun 23 06:02:05 PM PDT 24
Finished Jun 23 06:02:07 PM PDT 24
Peak memory 199504 kb
Host smart-4484296f-e76e-406b-8086-6dd2430e361e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715439741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.715439741
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1800074237
Short name T774
Test name
Test status
Simulation time 15148270 ps
CPU time 0.73 seconds
Started Jun 23 06:02:07 PM PDT 24
Finished Jun 23 06:02:08 PM PDT 24
Peak memory 197444 kb
Host smart-7e5c7deb-e2d6-4338-a5b8-77a8080f2511
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800074237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1800074237
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.331154664
Short name T726
Test name
Test status
Simulation time 31970070 ps
CPU time 0.62 seconds
Started Jun 23 06:02:03 PM PDT 24
Finished Jun 23 06:02:03 PM PDT 24
Peak memory 194436 kb
Host smart-20e4a3a2-19ea-4422-ae70-9659a3fec854
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331154664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.331154664
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3291141385
Short name T729
Test name
Test status
Simulation time 48072059 ps
CPU time 1.19 seconds
Started Jun 23 06:02:05 PM PDT 24
Finished Jun 23 06:02:07 PM PDT 24
Peak memory 199624 kb
Host smart-3966a56f-ad03-4b0e-98e4-f0849e37f814
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291141385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3291141385
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4123170339
Short name T764
Test name
Test status
Simulation time 268451481 ps
CPU time 4.28 seconds
Started Jun 23 06:02:05 PM PDT 24
Finished Jun 23 06:02:10 PM PDT 24
Peak memory 199684 kb
Host smart-1dcda872-87b1-4451-b44c-eb9245dbf002
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123170339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.4123170339
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1621365073
Short name T138
Test name
Test status
Simulation time 156720630 ps
CPU time 3.1 seconds
Started Jun 23 06:02:07 PM PDT 24
Finished Jun 23 06:02:10 PM PDT 24
Peak memory 199720 kb
Host smart-dbae1f17-0863-4d68-89f7-f68f2fe299a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621365073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1621365073
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1221412459
Short name T692
Test name
Test status
Simulation time 372456163 ps
CPU time 2.15 seconds
Started Jun 23 06:02:12 PM PDT 24
Finished Jun 23 06:02:14 PM PDT 24
Peak memory 199608 kb
Host smart-b2514e0e-beec-41d5-b3be-fc58bc4d8459
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221412459 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1221412459
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3151399276
Short name T709
Test name
Test status
Simulation time 59680084 ps
CPU time 0.94 seconds
Started Jun 23 06:02:11 PM PDT 24
Finished Jun 23 06:02:12 PM PDT 24
Peak memory 199220 kb
Host smart-16f480bc-95cc-4f8f-942c-fbad1232b728
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151399276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3151399276
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.541449138
Short name T775
Test name
Test status
Simulation time 25949576 ps
CPU time 0.63 seconds
Started Jun 23 06:02:09 PM PDT 24
Finished Jun 23 06:02:10 PM PDT 24
Peak memory 194688 kb
Host smart-7381e70b-3477-410b-b3cc-00ffec9d2542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541449138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.541449138
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1367919336
Short name T105
Test name
Test status
Simulation time 136382532 ps
CPU time 2.31 seconds
Started Jun 23 06:02:10 PM PDT 24
Finished Jun 23 06:02:13 PM PDT 24
Peak memory 199592 kb
Host smart-0d7b0d8d-9e60-4209-a5af-f3f022cf66ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367919336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1367919336
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.362463723
Short name T754
Test name
Test status
Simulation time 732653914 ps
CPU time 4.34 seconds
Started Jun 23 06:02:05 PM PDT 24
Finished Jun 23 06:02:10 PM PDT 24
Peak memory 199632 kb
Host smart-8d95e634-732d-434f-a0ee-a4c4ed6a1380
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362463723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.362463723
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1059068200
Short name T693
Test name
Test status
Simulation time 115234133 ps
CPU time 1.23 seconds
Started Jun 23 06:02:11 PM PDT 24
Finished Jun 23 06:02:13 PM PDT 24
Peak memory 199536 kb
Host smart-f07ad7d6-e84d-4ec4-b4b1-dd700e8d38d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059068200 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1059068200
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3975050691
Short name T706
Test name
Test status
Simulation time 277463723 ps
CPU time 0.95 seconds
Started Jun 23 06:02:08 PM PDT 24
Finished Jun 23 06:02:09 PM PDT 24
Peak memory 199452 kb
Host smart-0474f51e-f63b-4971-ada7-13837c799360
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975050691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3975050691
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1516732724
Short name T668
Test name
Test status
Simulation time 78967582 ps
CPU time 0.6 seconds
Started Jun 23 06:02:09 PM PDT 24
Finished Jun 23 06:02:10 PM PDT 24
Peak memory 194428 kb
Host smart-8fce5e2a-4850-462c-9065-1569bbdc161b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516732724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1516732724
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.527563845
Short name T710
Test name
Test status
Simulation time 94974105 ps
CPU time 1.21 seconds
Started Jun 23 06:02:11 PM PDT 24
Finished Jun 23 06:02:12 PM PDT 24
Peak memory 198040 kb
Host smart-94a39e74-d8a6-4fe7-bdc9-b1ee1043ca76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527563845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr
_outstanding.527563845
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1533238630
Short name T773
Test name
Test status
Simulation time 82480211 ps
CPU time 4.41 seconds
Started Jun 23 06:02:12 PM PDT 24
Finished Jun 23 06:02:16 PM PDT 24
Peak memory 199640 kb
Host smart-e7fc3a0c-8f60-4fe3-baed-7e2aeba3ce54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533238630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1533238630
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.518540838
Short name T739
Test name
Test status
Simulation time 312920342 ps
CPU time 2.9 seconds
Started Jun 23 06:02:10 PM PDT 24
Finished Jun 23 06:02:14 PM PDT 24
Peak memory 199652 kb
Host smart-a83316d3-b20a-4621-bb01-94329c3f0f2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518540838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.518540838
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.624121643
Short name T67
Test name
Test status
Simulation time 133497282 ps
CPU time 1.71 seconds
Started Jun 23 06:02:11 PM PDT 24
Finished Jun 23 06:02:13 PM PDT 24
Peak memory 199732 kb
Host smart-fea0dd61-7010-4f16-b6f0-188cd09477f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624121643 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.624121643
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2015428806
Short name T701
Test name
Test status
Simulation time 16784068 ps
CPU time 0.8 seconds
Started Jun 23 06:02:10 PM PDT 24
Finished Jun 23 06:02:11 PM PDT 24
Peak memory 199432 kb
Host smart-67e96d77-f500-4e37-9586-1aeaaacc6a3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015428806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2015428806
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1801481028
Short name T699
Test name
Test status
Simulation time 76982195 ps
CPU time 0.62 seconds
Started Jun 23 06:02:10 PM PDT 24
Finished Jun 23 06:02:11 PM PDT 24
Peak memory 194584 kb
Host smart-6d329776-5988-4901-9d86-2ae8abea4a09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801481028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1801481028
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2268867516
Short name T700
Test name
Test status
Simulation time 90328353 ps
CPU time 1.68 seconds
Started Jun 23 06:02:11 PM PDT 24
Finished Jun 23 06:02:13 PM PDT 24
Peak memory 199644 kb
Host smart-94d3a957-f6c1-49d7-88d6-2824c5c19294
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268867516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2268867516
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1322940307
Short name T746
Test name
Test status
Simulation time 71312641 ps
CPU time 3.42 seconds
Started Jun 23 06:02:09 PM PDT 24
Finished Jun 23 06:02:13 PM PDT 24
Peak memory 199656 kb
Host smart-ae65cb8b-38d1-4f7a-b32a-dcb0b2457192
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322940307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1322940307
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2564869040
Short name T135
Test name
Test status
Simulation time 98962980 ps
CPU time 1.98 seconds
Started Jun 23 06:02:11 PM PDT 24
Finished Jun 23 06:02:14 PM PDT 24
Peak memory 199716 kb
Host smart-7bf48c0d-2f70-4115-b94d-81a0c7edc6dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564869040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2564869040
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1709349378
Short name T770
Test name
Test status
Simulation time 73190547 ps
CPU time 1.1 seconds
Started Jun 23 06:02:15 PM PDT 24
Finished Jun 23 06:02:17 PM PDT 24
Peak memory 199484 kb
Host smart-940cabed-8fea-4ac5-843d-acec19dfd284
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709349378 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1709349378
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2157293188
Short name T97
Test name
Test status
Simulation time 51006982 ps
CPU time 0.81 seconds
Started Jun 23 06:02:17 PM PDT 24
Finished Jun 23 06:02:18 PM PDT 24
Peak memory 199444 kb
Host smart-8d7650bc-a097-48dc-8063-c2ad27ee4f1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157293188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2157293188
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2318082823
Short name T686
Test name
Test status
Simulation time 49520906 ps
CPU time 0.61 seconds
Started Jun 23 06:02:12 PM PDT 24
Finished Jun 23 06:02:13 PM PDT 24
Peak memory 194460 kb
Host smart-c2946fcd-6d47-4241-afb3-8ce66b4827ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318082823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2318082823
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3207699828
Short name T104
Test name
Test status
Simulation time 40137429 ps
CPU time 1.56 seconds
Started Jun 23 06:02:14 PM PDT 24
Finished Jun 23 06:02:16 PM PDT 24
Peak memory 199612 kb
Host smart-c4b8c486-3da8-4a7c-b07c-4bb26e03f3f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207699828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3207699828
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3373314846
Short name T720
Test name
Test status
Simulation time 306101226 ps
CPU time 4.18 seconds
Started Jun 23 06:02:12 PM PDT 24
Finished Jun 23 06:02:17 PM PDT 24
Peak memory 199644 kb
Host smart-53e01e2b-7c0e-4d9d-afeb-68e55f6ee1de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373314846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3373314846
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1067683550
Short name T136
Test name
Test status
Simulation time 154208463 ps
CPU time 4.17 seconds
Started Jun 23 06:02:15 PM PDT 24
Finished Jun 23 06:02:20 PM PDT 24
Peak memory 199720 kb
Host smart-98ba9095-ba17-475a-9d0f-25147c3e0043
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067683550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1067683550
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2340750499
Short name T61
Test name
Test status
Simulation time 20652778 ps
CPU time 1.35 seconds
Started Jun 23 06:02:17 PM PDT 24
Finished Jun 23 06:02:19 PM PDT 24
Peak memory 199668 kb
Host smart-bc8ad29a-5592-4f3d-9358-61b0e8797c38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340750499 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2340750499
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2647736440
Short name T92
Test name
Test status
Simulation time 128907359 ps
CPU time 0.95 seconds
Started Jun 23 06:02:16 PM PDT 24
Finished Jun 23 06:02:17 PM PDT 24
Peak memory 199476 kb
Host smart-001ef339-cf65-43df-b509-aea56f9bdf6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647736440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2647736440
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3087699307
Short name T681
Test name
Test status
Simulation time 23819210 ps
CPU time 0.63 seconds
Started Jun 23 06:02:16 PM PDT 24
Finished Jun 23 06:02:17 PM PDT 24
Peak memory 194460 kb
Host smart-97d71f86-a995-4d9a-9f37-88d466f40021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087699307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3087699307
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.4066230211
Short name T771
Test name
Test status
Simulation time 579183987 ps
CPU time 2.33 seconds
Started Jun 23 06:02:14 PM PDT 24
Finished Jun 23 06:02:18 PM PDT 24
Peak memory 199632 kb
Host smart-1ce5d8cf-c0db-46e2-878b-b918e02236fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066230211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.4066230211
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2217359027
Short name T713
Test name
Test status
Simulation time 340000406 ps
CPU time 2.06 seconds
Started Jun 23 06:02:15 PM PDT 24
Finished Jun 23 06:02:17 PM PDT 24
Peak memory 199644 kb
Host smart-9819bdca-2995-4fe5-9721-8b86454c3969
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217359027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2217359027
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.158374092
Short name T738
Test name
Test status
Simulation time 674680310 ps
CPU time 3.17 seconds
Started Jun 23 06:02:15 PM PDT 24
Finished Jun 23 06:02:19 PM PDT 24
Peak memory 199644 kb
Host smart-3bce5673-5ed3-4ef2-8254-b062cbf9cebe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158374092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.158374092
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2089188063
Short name T711
Test name
Test status
Simulation time 83692577 ps
CPU time 2.78 seconds
Started Jun 23 06:02:23 PM PDT 24
Finished Jun 23 06:02:26 PM PDT 24
Peak memory 215020 kb
Host smart-b5e9c8da-f686-4958-8897-549d399ca875
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089188063 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2089188063
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2538731162
Short name T724
Test name
Test status
Simulation time 53012566 ps
CPU time 0.82 seconds
Started Jun 23 06:02:20 PM PDT 24
Finished Jun 23 06:02:21 PM PDT 24
Peak memory 199128 kb
Host smart-e2012ab9-e204-48f5-82b6-b89a02383270
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538731162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2538731162
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3557495831
Short name T704
Test name
Test status
Simulation time 14900962 ps
CPU time 0.64 seconds
Started Jun 23 06:02:15 PM PDT 24
Finished Jun 23 06:02:16 PM PDT 24
Peak memory 194404 kb
Host smart-03f3061f-1fb5-410f-8079-3ce8f22eae8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557495831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3557495831
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3565950312
Short name T740
Test name
Test status
Simulation time 154045212 ps
CPU time 1.72 seconds
Started Jun 23 06:02:24 PM PDT 24
Finished Jun 23 06:02:26 PM PDT 24
Peak memory 199520 kb
Host smart-0ef38b39-6ce5-4263-9bad-beb56c891217
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565950312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3565950312
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2605541633
Short name T736
Test name
Test status
Simulation time 1099601481 ps
CPU time 1.43 seconds
Started Jun 23 06:02:21 PM PDT 24
Finished Jun 23 06:02:23 PM PDT 24
Peak memory 199612 kb
Host smart-22bee3c1-9c9a-44db-a111-5106d4a48d17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605541633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2605541633
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2930036789
Short name T734
Test name
Test status
Simulation time 134013918 ps
CPU time 2.02 seconds
Started Jun 23 06:02:22 PM PDT 24
Finished Jun 23 06:02:25 PM PDT 24
Peak memory 199704 kb
Host smart-088e7d43-bf35-4931-94f8-0a3947d270da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930036789 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2930036789
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.734002578
Short name T752
Test name
Test status
Simulation time 64556904 ps
CPU time 0.67 seconds
Started Jun 23 06:02:22 PM PDT 24
Finished Jun 23 06:02:23 PM PDT 24
Peak memory 197116 kb
Host smart-159de600-e20d-4b70-a61e-987f3e79f82b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734002578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.734002578
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.4090537321
Short name T708
Test name
Test status
Simulation time 14368619 ps
CPU time 0.58 seconds
Started Jun 23 06:02:24 PM PDT 24
Finished Jun 23 06:02:25 PM PDT 24
Peak memory 194468 kb
Host smart-e71ef7b4-d5aa-4602-bdc5-7bc68c82bc8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090537321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.4090537321
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2195183449
Short name T689
Test name
Test status
Simulation time 495940206 ps
CPU time 1.08 seconds
Started Jun 23 06:02:20 PM PDT 24
Finished Jun 23 06:02:21 PM PDT 24
Peak memory 199548 kb
Host smart-c293cb07-ac2d-4fa7-b2ca-b7ec8b1bbf3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195183449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2195183449
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2513103357
Short name T712
Test name
Test status
Simulation time 207662947 ps
CPU time 3.7 seconds
Started Jun 23 06:02:24 PM PDT 24
Finished Jun 23 06:02:28 PM PDT 24
Peak memory 199640 kb
Host smart-0ed9d68b-90a4-481a-9366-33f85be74c07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513103357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2513103357
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3502611960
Short name T760
Test name
Test status
Simulation time 270614731 ps
CPU time 4.48 seconds
Started Jun 23 06:02:21 PM PDT 24
Finished Jun 23 06:02:27 PM PDT 24
Peak memory 199664 kb
Host smart-f47a7349-439a-4a2e-909d-ecd6ae510bc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502611960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3502611960
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3738417904
Short name T674
Test name
Test status
Simulation time 110569233 ps
CPU time 1.85 seconds
Started Jun 23 06:02:23 PM PDT 24
Finished Jun 23 06:02:25 PM PDT 24
Peak memory 199708 kb
Host smart-3c28fe87-bfca-4e4e-baa8-f36a08c9448d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738417904 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3738417904
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3069161240
Short name T677
Test name
Test status
Simulation time 75053077 ps
CPU time 0.72 seconds
Started Jun 23 06:02:22 PM PDT 24
Finished Jun 23 06:02:23 PM PDT 24
Peak memory 197660 kb
Host smart-fb364f7b-834f-4909-87c6-1a595190d34d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069161240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3069161240
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1783553904
Short name T676
Test name
Test status
Simulation time 12712255 ps
CPU time 0.59 seconds
Started Jun 23 06:02:22 PM PDT 24
Finished Jun 23 06:02:23 PM PDT 24
Peak memory 194400 kb
Host smart-6786bee7-895e-4a85-adce-acf4cef8f82e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783553904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1783553904
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1775458826
Short name T100
Test name
Test status
Simulation time 70961693 ps
CPU time 1.15 seconds
Started Jun 23 06:02:23 PM PDT 24
Finished Jun 23 06:02:25 PM PDT 24
Peak memory 197916 kb
Host smart-35c1e2de-dbda-4c4f-98f4-6c8d187c0b77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775458826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1775458826
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1419321646
Short name T687
Test name
Test status
Simulation time 88681354 ps
CPU time 4.41 seconds
Started Jun 23 06:02:21 PM PDT 24
Finished Jun 23 06:02:26 PM PDT 24
Peak memory 199624 kb
Host smart-d11e20a9-0fb1-4bb3-8a2d-e6fbba14fca9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419321646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1419321646
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3902447772
Short name T716
Test name
Test status
Simulation time 727130496 ps
CPU time 2.98 seconds
Started Jun 23 06:02:24 PM PDT 24
Finished Jun 23 06:02:27 PM PDT 24
Peak memory 199716 kb
Host smart-7f6fb0ef-1f2e-4119-a1b5-3d13173d5d1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902447772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3902447772
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.146772335
Short name T87
Test name
Test status
Simulation time 652042692 ps
CPU time 5.39 seconds
Started Jun 23 06:01:52 PM PDT 24
Finished Jun 23 06:01:57 PM PDT 24
Peak memory 199876 kb
Host smart-9dd479c7-514f-4c65-8f50-d9e2bc8ed927
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146772335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.146772335
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1832117531
Short name T95
Test name
Test status
Simulation time 2100122371 ps
CPU time 11.04 seconds
Started Jun 23 06:01:46 PM PDT 24
Finished Jun 23 06:01:58 PM PDT 24
Peak memory 198784 kb
Host smart-ff7615a0-ee6f-4211-84e9-1efcbac3962d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832117531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1832117531
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1172033060
Short name T747
Test name
Test status
Simulation time 49696431 ps
CPU time 0.74 seconds
Started Jun 23 06:01:51 PM PDT 24
Finished Jun 23 06:01:52 PM PDT 24
Peak memory 197684 kb
Host smart-d0e413f8-d134-41b2-87c3-3bc10c8a1dc9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172033060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1172033060
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1342431338
Short name T671
Test name
Test status
Simulation time 261843166 ps
CPU time 1.52 seconds
Started Jun 23 06:01:54 PM PDT 24
Finished Jun 23 06:01:56 PM PDT 24
Peak memory 199740 kb
Host smart-9bf382fe-5af9-4b46-967e-1479bd25ec52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342431338 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1342431338
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3259265717
Short name T717
Test name
Test status
Simulation time 442217206 ps
CPU time 0.9 seconds
Started Jun 23 06:01:51 PM PDT 24
Finished Jun 23 06:01:52 PM PDT 24
Peak memory 199476 kb
Host smart-4c4b3ee2-4869-485e-b754-3d2122aa82da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259265717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3259265717
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.3207787863
Short name T730
Test name
Test status
Simulation time 21268167 ps
CPU time 0.59 seconds
Started Jun 23 06:01:51 PM PDT 24
Finished Jun 23 06:01:52 PM PDT 24
Peak memory 194716 kb
Host smart-6f65120a-2ceb-471f-bc12-1720ec811159
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207787863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3207787863
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1114668588
Short name T715
Test name
Test status
Simulation time 857900087 ps
CPU time 1.8 seconds
Started Jun 23 06:01:54 PM PDT 24
Finished Jun 23 06:01:57 PM PDT 24
Peak memory 199512 kb
Host smart-48f2a9db-fa2c-4507-8190-e6364526b970
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114668588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1114668588
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.866038086
Short name T679
Test name
Test status
Simulation time 699447214 ps
CPU time 3.77 seconds
Started Jun 23 06:01:56 PM PDT 24
Finished Jun 23 06:02:00 PM PDT 24
Peak memory 199628 kb
Host smart-bdbc1f1d-6085-4e8d-84a5-d1fe5f1403b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866038086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.866038086
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.45840842
Short name T60
Test name
Test status
Simulation time 91758707 ps
CPU time 1.76 seconds
Started Jun 23 06:01:49 PM PDT 24
Finished Jun 23 06:01:52 PM PDT 24
Peak memory 199684 kb
Host smart-023441f8-d101-4755-92ac-84b889457a31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45840842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.45840842
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.393086571
Short name T744
Test name
Test status
Simulation time 19775945 ps
CPU time 0.68 seconds
Started Jun 23 06:02:26 PM PDT 24
Finished Jun 23 06:02:27 PM PDT 24
Peak memory 194484 kb
Host smart-e52f47f9-9cda-48ad-83d6-978e25019ea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393086571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.393086571
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2054650408
Short name T742
Test name
Test status
Simulation time 11241781 ps
CPU time 0.58 seconds
Started Jun 23 06:02:21 PM PDT 24
Finished Jun 23 06:02:22 PM PDT 24
Peak memory 194356 kb
Host smart-04d6c602-ae66-4e2b-94a0-76b4bbccdddc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054650408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2054650408
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3286450466
Short name T667
Test name
Test status
Simulation time 98771356 ps
CPU time 0.61 seconds
Started Jun 23 06:02:23 PM PDT 24
Finished Jun 23 06:02:24 PM PDT 24
Peak memory 194436 kb
Host smart-6f5fc747-6b03-44fc-a77f-e946698c480e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286450466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3286450466
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.179163911
Short name T703
Test name
Test status
Simulation time 87729756 ps
CPU time 0.59 seconds
Started Jun 23 06:02:21 PM PDT 24
Finished Jun 23 06:02:23 PM PDT 24
Peak memory 194404 kb
Host smart-6f89d38d-b472-4a41-a163-b3e2ae629467
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179163911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.179163911
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3461003937
Short name T718
Test name
Test status
Simulation time 11323368 ps
CPU time 0.58 seconds
Started Jun 23 06:02:24 PM PDT 24
Finished Jun 23 06:02:25 PM PDT 24
Peak memory 194476 kb
Host smart-a65750b9-4906-44e1-95e1-1dfc75a40c8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461003937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3461003937
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1714254026
Short name T743
Test name
Test status
Simulation time 13160912 ps
CPU time 0.58 seconds
Started Jun 23 06:02:23 PM PDT 24
Finished Jun 23 06:02:24 PM PDT 24
Peak memory 194400 kb
Host smart-400db36d-0fe9-446c-95aa-008928c89cc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714254026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1714254026
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.27395491
Short name T662
Test name
Test status
Simulation time 38927978 ps
CPU time 0.61 seconds
Started Jun 23 06:02:23 PM PDT 24
Finished Jun 23 06:02:25 PM PDT 24
Peak memory 194468 kb
Host smart-00f1e443-afef-413a-850a-77a3f58f6706
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27395491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.27395491
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3666394178
Short name T719
Test name
Test status
Simulation time 12138164 ps
CPU time 0.59 seconds
Started Jun 23 06:02:25 PM PDT 24
Finished Jun 23 06:02:26 PM PDT 24
Peak memory 194464 kb
Host smart-8712674c-168b-4912-89a5-0eef157189c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666394178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3666394178
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1452092903
Short name T664
Test name
Test status
Simulation time 14771768 ps
CPU time 0.6 seconds
Started Jun 23 06:02:26 PM PDT 24
Finished Jun 23 06:02:28 PM PDT 24
Peak memory 194392 kb
Host smart-dcea97a5-2299-4ff8-a793-0c0e3821de31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452092903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1452092903
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.517172558
Short name T688
Test name
Test status
Simulation time 141174632 ps
CPU time 0.64 seconds
Started Jun 23 06:02:27 PM PDT 24
Finished Jun 23 06:02:28 PM PDT 24
Peak memory 194460 kb
Host smart-2a5d7598-d535-4c6c-a6c4-ee67662f25c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517172558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.517172558
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4011682847
Short name T91
Test name
Test status
Simulation time 409215344 ps
CPU time 3.31 seconds
Started Jun 23 06:01:54 PM PDT 24
Finished Jun 23 06:01:57 PM PDT 24
Peak memory 198576 kb
Host smart-26a8238b-1a57-46ff-b326-e645df59943e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011682847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.4011682847
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3845261189
Short name T94
Test name
Test status
Simulation time 2701184091 ps
CPU time 15.86 seconds
Started Jun 23 06:01:52 PM PDT 24
Finished Jun 23 06:02:08 PM PDT 24
Peak memory 199172 kb
Host smart-1f6c9469-62fb-4758-89dd-a4f2a73780ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845261189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3845261189
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2412877402
Short name T93
Test name
Test status
Simulation time 515121949 ps
CPU time 0.89 seconds
Started Jun 23 06:01:55 PM PDT 24
Finished Jun 23 06:01:56 PM PDT 24
Peak memory 199188 kb
Host smart-61953b6e-7cb4-435f-a5f0-5e61f8808b60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412877402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2412877402
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.669847125
Short name T57
Test name
Test status
Simulation time 109097082 ps
CPU time 1.23 seconds
Started Jun 23 06:01:52 PM PDT 24
Finished Jun 23 06:01:54 PM PDT 24
Peak memory 199492 kb
Host smart-75cf7ba6-79fe-4346-8c7c-3de9f65b7373
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669847125 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.669847125
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1288884342
Short name T90
Test name
Test status
Simulation time 31038377 ps
CPU time 0.7 seconds
Started Jun 23 06:01:56 PM PDT 24
Finished Jun 23 06:01:57 PM PDT 24
Peak memory 197184 kb
Host smart-d8962777-83fe-499d-9689-721b2ddfa54f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288884342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1288884342
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2996173325
Short name T70
Test name
Test status
Simulation time 45473173 ps
CPU time 0.56 seconds
Started Jun 23 06:01:52 PM PDT 24
Finished Jun 23 06:01:53 PM PDT 24
Peak memory 194468 kb
Host smart-d99a3a45-416d-4bd8-b6de-50ba3e6c6c2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996173325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2996173325
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1048110142
Short name T101
Test name
Test status
Simulation time 22403831 ps
CPU time 1.11 seconds
Started Jun 23 06:01:56 PM PDT 24
Finished Jun 23 06:01:58 PM PDT 24
Peak memory 198104 kb
Host smart-82e4a577-a1d8-44c8-ba83-58dd555c60d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048110142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1048110142
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1185798591
Short name T678
Test name
Test status
Simulation time 52515206 ps
CPU time 2.68 seconds
Started Jun 23 06:01:56 PM PDT 24
Finished Jun 23 06:01:59 PM PDT 24
Peak memory 199548 kb
Host smart-205a644d-020e-43fc-ba7f-dd20a5438be3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185798591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1185798591
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.582694105
Short name T41
Test name
Test status
Simulation time 114047975 ps
CPU time 2.71 seconds
Started Jun 23 06:01:53 PM PDT 24
Finished Jun 23 06:01:56 PM PDT 24
Peak memory 199628 kb
Host smart-979bdfe2-bd30-48f0-8882-10064225b396
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582694105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.582694105
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3179195364
Short name T762
Test name
Test status
Simulation time 31972321 ps
CPU time 0.63 seconds
Started Jun 23 06:02:23 PM PDT 24
Finished Jun 23 06:02:24 PM PDT 24
Peak memory 194472 kb
Host smart-918bd1ce-9bec-4c37-9aaf-6f2f2e701766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179195364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3179195364
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1947144476
Short name T672
Test name
Test status
Simulation time 15349009 ps
CPU time 0.6 seconds
Started Jun 23 06:02:25 PM PDT 24
Finished Jun 23 06:02:26 PM PDT 24
Peak memory 194716 kb
Host smart-b94b36f2-e541-45f4-9c74-1b8238ba0d52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947144476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1947144476
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.2387639678
Short name T745
Test name
Test status
Simulation time 14029036 ps
CPU time 0.59 seconds
Started Jun 23 06:02:24 PM PDT 24
Finished Jun 23 06:02:25 PM PDT 24
Peak memory 194520 kb
Host smart-888867ab-bd78-4e1f-b992-219c2d482c5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387639678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.2387639678
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2358815030
Short name T727
Test name
Test status
Simulation time 22162763 ps
CPU time 0.58 seconds
Started Jun 23 06:02:22 PM PDT 24
Finished Jun 23 06:02:23 PM PDT 24
Peak memory 194460 kb
Host smart-d25363e0-875f-468d-81b3-8cb3eea4e98c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358815030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2358815030
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.823957082
Short name T761
Test name
Test status
Simulation time 11963770 ps
CPU time 0.6 seconds
Started Jun 23 06:02:27 PM PDT 24
Finished Jun 23 06:02:28 PM PDT 24
Peak memory 194376 kb
Host smart-5e87fc1b-f928-41d9-a6cd-2bb72ac4a733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823957082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.823957082
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1922405865
Short name T723
Test name
Test status
Simulation time 113110707 ps
CPU time 0.58 seconds
Started Jun 23 06:02:26 PM PDT 24
Finished Jun 23 06:02:27 PM PDT 24
Peak memory 194476 kb
Host smart-12a46a1e-f9d3-4663-b3da-6e1b7aaf44b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922405865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1922405865
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2610851416
Short name T690
Test name
Test status
Simulation time 19976924 ps
CPU time 0.57 seconds
Started Jun 23 06:02:26 PM PDT 24
Finished Jun 23 06:02:27 PM PDT 24
Peak memory 194380 kb
Host smart-ce5bbd77-7d07-4d67-ae2f-1bb753d6a2d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610851416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2610851416
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1544282137
Short name T695
Test name
Test status
Simulation time 46763646 ps
CPU time 0.6 seconds
Started Jun 23 06:02:25 PM PDT 24
Finished Jun 23 06:02:26 PM PDT 24
Peak memory 194460 kb
Host smart-d0915dde-3147-44f5-8a79-99593d7a12c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544282137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1544282137
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.61704682
Short name T767
Test name
Test status
Simulation time 17719438 ps
CPU time 0.61 seconds
Started Jun 23 06:02:29 PM PDT 24
Finished Jun 23 06:02:30 PM PDT 24
Peak memory 194436 kb
Host smart-5a04aea6-2cf6-4c47-af88-ff9db5981c4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61704682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.61704682
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.207099783
Short name T669
Test name
Test status
Simulation time 52749075 ps
CPU time 0.6 seconds
Started Jun 23 06:02:28 PM PDT 24
Finished Jun 23 06:02:30 PM PDT 24
Peak memory 194520 kb
Host smart-736f52dd-b050-4c0a-8dbb-f0e7e0147920
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207099783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.207099783
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2965419341
Short name T696
Test name
Test status
Simulation time 200836198 ps
CPU time 3.22 seconds
Started Jun 23 06:01:53 PM PDT 24
Finished Jun 23 06:01:57 PM PDT 24
Peak memory 198368 kb
Host smart-35d6c3ae-163d-4116-a335-3ab8060aa91a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965419341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2965419341
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1824753372
Short name T85
Test name
Test status
Simulation time 612581787 ps
CPU time 13.78 seconds
Started Jun 23 06:01:55 PM PDT 24
Finished Jun 23 06:02:09 PM PDT 24
Peak memory 199584 kb
Host smart-1386842a-6739-4430-939a-b205b4d9b506
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824753372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1824753372
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1727246560
Short name T96
Test name
Test status
Simulation time 155411923 ps
CPU time 1.01 seconds
Started Jun 23 06:01:54 PM PDT 24
Finished Jun 23 06:01:56 PM PDT 24
Peak memory 199404 kb
Host smart-2bb775ad-4a4e-468b-acec-c35aac3c3566
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727246560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1727246560
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1533167853
Short name T43
Test name
Test status
Simulation time 75562917 ps
CPU time 2.49 seconds
Started Jun 23 06:01:55 PM PDT 24
Finished Jun 23 06:01:58 PM PDT 24
Peak memory 199640 kb
Host smart-c106536a-a2c5-4828-bbe5-e47a96090035
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533167853 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1533167853
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2700650301
Short name T763
Test name
Test status
Simulation time 150392688 ps
CPU time 0.92 seconds
Started Jun 23 06:01:53 PM PDT 24
Finished Jun 23 06:01:55 PM PDT 24
Peak memory 199480 kb
Host smart-e0e8734d-c1af-4c45-a2b0-aee10b8a218b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700650301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2700650301
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1494485026
Short name T665
Test name
Test status
Simulation time 22629365 ps
CPU time 0.57 seconds
Started Jun 23 06:01:51 PM PDT 24
Finished Jun 23 06:01:52 PM PDT 24
Peak memory 194392 kb
Host smart-0c400a07-a4e6-4278-b678-f3984401cf23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494485026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1494485026
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4153679475
Short name T766
Test name
Test status
Simulation time 106256102 ps
CPU time 1.8 seconds
Started Jun 23 06:01:56 PM PDT 24
Finished Jun 23 06:01:58 PM PDT 24
Peak memory 199616 kb
Host smart-1adeb124-da86-4590-b0e0-d3f5ae03cb81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153679475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.4153679475
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1701747957
Short name T732
Test name
Test status
Simulation time 130051368 ps
CPU time 1.58 seconds
Started Jun 23 06:01:54 PM PDT 24
Finished Jun 23 06:01:56 PM PDT 24
Peak memory 199704 kb
Host smart-8780eaa5-ed50-4f58-9706-7630cba51080
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701747957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1701747957
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1715868472
Short name T735
Test name
Test status
Simulation time 23495061 ps
CPU time 0.58 seconds
Started Jun 23 06:02:29 PM PDT 24
Finished Jun 23 06:02:30 PM PDT 24
Peak memory 194464 kb
Host smart-2dcc7152-1351-46e7-aa24-868583a00d66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715868472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1715868472
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2514111251
Short name T683
Test name
Test status
Simulation time 47113497 ps
CPU time 0.57 seconds
Started Jun 23 06:02:29 PM PDT 24
Finished Jun 23 06:02:30 PM PDT 24
Peak memory 194396 kb
Host smart-16969c39-5bb6-4cb4-b980-764d19ba96a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514111251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2514111251
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3027068640
Short name T748
Test name
Test status
Simulation time 13098939 ps
CPU time 0.61 seconds
Started Jun 23 06:02:28 PM PDT 24
Finished Jun 23 06:02:30 PM PDT 24
Peak memory 194444 kb
Host smart-6d7315b7-e0eb-468d-adea-a64f0a203e5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027068640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3027068640
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2383189082
Short name T751
Test name
Test status
Simulation time 39821894 ps
CPU time 0.58 seconds
Started Jun 23 06:02:30 PM PDT 24
Finished Jun 23 06:02:31 PM PDT 24
Peak memory 194432 kb
Host smart-46b986ea-5c37-40d1-a880-e99e57209ee4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383189082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2383189082
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.1481939942
Short name T741
Test name
Test status
Simulation time 18016437 ps
CPU time 0.58 seconds
Started Jun 23 06:02:28 PM PDT 24
Finished Jun 23 06:02:30 PM PDT 24
Peak memory 194500 kb
Host smart-2e28fc9e-1d81-4098-825d-0d11727e1d42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481939942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1481939942
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1913261450
Short name T702
Test name
Test status
Simulation time 52548768 ps
CPU time 0.62 seconds
Started Jun 23 06:02:26 PM PDT 24
Finished Jun 23 06:02:27 PM PDT 24
Peak memory 194400 kb
Host smart-3cd16d50-a7b2-4acd-b40c-12806a42c93c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913261450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1913261450
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3818943869
Short name T663
Test name
Test status
Simulation time 33142499 ps
CPU time 0.59 seconds
Started Jun 23 06:02:27 PM PDT 24
Finished Jun 23 06:02:28 PM PDT 24
Peak memory 194460 kb
Host smart-4133bab3-9a1f-4a8d-b74b-37ee373f4ca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818943869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3818943869
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3226775822
Short name T670
Test name
Test status
Simulation time 16722777 ps
CPU time 0.62 seconds
Started Jun 23 06:02:29 PM PDT 24
Finished Jun 23 06:02:31 PM PDT 24
Peak memory 194568 kb
Host smart-8e227204-0d3d-4f4c-bd54-10bbed98c99e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226775822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3226775822
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.148844271
Short name T705
Test name
Test status
Simulation time 16752039 ps
CPU time 0.62 seconds
Started Jun 23 06:02:25 PM PDT 24
Finished Jun 23 06:02:26 PM PDT 24
Peak memory 194544 kb
Host smart-91ee5345-fc2c-4c9c-9aa2-dbd4626d8cf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148844271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.148844271
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1516942164
Short name T133
Test name
Test status
Simulation time 43274793 ps
CPU time 0.63 seconds
Started Jun 23 06:02:28 PM PDT 24
Finished Jun 23 06:02:30 PM PDT 24
Peak memory 194472 kb
Host smart-91b6f086-7350-4573-9f0e-69a290d0d527
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516942164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1516942164
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3190714063
Short name T58
Test name
Test status
Simulation time 27549600042 ps
CPU time 386.4 seconds
Started Jun 23 06:02:02 PM PDT 24
Finished Jun 23 06:08:29 PM PDT 24
Peak memory 215504 kb
Host smart-423572f5-4efb-4a4f-bff5-c9eedc015f86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190714063 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3190714063
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1103378243
Short name T768
Test name
Test status
Simulation time 18198327 ps
CPU time 0.92 seconds
Started Jun 23 06:02:06 PM PDT 24
Finished Jun 23 06:02:07 PM PDT 24
Peak memory 199476 kb
Host smart-911c0627-2824-4bab-aff6-b73c60c4525b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103378243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1103378243
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.56651575
Short name T728
Test name
Test status
Simulation time 50393252 ps
CPU time 0.66 seconds
Started Jun 23 06:01:56 PM PDT 24
Finished Jun 23 06:01:57 PM PDT 24
Peak memory 194564 kb
Host smart-061e0e00-53ee-4eff-9e2b-519f882a0aea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56651575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.56651575
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3988687311
Short name T755
Test name
Test status
Simulation time 45314520 ps
CPU time 1.13 seconds
Started Jun 23 06:01:53 PM PDT 24
Finished Jun 23 06:01:55 PM PDT 24
Peak memory 198292 kb
Host smart-6b8e848f-b5ef-41f8-b47c-50092fed25de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988687311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3988687311
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3272633090
Short name T42
Test name
Test status
Simulation time 126418534 ps
CPU time 2.72 seconds
Started Jun 23 06:01:54 PM PDT 24
Finished Jun 23 06:01:58 PM PDT 24
Peak memory 199708 kb
Host smart-96aeeb02-0163-4e6b-9e8d-3af207b0249a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272633090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3272633090
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1941089673
Short name T59
Test name
Test status
Simulation time 243851328 ps
CPU time 4.01 seconds
Started Jun 23 06:01:53 PM PDT 24
Finished Jun 23 06:01:57 PM PDT 24
Peak memory 199652 kb
Host smart-dfc092de-ada5-4be5-a808-f0aa38f65157
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941089673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1941089673
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.4292803610
Short name T707
Test name
Test status
Simulation time 91744779 ps
CPU time 2.25 seconds
Started Jun 23 06:01:59 PM PDT 24
Finished Jun 23 06:02:02 PM PDT 24
Peak memory 199768 kb
Host smart-7650dd7a-78e8-4a38-bd57-5eb65ae99aa4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292803610 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.4292803610
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3072641215
Short name T89
Test name
Test status
Simulation time 58824743 ps
CPU time 0.72 seconds
Started Jun 23 06:02:12 PM PDT 24
Finished Jun 23 06:02:13 PM PDT 24
Peak memory 197096 kb
Host smart-31744807-269d-4ac4-abff-d0013d8195b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072641215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3072641215
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3720361508
Short name T697
Test name
Test status
Simulation time 14755402 ps
CPU time 0.6 seconds
Started Jun 23 06:02:12 PM PDT 24
Finished Jun 23 06:02:13 PM PDT 24
Peak memory 194464 kb
Host smart-ee06aa87-5487-4c52-97aa-1be39ee39ad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720361508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3720361508
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2576167204
Short name T691
Test name
Test status
Simulation time 44511348 ps
CPU time 2.2 seconds
Started Jun 23 06:02:01 PM PDT 24
Finished Jun 23 06:02:04 PM PDT 24
Peak memory 199616 kb
Host smart-d8dd8eb6-8422-44f2-a250-c46419492fb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576167204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2576167204
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1382479041
Short name T698
Test name
Test status
Simulation time 532641625 ps
CPU time 2.35 seconds
Started Jun 23 06:02:01 PM PDT 24
Finished Jun 23 06:02:04 PM PDT 24
Peak memory 199652 kb
Host smart-6eee8dd7-1fbe-4733-8dcc-9599098ae852
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382479041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1382479041
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.290894871
Short name T81
Test name
Test status
Simulation time 172669461 ps
CPU time 2.9 seconds
Started Jun 23 06:01:59 PM PDT 24
Finished Jun 23 06:02:02 PM PDT 24
Peak memory 199716 kb
Host smart-54007ebc-208c-4713-b733-f5f4554537e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290894871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.290894871
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.37967008
Short name T65
Test name
Test status
Simulation time 46606726 ps
CPU time 1.74 seconds
Started Jun 23 06:01:58 PM PDT 24
Finished Jun 23 06:02:00 PM PDT 24
Peak memory 199780 kb
Host smart-5cbb9622-0cd7-48a4-85df-824056f9c062
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37967008 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.37967008
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2383931349
Short name T714
Test name
Test status
Simulation time 22471077 ps
CPU time 0.81 seconds
Started Jun 23 06:02:04 PM PDT 24
Finished Jun 23 06:02:05 PM PDT 24
Peak memory 198624 kb
Host smart-438f65c6-d7c8-4aa4-b5b4-55a21a38bfac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383931349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2383931349
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2258510205
Short name T685
Test name
Test status
Simulation time 82110685 ps
CPU time 0.61 seconds
Started Jun 23 06:01:58 PM PDT 24
Finished Jun 23 06:01:59 PM PDT 24
Peak memory 194504 kb
Host smart-a0c094ad-78a7-4fcf-bdbf-64d81037e61a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258510205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2258510205
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3431722196
Short name T680
Test name
Test status
Simulation time 52158599 ps
CPU time 1.21 seconds
Started Jun 23 06:02:01 PM PDT 24
Finished Jun 23 06:02:02 PM PDT 24
Peak memory 199584 kb
Host smart-a5d3c08e-8bc0-4c70-b822-f40bc9541e33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431722196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3431722196
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3768157411
Short name T66
Test name
Test status
Simulation time 49770804 ps
CPU time 1.36 seconds
Started Jun 23 06:02:12 PM PDT 24
Finished Jun 23 06:02:14 PM PDT 24
Peak memory 199456 kb
Host smart-a960ec29-39f7-479f-84ea-177e1292953d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768157411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3768157411
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.551081014
Short name T682
Test name
Test status
Simulation time 151471466 ps
CPU time 3.79 seconds
Started Jun 23 06:02:02 PM PDT 24
Finished Jun 23 06:02:06 PM PDT 24
Peak memory 199716 kb
Host smart-6b6ecda3-37a8-461d-9926-6f38ed57bcfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551081014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.551081014
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2245340752
Short name T684
Test name
Test status
Simulation time 147608551 ps
CPU time 1.15 seconds
Started Jun 23 06:01:57 PM PDT 24
Finished Jun 23 06:01:59 PM PDT 24
Peak memory 199472 kb
Host smart-ac4fce7d-8f20-4d43-9917-3d4af856f352
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245340752 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2245340752
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2597125245
Short name T673
Test name
Test status
Simulation time 14460260 ps
CPU time 0.6 seconds
Started Jun 23 06:02:00 PM PDT 24
Finished Jun 23 06:02:01 PM PDT 24
Peak memory 194432 kb
Host smart-d5f306dc-26f2-4de7-ba3d-0d8465e62148
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597125245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2597125245
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2577000760
Short name T71
Test name
Test status
Simulation time 169881312 ps
CPU time 2.43 seconds
Started Jun 23 06:02:00 PM PDT 24
Finished Jun 23 06:02:03 PM PDT 24
Peak memory 199700 kb
Host smart-71b96d4f-c6df-4c0f-a2c5-ad61158cfb4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577000760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2577000760
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1483369301
Short name T737
Test name
Test status
Simulation time 98167435 ps
CPU time 2.51 seconds
Started Jun 23 06:02:12 PM PDT 24
Finished Jun 23 06:02:15 PM PDT 24
Peak memory 199612 kb
Host smart-a734417d-7e27-4c6e-a2bf-54d8d09706df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483369301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1483369301
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3081797814
Short name T725
Test name
Test status
Simulation time 397972164 ps
CPU time 1.97 seconds
Started Jun 23 06:02:12 PM PDT 24
Finished Jun 23 06:02:15 PM PDT 24
Peak memory 198884 kb
Host smart-9c8d48f4-37b9-4cc8-b62c-cd0480cfc274
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081797814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3081797814
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3068449931
Short name T694
Test name
Test status
Simulation time 85100645 ps
CPU time 2.76 seconds
Started Jun 23 06:02:05 PM PDT 24
Finished Jun 23 06:02:08 PM PDT 24
Peak memory 199672 kb
Host smart-368e444b-7bf7-48db-8652-550a4bb4dd03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068449931 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3068449931
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.497629131
Short name T675
Test name
Test status
Simulation time 70486674 ps
CPU time 0.79 seconds
Started Jun 23 06:02:12 PM PDT 24
Finished Jun 23 06:02:14 PM PDT 24
Peak memory 198636 kb
Host smart-559474dc-b65d-4171-857f-848d3b28517f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497629131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.497629131
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.3582337736
Short name T733
Test name
Test status
Simulation time 18734619 ps
CPU time 0.59 seconds
Started Jun 23 06:02:12 PM PDT 24
Finished Jun 23 06:02:13 PM PDT 24
Peak memory 193376 kb
Host smart-3d47ff2a-0d6a-4605-9709-e879a6a897bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582337736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3582337736
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.380570283
Short name T749
Test name
Test status
Simulation time 36001377 ps
CPU time 1.71 seconds
Started Jun 23 06:02:05 PM PDT 24
Finished Jun 23 06:02:07 PM PDT 24
Peak memory 199568 kb
Host smart-558ae132-6113-435f-bb16-c793e3e8a3b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380570283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.380570283
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1073334760
Short name T765
Test name
Test status
Simulation time 1268117840 ps
CPU time 3.73 seconds
Started Jun 23 06:02:02 PM PDT 24
Finished Jun 23 06:02:07 PM PDT 24
Peak memory 199656 kb
Host smart-cdc07abf-2fc3-4c1a-ba3a-c32561155d0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073334760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1073334760
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2527147467
Short name T757
Test name
Test status
Simulation time 87178442 ps
CPU time 1.71 seconds
Started Jun 23 06:02:01 PM PDT 24
Finished Jun 23 06:02:03 PM PDT 24
Peak memory 199652 kb
Host smart-13eab622-6510-48d7-b191-10572d9ea12b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527147467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2527147467
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1149324281
Short name T306
Test name
Test status
Simulation time 50292338 ps
CPU time 0.56 seconds
Started Jun 23 05:10:59 PM PDT 24
Finished Jun 23 05:11:00 PM PDT 24
Peak memory 195120 kb
Host smart-c5c19d46-4114-4137-8c3c-3c9e6b34eab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149324281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1149324281
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3805468804
Short name T618
Test name
Test status
Simulation time 558293956 ps
CPU time 25.03 seconds
Started Jun 23 05:10:59 PM PDT 24
Finished Jun 23 05:11:25 PM PDT 24
Peak memory 200068 kb
Host smart-540cfae3-a557-4d50-87d4-da1017d23746
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3805468804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3805468804
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2002260111
Short name T521
Test name
Test status
Simulation time 6685736114 ps
CPU time 47.4 seconds
Started Jun 23 05:10:59 PM PDT 24
Finished Jun 23 05:11:47 PM PDT 24
Peak memory 200100 kb
Host smart-f6096dee-6127-4291-aeb1-57d889092d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002260111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2002260111
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3288922006
Short name T564
Test name
Test status
Simulation time 911875474 ps
CPU time 205.17 seconds
Started Jun 23 05:11:02 PM PDT 24
Finished Jun 23 05:14:28 PM PDT 24
Peak memory 593624 kb
Host smart-2622aab9-0892-4fad-bedd-8df4082c5d55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3288922006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3288922006
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2829111528
Short name T329
Test name
Test status
Simulation time 3815513424 ps
CPU time 50.84 seconds
Started Jun 23 05:11:01 PM PDT 24
Finished Jun 23 05:11:52 PM PDT 24
Peak memory 200112 kb
Host smart-2ff55146-2749-45c7-9081-63a541c20573
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829111528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2829111528
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3603501712
Short name T560
Test name
Test status
Simulation time 2158820401 ps
CPU time 66.92 seconds
Started Jun 23 05:10:59 PM PDT 24
Finished Jun 23 05:12:06 PM PDT 24
Peak memory 200032 kb
Host smart-8f98a002-9cce-4284-8796-fd3c3fd4fccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603501712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3603501712
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.4033420018
Short name T46
Test name
Test status
Simulation time 206855529 ps
CPU time 0.84 seconds
Started Jun 23 05:11:05 PM PDT 24
Finished Jun 23 05:11:06 PM PDT 24
Peak memory 218244 kb
Host smart-d8408c4e-921e-4c99-a267-e1fd2cd2d3c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033420018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.4033420018
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.2164700579
Short name T505
Test name
Test status
Simulation time 1253253823 ps
CPU time 12.37 seconds
Started Jun 23 05:11:01 PM PDT 24
Finished Jun 23 05:11:15 PM PDT 24
Peak memory 200108 kb
Host smart-8b6f1777-9b47-43e0-a783-a003d31993f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164700579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2164700579
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.3927731813
Short name T193
Test name
Test status
Simulation time 110852356 ps
CPU time 1.12 seconds
Started Jun 23 05:11:01 PM PDT 24
Finished Jun 23 05:11:03 PM PDT 24
Peak memory 200156 kb
Host smart-03942c95-35f6-4576-a438-2b72b5597796
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927731813 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac_vectors.3927731813
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.3233394106
Short name T363
Test name
Test status
Simulation time 171844840545 ps
CPU time 544.99 seconds
Started Jun 23 05:11:05 PM PDT 24
Finished Jun 23 05:20:11 PM PDT 24
Peak memory 200104 kb
Host smart-80ab6d61-421a-4a62-9e2c-055076db8e0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3233394106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3233394106
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.3545601478
Short name T254
Test name
Test status
Simulation time 59122778410 ps
CPU time 1651.1 seconds
Started Jun 23 05:10:58 PM PDT 24
Finished Jun 23 05:38:30 PM PDT 24
Peak memory 215592 kb
Host smart-4b2d49ef-8cda-4568-835c-a414af60e800
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3545601478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.3545601478
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.1635300479
Short name T73
Test name
Test status
Simulation time 324935702810 ps
CPU time 1788.5 seconds
Started Jun 23 05:11:02 PM PDT 24
Finished Jun 23 05:40:51 PM PDT 24
Peak memory 216480 kb
Host smart-7fb9e400-aea3-49d6-ba1e-732be4ace3d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1635300479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.1635300479
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_alert_test.1836588150
Short name T292
Test name
Test status
Simulation time 15609629 ps
CPU time 0.6 seconds
Started Jun 23 05:11:10 PM PDT 24
Finished Jun 23 05:11:11 PM PDT 24
Peak memory 195680 kb
Host smart-77bc6b75-575b-4661-8719-fddb87fb7948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836588150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1836588150
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3896146342
Short name T84
Test name
Test status
Simulation time 62007602 ps
CPU time 3.37 seconds
Started Jun 23 05:11:01 PM PDT 24
Finished Jun 23 05:11:05 PM PDT 24
Peak memory 200052 kb
Host smart-35d9c314-02ae-4cdf-828c-3c380b1110ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3896146342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3896146342
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3512277849
Short name T76
Test name
Test status
Simulation time 4314712008 ps
CPU time 14.11 seconds
Started Jun 23 05:11:06 PM PDT 24
Finished Jun 23 05:11:21 PM PDT 24
Peak memory 200100 kb
Host smart-6cb221cd-8b23-4fe5-bdff-cd4e75431342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512277849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3512277849
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2960238994
Short name T215
Test name
Test status
Simulation time 895242094 ps
CPU time 52.86 seconds
Started Jun 23 05:10:59 PM PDT 24
Finished Jun 23 05:11:53 PM PDT 24
Peak memory 200052 kb
Host smart-4216830c-9aea-47d8-a383-33e71aecc4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960238994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2960238994
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.3043405664
Short name T429
Test name
Test status
Simulation time 892752740 ps
CPU time 8.84 seconds
Started Jun 23 05:11:02 PM PDT 24
Finished Jun 23 05:11:11 PM PDT 24
Peak memory 200072 kb
Host smart-01cd2261-8046-4e0b-bdc0-3f3b3ab74e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043405664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3043405664
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.2941870466
Short name T481
Test name
Test status
Simulation time 238503603 ps
CPU time 1.38 seconds
Started Jun 23 05:11:10 PM PDT 24
Finished Jun 23 05:11:11 PM PDT 24
Peak memory 199960 kb
Host smart-9a4eccf6-3116-491a-a6bb-1d25605da72e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941870466 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac_vectors.2941870466
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.22133899
Short name T364
Test name
Test status
Simulation time 38120240989 ps
CPU time 467.58 seconds
Started Jun 23 05:11:04 PM PDT 24
Finished Jun 23 05:18:52 PM PDT 24
Peak memory 200108 kb
Host smart-8a85653e-f1d5-4594-9a52-a1d7bff8225f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=22133899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.22133899
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.684678568
Short name T534
Test name
Test status
Simulation time 421386906679 ps
CPU time 1835.21 seconds
Started Jun 23 05:11:05 PM PDT 24
Finished Jun 23 05:41:41 PM PDT 24
Peak memory 215532 kb
Host smart-d0547ab4-0bb5-409e-96fc-329a8fe64b28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=684678568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.684678568
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.215805074
Short name T561
Test name
Test status
Simulation time 61681808452 ps
CPU time 1761.4 seconds
Started Jun 23 05:11:03 PM PDT 24
Finished Jun 23 05:40:25 PM PDT 24
Peak memory 215712 kb
Host smart-627e1f88-2e08-486a-b6e9-536968fd26db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=215805074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.215805074
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.4101457817
Short name T111
Test name
Test status
Simulation time 7971114352 ps
CPU time 30.05 seconds
Started Jun 23 05:11:09 PM PDT 24
Finished Jun 23 05:11:39 PM PDT 24
Peak memory 200164 kb
Host smart-9dc737dc-a482-4ef8-b7df-a2866e4934f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101457817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.4101457817
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.2853102895
Short name T515
Test name
Test status
Simulation time 2139752022 ps
CPU time 28.49 seconds
Started Jun 23 05:11:17 PM PDT 24
Finished Jun 23 05:11:47 PM PDT 24
Peak memory 200076 kb
Host smart-2a1cb712-4a16-434f-a585-6ee4933c8286
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2853102895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2853102895
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.4268649925
Short name T418
Test name
Test status
Simulation time 14597921569 ps
CPU time 51.86 seconds
Started Jun 23 05:11:17 PM PDT 24
Finished Jun 23 05:12:10 PM PDT 24
Peak memory 200140 kb
Host smart-dc40abe5-af1d-444e-8eef-d77ae2149eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268649925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.4268649925
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2960910969
Short name T175
Test name
Test status
Simulation time 10124307341 ps
CPU time 668.61 seconds
Started Jun 23 05:11:17 PM PDT 24
Finished Jun 23 05:22:26 PM PDT 24
Peak memory 746592 kb
Host smart-171cd1d9-c8b1-4631-98c0-29345dbf3bd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2960910969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2960910969
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.874505339
Short name T508
Test name
Test status
Simulation time 4932374051 ps
CPU time 130.44 seconds
Started Jun 23 05:11:20 PM PDT 24
Finished Jun 23 05:13:31 PM PDT 24
Peak memory 200072 kb
Host smart-119c85fa-b01b-4169-887f-c4f2d6eb1eb1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874505339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.874505339
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3285892502
Short name T375
Test name
Test status
Simulation time 433321944 ps
CPU time 12.73 seconds
Started Jun 23 05:11:16 PM PDT 24
Finished Jun 23 05:11:30 PM PDT 24
Peak memory 200068 kb
Host smart-75d1b599-c9be-4454-a018-65df62be3000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285892502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3285892502
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.3653108101
Short name T455
Test name
Test status
Simulation time 698349805 ps
CPU time 8.3 seconds
Started Jun 23 05:11:17 PM PDT 24
Finished Jun 23 05:11:27 PM PDT 24
Peak memory 199988 kb
Host smart-6c3041b1-2b2c-413e-8c78-5d005ea33759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653108101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3653108101
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.3504306270
Short name T424
Test name
Test status
Simulation time 28843714 ps
CPU time 1.03 seconds
Started Jun 23 05:11:21 PM PDT 24
Finished Jun 23 05:11:23 PM PDT 24
Peak memory 199812 kb
Host smart-efd2c5d2-c4ca-4193-840a-1a8ef8cb8512
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504306270 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_hmac_vectors.3504306270
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha256_vectors.3580312413
Short name T165
Test name
Test status
Simulation time 27706408372 ps
CPU time 506.91 seconds
Started Jun 23 05:11:20 PM PDT 24
Finished Jun 23 05:19:48 PM PDT 24
Peak memory 199832 kb
Host smart-bd81e9ad-5b24-47a4-b8a9-88dd6055ba52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3580312413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha256_vectors.3580312413
Directory /workspace/10.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha384_vectors.2269713361
Short name T50
Test name
Test status
Simulation time 161731496097 ps
CPU time 2041.14 seconds
Started Jun 23 05:11:16 PM PDT 24
Finished Jun 23 05:45:19 PM PDT 24
Peak memory 215476 kb
Host smart-bbb50698-e657-463e-b71d-d9926ead0ca6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2269713361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha384_vectors.2269713361
Directory /workspace/10.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha512_vectors.2030347025
Short name T658
Test name
Test status
Simulation time 110702116380 ps
CPU time 1903.61 seconds
Started Jun 23 05:11:18 PM PDT 24
Finished Jun 23 05:43:03 PM PDT 24
Peak memory 208356 kb
Host smart-9d5a84e3-5155-4c88-b860-398a6206c921
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2030347025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha512_vectors.2030347025
Directory /workspace/10.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.3893307664
Short name T112
Test name
Test status
Simulation time 427029949 ps
CPU time 26.38 seconds
Started Jun 23 05:11:16 PM PDT 24
Finished Jun 23 05:11:43 PM PDT 24
Peak memory 200072 kb
Host smart-55572775-08b5-44eb-8f24-1a53c9b66bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893307664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.3893307664
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1637229498
Short name T52
Test name
Test status
Simulation time 46449609 ps
CPU time 0.6 seconds
Started Jun 23 05:11:20 PM PDT 24
Finished Jun 23 05:11:21 PM PDT 24
Peak memory 195316 kb
Host smart-2372df29-16a1-4a54-9968-b5062c4860c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637229498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1637229498
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1546302000
Short name T647
Test name
Test status
Simulation time 944837453 ps
CPU time 41.49 seconds
Started Jun 23 05:11:23 PM PDT 24
Finished Jun 23 05:12:05 PM PDT 24
Peak memory 199956 kb
Host smart-8566910d-e379-4b87-94eb-639c6ed89327
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1546302000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1546302000
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.4002813526
Short name T548
Test name
Test status
Simulation time 920919273 ps
CPU time 7.02 seconds
Started Jun 23 05:11:18 PM PDT 24
Finished Jun 23 05:11:26 PM PDT 24
Peak memory 200072 kb
Host smart-3edefcd4-01e2-4e8a-b8cf-6b9921a2fa13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002813526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.4002813526
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.4133707958
Short name T589
Test name
Test status
Simulation time 8667997904 ps
CPU time 499.45 seconds
Started Jun 23 05:11:17 PM PDT 24
Finished Jun 23 05:19:37 PM PDT 24
Peak memory 639956 kb
Host smart-9f590dae-1456-43ea-a64a-336eadd59461
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4133707958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.4133707958
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1810285560
Short name T118
Test name
Test status
Simulation time 7761434496 ps
CPU time 108.51 seconds
Started Jun 23 05:11:20 PM PDT 24
Finished Jun 23 05:13:08 PM PDT 24
Peak memory 200072 kb
Host smart-ed525872-20cd-4b6c-b21f-a46477900b29
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810285560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1810285560
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2491975544
Short name T443
Test name
Test status
Simulation time 459130939 ps
CPU time 9.51 seconds
Started Jun 23 05:11:17 PM PDT 24
Finished Jun 23 05:11:28 PM PDT 24
Peak memory 200064 kb
Host smart-29e79704-7804-44b7-b27a-2827338aa97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491975544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2491975544
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1996972078
Short name T488
Test name
Test status
Simulation time 849834253 ps
CPU time 12.1 seconds
Started Jun 23 05:11:16 PM PDT 24
Finished Jun 23 05:11:28 PM PDT 24
Peak memory 200084 kb
Host smart-f0c9c1f1-9c0f-4d9b-9297-1268f4046049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996972078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1996972078
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.3044604542
Short name T343
Test name
Test status
Simulation time 603211854 ps
CPU time 1.31 seconds
Started Jun 23 05:11:22 PM PDT 24
Finished Jun 23 05:11:24 PM PDT 24
Peak memory 200000 kb
Host smart-05132ae4-a371-4b47-800b-a0688f5b07fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044604542 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_hmac_vectors.3044604542
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha256_vectors.428915304
Short name T233
Test name
Test status
Simulation time 171522055387 ps
CPU time 564.72 seconds
Started Jun 23 05:11:15 PM PDT 24
Finished Jun 23 05:20:40 PM PDT 24
Peak memory 200120 kb
Host smart-177b50e0-a33f-44f0-9048-e4601556b8ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=428915304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha256_vectors.428915304
Directory /workspace/11.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha384_vectors.2888720586
Short name T615
Test name
Test status
Simulation time 164595352945 ps
CPU time 2164.84 seconds
Started Jun 23 05:11:22 PM PDT 24
Finished Jun 23 05:47:27 PM PDT 24
Peak memory 216060 kb
Host smart-85a961e3-ec4b-4d08-94da-846b5107546c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2888720586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha384_vectors.2888720586
Directory /workspace/11.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha512_vectors.1159223757
Short name T565
Test name
Test status
Simulation time 214803340023 ps
CPU time 1940.84 seconds
Started Jun 23 05:11:16 PM PDT 24
Finished Jun 23 05:43:38 PM PDT 24
Peak memory 215640 kb
Host smart-06b5971e-527b-4367-8126-49cf6c57553a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1159223757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha512_vectors.1159223757
Directory /workspace/11.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1891111246
Short name T106
Test name
Test status
Simulation time 596813484 ps
CPU time 33.64 seconds
Started Jun 23 05:11:18 PM PDT 24
Finished Jun 23 05:11:53 PM PDT 24
Peak memory 200060 kb
Host smart-4cd634f1-9107-46b2-b5e7-b0db6142c0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891111246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1891111246
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.947440380
Short name T558
Test name
Test status
Simulation time 57487248 ps
CPU time 0.59 seconds
Started Jun 23 05:11:18 PM PDT 24
Finished Jun 23 05:11:20 PM PDT 24
Peak memory 194960 kb
Host smart-26cb81cb-ae85-4e59-9150-222e0daa621a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947440380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.947440380
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.400697827
Short name T321
Test name
Test status
Simulation time 161519291 ps
CPU time 7.54 seconds
Started Jun 23 05:11:16 PM PDT 24
Finished Jun 23 05:11:24 PM PDT 24
Peak memory 200060 kb
Host smart-a8148ea7-db7e-46e1-8684-839d29727b7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=400697827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.400697827
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1617981541
Short name T412
Test name
Test status
Simulation time 10193061224 ps
CPU time 47.44 seconds
Started Jun 23 05:11:17 PM PDT 24
Finished Jun 23 05:12:05 PM PDT 24
Peak memory 200112 kb
Host smart-fd23ae26-fd9e-44e5-8848-c0cccc6e36bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617981541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1617981541
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2379516080
Short name T509
Test name
Test status
Simulation time 16624965337 ps
CPU time 305.02 seconds
Started Jun 23 05:11:17 PM PDT 24
Finished Jun 23 05:16:23 PM PDT 24
Peak memory 641900 kb
Host smart-df46a229-04f0-4ff4-bc80-d3d3bef0457d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2379516080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2379516080
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2932746170
Short name T337
Test name
Test status
Simulation time 314189808 ps
CPU time 6.04 seconds
Started Jun 23 05:11:22 PM PDT 24
Finished Jun 23 05:11:28 PM PDT 24
Peak memory 199992 kb
Host smart-27f4c364-fed4-454b-baec-9792cb174c3f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932746170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2932746170
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.310549312
Short name T173
Test name
Test status
Simulation time 35632662091 ps
CPU time 121.42 seconds
Started Jun 23 05:11:22 PM PDT 24
Finished Jun 23 05:13:24 PM PDT 24
Peak memory 200332 kb
Host smart-7d78f61d-241d-487a-a2bb-54473fb7cfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310549312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.310549312
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1534926466
Short name T202
Test name
Test status
Simulation time 184974589 ps
CPU time 7.58 seconds
Started Jun 23 05:11:17 PM PDT 24
Finished Jun 23 05:11:26 PM PDT 24
Peak memory 200068 kb
Host smart-0c2e7e65-5de1-4e40-a9bf-bb6af08da2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534926466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1534926466
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.3984858949
Short name T620
Test name
Test status
Simulation time 291737543 ps
CPU time 1.36 seconds
Started Jun 23 05:11:20 PM PDT 24
Finished Jun 23 05:11:22 PM PDT 24
Peak memory 200072 kb
Host smart-da9a11d7-bc2d-4ad2-abe3-b93430b7816e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984858949 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_hmac_vectors.3984858949
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha256_vectors.3258971487
Short name T633
Test name
Test status
Simulation time 58391169034 ps
CPU time 468.3 seconds
Started Jun 23 05:11:23 PM PDT 24
Finished Jun 23 05:19:12 PM PDT 24
Peak memory 200104 kb
Host smart-677d3a19-8ffa-4710-b970-34219fbf2347
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3258971487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha256_vectors.3258971487
Directory /workspace/12.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha512_vectors.1841185258
Short name T417
Test name
Test status
Simulation time 226711327626 ps
CPU time 1937.39 seconds
Started Jun 23 05:11:22 PM PDT 24
Finished Jun 23 05:43:41 PM PDT 24
Peak memory 216060 kb
Host smart-903872e1-9d96-415b-b883-09e750f6f541
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1841185258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha512_vectors.1841185258
Directory /workspace/12.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1250409223
Short name T107
Test name
Test status
Simulation time 3094524865 ps
CPU time 44.27 seconds
Started Jun 23 05:11:16 PM PDT 24
Finished Jun 23 05:12:01 PM PDT 24
Peak memory 200156 kb
Host smart-2dbd6494-e053-45be-818b-4243b95bfdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250409223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1250409223
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.846027881
Short name T614
Test name
Test status
Simulation time 117449251 ps
CPU time 0.61 seconds
Started Jun 23 05:11:24 PM PDT 24
Finished Jun 23 05:11:25 PM PDT 24
Peak memory 196276 kb
Host smart-8f0543bf-143b-4cc7-bc34-91aeb2ba0962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846027881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.846027881
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.4278242354
Short name T648
Test name
Test status
Simulation time 1189356064 ps
CPU time 51.02 seconds
Started Jun 23 05:11:22 PM PDT 24
Finished Jun 23 05:12:13 PM PDT 24
Peak memory 200036 kb
Host smart-c086a254-9bc4-4710-b07f-4ec176e7a861
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4278242354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.4278242354
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.3182872562
Short name T402
Test name
Test status
Simulation time 1402311956 ps
CPU time 6.46 seconds
Started Jun 23 05:11:25 PM PDT 24
Finished Jun 23 05:11:32 PM PDT 24
Peak memory 200036 kb
Host smart-24847174-15de-49a0-a6fc-e3a119eab6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182872562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3182872562
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2684449860
Short name T377
Test name
Test status
Simulation time 2429695087 ps
CPU time 371.89 seconds
Started Jun 23 05:11:24 PM PDT 24
Finished Jun 23 05:17:36 PM PDT 24
Peak memory 665328 kb
Host smart-89412449-e400-4c96-8115-ac61657ee99c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2684449860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2684449860
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1723760138
Short name T312
Test name
Test status
Simulation time 1696432281 ps
CPU time 95.78 seconds
Started Jun 23 05:11:25 PM PDT 24
Finished Jun 23 05:13:01 PM PDT 24
Peak memory 200080 kb
Host smart-d41ec758-9aa8-429f-969f-d373e35a3b69
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723760138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1723760138
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1824161897
Short name T422
Test name
Test status
Simulation time 4319925685 ps
CPU time 54.92 seconds
Started Jun 23 05:11:22 PM PDT 24
Finished Jun 23 05:12:17 PM PDT 24
Peak memory 200108 kb
Host smart-0b34f5c1-4262-40c2-bab0-bb0ccec78339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824161897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1824161897
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2740285788
Short name T426
Test name
Test status
Simulation time 262779950 ps
CPU time 2.83 seconds
Started Jun 23 05:11:22 PM PDT 24
Finished Jun 23 05:11:26 PM PDT 24
Peak memory 199996 kb
Host smart-bb478c14-90f5-4959-b16c-11ff436e56fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740285788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2740285788
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.2047010196
Short name T582
Test name
Test status
Simulation time 62132986 ps
CPU time 1.22 seconds
Started Jun 23 05:11:23 PM PDT 24
Finished Jun 23 05:11:25 PM PDT 24
Peak memory 200032 kb
Host smart-ff85aaf6-e2f2-4779-8d05-d37538d94a9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047010196 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_hmac_vectors.2047010196
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha256_vectors.3484203288
Short name T427
Test name
Test status
Simulation time 6317147316 ps
CPU time 362.08 seconds
Started Jun 23 05:11:24 PM PDT 24
Finished Jun 23 05:17:26 PM PDT 24
Peak memory 200156 kb
Host smart-9c6196ad-851d-4daa-a579-0c9f9d4cb5e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3484203288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha256_vectors.3484203288
Directory /workspace/13.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha384_vectors.1769746269
Short name T632
Test name
Test status
Simulation time 34266371325 ps
CPU time 2009.86 seconds
Started Jun 23 05:11:27 PM PDT 24
Finished Jun 23 05:44:57 PM PDT 24
Peak memory 215844 kb
Host smart-5668fd1d-7e93-411f-aebc-c3b5a961f7bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1769746269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha384_vectors.1769746269
Directory /workspace/13.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha512_vectors.1148262422
Short name T371
Test name
Test status
Simulation time 173225796536 ps
CPU time 2117.35 seconds
Started Jun 23 05:11:26 PM PDT 24
Finished Jun 23 05:46:44 PM PDT 24
Peak memory 200128 kb
Host smart-350a9d9e-61dd-405c-bb63-d3f6a8ed8500
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1148262422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha512_vectors.1148262422
Directory /workspace/13.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2357912140
Short name T584
Test name
Test status
Simulation time 2032881415 ps
CPU time 29.87 seconds
Started Jun 23 05:11:27 PM PDT 24
Finished Jun 23 05:11:57 PM PDT 24
Peak memory 200080 kb
Host smart-b08132eb-bcf4-4e99-979a-0e31cdd8d7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357912140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2357912140
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1686926600
Short name T217
Test name
Test status
Simulation time 12119441 ps
CPU time 0.63 seconds
Started Jun 23 05:11:23 PM PDT 24
Finished Jun 23 05:11:24 PM PDT 24
Peak memory 194976 kb
Host smart-e30831e2-a040-47f7-aa0e-aaea44824c22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686926600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1686926600
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2741258090
Short name T634
Test name
Test status
Simulation time 5840917901 ps
CPU time 80.68 seconds
Started Jun 23 05:11:22 PM PDT 24
Finished Jun 23 05:12:43 PM PDT 24
Peak memory 216372 kb
Host smart-21fe840f-4531-49e3-aff3-d4bb9ec43bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741258090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2741258090
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3037857389
Short name T638
Test name
Test status
Simulation time 6738048734 ps
CPU time 747.86 seconds
Started Jun 23 05:11:25 PM PDT 24
Finished Jun 23 05:23:54 PM PDT 24
Peak memory 709504 kb
Host smart-05d44836-d72a-4acc-8f91-9777726470e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3037857389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3037857389
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3513313223
Short name T314
Test name
Test status
Simulation time 4644721814 ps
CPU time 67.17 seconds
Started Jun 23 05:11:23 PM PDT 24
Finished Jun 23 05:12:31 PM PDT 24
Peak memory 200124 kb
Host smart-9c1ba938-75d6-4f17-a7a8-deb5d84de673
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513313223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3513313223
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2774943779
Short name T389
Test name
Test status
Simulation time 19066224408 ps
CPU time 71.83 seconds
Started Jun 23 05:11:25 PM PDT 24
Finished Jun 23 05:12:37 PM PDT 24
Peak memory 216560 kb
Host smart-55f3db38-4135-4006-8e4f-c63c42598319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774943779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2774943779
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1800421680
Short name T553
Test name
Test status
Simulation time 262412368 ps
CPU time 8.91 seconds
Started Jun 23 05:11:23 PM PDT 24
Finished Jun 23 05:11:33 PM PDT 24
Peak memory 200072 kb
Host smart-85704310-2b9b-40c8-812c-e58aed2ea362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800421680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1800421680
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.2038496005
Short name T629
Test name
Test status
Simulation time 196629018 ps
CPU time 1.05 seconds
Started Jun 23 05:11:27 PM PDT 24
Finished Jun 23 05:11:28 PM PDT 24
Peak memory 199856 kb
Host smart-72983a1d-e186-4a23-82c5-515d78005680
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038496005 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_hmac_vectors.2038496005
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha256_vectors.3551118780
Short name T257
Test name
Test status
Simulation time 31516265562 ps
CPU time 444.25 seconds
Started Jun 23 05:11:28 PM PDT 24
Finished Jun 23 05:18:53 PM PDT 24
Peak memory 200128 kb
Host smart-bc625941-f582-4854-8bdb-2692f8dda5e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3551118780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha256_vectors.3551118780
Directory /workspace/14.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha384_vectors.1943901419
Short name T619
Test name
Test status
Simulation time 110332057239 ps
CPU time 1733.87 seconds
Started Jun 23 05:11:28 PM PDT 24
Finished Jun 23 05:40:23 PM PDT 24
Peak memory 216256 kb
Host smart-0e90f91b-b79a-4e78-8de0-ec445a5d96a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1943901419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha384_vectors.1943901419
Directory /workspace/14.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha512_vectors.3593236125
Short name T458
Test name
Test status
Simulation time 27142286852 ps
CPU time 1668.62 seconds
Started Jun 23 05:11:23 PM PDT 24
Finished Jun 23 05:39:12 PM PDT 24
Peak memory 215668 kb
Host smart-4104340d-dc0f-4e64-a97b-02332c7baafc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3593236125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha512_vectors.3593236125
Directory /workspace/14.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3599843705
Short name T108
Test name
Test status
Simulation time 22794448990 ps
CPU time 80.07 seconds
Started Jun 23 05:11:26 PM PDT 24
Finished Jun 23 05:12:47 PM PDT 24
Peak memory 200064 kb
Host smart-07cf63b9-b602-4837-803c-c2ea0eca4462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599843705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3599843705
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1380495372
Short name T188
Test name
Test status
Simulation time 73011721 ps
CPU time 0.55 seconds
Started Jun 23 05:11:31 PM PDT 24
Finished Jun 23 05:11:32 PM PDT 24
Peak memory 194980 kb
Host smart-8ff1608d-4a70-4e54-8b6c-dd60a9976d88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380495372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1380495372
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3670848562
Short name T452
Test name
Test status
Simulation time 470914586 ps
CPU time 23.42 seconds
Started Jun 23 05:11:26 PM PDT 24
Finished Jun 23 05:11:50 PM PDT 24
Peak memory 199952 kb
Host smart-21537be6-b833-4c37-9f92-73c4301e5d58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3670848562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3670848562
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3395598045
Short name T399
Test name
Test status
Simulation time 94232186 ps
CPU time 1.73 seconds
Started Jun 23 05:11:28 PM PDT 24
Finished Jun 23 05:11:31 PM PDT 24
Peak memory 200080 kb
Host smart-9aae5d70-5722-4be4-8d2b-85a0a727079c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395598045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3395598045
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.231870907
Short name T519
Test name
Test status
Simulation time 11235540813 ps
CPU time 787.88 seconds
Started Jun 23 05:11:26 PM PDT 24
Finished Jun 23 05:24:34 PM PDT 24
Peak memory 718776 kb
Host smart-8b28d6f0-93be-4fb6-9388-4d50d5e5b637
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=231870907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.231870907
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2654356930
Short name T630
Test name
Test status
Simulation time 31324368322 ps
CPU time 77.95 seconds
Started Jun 23 05:11:28 PM PDT 24
Finished Jun 23 05:12:46 PM PDT 24
Peak memory 200052 kb
Host smart-805f7799-11ce-42c3-b1d8-325466f501d3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654356930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2654356930
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3949822157
Short name T226
Test name
Test status
Simulation time 23274509296 ps
CPU time 120.26 seconds
Started Jun 23 05:11:24 PM PDT 24
Finished Jun 23 05:13:25 PM PDT 24
Peak memory 208372 kb
Host smart-e4c2c1b2-7bc4-4860-8a5a-a8f490c63ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949822157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3949822157
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1903667591
Short name T224
Test name
Test status
Simulation time 127763237 ps
CPU time 1.04 seconds
Started Jun 23 05:11:25 PM PDT 24
Finished Jun 23 05:11:26 PM PDT 24
Peak memory 199808 kb
Host smart-465be565-a73e-451a-85e9-1872f37b9312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903667591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1903667591
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3842520776
Short name T391
Test name
Test status
Simulation time 80140811 ps
CPU time 1.76 seconds
Started Jun 23 05:11:34 PM PDT 24
Finished Jun 23 05:11:36 PM PDT 24
Peak memory 199952 kb
Host smart-5d38b076-46a0-4451-ad7e-7e96f4e96edc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842520776 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3842520776
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.3648457350
Short name T572
Test name
Test status
Simulation time 258203937 ps
CPU time 1.14 seconds
Started Jun 23 05:11:30 PM PDT 24
Finished Jun 23 05:11:31 PM PDT 24
Peak memory 199048 kb
Host smart-e0a79c86-1926-4da9-826d-4b192d3b311b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648457350 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_hmac_vectors.3648457350
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha256_vectors.3997724715
Short name T396
Test name
Test status
Simulation time 8534760609 ps
CPU time 413.27 seconds
Started Jun 23 05:11:33 PM PDT 24
Finished Jun 23 05:18:26 PM PDT 24
Peak memory 200140 kb
Host smart-3856f7c6-c68d-46c6-918a-b9a5965c7659
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3997724715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha256_vectors.3997724715
Directory /workspace/15.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha384_vectors.3992091106
Short name T604
Test name
Test status
Simulation time 385268208587 ps
CPU time 1993.84 seconds
Started Jun 23 05:11:32 PM PDT 24
Finished Jun 23 05:44:46 PM PDT 24
Peak memory 216452 kb
Host smart-df7a9919-8d57-4e8d-8dd1-99867f6a60fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3992091106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha384_vectors.3992091106
Directory /workspace/15.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha512_vectors.4294837419
Short name T194
Test name
Test status
Simulation time 65485015231 ps
CPU time 1806.77 seconds
Started Jun 23 05:11:31 PM PDT 24
Finished Jun 23 05:41:39 PM PDT 24
Peak memory 215836 kb
Host smart-df88c10e-0882-486d-a513-8fdc531c74e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4294837419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha512_vectors.4294837419
Directory /workspace/15.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1811592716
Short name T251
Test name
Test status
Simulation time 2615770111 ps
CPU time 81.81 seconds
Started Jun 23 05:11:31 PM PDT 24
Finished Jun 23 05:12:53 PM PDT 24
Peak memory 200124 kb
Host smart-f4aa9919-e362-4caf-b48d-330f5a0d26ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811592716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1811592716
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2562546597
Short name T493
Test name
Test status
Simulation time 147753626 ps
CPU time 0.58 seconds
Started Jun 23 05:11:29 PM PDT 24
Finished Jun 23 05:11:30 PM PDT 24
Peak memory 195904 kb
Host smart-4a280324-2ce0-4a19-bb84-813954664485
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562546597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2562546597
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2015419849
Short name T660
Test name
Test status
Simulation time 701106054 ps
CPU time 29.67 seconds
Started Jun 23 05:11:30 PM PDT 24
Finished Jun 23 05:12:01 PM PDT 24
Peak memory 200052 kb
Host smart-254e63b1-64f8-43c7-b76b-0b6e762dea6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2015419849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2015419849
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2568947594
Short name T397
Test name
Test status
Simulation time 16265683771 ps
CPU time 64.92 seconds
Started Jun 23 05:11:33 PM PDT 24
Finished Jun 23 05:12:38 PM PDT 24
Peak memory 208320 kb
Host smart-7444fc00-3bcc-4ecb-8ed9-099f94c4ea63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568947594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2568947594
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.536343996
Short name T283
Test name
Test status
Simulation time 35810144 ps
CPU time 0.73 seconds
Started Jun 23 05:11:34 PM PDT 24
Finished Jun 23 05:11:35 PM PDT 24
Peak memory 198192 kb
Host smart-fb57c82f-457e-43de-b601-be514e2ec0da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=536343996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.536343996
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.3933667341
Short name T385
Test name
Test status
Simulation time 4262774522 ps
CPU time 56.1 seconds
Started Jun 23 05:11:31 PM PDT 24
Finished Jun 23 05:12:28 PM PDT 24
Peak memory 200064 kb
Host smart-46f40073-7902-4821-9028-dae620a521e4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933667341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3933667341
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2152353668
Short name T28
Test name
Test status
Simulation time 8554922417 ps
CPU time 105.17 seconds
Started Jun 23 05:11:30 PM PDT 24
Finished Jun 23 05:13:16 PM PDT 24
Peak memory 200280 kb
Host smart-0f15a12f-6568-4525-9848-e2ec300be76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152353668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2152353668
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.183212292
Short name T209
Test name
Test status
Simulation time 428340768 ps
CPU time 8.8 seconds
Started Jun 23 05:11:32 PM PDT 24
Finished Jun 23 05:11:41 PM PDT 24
Peak memory 200016 kb
Host smart-63320773-90e8-4e26-9cca-02a4c221a00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183212292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.183212292
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.3534971477
Short name T219
Test name
Test status
Simulation time 28815858 ps
CPU time 1.15 seconds
Started Jun 23 05:11:32 PM PDT 24
Finished Jun 23 05:11:34 PM PDT 24
Peak memory 199808 kb
Host smart-820f6452-edb0-4baf-9b61-24d927eeeb5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534971477 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_hmac_vectors.3534971477
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha256_vectors.14625923
Short name T652
Test name
Test status
Simulation time 31537826438 ps
CPU time 451.63 seconds
Started Jun 23 05:11:30 PM PDT 24
Finished Jun 23 05:19:02 PM PDT 24
Peak memory 200092 kb
Host smart-4678479d-0999-4a08-9818-71887409bed2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=14625923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha256_vectors.14625923
Directory /workspace/16.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha384_vectors.3493952765
Short name T617
Test name
Test status
Simulation time 30136208009 ps
CPU time 1860.06 seconds
Started Jun 23 05:11:31 PM PDT 24
Finished Jun 23 05:42:32 PM PDT 24
Peak memory 215996 kb
Host smart-aa5cd450-5db1-4ab4-9e6d-52460883bc92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3493952765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha384_vectors.3493952765
Directory /workspace/16.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha512_vectors.1476619485
Short name T327
Test name
Test status
Simulation time 885299560960 ps
CPU time 1970.96 seconds
Started Jun 23 05:11:28 PM PDT 24
Finished Jun 23 05:44:20 PM PDT 24
Peak memory 216300 kb
Host smart-8f83a75a-8625-4cd8-871d-41d0c6d3f2a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1476619485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha512_vectors.1476619485
Directory /workspace/16.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.305111006
Short name T386
Test name
Test status
Simulation time 5376935431 ps
CPU time 36.8 seconds
Started Jun 23 05:11:33 PM PDT 24
Finished Jun 23 05:12:10 PM PDT 24
Peak memory 200136 kb
Host smart-e511165c-99aa-45dd-abc8-fd74aacf76ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305111006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.305111006
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2471001073
Short name T539
Test name
Test status
Simulation time 109059947 ps
CPU time 0.62 seconds
Started Jun 23 05:11:36 PM PDT 24
Finished Jun 23 05:11:38 PM PDT 24
Peak memory 196080 kb
Host smart-db900a1a-f344-4f03-badc-e284f5601ec4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471001073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2471001073
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.466639092
Short name T462
Test name
Test status
Simulation time 865055089 ps
CPU time 40.23 seconds
Started Jun 23 05:11:29 PM PDT 24
Finished Jun 23 05:12:10 PM PDT 24
Peak memory 200080 kb
Host smart-9e25f7ac-4439-4898-a84e-fd9cf39575a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=466639092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.466639092
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.4089710122
Short name T72
Test name
Test status
Simulation time 2286613143 ps
CPU time 38 seconds
Started Jun 23 05:11:31 PM PDT 24
Finished Jun 23 05:12:09 PM PDT 24
Peak memory 200008 kb
Host smart-0ba37b0f-47d9-43bd-8b8e-c436f492511b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089710122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.4089710122
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2002514731
Short name T445
Test name
Test status
Simulation time 1777753960 ps
CPU time 452.26 seconds
Started Jun 23 05:11:34 PM PDT 24
Finished Jun 23 05:19:07 PM PDT 24
Peak memory 702928 kb
Host smart-99d06b4e-3755-467f-923a-7ac68e42a103
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2002514731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2002514731
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1431890879
Short name T622
Test name
Test status
Simulation time 9972636317 ps
CPU time 144.35 seconds
Started Jun 23 05:11:32 PM PDT 24
Finished Jun 23 05:13:57 PM PDT 24
Peak memory 200128 kb
Host smart-4934538e-c74e-44fc-8a03-697bbc038634
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431890879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1431890879
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1036491265
Short name T538
Test name
Test status
Simulation time 18025134677 ps
CPU time 58.16 seconds
Started Jun 23 05:11:30 PM PDT 24
Finished Jun 23 05:12:29 PM PDT 24
Peak memory 200132 kb
Host smart-0d31877c-feef-4dc3-8d4c-4c32ffb0143b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036491265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1036491265
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2677975851
Short name T151
Test name
Test status
Simulation time 472507393 ps
CPU time 8.06 seconds
Started Jun 23 05:11:34 PM PDT 24
Finished Jun 23 05:11:42 PM PDT 24
Peak memory 200080 kb
Host smart-892fa55a-2134-4959-92ed-f4c9cfb44709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677975851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2677975851
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3890687939
Short name T275
Test name
Test status
Simulation time 10189135022 ps
CPU time 57.91 seconds
Started Jun 23 05:11:31 PM PDT 24
Finished Jun 23 05:12:29 PM PDT 24
Peak memory 200124 kb
Host smart-c1fedcd5-f191-44ec-8e99-a1b6f8ecce0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890687939 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3890687939
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.381541039
Short name T284
Test name
Test status
Simulation time 43786242 ps
CPU time 1.09 seconds
Started Jun 23 05:11:31 PM PDT 24
Finished Jun 23 05:11:32 PM PDT 24
Peak memory 199596 kb
Host smart-01860581-7278-4ee8-b977-ff5d281462c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381541039 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_hmac_vectors.381541039
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha256_vectors.1231877394
Short name T263
Test name
Test status
Simulation time 30618346656 ps
CPU time 428.5 seconds
Started Jun 23 05:11:29 PM PDT 24
Finished Jun 23 05:18:38 PM PDT 24
Peak memory 200140 kb
Host smart-b1d163ec-3578-40ea-8ad7-ff622a30b998
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1231877394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha256_vectors.1231877394
Directory /workspace/17.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha384_vectors.2899987738
Short name T324
Test name
Test status
Simulation time 33329894566 ps
CPU time 1821.67 seconds
Started Jun 23 05:11:33 PM PDT 24
Finished Jun 23 05:41:55 PM PDT 24
Peak memory 215668 kb
Host smart-813af29e-4c95-42b9-86b5-75e4d87f9525
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2899987738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha384_vectors.2899987738
Directory /workspace/17.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha512_vectors.1585413531
Short name T639
Test name
Test status
Simulation time 152746159489 ps
CPU time 2028.47 seconds
Started Jun 23 05:11:30 PM PDT 24
Finished Jun 23 05:45:20 PM PDT 24
Peak memory 216556 kb
Host smart-aa240a6e-d269-4a25-9732-079ce799ce11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1585413531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha512_vectors.1585413531
Directory /workspace/17.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1900675663
Short name T178
Test name
Test status
Simulation time 2905670890 ps
CPU time 47.71 seconds
Started Jun 23 05:11:29 PM PDT 24
Finished Jun 23 05:12:17 PM PDT 24
Peak memory 200164 kb
Host smart-fda53e5f-e237-4bed-b088-27e4f6c6b088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900675663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1900675663
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2666363122
Short name T598
Test name
Test status
Simulation time 124569716 ps
CPU time 0.63 seconds
Started Jun 23 05:11:38 PM PDT 24
Finished Jun 23 05:11:39 PM PDT 24
Peak memory 196004 kb
Host smart-92cc0603-db69-45b0-9e65-aa47d39367b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666363122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2666363122
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2172547183
Short name T317
Test name
Test status
Simulation time 1933650579 ps
CPU time 45.8 seconds
Started Jun 23 05:11:36 PM PDT 24
Finished Jun 23 05:12:22 PM PDT 24
Peak memory 200104 kb
Host smart-986c20fb-cb90-4647-ab23-06852862ee93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2172547183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2172547183
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3106406276
Short name T281
Test name
Test status
Simulation time 9059734190 ps
CPU time 61.9 seconds
Started Jun 23 05:11:40 PM PDT 24
Finished Jun 23 05:12:42 PM PDT 24
Peak memory 200156 kb
Host smart-0c735d93-7e63-409c-a50a-3b1ede3632e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106406276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3106406276
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1188882037
Short name T595
Test name
Test status
Simulation time 5978354877 ps
CPU time 768.16 seconds
Started Jun 23 05:11:35 PM PDT 24
Finished Jun 23 05:24:24 PM PDT 24
Peak memory 726064 kb
Host smart-3e6a7705-22eb-4ec5-b113-f5276d17501a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1188882037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1188882037
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2476790198
Short name T37
Test name
Test status
Simulation time 3814644143 ps
CPU time 71.02 seconds
Started Jun 23 05:11:40 PM PDT 24
Finished Jun 23 05:12:52 PM PDT 24
Peak memory 200076 kb
Host smart-99ffa458-0d5a-42b8-8288-0ca75f1aca43
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476790198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2476790198
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1976955055
Short name T537
Test name
Test status
Simulation time 12827919080 ps
CPU time 119.29 seconds
Started Jun 23 05:11:40 PM PDT 24
Finished Jun 23 05:13:40 PM PDT 24
Peak memory 200124 kb
Host smart-66ccfe55-b939-4bec-8a73-4d4dc111c830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976955055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1976955055
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3280263707
Short name T654
Test name
Test status
Simulation time 596201992 ps
CPU time 9.43 seconds
Started Jun 23 05:11:35 PM PDT 24
Finished Jun 23 05:11:45 PM PDT 24
Peak memory 200044 kb
Host smart-19eb3b7f-b900-409b-a03b-4dc0f5f73786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280263707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3280263707
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.922533162
Short name T626
Test name
Test status
Simulation time 171794259 ps
CPU time 1.04 seconds
Started Jun 23 05:11:35 PM PDT 24
Finished Jun 23 05:11:37 PM PDT 24
Peak memory 199812 kb
Host smart-37e7899a-7444-4a95-88cc-88e382a5c1c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922533162 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_hmac_vectors.922533162
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha256_vectors.1430396851
Short name T592
Test name
Test status
Simulation time 39843193970 ps
CPU time 478.47 seconds
Started Jun 23 05:11:37 PM PDT 24
Finished Jun 23 05:19:36 PM PDT 24
Peak memory 200128 kb
Host smart-599e7866-ee86-454e-ace3-3d45cc570890
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1430396851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha256_vectors.1430396851
Directory /workspace/18.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha384_vectors.1885025197
Short name T469
Test name
Test status
Simulation time 30817799248 ps
CPU time 1777.28 seconds
Started Jun 23 05:11:34 PM PDT 24
Finished Jun 23 05:41:12 PM PDT 24
Peak memory 216200 kb
Host smart-8d5c37e7-d50e-4f72-9cf4-bcc04c6b27b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1885025197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha384_vectors.1885025197
Directory /workspace/18.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha512_vectors.2202681127
Short name T643
Test name
Test status
Simulation time 111664102751 ps
CPU time 1915.02 seconds
Started Jun 23 05:11:35 PM PDT 24
Finished Jun 23 05:43:31 PM PDT 24
Peak memory 214976 kb
Host smart-d3e55bd9-d19c-4a15-8ec5-6ceacc6c81e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2202681127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha512_vectors.2202681127
Directory /workspace/18.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.583269969
Short name T546
Test name
Test status
Simulation time 226813329 ps
CPU time 8.32 seconds
Started Jun 23 05:11:37 PM PDT 24
Finished Jun 23 05:11:46 PM PDT 24
Peak memory 200056 kb
Host smart-8717994e-87ff-4e95-a250-d9aa05973107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583269969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.583269969
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.646960852
Short name T25
Test name
Test status
Simulation time 14947569 ps
CPU time 0.59 seconds
Started Jun 23 05:11:40 PM PDT 24
Finished Jun 23 05:11:41 PM PDT 24
Peak memory 195996 kb
Host smart-d283cf76-ecf4-415e-9dc3-6190ce325f28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646960852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.646960852
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1252464318
Short name T218
Test name
Test status
Simulation time 2663978852 ps
CPU time 11.42 seconds
Started Jun 23 05:11:36 PM PDT 24
Finished Jun 23 05:11:49 PM PDT 24
Peak memory 200052 kb
Host smart-57291bbc-daa5-4ff9-b422-24f7ddf69768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252464318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1252464318
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.22907974
Short name T541
Test name
Test status
Simulation time 13279198524 ps
CPU time 1001.47 seconds
Started Jun 23 05:11:36 PM PDT 24
Finished Jun 23 05:28:19 PM PDT 24
Peak memory 756640 kb
Host smart-afd8bf0d-3c00-4262-8afe-abdead255fba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=22907974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.22907974
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3125580715
Short name T494
Test name
Test status
Simulation time 1054176333 ps
CPU time 57.19 seconds
Started Jun 23 05:11:35 PM PDT 24
Finished Jun 23 05:12:33 PM PDT 24
Peak memory 200048 kb
Host smart-80026ca8-dce9-4ec1-9a0d-49b0a252e9df
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125580715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3125580715
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1271130488
Short name T225
Test name
Test status
Simulation time 3975883501 ps
CPU time 72.9 seconds
Started Jun 23 05:11:37 PM PDT 24
Finished Jun 23 05:12:50 PM PDT 24
Peak memory 200160 kb
Host smart-df66ef94-0294-442e-90eb-c4d765ba4b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271130488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1271130488
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1127615882
Short name T437
Test name
Test status
Simulation time 3747606920 ps
CPU time 16.57 seconds
Started Jun 23 05:11:36 PM PDT 24
Finished Jun 23 05:11:53 PM PDT 24
Peak memory 200140 kb
Host smart-075cec5f-5ff8-48be-aff1-10ef852189a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127615882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1127615882
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.3949042795
Short name T599
Test name
Test status
Simulation time 55864923 ps
CPU time 1.14 seconds
Started Jun 23 05:11:34 PM PDT 24
Finished Jun 23 05:11:36 PM PDT 24
Peak memory 199788 kb
Host smart-44be4184-6f6a-4e19-ba5c-5fe30f199b93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949042795 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_hmac_vectors.3949042795
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha256_vectors.3533343529
Short name T346
Test name
Test status
Simulation time 26294983455 ps
CPU time 381.14 seconds
Started Jun 23 05:11:36 PM PDT 24
Finished Jun 23 05:17:58 PM PDT 24
Peak memory 200128 kb
Host smart-c52f35d0-b233-4509-98d1-4c64e2f18abb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3533343529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha256_vectors.3533343529
Directory /workspace/19.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha384_vectors.4153898276
Short name T264
Test name
Test status
Simulation time 166293126632 ps
CPU time 2281.48 seconds
Started Jun 23 05:11:41 PM PDT 24
Finished Jun 23 05:49:43 PM PDT 24
Peak memory 215512 kb
Host smart-fe059716-890a-4775-b278-06f5bd18f562
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4153898276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha384_vectors.4153898276
Directory /workspace/19.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha512_vectors.1929035144
Short name T466
Test name
Test status
Simulation time 277584200604 ps
CPU time 1892.3 seconds
Started Jun 23 05:11:36 PM PDT 24
Finished Jun 23 05:43:09 PM PDT 24
Peak memory 215732 kb
Host smart-ea10d9d6-326d-4ebc-b206-beff605901af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1929035144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha512_vectors.1929035144
Directory /workspace/19.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1103277086
Short name T574
Test name
Test status
Simulation time 15833709108 ps
CPU time 74.35 seconds
Started Jun 23 05:11:34 PM PDT 24
Finished Jun 23 05:12:49 PM PDT 24
Peak memory 200144 kb
Host smart-9861cedc-dac6-4f0a-a15b-3df319a32487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103277086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1103277086
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2480280152
Short name T527
Test name
Test status
Simulation time 15813046 ps
CPU time 0.58 seconds
Started Jun 23 05:11:11 PM PDT 24
Finished Jun 23 05:11:12 PM PDT 24
Peak memory 195996 kb
Host smart-2a3d45f2-ca64-4a8d-bdf9-1d87886c9f4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480280152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2480280152
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3841158587
Short name T474
Test name
Test status
Simulation time 2478243218 ps
CPU time 38.76 seconds
Started Jun 23 05:11:08 PM PDT 24
Finished Jun 23 05:11:47 PM PDT 24
Peak memory 200048 kb
Host smart-2db8e13e-2f1d-48ef-9fc1-01243408f384
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3841158587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3841158587
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3269518817
Short name T421
Test name
Test status
Simulation time 1456526076 ps
CPU time 353.32 seconds
Started Jun 23 05:11:07 PM PDT 24
Finished Jun 23 05:17:01 PM PDT 24
Peak memory 655940 kb
Host smart-a9970266-b36f-40c2-926a-e7aa69d77f1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3269518817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3269518817
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3523153449
Short name T489
Test name
Test status
Simulation time 4129887853 ps
CPU time 115.74 seconds
Started Jun 23 05:11:04 PM PDT 24
Finished Jun 23 05:13:00 PM PDT 24
Peak memory 200120 kb
Host smart-b582c1f2-c2bc-487b-b1cc-451d32bc9eaf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523153449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3523153449
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3127044156
Short name T384
Test name
Test status
Simulation time 406989250 ps
CPU time 23.49 seconds
Started Jun 23 05:11:11 PM PDT 24
Finished Jun 23 05:11:35 PM PDT 24
Peak memory 200068 kb
Host smart-58537630-93d7-44a6-9aff-f554de620a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127044156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3127044156
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3605094125
Short name T47
Test name
Test status
Simulation time 753512801 ps
CPU time 1.04 seconds
Started Jun 23 05:11:07 PM PDT 24
Finished Jun 23 05:11:08 PM PDT 24
Peak memory 219292 kb
Host smart-76f39440-830d-499d-bebf-b4abdb1d6a2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605094125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3605094125
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2278559311
Short name T335
Test name
Test status
Simulation time 276520734 ps
CPU time 2.52 seconds
Started Jun 23 05:11:09 PM PDT 24
Finished Jun 23 05:11:11 PM PDT 24
Peak memory 199800 kb
Host smart-0dd9847d-a53b-4ceb-b478-81ff3c67de6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278559311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2278559311
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1090908634
Short name T347
Test name
Test status
Simulation time 42704984 ps
CPU time 1.14 seconds
Started Jun 23 05:11:08 PM PDT 24
Finished Jun 23 05:11:09 PM PDT 24
Peak memory 199824 kb
Host smart-6711a785-8c62-42ee-8465-f5412b10253a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090908634 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac_vectors.1090908634
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.3837415060
Short name T447
Test name
Test status
Simulation time 111923321098 ps
CPU time 508.43 seconds
Started Jun 23 05:11:05 PM PDT 24
Finished Jun 23 05:19:33 PM PDT 24
Peak memory 200128 kb
Host smart-aa5713d6-c16c-4453-9f35-51e7fa5a79a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3837415060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.3837415060
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.4256762943
Short name T657
Test name
Test status
Simulation time 157239046622 ps
CPU time 2005.13 seconds
Started Jun 23 05:11:08 PM PDT 24
Finished Jun 23 05:44:33 PM PDT 24
Peak memory 216168 kb
Host smart-c3f782d5-6db5-47a0-b7a6-9557bcebd7ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4256762943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.4256762943
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2411376136
Short name T4
Test name
Test status
Simulation time 399227772 ps
CPU time 12.37 seconds
Started Jun 23 05:11:06 PM PDT 24
Finished Jun 23 05:11:19 PM PDT 24
Peak memory 200096 kb
Host smart-3f4e65e4-f186-40d5-be2c-38c04fc6593c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411376136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2411376136
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.287728066
Short name T605
Test name
Test status
Simulation time 47145773 ps
CPU time 0.6 seconds
Started Jun 23 05:11:39 PM PDT 24
Finished Jun 23 05:11:40 PM PDT 24
Peak memory 195996 kb
Host smart-27869d83-8325-455d-a391-0eb2967158c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287728066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.287728066
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1789047228
Short name T253
Test name
Test status
Simulation time 306169702 ps
CPU time 14.06 seconds
Started Jun 23 05:11:35 PM PDT 24
Finished Jun 23 05:11:50 PM PDT 24
Peak memory 199984 kb
Host smart-b95f0a9b-1a2c-49a5-997a-65e77ef2b5d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1789047228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1789047228
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2442229139
Short name T212
Test name
Test status
Simulation time 7768273817 ps
CPU time 28.3 seconds
Started Jun 23 05:11:36 PM PDT 24
Finished Jun 23 05:12:05 PM PDT 24
Peak memory 200096 kb
Host smart-34c34bd2-3d1e-4c1f-b118-a1245df9c916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442229139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2442229139
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1174444242
Short name T352
Test name
Test status
Simulation time 8746141326 ps
CPU time 624.48 seconds
Started Jun 23 05:11:35 PM PDT 24
Finished Jun 23 05:22:00 PM PDT 24
Peak memory 693928 kb
Host smart-296b1c11-c476-4a1b-bf3e-928d62f88f66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1174444242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1174444242
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1941545262
Short name T379
Test name
Test status
Simulation time 10735374927 ps
CPU time 136.12 seconds
Started Jun 23 05:11:37 PM PDT 24
Finished Jun 23 05:13:54 PM PDT 24
Peak memory 200116 kb
Host smart-52bd9547-ac09-40c6-9641-bc76935c8280
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941545262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1941545262
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.961540923
Short name T150
Test name
Test status
Simulation time 99569915 ps
CPU time 3.16 seconds
Started Jun 23 05:11:41 PM PDT 24
Finished Jun 23 05:11:44 PM PDT 24
Peak memory 200020 kb
Host smart-a5293948-7306-45a6-a4af-4ecdc6fee47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961540923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.961540923
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2240039482
Short name T213
Test name
Test status
Simulation time 696523981 ps
CPU time 3 seconds
Started Jun 23 05:11:35 PM PDT 24
Finished Jun 23 05:11:38 PM PDT 24
Peak memory 200076 kb
Host smart-78e34007-5291-4777-a2a5-98341a650227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240039482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2240039482
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.1518799718
Short name T269
Test name
Test status
Simulation time 89589476 ps
CPU time 1.06 seconds
Started Jun 23 05:11:43 PM PDT 24
Finished Jun 23 05:11:45 PM PDT 24
Peak memory 199812 kb
Host smart-8a3c2ad6-8f22-4306-9c2b-d06d6b5d863c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518799718 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_hmac_vectors.1518799718
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha256_vectors.718945225
Short name T180
Test name
Test status
Simulation time 133752271170 ps
CPU time 472.56 seconds
Started Jun 23 05:11:35 PM PDT 24
Finished Jun 23 05:19:28 PM PDT 24
Peak memory 200128 kb
Host smart-70bae6e3-1b71-4d21-9f77-417b373a4c0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=718945225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha256_vectors.718945225
Directory /workspace/20.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha384_vectors.2973055978
Short name T644
Test name
Test status
Simulation time 667059917496 ps
CPU time 1972.98 seconds
Started Jun 23 05:11:35 PM PDT 24
Finished Jun 23 05:44:29 PM PDT 24
Peak memory 216076 kb
Host smart-ad2935f1-ce18-4220-ae26-83fd9b594236
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2973055978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha384_vectors.2973055978
Directory /workspace/20.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha512_vectors.3574282662
Short name T587
Test name
Test status
Simulation time 31921466195 ps
CPU time 1802.34 seconds
Started Jun 23 05:11:36 PM PDT 24
Finished Jun 23 05:41:40 PM PDT 24
Peak memory 215696 kb
Host smart-a79f3c10-e3ac-453b-aba4-25bf397ccb66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3574282662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha512_vectors.3574282662
Directory /workspace/20.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.4242868538
Short name T522
Test name
Test status
Simulation time 8557917355 ps
CPU time 52.87 seconds
Started Jun 23 05:11:36 PM PDT 24
Finished Jun 23 05:12:30 PM PDT 24
Peak memory 200320 kb
Host smart-6bf6c1ae-7ab1-470a-878c-32c425b030d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242868538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.4242868538
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3336029970
Short name T330
Test name
Test status
Simulation time 52839183 ps
CPU time 0.56 seconds
Started Jun 23 05:11:43 PM PDT 24
Finished Jun 23 05:11:43 PM PDT 24
Peak memory 194828 kb
Host smart-311091fa-9c50-4e87-b916-ebf8deff09ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336029970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3336029970
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1917975216
Short name T454
Test name
Test status
Simulation time 760656444 ps
CPU time 35.41 seconds
Started Jun 23 05:11:41 PM PDT 24
Finished Jun 23 05:12:17 PM PDT 24
Peak memory 200100 kb
Host smart-efa8102a-c637-46bf-ad27-9a2cc5210af1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1917975216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1917975216
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.439095082
Short name T376
Test name
Test status
Simulation time 9481515917 ps
CPU time 34.29 seconds
Started Jun 23 05:11:44 PM PDT 24
Finished Jun 23 05:12:18 PM PDT 24
Peak memory 200040 kb
Host smart-182ed224-5ed1-477c-b690-c2a9d7937e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439095082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.439095082
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3028735154
Short name T268
Test name
Test status
Simulation time 3156213030 ps
CPU time 1008.14 seconds
Started Jun 23 05:11:40 PM PDT 24
Finished Jun 23 05:28:29 PM PDT 24
Peak memory 689456 kb
Host smart-fb4cd8e4-8ab1-4f4a-9b97-4b3ee308a92b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3028735154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3028735154
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.252348931
Short name T350
Test name
Test status
Simulation time 622058197 ps
CPU time 9.07 seconds
Started Jun 23 05:11:40 PM PDT 24
Finished Jun 23 05:11:49 PM PDT 24
Peak memory 199988 kb
Host smart-d46b0378-25f4-49ed-88c8-4d16665e8935
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252348931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.252348931
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1374555911
Short name T641
Test name
Test status
Simulation time 9898412721 ps
CPU time 139.13 seconds
Started Jun 23 05:11:42 PM PDT 24
Finished Jun 23 05:14:01 PM PDT 24
Peak memory 200236 kb
Host smart-1597a747-5f56-4725-813c-7262977cef71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374555911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1374555911
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2167534364
Short name T355
Test name
Test status
Simulation time 1451113264 ps
CPU time 6.96 seconds
Started Jun 23 05:11:42 PM PDT 24
Finished Jun 23 05:11:50 PM PDT 24
Peak memory 200300 kb
Host smart-fc867b2b-8fca-4612-8c3a-2f6621d5d612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167534364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2167534364
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.2507086335
Short name T631
Test name
Test status
Simulation time 81068213 ps
CPU time 1.1 seconds
Started Jun 23 05:11:42 PM PDT 24
Finished Jun 23 05:11:44 PM PDT 24
Peak memory 199872 kb
Host smart-376d308b-d759-4149-98c2-c1a8c676c4cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507086335 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_hmac_vectors.2507086335
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha256_vectors.9059804
Short name T583
Test name
Test status
Simulation time 31685520329 ps
CPU time 415.44 seconds
Started Jun 23 05:11:43 PM PDT 24
Finished Jun 23 05:18:39 PM PDT 24
Peak memory 200128 kb
Host smart-d06fc6c7-f531-4091-860c-7e90633490ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=9059804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha256_vectors.9059804
Directory /workspace/21.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha384_vectors.832321785
Short name T310
Test name
Test status
Simulation time 32240575327 ps
CPU time 1807.91 seconds
Started Jun 23 05:11:41 PM PDT 24
Finished Jun 23 05:41:49 PM PDT 24
Peak memory 216004 kb
Host smart-782e999b-c561-48a0-9247-b1cdbd8630a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=832321785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha384_vectors.832321785
Directory /workspace/21.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha512_vectors.825198442
Short name T163
Test name
Test status
Simulation time 99192836028 ps
CPU time 1871.41 seconds
Started Jun 23 05:11:40 PM PDT 24
Finished Jun 23 05:42:52 PM PDT 24
Peak memory 216584 kb
Host smart-34a60849-29a9-4e9b-b616-d16495200ad0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=825198442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha512_vectors.825198442
Directory /workspace/21.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2121854051
Short name T623
Test name
Test status
Simulation time 1211046406 ps
CPU time 18.77 seconds
Started Jun 23 05:11:44 PM PDT 24
Finished Jun 23 05:12:03 PM PDT 24
Peak memory 200000 kb
Host smart-bbda8120-5338-41a5-b0ce-bc8f8db38d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121854051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2121854051
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1837548381
Short name T291
Test name
Test status
Simulation time 10170731 ps
CPU time 0.59 seconds
Started Jun 23 05:11:47 PM PDT 24
Finished Jun 23 05:11:48 PM PDT 24
Peak memory 194968 kb
Host smart-bba9baba-0367-4588-961c-ba73c4b9e971
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837548381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1837548381
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3049311392
Short name T603
Test name
Test status
Simulation time 654586757 ps
CPU time 7.53 seconds
Started Jun 23 05:11:42 PM PDT 24
Finished Jun 23 05:11:50 PM PDT 24
Peak memory 200040 kb
Host smart-23b1073c-aebe-4277-9048-0050271df9a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3049311392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3049311392
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2388750013
Short name T380
Test name
Test status
Simulation time 5032908937 ps
CPU time 63.96 seconds
Started Jun 23 05:11:43 PM PDT 24
Finished Jun 23 05:12:47 PM PDT 24
Peak memory 200040 kb
Host smart-b745ddc8-5cb8-47cc-b098-fca279c3454a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388750013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2388750013
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3428228316
Short name T463
Test name
Test status
Simulation time 1450791889 ps
CPU time 369.03 seconds
Started Jun 23 05:11:43 PM PDT 24
Finished Jun 23 05:17:53 PM PDT 24
Peak memory 646692 kb
Host smart-80a186db-49ec-4afd-9b8f-368220bd8fa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3428228316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3428228316
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.139903618
Short name T450
Test name
Test status
Simulation time 4964439489 ps
CPU time 68.7 seconds
Started Jun 23 05:11:40 PM PDT 24
Finished Jun 23 05:12:49 PM PDT 24
Peak memory 200108 kb
Host smart-5b404594-2cbd-48a2-af17-40f1edc5d936
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139903618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.139903618
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3154459984
Short name T143
Test name
Test status
Simulation time 18293832547 ps
CPU time 63.35 seconds
Started Jun 23 05:11:42 PM PDT 24
Finished Jun 23 05:12:46 PM PDT 24
Peak memory 208396 kb
Host smart-26def01b-de37-4203-bd85-bcdd76082f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154459984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3154459984
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3465848477
Short name T191
Test name
Test status
Simulation time 804130887 ps
CPU time 5.05 seconds
Started Jun 23 05:11:42 PM PDT 24
Finished Jun 23 05:11:47 PM PDT 24
Peak memory 199936 kb
Host smart-32801651-d7f6-4654-b87b-06bd7932993c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465848477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3465848477
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.3894139217
Short name T655
Test name
Test status
Simulation time 115818129 ps
CPU time 1.13 seconds
Started Jun 23 05:11:47 PM PDT 24
Finished Jun 23 05:11:49 PM PDT 24
Peak memory 199964 kb
Host smart-ddbd5dec-926a-4c7f-b031-f3ae1d4fcacd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894139217 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_hmac_vectors.3894139217
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha256_vectors.1896465892
Short name T514
Test name
Test status
Simulation time 38465942749 ps
CPU time 541.77 seconds
Started Jun 23 05:11:41 PM PDT 24
Finished Jun 23 05:20:43 PM PDT 24
Peak memory 200140 kb
Host smart-7f50d5c4-9527-40d0-a0b1-3645d9d01845
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1896465892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha256_vectors.1896465892
Directory /workspace/22.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha384_vectors.4253853702
Short name T204
Test name
Test status
Simulation time 80896020301 ps
CPU time 1617.54 seconds
Started Jun 23 05:11:49 PM PDT 24
Finished Jun 23 05:38:47 PM PDT 24
Peak memory 216112 kb
Host smart-ff580c3d-045e-4ccc-a627-7ca6b2f2ff71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4253853702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha384_vectors.4253853702
Directory /workspace/22.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha512_vectors.1884474526
Short name T451
Test name
Test status
Simulation time 604612973825 ps
CPU time 1747.52 seconds
Started Jun 23 05:11:48 PM PDT 24
Finished Jun 23 05:40:56 PM PDT 24
Peak memory 216448 kb
Host smart-b5719a94-0223-41a9-ab19-6468c4bc0ab8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1884474526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha512_vectors.1884474526
Directory /workspace/22.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2362671748
Short name T575
Test name
Test status
Simulation time 9287118034 ps
CPU time 92.78 seconds
Started Jun 23 05:11:40 PM PDT 24
Finished Jun 23 05:13:14 PM PDT 24
Peak memory 200172 kb
Host smart-75d9ad91-43e0-4ff9-8da9-fa2be4c0251e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362671748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2362671748
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2485720281
Short name T183
Test name
Test status
Simulation time 24784372 ps
CPU time 0.55 seconds
Started Jun 23 05:11:48 PM PDT 24
Finished Jun 23 05:11:49 PM PDT 24
Peak memory 194980 kb
Host smart-8f53389f-ac5f-4473-abeb-6832d7aceee0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485720281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2485720281
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3497506377
Short name T237
Test name
Test status
Simulation time 1972769521 ps
CPU time 46.09 seconds
Started Jun 23 05:11:48 PM PDT 24
Finished Jun 23 05:12:35 PM PDT 24
Peak memory 200036 kb
Host smart-a50e0877-8917-4970-b33e-57912152ffd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3497506377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3497506377
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1032040030
Short name T161
Test name
Test status
Simulation time 3546334687 ps
CPU time 12.04 seconds
Started Jun 23 05:11:47 PM PDT 24
Finished Jun 23 05:11:59 PM PDT 24
Peak memory 200140 kb
Host smart-acc1dbb3-6c70-4bea-aac7-cb4a4c2a3ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032040030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1032040030
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1655251251
Short name T182
Test name
Test status
Simulation time 13923466520 ps
CPU time 700.18 seconds
Started Jun 23 05:11:46 PM PDT 24
Finished Jun 23 05:23:27 PM PDT 24
Peak memory 677888 kb
Host smart-eda5c31f-1db4-4df0-a9c6-e813077c14a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1655251251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1655251251
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1117208242
Short name T187
Test name
Test status
Simulation time 2839900613 ps
CPU time 14.38 seconds
Started Jun 23 05:11:46 PM PDT 24
Finished Jun 23 05:12:01 PM PDT 24
Peak memory 200080 kb
Host smart-2ea6fd82-240a-4321-a5c8-b9aabde99cc5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117208242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1117208242
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1470762743
Short name T53
Test name
Test status
Simulation time 13973836330 ps
CPU time 102.11 seconds
Started Jun 23 05:11:47 PM PDT 24
Finished Jun 23 05:13:30 PM PDT 24
Peak memory 200332 kb
Host smart-be61172f-38c4-4967-baa1-d62b38656bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470762743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1470762743
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1987771627
Short name T606
Test name
Test status
Simulation time 567074535 ps
CPU time 10.39 seconds
Started Jun 23 05:11:48 PM PDT 24
Finished Jun 23 05:11:59 PM PDT 24
Peak memory 200080 kb
Host smart-ffc10261-1d73-4f40-81d2-7d9437bb038b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987771627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1987771627
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.1832394464
Short name T533
Test name
Test status
Simulation time 81710122 ps
CPU time 1.09 seconds
Started Jun 23 05:11:48 PM PDT 24
Finished Jun 23 05:11:49 PM PDT 24
Peak memory 199628 kb
Host smart-8cee3f43-418f-41e5-b6a0-cb3b568c2e10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832394464 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_hmac_vectors.1832394464
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha256_vectors.650670561
Short name T516
Test name
Test status
Simulation time 8803069329 ps
CPU time 418.35 seconds
Started Jun 23 05:11:47 PM PDT 24
Finished Jun 23 05:18:46 PM PDT 24
Peak memory 200120 kb
Host smart-640b7346-6b95-4399-88f7-565ffcf328e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=650670561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha256_vectors.650670561
Directory /workspace/23.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha384_vectors.2623537574
Short name T503
Test name
Test status
Simulation time 334134686996 ps
CPU time 2114.69 seconds
Started Jun 23 05:11:46 PM PDT 24
Finished Jun 23 05:47:02 PM PDT 24
Peak memory 216488 kb
Host smart-7501c543-02ae-48f9-961b-39c7c0d47c2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2623537574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha384_vectors.2623537574
Directory /workspace/23.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha512_vectors.3157312696
Short name T430
Test name
Test status
Simulation time 656813778865 ps
CPU time 2085.55 seconds
Started Jun 23 05:11:47 PM PDT 24
Finished Jun 23 05:46:33 PM PDT 24
Peak memory 215832 kb
Host smart-ee3e1243-a47b-4dda-a49b-c1ef20462345
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3157312696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha512_vectors.3157312696
Directory /workspace/23.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3526140822
Short name T110
Test name
Test status
Simulation time 281433300 ps
CPU time 8.36 seconds
Started Jun 23 05:11:50 PM PDT 24
Finished Jun 23 05:11:59 PM PDT 24
Peak memory 200120 kb
Host smart-16c1c38a-d399-4a73-833b-3505fe723fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526140822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3526140822
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3088648652
Short name T499
Test name
Test status
Simulation time 11851914 ps
CPU time 0.61 seconds
Started Jun 23 05:11:53 PM PDT 24
Finished Jun 23 05:11:54 PM PDT 24
Peak memory 195992 kb
Host smart-9f9fd6f8-ec89-4006-bae7-8b7d804aeac9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088648652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3088648652
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.76607500
Short name T394
Test name
Test status
Simulation time 433972202 ps
CPU time 22.49 seconds
Started Jun 23 05:11:51 PM PDT 24
Finished Jun 23 05:12:14 PM PDT 24
Peak memory 200040 kb
Host smart-7a39b9a5-fd0d-472f-b42c-23886e45c02f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=76607500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.76607500
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.4152859606
Short name T642
Test name
Test status
Simulation time 716422573 ps
CPU time 22.31 seconds
Started Jun 23 05:11:53 PM PDT 24
Finished Jun 23 05:12:16 PM PDT 24
Peak memory 200000 kb
Host smart-fe5b897f-c333-460e-8ed1-c56069e050d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152859606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.4152859606
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3861955792
Short name T245
Test name
Test status
Simulation time 685977158 ps
CPU time 101.51 seconds
Started Jun 23 05:11:53 PM PDT 24
Finished Jun 23 05:13:35 PM PDT 24
Peak memory 605744 kb
Host smart-c80eb8a2-4582-48dd-8ed3-013990dc5dbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3861955792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3861955792
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3218007006
Short name T203
Test name
Test status
Simulation time 13856122264 ps
CPU time 40.5 seconds
Started Jun 23 05:11:51 PM PDT 24
Finished Jun 23 05:12:32 PM PDT 24
Peak memory 200092 kb
Host smart-5643124b-b76d-462d-b472-d9f767dbd740
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218007006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3218007006
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2505053585
Short name T31
Test name
Test status
Simulation time 2686532904 ps
CPU time 80.41 seconds
Started Jun 23 05:11:51 PM PDT 24
Finished Jun 23 05:13:12 PM PDT 24
Peak memory 200148 kb
Host smart-323318c6-6aee-4c29-aebb-765cc756771c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505053585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2505053585
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1570568495
Short name T196
Test name
Test status
Simulation time 1121173381 ps
CPU time 9.61 seconds
Started Jun 23 05:11:47 PM PDT 24
Finished Jun 23 05:11:58 PM PDT 24
Peak memory 200072 kb
Host smart-f88d2249-cd79-48ab-ab74-acae2e173f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570568495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1570568495
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.167695067
Short name T360
Test name
Test status
Simulation time 59295497 ps
CPU time 1.37 seconds
Started Jun 23 05:11:52 PM PDT 24
Finished Jun 23 05:11:53 PM PDT 24
Peak memory 200200 kb
Host smart-3bac20c4-7a5e-4e61-86ef-277c49c27418
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167695067 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_hmac_vectors.167695067
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha256_vectors.1357933930
Short name T247
Test name
Test status
Simulation time 45626817352 ps
CPU time 494.92 seconds
Started Jun 23 05:11:53 PM PDT 24
Finished Jun 23 05:20:08 PM PDT 24
Peak memory 200088 kb
Host smart-3077f68e-9d73-428d-8821-628176f4e5bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1357933930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha256_vectors.1357933930
Directory /workspace/24.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha384_vectors.4200093038
Short name T366
Test name
Test status
Simulation time 132115196828 ps
CPU time 1942.27 seconds
Started Jun 23 05:11:52 PM PDT 24
Finished Jun 23 05:44:15 PM PDT 24
Peak memory 216520 kb
Host smart-f348ee3e-c256-4fea-8eaa-30273889018f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4200093038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha384_vectors.4200093038
Directory /workspace/24.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha512_vectors.3454232969
Short name T75
Test name
Test status
Simulation time 472279026238 ps
CPU time 2059.71 seconds
Started Jun 23 05:11:52 PM PDT 24
Finished Jun 23 05:46:13 PM PDT 24
Peak memory 215640 kb
Host smart-b2dee70a-e2da-470b-b22d-1a6001ec99d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3454232969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha512_vectors.3454232969
Directory /workspace/24.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2795062926
Short name T382
Test name
Test status
Simulation time 14482473993 ps
CPU time 36.2 seconds
Started Jun 23 05:11:54 PM PDT 24
Finished Jun 23 05:12:31 PM PDT 24
Peak memory 200164 kb
Host smart-2f9fbddc-9490-4e99-a2f0-36cfaa042d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795062926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2795062926
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3942628370
Short name T439
Test name
Test status
Simulation time 11764712 ps
CPU time 0.6 seconds
Started Jun 23 05:11:55 PM PDT 24
Finished Jun 23 05:11:56 PM PDT 24
Peak memory 196052 kb
Host smart-97037f83-fd0f-40dc-9246-2391b6ab508e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942628370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3942628370
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2183277798
Short name T227
Test name
Test status
Simulation time 9969655811 ps
CPU time 43.16 seconds
Started Jun 23 05:11:52 PM PDT 24
Finished Jun 23 05:12:36 PM PDT 24
Peak memory 200288 kb
Host smart-25f42bc0-7590-4215-b02b-7a54834766b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2183277798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2183277798
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2266026829
Short name T323
Test name
Test status
Simulation time 2003492377 ps
CPU time 13.47 seconds
Started Jun 23 05:11:54 PM PDT 24
Finished Jun 23 05:12:08 PM PDT 24
Peak memory 200096 kb
Host smart-946b885c-734e-4818-a7cb-d27cf17ba808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266026829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2266026829
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.4051729485
Short name T211
Test name
Test status
Simulation time 1128248609 ps
CPU time 250.36 seconds
Started Jun 23 05:11:53 PM PDT 24
Finished Jun 23 05:16:04 PM PDT 24
Peak memory 496068 kb
Host smart-89c28245-bec2-4952-adc5-9ed22b2956af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4051729485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.4051729485
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3457920505
Short name T298
Test name
Test status
Simulation time 879161520 ps
CPU time 24.29 seconds
Started Jun 23 05:11:59 PM PDT 24
Finished Jun 23 05:12:24 PM PDT 24
Peak memory 200028 kb
Host smart-277a338d-7f73-4719-8d75-0eb9266e2545
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457920505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3457920505
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.4041633991
Short name T554
Test name
Test status
Simulation time 436544478 ps
CPU time 12.89 seconds
Started Jun 23 05:11:52 PM PDT 24
Finished Jun 23 05:12:05 PM PDT 24
Peak memory 200080 kb
Host smart-f0c8145d-668a-4b7f-87a2-32e47b9b4a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041633991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.4041633991
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2707593827
Short name T357
Test name
Test status
Simulation time 382582089 ps
CPU time 7.64 seconds
Started Jun 23 05:11:54 PM PDT 24
Finished Jun 23 05:12:02 PM PDT 24
Peak memory 200052 kb
Host smart-e3629d96-f4df-48d8-85eb-4847e29ddc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707593827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2707593827
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.2982602131
Short name T177
Test name
Test status
Simulation time 118271288 ps
CPU time 1.26 seconds
Started Jun 23 05:11:59 PM PDT 24
Finished Jun 23 05:12:01 PM PDT 24
Peak memory 200024 kb
Host smart-b0cca83d-d5b2-482f-9dd9-15bb153e956f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982602131 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_hmac_vectors.2982602131
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha256_vectors.3997893105
Short name T8
Test name
Test status
Simulation time 43836613667 ps
CPU time 554.02 seconds
Started Jun 23 05:11:57 PM PDT 24
Finished Jun 23 05:21:12 PM PDT 24
Peak memory 200100 kb
Host smart-649ae0c5-59ae-49ea-90e4-f645d4cad716
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3997893105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha256_vectors.3997893105
Directory /workspace/25.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha384_vectors.1524873131
Short name T157
Test name
Test status
Simulation time 319292010047 ps
CPU time 2040.75 seconds
Started Jun 23 05:11:56 PM PDT 24
Finished Jun 23 05:45:58 PM PDT 24
Peak memory 216532 kb
Host smart-6b22b5c1-9839-4882-bb35-e7fcac55252e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1524873131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha384_vectors.1524873131
Directory /workspace/25.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3458833794
Short name T290
Test name
Test status
Simulation time 3036586922 ps
CPU time 42.56 seconds
Started Jun 23 05:11:58 PM PDT 24
Finished Jun 23 05:12:41 PM PDT 24
Peak memory 200124 kb
Host smart-136c5882-2dbc-44d8-bf21-11f9abb809f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458833794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3458833794
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.318689224
Short name T613
Test name
Test status
Simulation time 23859034 ps
CPU time 0.61 seconds
Started Jun 23 05:12:05 PM PDT 24
Finished Jun 23 05:12:06 PM PDT 24
Peak memory 195736 kb
Host smart-42105e57-1925-4096-8c23-3b9b6e1a0706
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318689224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.318689224
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.965849831
Short name T82
Test name
Test status
Simulation time 1036931673 ps
CPU time 49.69 seconds
Started Jun 23 05:11:57 PM PDT 24
Finished Jun 23 05:12:48 PM PDT 24
Peak memory 200072 kb
Host smart-2968280b-2fdc-4cc9-82b5-185623ed1f7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=965849831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.965849831
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.4137376672
Short name T520
Test name
Test status
Simulation time 6865314944 ps
CPU time 27.66 seconds
Started Jun 23 05:11:57 PM PDT 24
Finished Jun 23 05:12:25 PM PDT 24
Peak memory 200120 kb
Host smart-56d979c3-3a1f-4e20-8972-cfb163b1e61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137376672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.4137376672
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2994513191
Short name T612
Test name
Test status
Simulation time 19689577883 ps
CPU time 1310.12 seconds
Started Jun 23 05:11:56 PM PDT 24
Finished Jun 23 05:33:47 PM PDT 24
Peak memory 772600 kb
Host smart-4c2b0c0e-c57d-463b-93bd-33dd9564512d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2994513191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2994513191
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.129327904
Short name T497
Test name
Test status
Simulation time 55582693198 ps
CPU time 76.89 seconds
Started Jun 23 05:11:58 PM PDT 24
Finished Jun 23 05:13:16 PM PDT 24
Peak memory 200132 kb
Host smart-efbdaff6-36f8-4fd0-b024-ab260aa1c622
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129327904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.129327904
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.4027835394
Short name T586
Test name
Test status
Simulation time 1340594602 ps
CPU time 27.6 seconds
Started Jun 23 05:12:00 PM PDT 24
Finished Jun 23 05:12:28 PM PDT 24
Peak memory 200080 kb
Host smart-64285688-3cee-4dc9-bd22-7e21245f578c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027835394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.4027835394
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2560544764
Short name T235
Test name
Test status
Simulation time 2829397106 ps
CPU time 15.12 seconds
Started Jun 23 05:11:57 PM PDT 24
Finished Jun 23 05:12:13 PM PDT 24
Peak memory 200100 kb
Host smart-d260d5d3-f3a9-4043-80b3-a85f6beb6076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560544764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2560544764
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.389945544
Short name T258
Test name
Test status
Simulation time 237278899 ps
CPU time 1.32 seconds
Started Jun 23 05:11:58 PM PDT 24
Finished Jun 23 05:12:00 PM PDT 24
Peak memory 200072 kb
Host smart-3589fe7a-32e6-4db2-937f-ba3a76bea199
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389945544 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_hmac_vectors.389945544
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha256_vectors.3647649499
Short name T239
Test name
Test status
Simulation time 108425634429 ps
CPU time 475.79 seconds
Started Jun 23 05:11:56 PM PDT 24
Finished Jun 23 05:19:52 PM PDT 24
Peak memory 200020 kb
Host smart-5ee43542-f74d-4069-adac-217396d47f5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3647649499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha256_vectors.3647649499
Directory /workspace/26.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha384_vectors.3447619603
Short name T562
Test name
Test status
Simulation time 236399646442 ps
CPU time 1970.05 seconds
Started Jun 23 05:11:55 PM PDT 24
Finished Jun 23 05:44:45 PM PDT 24
Peak memory 216424 kb
Host smart-249a32be-5de3-4e2f-a04d-17c803ad01b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3447619603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha384_vectors.3447619603
Directory /workspace/26.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha512_vectors.4222427596
Short name T342
Test name
Test status
Simulation time 442525885511 ps
CPU time 2055.86 seconds
Started Jun 23 05:11:57 PM PDT 24
Finished Jun 23 05:46:14 PM PDT 24
Peak memory 216336 kb
Host smart-5a078f3e-2f82-470d-a83d-10d3d327dd84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4222427596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha512_vectors.4222427596
Directory /workspace/26.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.108825891
Short name T566
Test name
Test status
Simulation time 2093292707 ps
CPU time 28.75 seconds
Started Jun 23 05:11:58 PM PDT 24
Finished Jun 23 05:12:27 PM PDT 24
Peak memory 200096 kb
Host smart-1e9240bf-c8a2-4e39-b3b1-d6a84efdac03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108825891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.108825891
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2024752776
Short name T190
Test name
Test status
Simulation time 14561855 ps
CPU time 0.63 seconds
Started Jun 23 05:12:03 PM PDT 24
Finished Jun 23 05:12:04 PM PDT 24
Peak memory 195808 kb
Host smart-145826db-fc03-4134-912f-bea823a58d31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024752776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2024752776
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1091954618
Short name T15
Test name
Test status
Simulation time 680794259 ps
CPU time 33.05 seconds
Started Jun 23 05:12:03 PM PDT 24
Finished Jun 23 05:12:36 PM PDT 24
Peak memory 200052 kb
Host smart-25453210-cfc5-4273-9836-7bb82b1fc086
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1091954618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1091954618
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.898640513
Short name T610
Test name
Test status
Simulation time 2762316712 ps
CPU time 56.76 seconds
Started Jun 23 05:12:06 PM PDT 24
Finished Jun 23 05:13:03 PM PDT 24
Peak memory 200164 kb
Host smart-838ec36b-5c49-42c5-9bbc-eceb10655680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898640513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.898640513
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.872023943
Short name T147
Test name
Test status
Simulation time 4868861895 ps
CPU time 245.26 seconds
Started Jun 23 05:12:06 PM PDT 24
Finished Jun 23 05:16:12 PM PDT 24
Peak memory 664532 kb
Host smart-99ecf883-93d7-4103-b88b-c16bda176011
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=872023943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.872023943
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.858232872
Short name T578
Test name
Test status
Simulation time 40584917588 ps
CPU time 179.61 seconds
Started Jun 23 05:12:03 PM PDT 24
Finished Jun 23 05:15:03 PM PDT 24
Peak memory 200128 kb
Host smart-06c29c2e-d1d4-4b95-ad1b-d5c53bea8de3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858232872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.858232872
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.129000935
Short name T207
Test name
Test status
Simulation time 3005795838 ps
CPU time 43.41 seconds
Started Jun 23 05:12:06 PM PDT 24
Finished Jun 23 05:12:50 PM PDT 24
Peak memory 200172 kb
Host smart-d0c21827-f2d1-495e-b82a-981a9c46a4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129000935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.129000935
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2713274589
Short name T255
Test name
Test status
Simulation time 1024465279 ps
CPU time 8.88 seconds
Started Jun 23 05:12:03 PM PDT 24
Finished Jun 23 05:12:12 PM PDT 24
Peak memory 200044 kb
Host smart-7a74af53-c215-4f18-926f-f45d5131d2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713274589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2713274589
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.818299519
Short name T413
Test name
Test status
Simulation time 741073922 ps
CPU time 1.51 seconds
Started Jun 23 05:12:06 PM PDT 24
Finished Jun 23 05:12:08 PM PDT 24
Peak memory 200084 kb
Host smart-fd1d777b-e328-4bf1-b204-9872eb99cdbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818299519 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_hmac_vectors.818299519
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha256_vectors.620892999
Short name T280
Test name
Test status
Simulation time 94638917674 ps
CPU time 485.77 seconds
Started Jun 23 05:12:03 PM PDT 24
Finished Jun 23 05:20:10 PM PDT 24
Peak memory 200332 kb
Host smart-6f80a1c7-d23a-459f-b906-ccc9882d6a96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=620892999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha256_vectors.620892999
Directory /workspace/27.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha384_vectors.4023618231
Short name T415
Test name
Test status
Simulation time 61693404266 ps
CPU time 1847.84 seconds
Started Jun 23 05:12:05 PM PDT 24
Finished Jun 23 05:42:54 PM PDT 24
Peak memory 208400 kb
Host smart-97a845ea-eaa8-4962-a9fe-a827286ddb50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4023618231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha384_vectors.4023618231
Directory /workspace/27.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha512_vectors.3512420658
Short name T636
Test name
Test status
Simulation time 112745281632 ps
CPU time 1616.86 seconds
Started Jun 23 05:12:05 PM PDT 24
Finished Jun 23 05:39:03 PM PDT 24
Peak memory 216500 kb
Host smart-110cece3-d6d4-4295-8a07-a21720f37de3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3512420658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha512_vectors.3512420658
Directory /workspace/27.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1992507731
Short name T189
Test name
Test status
Simulation time 213400673 ps
CPU time 0.61 seconds
Started Jun 23 05:12:06 PM PDT 24
Finished Jun 23 05:12:07 PM PDT 24
Peak memory 196064 kb
Host smart-e62a926f-85fc-4089-bdef-c693ea302fff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992507731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1992507731
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.952671613
Short name T305
Test name
Test status
Simulation time 192002694 ps
CPU time 9.06 seconds
Started Jun 23 05:12:02 PM PDT 24
Finished Jun 23 05:12:12 PM PDT 24
Peak memory 200064 kb
Host smart-c536c88e-25e6-4f32-8c5a-6309d7e91744
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=952671613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.952671613
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2372574028
Short name T38
Test name
Test status
Simulation time 14142294635 ps
CPU time 62.32 seconds
Started Jun 23 05:12:02 PM PDT 24
Finished Jun 23 05:13:04 PM PDT 24
Peak memory 200112 kb
Host smart-9bac1c8d-cb59-44ec-af1a-2cd686a23330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372574028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2372574028
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.4205971027
Short name T608
Test name
Test status
Simulation time 4692911720 ps
CPU time 703.4 seconds
Started Jun 23 05:12:04 PM PDT 24
Finished Jun 23 05:23:48 PM PDT 24
Peak memory 694012 kb
Host smart-1b65a539-d579-4c6b-8195-baea482773b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4205971027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.4205971027
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3215540051
Short name T390
Test name
Test status
Simulation time 26318109012 ps
CPU time 51.83 seconds
Started Jun 23 05:12:05 PM PDT 24
Finished Jun 23 05:12:58 PM PDT 24
Peak memory 200192 kb
Host smart-a21c84c9-afdc-470b-8a5f-1b3f8f89a0fd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215540051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3215540051
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1052354131
Short name T13
Test name
Test status
Simulation time 11217393234 ps
CPU time 106.51 seconds
Started Jun 23 05:12:02 PM PDT 24
Finished Jun 23 05:13:49 PM PDT 24
Peak memory 200168 kb
Host smart-00f21259-71ec-4fc0-8e16-75b534f52df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052354131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1052354131
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2159347318
Short name T307
Test name
Test status
Simulation time 1771111883 ps
CPU time 11.72 seconds
Started Jun 23 05:12:06 PM PDT 24
Finished Jun 23 05:12:18 PM PDT 24
Peak memory 200016 kb
Host smart-57b9a6eb-4354-453a-8a09-917889522355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159347318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2159347318
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.236474811
Short name T405
Test name
Test status
Simulation time 100819622 ps
CPU time 1.17 seconds
Started Jun 23 05:12:02 PM PDT 24
Finished Jun 23 05:12:04 PM PDT 24
Peak memory 199812 kb
Host smart-232cee33-97a4-4d3a-b391-f3fc84383f91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236474811 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_hmac_vectors.236474811
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha256_vectors.1327939029
Short name T579
Test name
Test status
Simulation time 245874694105 ps
CPU time 530.31 seconds
Started Jun 23 05:12:03 PM PDT 24
Finished Jun 23 05:20:54 PM PDT 24
Peak memory 200128 kb
Host smart-37c62e75-b262-4af1-9ef1-9cb426223bbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1327939029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha256_vectors.1327939029
Directory /workspace/28.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha384_vectors.1667857048
Short name T293
Test name
Test status
Simulation time 61494883497 ps
CPU time 1776.49 seconds
Started Jun 23 05:12:04 PM PDT 24
Finished Jun 23 05:41:41 PM PDT 24
Peak memory 216248 kb
Host smart-b82aed2f-e643-4f67-b0f1-34886d8ff942
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1667857048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha384_vectors.1667857048
Directory /workspace/28.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha512_vectors.1003073449
Short name T361
Test name
Test status
Simulation time 171330269297 ps
CPU time 1920 seconds
Started Jun 23 05:12:02 PM PDT 24
Finished Jun 23 05:44:02 PM PDT 24
Peak memory 215560 kb
Host smart-59950879-3013-4b05-a532-dbc5515927f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1003073449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha512_vectors.1003073449
Directory /workspace/28.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.10897173
Short name T593
Test name
Test status
Simulation time 8455172472 ps
CPU time 76.22 seconds
Started Jun 23 05:12:02 PM PDT 24
Finished Jun 23 05:13:19 PM PDT 24
Peak memory 200100 kb
Host smart-fbf22bb1-a9b3-4f18-aeb6-0757712abea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10897173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.10897173
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.292452288
Short name T432
Test name
Test status
Simulation time 37699457 ps
CPU time 0.56 seconds
Started Jun 23 05:12:07 PM PDT 24
Finished Jun 23 05:12:08 PM PDT 24
Peak memory 194968 kb
Host smart-a2f918e5-e125-4d13-85c8-92af52e81f5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292452288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.292452288
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2497163816
Short name T22
Test name
Test status
Simulation time 4698330874 ps
CPU time 42.49 seconds
Started Jun 23 05:12:09 PM PDT 24
Finished Jun 23 05:12:52 PM PDT 24
Peak memory 200004 kb
Host smart-cb08cad5-9783-4686-a98d-889efe5cc562
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2497163816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2497163816
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.785921194
Short name T408
Test name
Test status
Simulation time 2596395015 ps
CPU time 24.25 seconds
Started Jun 23 05:12:10 PM PDT 24
Finished Jun 23 05:12:34 PM PDT 24
Peak memory 200048 kb
Host smart-a1d1d042-48ed-42ec-b511-7fd0397123f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785921194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.785921194
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.2648372149
Short name T637
Test name
Test status
Simulation time 578277708 ps
CPU time 60.79 seconds
Started Jun 23 05:12:09 PM PDT 24
Finished Jun 23 05:13:10 PM PDT 24
Peak memory 337252 kb
Host smart-a9d6bd20-4a57-477e-b030-1f7b68be0144
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2648372149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2648372149
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.3532549796
Short name T282
Test name
Test status
Simulation time 2207388459 ps
CPU time 32.27 seconds
Started Jun 23 05:12:11 PM PDT 24
Finished Jun 23 05:12:44 PM PDT 24
Peak memory 200004 kb
Host smart-9880ff4c-48c2-4194-8d41-9010db033021
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532549796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3532549796
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2967287762
Short name T56
Test name
Test status
Simulation time 1116099145 ps
CPU time 34.13 seconds
Started Jun 23 05:12:08 PM PDT 24
Finished Jun 23 05:12:43 PM PDT 24
Peak memory 200128 kb
Host smart-bc35b741-ff25-422f-b209-fee7f451f2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967287762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2967287762
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1638422297
Short name T569
Test name
Test status
Simulation time 172661873 ps
CPU time 8.84 seconds
Started Jun 23 05:12:08 PM PDT 24
Finished Jun 23 05:12:18 PM PDT 24
Peak memory 200096 kb
Host smart-560e7aed-2e49-413e-93e0-ad6b87ba4f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638422297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1638422297
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.1132095841
Short name T485
Test name
Test status
Simulation time 60908393 ps
CPU time 1.39 seconds
Started Jun 23 05:12:08 PM PDT 24
Finished Jun 23 05:12:10 PM PDT 24
Peak memory 199996 kb
Host smart-b61fcf9a-c61e-4149-b81d-f8c02d5f36d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132095841 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_hmac_vectors.1132095841
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha256_vectors.561705183
Short name T214
Test name
Test status
Simulation time 56901532043 ps
CPU time 504.71 seconds
Started Jun 23 05:12:08 PM PDT 24
Finished Jun 23 05:20:33 PM PDT 24
Peak memory 200112 kb
Host smart-e38596b8-2245-440e-a742-d88cfa913ee0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=561705183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha256_vectors.561705183
Directory /workspace/29.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha384_vectors.3788740054
Short name T414
Test name
Test status
Simulation time 328734641429 ps
CPU time 1816.87 seconds
Started Jun 23 05:12:07 PM PDT 24
Finished Jun 23 05:42:24 PM PDT 24
Peak memory 216516 kb
Host smart-04a78bef-d361-48c5-9f8e-6bb63d539411
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3788740054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha384_vectors.3788740054
Directory /workspace/29.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha512_vectors.80916811
Short name T435
Test name
Test status
Simulation time 159462298533 ps
CPU time 2045.07 seconds
Started Jun 23 05:12:08 PM PDT 24
Finished Jun 23 05:46:14 PM PDT 24
Peak memory 215648 kb
Host smart-0d4ff66d-903b-4755-a1fc-520a543be18a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=80916811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha512_vectors.80916811
Directory /workspace/29.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.53423720
Short name T368
Test name
Test status
Simulation time 169520370 ps
CPU time 3.68 seconds
Started Jun 23 05:12:08 PM PDT 24
Finished Jun 23 05:12:12 PM PDT 24
Peak memory 200048 kb
Host smart-49db7fc8-7727-4230-9e13-30d48f1b02d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53423720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.53423720
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3827530396
Short name T296
Test name
Test status
Simulation time 73563486 ps
CPU time 0.59 seconds
Started Jun 23 05:11:11 PM PDT 24
Finished Jun 23 05:11:12 PM PDT 24
Peak memory 194976 kb
Host smart-a77b5b5b-088d-4193-b386-11d88fe827e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827530396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3827530396
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2180575144
Short name T124
Test name
Test status
Simulation time 3002075013 ps
CPU time 32.08 seconds
Started Jun 23 05:11:05 PM PDT 24
Finished Jun 23 05:11:38 PM PDT 24
Peak memory 200084 kb
Host smart-8aa28a09-2320-41c7-b640-d83ace080149
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2180575144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2180575144
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1454885922
Short name T436
Test name
Test status
Simulation time 6770320862 ps
CPU time 48.56 seconds
Started Jun 23 05:11:12 PM PDT 24
Finished Jun 23 05:12:01 PM PDT 24
Peak memory 208252 kb
Host smart-7d3d4fd6-5261-45aa-acc4-b0cd01eab39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454885922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1454885922
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3995976097
Short name T309
Test name
Test status
Simulation time 2584570678 ps
CPU time 750.88 seconds
Started Jun 23 05:11:08 PM PDT 24
Finished Jun 23 05:23:40 PM PDT 24
Peak memory 712616 kb
Host smart-6bd29241-271a-41b0-927a-3c3de159ddbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3995976097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3995976097
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.4043042257
Short name T304
Test name
Test status
Simulation time 389411620 ps
CPU time 21.5 seconds
Started Jun 23 05:11:08 PM PDT 24
Finished Jun 23 05:11:30 PM PDT 24
Peak memory 199996 kb
Host smart-cf25e210-e795-4166-b933-7646e493e3c9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043042257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.4043042257
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2987009685
Short name T30
Test name
Test status
Simulation time 9594327162 ps
CPU time 68.25 seconds
Started Jun 23 05:11:11 PM PDT 24
Finished Jun 23 05:12:20 PM PDT 24
Peak memory 200136 kb
Host smart-a39ffbd3-fefc-4f3a-ac28-d8d6a20a99bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987009685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2987009685
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3641822815
Short name T45
Test name
Test status
Simulation time 197440089 ps
CPU time 1 seconds
Started Jun 23 05:11:11 PM PDT 24
Finished Jun 23 05:11:13 PM PDT 24
Peak memory 219216 kb
Host smart-5ae90ef4-7358-4145-9e58-0ee891275bfe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641822815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3641822815
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.2499278747
Short name T179
Test name
Test status
Simulation time 681837195 ps
CPU time 10.69 seconds
Started Jun 23 05:11:12 PM PDT 24
Finished Jun 23 05:11:24 PM PDT 24
Peak memory 199944 kb
Host smart-0a36e69e-fa87-47e3-bca8-bb1a4ae2bfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499278747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2499278747
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.1241556103
Short name T483
Test name
Test status
Simulation time 116992372 ps
CPU time 1.35 seconds
Started Jun 23 05:11:11 PM PDT 24
Finished Jun 23 05:11:13 PM PDT 24
Peak memory 200068 kb
Host smart-a8aee3d4-a4b3-4c57-a885-f27c8095e5d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241556103 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac_vectors.1241556103
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.3965501180
Short name T14
Test name
Test status
Simulation time 366356839720 ps
CPU time 467.02 seconds
Started Jun 23 05:11:06 PM PDT 24
Finished Jun 23 05:18:54 PM PDT 24
Peak memory 200116 kb
Host smart-c09cff15-9058-4026-a14c-54a425cfd51d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3965501180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.3965501180
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.3893575389
Short name T308
Test name
Test status
Simulation time 70523420388 ps
CPU time 1861.75 seconds
Started Jun 23 05:11:04 PM PDT 24
Finished Jun 23 05:42:06 PM PDT 24
Peak memory 215656 kb
Host smart-50a6730d-b6cc-4ff7-8398-4b2c2e36ef69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3893575389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.3893575389
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.1358485251
Short name T476
Test name
Test status
Simulation time 136720689194 ps
CPU time 1890.93 seconds
Started Jun 23 05:11:08 PM PDT 24
Finished Jun 23 05:42:40 PM PDT 24
Peak memory 215512 kb
Host smart-8d276797-ef0a-472b-915c-a1dc4a80da52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1358485251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.1358485251
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/30.hmac_alert_test.955947458
Short name T11
Test name
Test status
Simulation time 98710564 ps
CPU time 0.61 seconds
Started Jun 23 05:12:13 PM PDT 24
Finished Jun 23 05:12:14 PM PDT 24
Peak memory 196048 kb
Host smart-f1d1b2e3-3774-4914-b9cf-25609a9d5545
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955947458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.955947458
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2587820338
Short name T19
Test name
Test status
Simulation time 3474902344 ps
CPU time 39.79 seconds
Started Jun 23 05:12:15 PM PDT 24
Finished Jun 23 05:12:55 PM PDT 24
Peak memory 200124 kb
Host smart-a4170c68-9b1b-46cf-9639-80df3cfc5b9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2587820338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2587820338
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.4165092224
Short name T223
Test name
Test status
Simulation time 2008143906 ps
CPU time 28.53 seconds
Started Jun 23 05:12:14 PM PDT 24
Finished Jun 23 05:12:43 PM PDT 24
Peak memory 200048 kb
Host smart-e7e6f20c-f36c-4cd3-816d-59c6d89cdd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165092224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.4165092224
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2390704083
Short name T478
Test name
Test status
Simulation time 202320308 ps
CPU time 45.72 seconds
Started Jun 23 05:12:13 PM PDT 24
Finished Jun 23 05:12:59 PM PDT 24
Peak memory 328972 kb
Host smart-615bd905-628f-4161-8371-278d8165ba41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2390704083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2390704083
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3878347455
Short name T568
Test name
Test status
Simulation time 1940770142 ps
CPU time 12.82 seconds
Started Jun 23 05:12:12 PM PDT 24
Finished Jun 23 05:12:26 PM PDT 24
Peak memory 199932 kb
Host smart-746d2486-5cee-4505-8320-0358542bc286
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878347455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3878347455
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_smoke.693767803
Short name T278
Test name
Test status
Simulation time 3105277799 ps
CPU time 13.53 seconds
Started Jun 23 05:12:13 PM PDT 24
Finished Jun 23 05:12:27 PM PDT 24
Peak memory 200112 kb
Host smart-2cbfce2b-0308-4cda-926a-2d8b06bba77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693767803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.693767803
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.3547604309
Short name T544
Test name
Test status
Simulation time 114845095 ps
CPU time 1.13 seconds
Started Jun 23 05:12:17 PM PDT 24
Finished Jun 23 05:12:19 PM PDT 24
Peak memory 199988 kb
Host smart-880fe33a-25f4-4c35-a4c2-00f16a00e4f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547604309 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_hmac_vectors.3547604309
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha256_vectors.2081419792
Short name T184
Test name
Test status
Simulation time 41341482016 ps
CPU time 476.42 seconds
Started Jun 23 05:12:12 PM PDT 24
Finished Jun 23 05:20:09 PM PDT 24
Peak memory 199936 kb
Host smart-40a9735c-e01e-4967-8771-3cb8676744b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2081419792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha256_vectors.2081419792
Directory /workspace/30.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha384_vectors.4044491301
Short name T406
Test name
Test status
Simulation time 30641796405 ps
CPU time 1790.78 seconds
Started Jun 23 05:12:13 PM PDT 24
Finished Jun 23 05:42:05 PM PDT 24
Peak memory 216456 kb
Host smart-f522cb22-a892-492e-a048-6b75b8fb30c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4044491301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha384_vectors.4044491301
Directory /workspace/30.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha512_vectors.1015460616
Short name T594
Test name
Test status
Simulation time 132559541341 ps
CPU time 1894.68 seconds
Started Jun 23 05:12:17 PM PDT 24
Finished Jun 23 05:43:52 PM PDT 24
Peak memory 215764 kb
Host smart-e62c84d4-92df-415a-af44-e046ca9646a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1015460616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha512_vectors.1015460616
Directory /workspace/30.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.1405392064
Short name T409
Test name
Test status
Simulation time 4903851971 ps
CPU time 33.67 seconds
Started Jun 23 05:12:13 PM PDT 24
Finished Jun 23 05:12:47 PM PDT 24
Peak memory 199896 kb
Host smart-f77d9453-0c5f-417f-a5d2-61b58995a6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405392064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1405392064
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1437645914
Short name T392
Test name
Test status
Simulation time 45421579 ps
CPU time 0.62 seconds
Started Jun 23 05:12:20 PM PDT 24
Finished Jun 23 05:12:21 PM PDT 24
Peak memory 196116 kb
Host smart-996bbae0-8a81-41fe-917f-ff579193a2d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437645914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1437645914
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2476215574
Short name T393
Test name
Test status
Simulation time 1310546840 ps
CPU time 15.47 seconds
Started Jun 23 05:12:17 PM PDT 24
Finished Jun 23 05:12:33 PM PDT 24
Peak memory 199992 kb
Host smart-a5f5fe63-3d5e-44dd-9f3b-6e5a6b92c0ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2476215574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2476215574
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2097102252
Short name T576
Test name
Test status
Simulation time 948654333 ps
CPU time 14.27 seconds
Started Jun 23 05:12:12 PM PDT 24
Finished Jun 23 05:12:26 PM PDT 24
Peak memory 200056 kb
Host smart-f79dfe85-aee7-497c-bb29-1426cde3468c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097102252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2097102252
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2667073236
Short name T555
Test name
Test status
Simulation time 3960976392 ps
CPU time 697.73 seconds
Started Jun 23 05:12:13 PM PDT 24
Finished Jun 23 05:23:52 PM PDT 24
Peak memory 695116 kb
Host smart-75629210-de2b-4a21-9562-c40189d90d05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2667073236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2667073236
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.581104551
Short name T381
Test name
Test status
Simulation time 2705680746 ps
CPU time 62.24 seconds
Started Jun 23 05:12:13 PM PDT 24
Finished Jun 23 05:13:15 PM PDT 24
Peak memory 200148 kb
Host smart-2c123a61-54b2-4e2e-871f-84cc52fac3c0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581104551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.581104551
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1056990556
Short name T650
Test name
Test status
Simulation time 4694489018 ps
CPU time 77.17 seconds
Started Jun 23 05:12:14 PM PDT 24
Finished Jun 23 05:13:32 PM PDT 24
Peak memory 200144 kb
Host smart-fe7ae54f-ba75-49b6-a7c5-ee723a20be6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056990556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1056990556
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2800581908
Short name T431
Test name
Test status
Simulation time 205425259 ps
CPU time 4.91 seconds
Started Jun 23 05:12:13 PM PDT 24
Finished Jun 23 05:12:19 PM PDT 24
Peak memory 200044 kb
Host smart-70151085-77ad-496e-9ce6-36f3122d78c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800581908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2800581908
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.4180261139
Short name T287
Test name
Test status
Simulation time 107949603 ps
CPU time 1.06 seconds
Started Jun 23 05:12:20 PM PDT 24
Finished Jun 23 05:12:22 PM PDT 24
Peak memory 199808 kb
Host smart-79054025-3d23-4694-a1f9-9b015e553465
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180261139 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_hmac_vectors.4180261139
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha256_vectors.2946778881
Short name T260
Test name
Test status
Simulation time 164813813302 ps
CPU time 502.07 seconds
Started Jun 23 05:12:19 PM PDT 24
Finished Jun 23 05:20:42 PM PDT 24
Peak memory 200104 kb
Host smart-cf437826-fe3b-47de-b003-5a0708c78b83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2946778881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha256_vectors.2946778881
Directory /workspace/31.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha384_vectors.3855120947
Short name T340
Test name
Test status
Simulation time 438577053078 ps
CPU time 1841.37 seconds
Started Jun 23 05:12:19 PM PDT 24
Finished Jun 23 05:43:01 PM PDT 24
Peak memory 216084 kb
Host smart-55fc5e14-5217-42b7-bb72-9f119fefb938
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3855120947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha384_vectors.3855120947
Directory /workspace/31.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha512_vectors.801831400
Short name T300
Test name
Test status
Simulation time 118644029297 ps
CPU time 2223.41 seconds
Started Jun 23 05:12:18 PM PDT 24
Finished Jun 23 05:49:23 PM PDT 24
Peak memory 215624 kb
Host smart-f62ddb33-69cf-4a1f-8276-507e3edc6269
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=801831400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha512_vectors.801831400
Directory /workspace/31.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.3316782422
Short name T596
Test name
Test status
Simulation time 9139675206 ps
CPU time 23.39 seconds
Started Jun 23 05:12:19 PM PDT 24
Finished Jun 23 05:12:43 PM PDT 24
Peak memory 200132 kb
Host smart-b5731884-553b-48a9-ab27-97e0a6dd2b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316782422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3316782422
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.923708621
Short name T646
Test name
Test status
Simulation time 22860574 ps
CPU time 0.6 seconds
Started Jun 23 05:12:26 PM PDT 24
Finished Jun 23 05:12:27 PM PDT 24
Peak memory 195724 kb
Host smart-77f05465-8d8f-4e3a-89a4-f5eceda9f458
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923708621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.923708621
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.137712634
Short name T299
Test name
Test status
Simulation time 3553296499 ps
CPU time 46.23 seconds
Started Jun 23 05:12:20 PM PDT 24
Finished Jun 23 05:13:07 PM PDT 24
Peak memory 200176 kb
Host smart-8b682488-c611-4114-8855-6172af573af4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=137712634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.137712634
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.4201697981
Short name T404
Test name
Test status
Simulation time 6600878769 ps
CPU time 42.89 seconds
Started Jun 23 05:12:20 PM PDT 24
Finished Jun 23 05:13:04 PM PDT 24
Peak memory 200140 kb
Host smart-1b638985-9cf8-4511-af1c-1eb9d1b80fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201697981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.4201697981
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3122169474
Short name T181
Test name
Test status
Simulation time 19024415398 ps
CPU time 1509.34 seconds
Started Jun 23 05:12:20 PM PDT 24
Finished Jun 23 05:37:30 PM PDT 24
Peak memory 791948 kb
Host smart-37c8b9bf-0a48-4896-89c3-a2bd961327da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3122169474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3122169474
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.1704542786
Short name T33
Test name
Test status
Simulation time 17782008756 ps
CPU time 60.25 seconds
Started Jun 23 05:12:18 PM PDT 24
Finished Jun 23 05:13:18 PM PDT 24
Peak memory 200304 kb
Host smart-f6271388-1b1a-4587-a55b-b4ef972b3197
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704542786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1704542786
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3204360344
Short name T367
Test name
Test status
Simulation time 44455409486 ps
CPU time 157.55 seconds
Started Jun 23 05:12:19 PM PDT 24
Finished Jun 23 05:14:57 PM PDT 24
Peak memory 200040 kb
Host smart-f332e9f0-6d38-4251-a54b-94e9de955fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204360344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3204360344
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2693520899
Short name T152
Test name
Test status
Simulation time 877081999 ps
CPU time 12.7 seconds
Started Jun 23 05:12:19 PM PDT 24
Finished Jun 23 05:12:32 PM PDT 24
Peak memory 200080 kb
Host smart-0dd3dd57-8997-4f13-9f4f-7f65e42da2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693520899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2693520899
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.3156556953
Short name T440
Test name
Test status
Simulation time 139735885 ps
CPU time 1.09 seconds
Started Jun 23 05:12:24 PM PDT 24
Finished Jun 23 05:12:26 PM PDT 24
Peak memory 200016 kb
Host smart-a8ee13ef-b05b-480f-9fe3-e61e0dd1197e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156556953 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_hmac_vectors.3156556953
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha256_vectors.541134256
Short name T600
Test name
Test status
Simulation time 7526412788 ps
CPU time 418.91 seconds
Started Jun 23 05:12:19 PM PDT 24
Finished Jun 23 05:19:19 PM PDT 24
Peak memory 200128 kb
Host smart-23817e8c-a6f2-402a-a8aa-2e8b90ace7fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=541134256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha256_vectors.541134256
Directory /workspace/32.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha384_vectors.1658605925
Short name T51
Test name
Test status
Simulation time 33397075177 ps
CPU time 1622.8 seconds
Started Jun 23 05:12:24 PM PDT 24
Finished Jun 23 05:39:28 PM PDT 24
Peak memory 215644 kb
Host smart-ebd8d938-638c-4e76-b965-6e22b8293075
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1658605925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha384_vectors.1658605925
Directory /workspace/32.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha512_vectors.1346071202
Short name T577
Test name
Test status
Simulation time 61879514639 ps
CPU time 1786.07 seconds
Started Jun 23 05:12:25 PM PDT 24
Finished Jun 23 05:42:12 PM PDT 24
Peak memory 215672 kb
Host smart-8ce48215-e61a-40b3-890b-ca38e1bcf187
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1346071202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha512_vectors.1346071202
Directory /workspace/32.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.814023696
Short name T248
Test name
Test status
Simulation time 5315956088 ps
CPU time 40.75 seconds
Started Jun 23 05:12:19 PM PDT 24
Finished Jun 23 05:13:01 PM PDT 24
Peak memory 200168 kb
Host smart-81ed6753-e632-4038-8888-0d239700acd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814023696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.814023696
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1235432207
Short name T585
Test name
Test status
Simulation time 13478263 ps
CPU time 0.57 seconds
Started Jun 23 05:12:24 PM PDT 24
Finished Jun 23 05:12:25 PM PDT 24
Peak memory 194964 kb
Host smart-f557a3d3-f622-4be9-9737-376bc13c93c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235432207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1235432207
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.2440629089
Short name T425
Test name
Test status
Simulation time 3070601323 ps
CPU time 32.08 seconds
Started Jun 23 05:12:26 PM PDT 24
Finished Jun 23 05:12:58 PM PDT 24
Peak memory 200112 kb
Host smart-238c09da-1d31-4a8e-9e5b-660747701f5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2440629089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2440629089
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.760908741
Short name T378
Test name
Test status
Simulation time 2515432957 ps
CPU time 674.59 seconds
Started Jun 23 05:12:24 PM PDT 24
Finished Jun 23 05:23:39 PM PDT 24
Peak memory 718736 kb
Host smart-1bde16df-1a37-44c3-b3f3-a2b044585363
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=760908741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.760908741
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1507869922
Short name T325
Test name
Test status
Simulation time 15569642086 ps
CPU time 95.78 seconds
Started Jun 23 05:12:24 PM PDT 24
Finished Jun 23 05:14:00 PM PDT 24
Peak memory 200104 kb
Host smart-12920d47-95a2-49a6-9562-1b1392e0205a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507869922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1507869922
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3710656667
Short name T535
Test name
Test status
Simulation time 26723788661 ps
CPU time 90.89 seconds
Started Jun 23 05:12:24 PM PDT 24
Finished Jun 23 05:13:55 PM PDT 24
Peak memory 200272 kb
Host smart-75dabf4d-a983-4041-b173-2c908eafd96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710656667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3710656667
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.204617361
Short name T353
Test name
Test status
Simulation time 713871308 ps
CPU time 11.44 seconds
Started Jun 23 05:12:25 PM PDT 24
Finished Jun 23 05:12:37 PM PDT 24
Peak memory 200060 kb
Host smart-e4720d7d-85a8-437c-a1a8-b8212240cf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204617361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.204617361
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.3437056347
Short name T465
Test name
Test status
Simulation time 147644558 ps
CPU time 1.36 seconds
Started Jun 23 05:12:28 PM PDT 24
Finished Jun 23 05:12:30 PM PDT 24
Peak memory 200008 kb
Host smart-cbdb81f9-24f6-4cb6-a61a-14b517365264
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437056347 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_hmac_vectors.3437056347
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha256_vectors.653693510
Short name T231
Test name
Test status
Simulation time 31724061089 ps
CPU time 429.92 seconds
Started Jun 23 05:12:24 PM PDT 24
Finished Jun 23 05:19:35 PM PDT 24
Peak memory 200132 kb
Host smart-40ac974b-b5f5-42a2-b0b6-414097dc6cab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=653693510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha256_vectors.653693510
Directory /workspace/33.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha384_vectors.2748444897
Short name T12
Test name
Test status
Simulation time 134420722395 ps
CPU time 1678.22 seconds
Started Jun 23 05:12:24 PM PDT 24
Finished Jun 23 05:40:23 PM PDT 24
Peak memory 216028 kb
Host smart-46427648-a7b5-491b-ba21-00b5c86b6008
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2748444897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha384_vectors.2748444897
Directory /workspace/33.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha512_vectors.3545228860
Short name T259
Test name
Test status
Simulation time 652763560962 ps
CPU time 2073.72 seconds
Started Jun 23 05:12:24 PM PDT 24
Finished Jun 23 05:46:59 PM PDT 24
Peak memory 215548 kb
Host smart-0d578e26-b916-43e3-90c9-50be65f72698
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3545228860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha512_vectors.3545228860
Directory /workspace/33.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2029825065
Short name T588
Test name
Test status
Simulation time 6578263142 ps
CPU time 94.05 seconds
Started Jun 23 05:12:25 PM PDT 24
Finished Jun 23 05:13:59 PM PDT 24
Peak memory 200088 kb
Host smart-988c069b-c095-4ed9-8f04-03fd258f32be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029825065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2029825065
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.14931765
Short name T333
Test name
Test status
Simulation time 48037411 ps
CPU time 0.57 seconds
Started Jun 23 05:12:31 PM PDT 24
Finished Jun 23 05:12:32 PM PDT 24
Peak memory 194956 kb
Host smart-790b09dc-bfc5-4a72-8ed4-699af631aabd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14931765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.14931765
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1920096235
Short name T24
Test name
Test status
Simulation time 1377599535 ps
CPU time 33.05 seconds
Started Jun 23 05:12:30 PM PDT 24
Finished Jun 23 05:13:04 PM PDT 24
Peak memory 200092 kb
Host smart-22199f09-24dc-458b-820d-cdff40dbb5f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1920096235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1920096235
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2520100423
Short name T186
Test name
Test status
Simulation time 11790531980 ps
CPU time 36.85 seconds
Started Jun 23 05:12:30 PM PDT 24
Finished Jun 23 05:13:07 PM PDT 24
Peak memory 200132 kb
Host smart-e5e272f1-e527-47e6-95c0-53820684d572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520100423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2520100423
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.936799003
Short name T492
Test name
Test status
Simulation time 3008544512 ps
CPU time 781.4 seconds
Started Jun 23 05:12:31 PM PDT 24
Finished Jun 23 05:25:33 PM PDT 24
Peak memory 762016 kb
Host smart-cad4699a-6ead-46a1-92f3-6ef79fc7e3b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=936799003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.936799003
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.355691396
Short name T262
Test name
Test status
Simulation time 1246485892 ps
CPU time 68.13 seconds
Started Jun 23 05:12:31 PM PDT 24
Finished Jun 23 05:13:39 PM PDT 24
Peak memory 200040 kb
Host smart-65e356ac-cf2b-4051-b66d-6fa10e6b198a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355691396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.355691396
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1216240664
Short name T457
Test name
Test status
Simulation time 18050806688 ps
CPU time 122.33 seconds
Started Jun 23 05:12:27 PM PDT 24
Finished Jun 23 05:14:30 PM PDT 24
Peak memory 200180 kb
Host smart-3d1770fc-0fe4-45c0-adbc-fb9a782d5e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216240664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1216240664
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3772046275
Short name T529
Test name
Test status
Simulation time 10019837478 ps
CPU time 31.24 seconds
Started Jun 23 05:12:25 PM PDT 24
Finished Jun 23 05:12:57 PM PDT 24
Peak memory 200084 kb
Host smart-de35ce16-8617-4c80-b367-13a3fb225ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772046275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3772046275
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.1190075105
Short name T635
Test name
Test status
Simulation time 154788848 ps
CPU time 1.04 seconds
Started Jun 23 05:12:31 PM PDT 24
Finished Jun 23 05:12:33 PM PDT 24
Peak memory 199860 kb
Host smart-d6f3603d-4e89-4e20-8fa4-fe23d72e0bd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190075105 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_hmac_vectors.1190075105
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha256_vectors.3053947228
Short name T411
Test name
Test status
Simulation time 160876166379 ps
CPU time 506.51 seconds
Started Jun 23 05:12:31 PM PDT 24
Finished Jun 23 05:20:58 PM PDT 24
Peak memory 200076 kb
Host smart-ee35032c-09ca-4b0a-aa8c-4dfeb3c82c23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3053947228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha256_vectors.3053947228
Directory /workspace/34.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha384_vectors.2447605532
Short name T159
Test name
Test status
Simulation time 636522196850 ps
CPU time 1854.82 seconds
Started Jun 23 05:12:30 PM PDT 24
Finished Jun 23 05:43:26 PM PDT 24
Peak memory 214880 kb
Host smart-7bcfcb23-6b6d-432b-8b9b-52cde828a02d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2447605532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha384_vectors.2447605532
Directory /workspace/34.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha512_vectors.3414073210
Short name T261
Test name
Test status
Simulation time 554824609631 ps
CPU time 1950.74 seconds
Started Jun 23 05:12:31 PM PDT 24
Finished Jun 23 05:45:02 PM PDT 24
Peak memory 215664 kb
Host smart-89b6a6c1-8fbb-4e9d-8ff1-cd54072faf14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3414073210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha512_vectors.3414073210
Directory /workspace/34.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.99555861
Short name T114
Test name
Test status
Simulation time 11080041146 ps
CPU time 79.38 seconds
Started Jun 23 05:12:32 PM PDT 24
Finished Jun 23 05:13:51 PM PDT 24
Peak memory 200136 kb
Host smart-342847c0-b032-46c3-bc92-e59a52b78526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99555861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.99555861
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.1766923309
Short name T210
Test name
Test status
Simulation time 12252195 ps
CPU time 0.59 seconds
Started Jun 23 05:12:39 PM PDT 24
Finished Jun 23 05:12:40 PM PDT 24
Peak memory 196004 kb
Host smart-2e4c003b-a999-4d8c-acaf-bfc73d81b7d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766923309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1766923309
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2462962440
Short name T423
Test name
Test status
Simulation time 2610705309 ps
CPU time 25.68 seconds
Started Jun 23 05:12:37 PM PDT 24
Finished Jun 23 05:13:04 PM PDT 24
Peak memory 200124 kb
Host smart-dafe60f9-c6b8-4f97-91e4-caf336f2e865
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2462962440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2462962440
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.4219659161
Short name T487
Test name
Test status
Simulation time 7020310831 ps
CPU time 34.53 seconds
Started Jun 23 05:12:37 PM PDT 24
Finished Jun 23 05:13:12 PM PDT 24
Peak memory 208256 kb
Host smart-88b26fd4-cf3c-4e48-9f42-a3af85ce4253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219659161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.4219659161
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1354527463
Short name T131
Test name
Test status
Simulation time 1049362076 ps
CPU time 127.07 seconds
Started Jun 23 05:12:36 PM PDT 24
Finished Jun 23 05:14:45 PM PDT 24
Peak memory 410396 kb
Host smart-1f18b617-553f-43dc-91f1-1a22bab0f95d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1354527463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1354527463
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.780030104
Short name T332
Test name
Test status
Simulation time 14181612964 ps
CPU time 91.14 seconds
Started Jun 23 05:12:36 PM PDT 24
Finished Jun 23 05:14:08 PM PDT 24
Peak memory 200104 kb
Host smart-035dd807-6fbf-4d03-b98d-dc4732f3122d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780030104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.780030104
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1002365109
Short name T496
Test name
Test status
Simulation time 3709388152 ps
CPU time 63.87 seconds
Started Jun 23 05:12:36 PM PDT 24
Finished Jun 23 05:13:41 PM PDT 24
Peak memory 200152 kb
Host smart-20a70586-5d84-46d0-b5d9-db7e59f5039c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002365109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1002365109
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.4175784316
Short name T326
Test name
Test status
Simulation time 48516678 ps
CPU time 1.05 seconds
Started Jun 23 05:12:35 PM PDT 24
Finished Jun 23 05:12:37 PM PDT 24
Peak memory 199576 kb
Host smart-7d162c9d-e28e-4228-8ecb-d6b6f6eb0c8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175784316 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_hmac_vectors.4175784316
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha256_vectors.3679459750
Short name T461
Test name
Test status
Simulation time 16673361553 ps
CPU time 459.37 seconds
Started Jun 23 05:12:37 PM PDT 24
Finished Jun 23 05:20:17 PM PDT 24
Peak memory 200148 kb
Host smart-307cee78-9290-4b5b-9a98-c9dcf7362d73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3679459750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha256_vectors.3679459750
Directory /workspace/35.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha384_vectors.2034617328
Short name T195
Test name
Test status
Simulation time 324253862832 ps
CPU time 2116.6 seconds
Started Jun 23 05:12:37 PM PDT 24
Finished Jun 23 05:47:55 PM PDT 24
Peak memory 216032 kb
Host smart-60dc2416-9a25-48ac-9eb9-d710036e29c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2034617328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha384_vectors.2034617328
Directory /workspace/35.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha512_vectors.3671075784
Short name T459
Test name
Test status
Simulation time 416073536928 ps
CPU time 1908.2 seconds
Started Jun 23 05:12:34 PM PDT 24
Finished Jun 23 05:44:23 PM PDT 24
Peak memory 215544 kb
Host smart-de266688-cca3-4268-b239-c40d520b43f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3671075784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha512_vectors.3671075784
Directory /workspace/35.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3356143122
Short name T486
Test name
Test status
Simulation time 6829830304 ps
CPU time 72.29 seconds
Started Jun 23 05:12:38 PM PDT 24
Finished Jun 23 05:13:50 PM PDT 24
Peak memory 200144 kb
Host smart-7f2563d8-6f97-4a02-875a-4f240ae18033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356143122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3356143122
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1950326580
Short name T153
Test name
Test status
Simulation time 14741696 ps
CPU time 0.59 seconds
Started Jun 23 05:12:47 PM PDT 24
Finished Jun 23 05:12:48 PM PDT 24
Peak memory 195648 kb
Host smart-069f5586-9871-410c-a73d-f8be820602cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950326580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1950326580
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.4028682068
Short name T6
Test name
Test status
Simulation time 2392582763 ps
CPU time 28.93 seconds
Started Jun 23 05:12:35 PM PDT 24
Finished Jun 23 05:13:05 PM PDT 24
Peak memory 200144 kb
Host smart-2600c92c-f7da-42af-a957-88f23a9ce92b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4028682068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.4028682068
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2621856885
Short name T145
Test name
Test status
Simulation time 1364541239 ps
CPU time 70.99 seconds
Started Jun 23 05:12:37 PM PDT 24
Finished Jun 23 05:13:49 PM PDT 24
Peak memory 200020 kb
Host smart-ac2bc220-5e60-4503-ac0e-93a3a804df2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621856885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2621856885
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.440441455
Short name T467
Test name
Test status
Simulation time 37756865551 ps
CPU time 595.6 seconds
Started Jun 23 05:12:35 PM PDT 24
Finished Jun 23 05:22:31 PM PDT 24
Peak memory 721404 kb
Host smart-3226b67c-b0ea-4b37-a653-382ffd671603
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=440441455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.440441455
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_long_msg.45186870
Short name T176
Test name
Test status
Simulation time 6894793762 ps
CPU time 130.06 seconds
Started Jun 23 05:12:39 PM PDT 24
Finished Jun 23 05:14:49 PM PDT 24
Peak memory 200168 kb
Host smart-4e498b8f-0e07-46a6-91a9-309a8febd930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45186870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.45186870
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2404477212
Short name T501
Test name
Test status
Simulation time 465072238 ps
CPU time 7.78 seconds
Started Jun 23 05:12:36 PM PDT 24
Finished Jun 23 05:12:45 PM PDT 24
Peak memory 200092 kb
Host smart-b47dbb28-1cd0-47a6-9866-059d0d2084de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404477212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2404477212
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.1798503103
Short name T511
Test name
Test status
Simulation time 80520818 ps
CPU time 1.44 seconds
Started Jun 23 05:12:42 PM PDT 24
Finished Jun 23 05:12:44 PM PDT 24
Peak memory 200116 kb
Host smart-5dd8abac-d228-49f5-a727-ad0cf786f210
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798503103 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_hmac_vectors.1798503103
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha256_vectors.3303533746
Short name T479
Test name
Test status
Simulation time 7573352945 ps
CPU time 415.8 seconds
Started Jun 23 05:12:43 PM PDT 24
Finished Jun 23 05:19:39 PM PDT 24
Peak memory 200128 kb
Host smart-85984c90-a36d-4db3-8b13-1e1a27122e59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3303533746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha256_vectors.3303533746
Directory /workspace/36.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha384_vectors.928388063
Short name T240
Test name
Test status
Simulation time 411213091479 ps
CPU time 1736.06 seconds
Started Jun 23 05:12:41 PM PDT 24
Finished Jun 23 05:41:38 PM PDT 24
Peak memory 216512 kb
Host smart-47609ac4-cbb2-4776-b004-8a039ac08be9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=928388063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha384_vectors.928388063
Directory /workspace/36.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha512_vectors.3708479718
Short name T581
Test name
Test status
Simulation time 60437429744 ps
CPU time 1725.83 seconds
Started Jun 23 05:12:42 PM PDT 24
Finished Jun 23 05:41:28 PM PDT 24
Peak memory 215552 kb
Host smart-c4023b87-4aa4-4e06-9183-3d0444182310
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3708479718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha512_vectors.3708479718
Directory /workspace/36.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2915090892
Short name T597
Test name
Test status
Simulation time 14302371043 ps
CPU time 67.51 seconds
Started Jun 23 05:12:41 PM PDT 24
Finished Jun 23 05:13:49 PM PDT 24
Peak memory 200176 kb
Host smart-274283d0-7f43-4e21-9082-e10c5ffb695d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915090892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2915090892
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.1010081288
Short name T238
Test name
Test status
Simulation time 41871774 ps
CPU time 0.59 seconds
Started Jun 23 05:12:49 PM PDT 24
Finished Jun 23 05:12:50 PM PDT 24
Peak memory 195040 kb
Host smart-1e552dec-cd4f-4cbb-809b-2b46e2abb750
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010081288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1010081288
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1681058681
Short name T249
Test name
Test status
Simulation time 102699069 ps
CPU time 2.14 seconds
Started Jun 23 05:12:43 PM PDT 24
Finished Jun 23 05:12:46 PM PDT 24
Peak memory 200052 kb
Host smart-be8c5f3f-9449-410a-868b-fea5f6c75b92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1681058681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1681058681
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.663999848
Short name T126
Test name
Test status
Simulation time 1904503931 ps
CPU time 27.67 seconds
Started Jun 23 05:12:42 PM PDT 24
Finished Jun 23 05:13:11 PM PDT 24
Peak memory 200048 kb
Host smart-004cbfae-1e91-40cb-8845-fbdc5f4f7deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663999848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.663999848
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.4121109024
Short name T198
Test name
Test status
Simulation time 36625865759 ps
CPU time 1219.87 seconds
Started Jun 23 05:12:41 PM PDT 24
Finished Jun 23 05:33:02 PM PDT 24
Peak memory 751356 kb
Host smart-6dd27a0d-64f6-49b3-9909-2713df2a010f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4121109024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.4121109024
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3175476183
Short name T372
Test name
Test status
Simulation time 6534446287 ps
CPU time 84.17 seconds
Started Jun 23 05:12:40 PM PDT 24
Finished Jun 23 05:14:05 PM PDT 24
Peak memory 200112 kb
Host smart-6694b179-dad6-4cb7-94f7-9fbb9c4ffc3a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175476183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3175476183
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2597203725
Short name T279
Test name
Test status
Simulation time 535829244 ps
CPU time 3.1 seconds
Started Jun 23 05:12:41 PM PDT 24
Finished Jun 23 05:12:45 PM PDT 24
Peak memory 200100 kb
Host smart-de69dec0-2e7e-42fc-a2ae-9e858d8250b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597203725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2597203725
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.4059713468
Short name T201
Test name
Test status
Simulation time 98460679 ps
CPU time 1.31 seconds
Started Jun 23 05:12:43 PM PDT 24
Finished Jun 23 05:12:45 PM PDT 24
Peak memory 200008 kb
Host smart-b7e58aac-9c13-40ea-8f57-670eb02ad8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059713468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.4059713468
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.3171949940
Short name T162
Test name
Test status
Simulation time 451850919 ps
CPU time 1.37 seconds
Started Jun 23 05:12:57 PM PDT 24
Finished Jun 23 05:12:59 PM PDT 24
Peak memory 200076 kb
Host smart-5cb3e1a7-1536-4d26-a61a-4c3df6b21321
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171949940 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_hmac_vectors.3171949940
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha256_vectors.3148245441
Short name T171
Test name
Test status
Simulation time 8007719928 ps
CPU time 435.91 seconds
Started Jun 23 05:12:43 PM PDT 24
Finished Jun 23 05:19:59 PM PDT 24
Peak memory 200108 kb
Host smart-3d3e4efa-675c-4463-b116-cae878a343ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3148245441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha256_vectors.3148245441
Directory /workspace/37.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha384_vectors.984667411
Short name T234
Test name
Test status
Simulation time 111490183095 ps
CPU time 1957.6 seconds
Started Jun 23 05:12:43 PM PDT 24
Finished Jun 23 05:45:21 PM PDT 24
Peak memory 216032 kb
Host smart-d94b0b79-723a-4484-a779-5a5aa2a9e6bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=984667411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha384_vectors.984667411
Directory /workspace/37.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha512_vectors.1310029324
Short name T470
Test name
Test status
Simulation time 169770820922 ps
CPU time 2145.26 seconds
Started Jun 23 05:12:41 PM PDT 24
Finished Jun 23 05:48:27 PM PDT 24
Peak memory 215636 kb
Host smart-9e0a86f1-9301-4e68-a2d8-5b669fbb6da4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1310029324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha512_vectors.1310029324
Directory /workspace/37.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2445166366
Short name T192
Test name
Test status
Simulation time 5439057667 ps
CPU time 52.08 seconds
Started Jun 23 05:12:40 PM PDT 24
Finished Jun 23 05:13:33 PM PDT 24
Peak memory 200168 kb
Host smart-e76a22ce-959c-45ff-bc64-82d369b08d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445166366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2445166366
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.553775319
Short name T205
Test name
Test status
Simulation time 13207367 ps
CPU time 0.59 seconds
Started Jun 23 05:12:52 PM PDT 24
Finished Jun 23 05:12:53 PM PDT 24
Peak memory 196748 kb
Host smart-60e60936-57b0-4277-9003-d7d3e8f991c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553775319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.553775319
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.678182527
Short name T524
Test name
Test status
Simulation time 293079650 ps
CPU time 8.12 seconds
Started Jun 23 05:12:48 PM PDT 24
Finished Jun 23 05:12:56 PM PDT 24
Peak memory 200056 kb
Host smart-686d2932-7154-414b-ab1f-75e85590ed85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=678182527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.678182527
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3088666390
Short name T55
Test name
Test status
Simulation time 13607222631 ps
CPU time 50.5 seconds
Started Jun 23 05:12:45 PM PDT 24
Finished Jun 23 05:13:36 PM PDT 24
Peak memory 200148 kb
Host smart-6c3ddb9b-ca40-42a5-b55d-9380623918cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088666390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3088666390
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.1635491561
Short name T531
Test name
Test status
Simulation time 59945998 ps
CPU time 1.42 seconds
Started Jun 23 05:12:54 PM PDT 24
Finished Jun 23 05:12:56 PM PDT 24
Peak memory 200052 kb
Host smart-3b0b9ff1-f538-4ce1-ab33-42b5c9b07a3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1635491561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.1635491561
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3118001618
Short name T656
Test name
Test status
Simulation time 3130732485 ps
CPU time 48.08 seconds
Started Jun 23 05:12:50 PM PDT 24
Finished Jun 23 05:13:39 PM PDT 24
Peak memory 200076 kb
Host smart-ee0b6537-0110-4772-b6c4-93e731763535
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118001618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3118001618
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.2887268711
Short name T490
Test name
Test status
Simulation time 1161937652 ps
CPU time 16.9 seconds
Started Jun 23 05:12:44 PM PDT 24
Finished Jun 23 05:13:01 PM PDT 24
Peak memory 200032 kb
Host smart-9fbd7ef1-84c4-44f2-9247-101ad501d577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887268711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2887268711
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.227149330
Short name T345
Test name
Test status
Simulation time 160117485 ps
CPU time 2.63 seconds
Started Jun 23 05:12:51 PM PDT 24
Finished Jun 23 05:12:55 PM PDT 24
Peak memory 199972 kb
Host smart-a1028378-02c6-489b-8a8d-319bec0dcba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227149330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.227149330
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.789323074
Short name T621
Test name
Test status
Simulation time 221533022 ps
CPU time 1.19 seconds
Started Jun 23 05:12:47 PM PDT 24
Finished Jun 23 05:12:48 PM PDT 24
Peak memory 199988 kb
Host smart-471f4b09-d8a0-474c-898c-06e76382d758
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789323074 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_hmac_vectors.789323074
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha256_vectors.3479418175
Short name T230
Test name
Test status
Simulation time 15024310521 ps
CPU time 418 seconds
Started Jun 23 05:12:50 PM PDT 24
Finished Jun 23 05:19:49 PM PDT 24
Peak memory 200100 kb
Host smart-c24ac5f7-63d1-448b-834f-80fc02444111
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3479418175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha256_vectors.3479418175
Directory /workspace/38.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha384_vectors.692869760
Short name T556
Test name
Test status
Simulation time 31518114798 ps
CPU time 1705.86 seconds
Started Jun 23 05:12:47 PM PDT 24
Finished Jun 23 05:41:13 PM PDT 24
Peak memory 216040 kb
Host smart-3d3b247d-2158-47ac-8e65-7e144918827d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=692869760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha384_vectors.692869760
Directory /workspace/38.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha512_vectors.331299412
Short name T512
Test name
Test status
Simulation time 650645137314 ps
CPU time 2238 seconds
Started Jun 23 05:12:51 PM PDT 24
Finished Jun 23 05:50:10 PM PDT 24
Peak memory 216532 kb
Host smart-c75529b3-0b62-4cf6-9159-9337e599c37a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=331299412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha512_vectors.331299412
Directory /workspace/38.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1409798846
Short name T552
Test name
Test status
Simulation time 7956750509 ps
CPU time 76.31 seconds
Started Jun 23 05:12:51 PM PDT 24
Finished Jun 23 05:14:08 PM PDT 24
Peak memory 200144 kb
Host smart-6dc7ada3-afd1-4115-9971-1c48c51fa89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409798846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1409798846
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2875151933
Short name T573
Test name
Test status
Simulation time 23285818 ps
CPU time 0.62 seconds
Started Jun 23 05:12:51 PM PDT 24
Finished Jun 23 05:12:52 PM PDT 24
Peak memory 196000 kb
Host smart-8f4e0956-45b9-4b8f-8ced-6ea1082f8fa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875151933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2875151933
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3314039786
Short name T473
Test name
Test status
Simulation time 773392243 ps
CPU time 38.89 seconds
Started Jun 23 05:12:51 PM PDT 24
Finished Jun 23 05:13:30 PM PDT 24
Peak memory 200052 kb
Host smart-655c0ee6-140f-4b38-af6d-b509687598d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3314039786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3314039786
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.231460083
Short name T208
Test name
Test status
Simulation time 4280587895 ps
CPU time 56.14 seconds
Started Jun 23 05:12:50 PM PDT 24
Finished Jun 23 05:13:47 PM PDT 24
Peak memory 200124 kb
Host smart-ddfa04bc-709c-4784-a1ef-c3b227323b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231460083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.231460083
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3525587806
Short name T464
Test name
Test status
Simulation time 1863845811 ps
CPU time 201.88 seconds
Started Jun 23 05:12:52 PM PDT 24
Finished Jun 23 05:16:14 PM PDT 24
Peak memory 604920 kb
Host smart-b1ced6fc-80a3-416b-9fc7-9d80f1661979
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3525587806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3525587806
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.289065704
Short name T36
Test name
Test status
Simulation time 1622213360 ps
CPU time 44.32 seconds
Started Jun 23 05:12:48 PM PDT 24
Finished Jun 23 05:13:32 PM PDT 24
Peak memory 200056 kb
Host smart-8bd8ca54-24cb-4a0e-9296-bfe744087788
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289065704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.289065704
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1394590338
Short name T420
Test name
Test status
Simulation time 2822156279 ps
CPU time 41.88 seconds
Started Jun 23 05:12:47 PM PDT 24
Finished Jun 23 05:13:29 PM PDT 24
Peak memory 200060 kb
Host smart-f50fb2c4-24de-477e-8e8e-2a34c8a93d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394590338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1394590338
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1987199707
Short name T48
Test name
Test status
Simulation time 3118329366 ps
CPU time 16.08 seconds
Started Jun 23 05:12:51 PM PDT 24
Finished Jun 23 05:13:08 PM PDT 24
Peak memory 200120 kb
Host smart-b3706cec-0d8f-42cb-a6ec-8a2ae305ead5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987199707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1987199707
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.1508818966
Short name T543
Test name
Test status
Simulation time 57653012 ps
CPU time 1.38 seconds
Started Jun 23 05:12:59 PM PDT 24
Finished Jun 23 05:13:00 PM PDT 24
Peak memory 200104 kb
Host smart-569dab2d-8604-4d22-a5da-b7a4aaa20eeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508818966 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_hmac_vectors.1508818966
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha256_vectors.784435836
Short name T199
Test name
Test status
Simulation time 33314443735 ps
CPU time 515.2 seconds
Started Jun 23 05:12:53 PM PDT 24
Finished Jun 23 05:21:29 PM PDT 24
Peak memory 200344 kb
Host smart-877398df-1e02-4f98-9122-fd737a1f3973
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=784435836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha256_vectors.784435836
Directory /workspace/39.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha384_vectors.1548506105
Short name T288
Test name
Test status
Simulation time 548339745736 ps
CPU time 1713.36 seconds
Started Jun 23 05:12:54 PM PDT 24
Finished Jun 23 05:41:28 PM PDT 24
Peak memory 215832 kb
Host smart-27e834f6-e0b4-4036-bfa6-6afc398564b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1548506105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha384_vectors.1548506105
Directory /workspace/39.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha512_vectors.1832390148
Short name T78
Test name
Test status
Simulation time 228552529003 ps
CPU time 2029.69 seconds
Started Jun 23 05:12:50 PM PDT 24
Finished Jun 23 05:46:41 PM PDT 24
Peak memory 215576 kb
Host smart-1c52e471-c61a-4659-8f06-8a940d4a9cc4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1832390148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha512_vectors.1832390148
Directory /workspace/39.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2282080302
Short name T338
Test name
Test status
Simulation time 1051245451 ps
CPU time 44.51 seconds
Started Jun 23 05:12:46 PM PDT 24
Finished Jun 23 05:13:31 PM PDT 24
Peak memory 200080 kb
Host smart-afb59e42-0ae5-4dcf-bed9-1bbc4a2ceaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282080302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2282080302
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.4284671642
Short name T557
Test name
Test status
Simulation time 12397527 ps
CPU time 0.58 seconds
Started Jun 23 05:11:07 PM PDT 24
Finished Jun 23 05:11:08 PM PDT 24
Peak memory 194980 kb
Host smart-ebd54233-d8bf-4fd1-9992-0bd209d6e79c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284671642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.4284671642
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2358517324
Short name T624
Test name
Test status
Simulation time 1162431085 ps
CPU time 31.65 seconds
Started Jun 23 05:11:07 PM PDT 24
Finished Jun 23 05:11:39 PM PDT 24
Peak memory 200024 kb
Host smart-9eab8a5d-34d5-4257-ba7d-dcfde95ab376
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2358517324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2358517324
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3002322335
Short name T228
Test name
Test status
Simulation time 7554869191 ps
CPU time 51.31 seconds
Started Jun 23 05:11:05 PM PDT 24
Finished Jun 23 05:11:57 PM PDT 24
Peak memory 200080 kb
Host smart-eaa32dca-4980-4e3c-8008-e3ab0d6c81b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002322335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3002322335
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.3835943223
Short name T358
Test name
Test status
Simulation time 1425033537 ps
CPU time 338.76 seconds
Started Jun 23 05:11:04 PM PDT 24
Finished Jun 23 05:16:43 PM PDT 24
Peak memory 666300 kb
Host smart-425d85e5-45e3-4e14-bb19-fda52046c529
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3835943223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.3835943223
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2318722024
Short name T297
Test name
Test status
Simulation time 21402255855 ps
CPU time 126.46 seconds
Started Jun 23 05:11:09 PM PDT 24
Finished Jun 23 05:13:16 PM PDT 24
Peak memory 200124 kb
Host smart-05e64088-ac1e-4c40-bc4a-f0fb179f6e05
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318722024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2318722024
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.895899339
Short name T123
Test name
Test status
Simulation time 10065819030 ps
CPU time 105.53 seconds
Started Jun 23 05:11:06 PM PDT 24
Finished Jun 23 05:12:52 PM PDT 24
Peak memory 216560 kb
Host smart-e57f24b1-7de0-41ee-ad84-508b7251b867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895899339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.895899339
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2093762156
Short name T44
Test name
Test status
Simulation time 136638478 ps
CPU time 0.87 seconds
Started Jun 23 05:11:07 PM PDT 24
Finished Jun 23 05:11:08 PM PDT 24
Peak memory 218304 kb
Host smart-9802043a-caa0-4a16-9552-d2027a9eb832
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093762156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2093762156
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1177742529
Short name T407
Test name
Test status
Simulation time 879525603 ps
CPU time 11.56 seconds
Started Jun 23 05:11:14 PM PDT 24
Finished Jun 23 05:11:27 PM PDT 24
Peak memory 200052 kb
Host smart-61c0053d-11f3-4598-8658-4b11bbc99b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177742529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1177742529
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.1377437700
Short name T388
Test name
Test status
Simulation time 28801458 ps
CPU time 1.14 seconds
Started Jun 23 05:11:08 PM PDT 24
Finished Jun 23 05:11:09 PM PDT 24
Peak memory 200048 kb
Host smart-42ec2bae-efb0-4fe1-af96-864b3342fbc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377437700 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac_vectors.1377437700
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.891286093
Short name T428
Test name
Test status
Simulation time 36284353107 ps
CPU time 461.28 seconds
Started Jun 23 05:11:06 PM PDT 24
Finished Jun 23 05:18:48 PM PDT 24
Peak memory 200140 kb
Host smart-9d1c8224-647d-4d37-b555-4317b7600f07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=891286093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.891286093
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.1099437148
Short name T651
Test name
Test status
Simulation time 194448670515 ps
CPU time 1732.32 seconds
Started Jun 23 05:11:11 PM PDT 24
Finished Jun 23 05:40:04 PM PDT 24
Peak memory 215832 kb
Host smart-5ae43b86-8fba-4ff3-a4a2-e190c0defaf6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1099437148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.1099437148
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.3069652438
Short name T301
Test name
Test status
Simulation time 59467065577 ps
CPU time 1738.5 seconds
Started Jun 23 05:11:05 PM PDT 24
Finished Jun 23 05:40:04 PM PDT 24
Peak memory 216064 kb
Host smart-7f59ff67-6f16-470b-b0c8-675da048f710
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3069652438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.3069652438
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2556493012
Short name T2
Test name
Test status
Simulation time 4647692874 ps
CPU time 25.27 seconds
Started Jun 23 05:11:06 PM PDT 24
Finished Jun 23 05:11:32 PM PDT 24
Peak memory 199760 kb
Host smart-0bf82baa-1c71-407a-a715-d4292956f3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556493012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2556493012
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2635858033
Short name T318
Test name
Test status
Simulation time 13659812 ps
CPU time 0.61 seconds
Started Jun 23 05:12:56 PM PDT 24
Finished Jun 23 05:12:57 PM PDT 24
Peak memory 194976 kb
Host smart-dda3e35f-1b34-4418-9b1a-b87d5cbb58f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635858033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2635858033
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.607707729
Short name T277
Test name
Test status
Simulation time 530822243 ps
CPU time 24.14 seconds
Started Jun 23 05:13:04 PM PDT 24
Finished Jun 23 05:13:28 PM PDT 24
Peak memory 200004 kb
Host smart-3eb7a65d-9472-4ac8-a1ed-618e615624a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=607707729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.607707729
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.85453150
Short name T449
Test name
Test status
Simulation time 11399823292 ps
CPU time 59.95 seconds
Started Jun 23 05:12:52 PM PDT 24
Finished Jun 23 05:13:52 PM PDT 24
Peak memory 200060 kb
Host smart-27deff12-e8ab-48df-b4b2-e5ecfbfdf855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85453150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.85453150
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3208870112
Short name T365
Test name
Test status
Simulation time 1357469413 ps
CPU time 7.58 seconds
Started Jun 23 05:13:01 PM PDT 24
Finished Jun 23 05:13:09 PM PDT 24
Peak memory 200016 kb
Host smart-24bfcc8e-5829-4bd8-a303-e1983310b8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208870112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3208870112
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1171993575
Short name T559
Test name
Test status
Simulation time 520564604 ps
CPU time 4.95 seconds
Started Jun 23 05:12:59 PM PDT 24
Finished Jun 23 05:13:04 PM PDT 24
Peak memory 200104 kb
Host smart-801fa8e6-f105-452e-ac65-938101ecf566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171993575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1171993575
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.841002206
Short name T64
Test name
Test status
Simulation time 93263438970 ps
CPU time 1140.13 seconds
Started Jun 23 05:12:57 PM PDT 24
Finished Jun 23 05:31:57 PM PDT 24
Peak memory 755524 kb
Host smart-229da373-7a1a-47ad-a9b9-e2fbc940c8db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841002206 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.841002206
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.1423916497
Short name T571
Test name
Test status
Simulation time 63623162 ps
CPU time 1.34 seconds
Started Jun 23 05:12:57 PM PDT 24
Finished Jun 23 05:12:58 PM PDT 24
Peak memory 200008 kb
Host smart-0de15263-e26c-4368-88c2-cf44295b7487
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423916497 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_hmac_vectors.1423916497
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha256_vectors.495971049
Short name T160
Test name
Test status
Simulation time 30556752164 ps
CPU time 441.63 seconds
Started Jun 23 05:12:57 PM PDT 24
Finished Jun 23 05:20:19 PM PDT 24
Peak memory 200128 kb
Host smart-0d98d015-ebb6-4cda-a312-bb5c6ebdcec3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=495971049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha256_vectors.495971049
Directory /workspace/40.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha384_vectors.1919236893
Short name T475
Test name
Test status
Simulation time 103595144234 ps
CPU time 1809.46 seconds
Started Jun 23 05:12:58 PM PDT 24
Finished Jun 23 05:43:08 PM PDT 24
Peak memory 216080 kb
Host smart-ff1f15ef-b2d3-45e2-9cf5-eeb560430d0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1919236893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha384_vectors.1919236893
Directory /workspace/40.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha512_vectors.645960694
Short name T273
Test name
Test status
Simulation time 171389751854 ps
CPU time 2121.96 seconds
Started Jun 23 05:13:03 PM PDT 24
Finished Jun 23 05:48:26 PM PDT 24
Peak memory 216540 kb
Host smart-b26efd96-472c-4dcd-9623-849e2719a3d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=645960694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha512_vectors.645960694
Directory /workspace/40.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2590433279
Short name T49
Test name
Test status
Simulation time 5380527771 ps
CPU time 31.14 seconds
Started Jun 23 05:12:56 PM PDT 24
Finished Jun 23 05:13:27 PM PDT 24
Peak memory 200056 kb
Host smart-f4d7ab23-a49c-4282-a295-c0fa00078c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590433279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2590433279
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.4227229354
Short name T243
Test name
Test status
Simulation time 15101511 ps
CPU time 0.62 seconds
Started Jun 23 05:13:03 PM PDT 24
Finished Jun 23 05:13:04 PM PDT 24
Peak memory 195676 kb
Host smart-f4c49730-4e1a-4470-b2f1-2f75a92eb292
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227229354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.4227229354
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1153712846
Short name T532
Test name
Test status
Simulation time 639642831 ps
CPU time 17.44 seconds
Started Jun 23 05:12:56 PM PDT 24
Finished Jun 23 05:13:14 PM PDT 24
Peak memory 199940 kb
Host smart-86f095fc-05c3-4250-a79f-c86ffec39db6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1153712846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1153712846
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2425592602
Short name T17
Test name
Test status
Simulation time 536281479 ps
CPU time 5.51 seconds
Started Jun 23 05:13:01 PM PDT 24
Finished Jun 23 05:13:06 PM PDT 24
Peak memory 199956 kb
Host smart-b3ecaf82-1b3d-4636-8f6d-83e0c22df94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425592602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2425592602
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.3130198356
Short name T242
Test name
Test status
Simulation time 2526360958 ps
CPU time 695.94 seconds
Started Jun 23 05:13:01 PM PDT 24
Finished Jun 23 05:24:38 PM PDT 24
Peak memory 701256 kb
Host smart-17d926be-85c8-49da-8947-df272b51cc99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3130198356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3130198356
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2162664687
Short name T32
Test name
Test status
Simulation time 2204523053 ps
CPU time 58.08 seconds
Started Jun 23 05:13:02 PM PDT 24
Finished Jun 23 05:14:00 PM PDT 24
Peak memory 200084 kb
Host smart-66f97743-e980-41db-87e5-7b5fe511c6fc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162664687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2162664687
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.20596639
Short name T446
Test name
Test status
Simulation time 1871061333 ps
CPU time 110.8 seconds
Started Jun 23 05:12:57 PM PDT 24
Finished Jun 23 05:14:48 PM PDT 24
Peak memory 200120 kb
Host smart-dbdd9273-7e16-4144-9164-1ddd6ad570b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20596639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.20596639
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.217083447
Short name T18
Test name
Test status
Simulation time 796564152 ps
CPU time 12.07 seconds
Started Jun 23 05:12:56 PM PDT 24
Finished Jun 23 05:13:08 PM PDT 24
Peak memory 200088 kb
Host smart-2c073bde-1cf9-46e1-bfb3-12f9c08e0582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217083447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.217083447
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2317259430
Short name T607
Test name
Test status
Simulation time 2453340936 ps
CPU time 34.92 seconds
Started Jun 23 05:13:03 PM PDT 24
Finished Jun 23 05:13:38 PM PDT 24
Peak memory 200080 kb
Host smart-5c332f76-5c43-4050-88ac-3c78fd55059c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317259430 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2317259430
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.3978411925
Short name T640
Test name
Test status
Simulation time 164697163 ps
CPU time 1.14 seconds
Started Jun 23 05:13:02 PM PDT 24
Finished Jun 23 05:13:03 PM PDT 24
Peak memory 200016 kb
Host smart-fac45471-6ce3-4f38-a389-01f16face65a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978411925 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_hmac_vectors.3978411925
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha256_vectors.2327113024
Short name T158
Test name
Test status
Simulation time 68046319271 ps
CPU time 488.25 seconds
Started Jun 23 05:13:03 PM PDT 24
Finished Jun 23 05:21:12 PM PDT 24
Peak memory 200080 kb
Host smart-849af312-a2c0-4ba8-b9fe-7b33eb2be1ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2327113024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha256_vectors.2327113024
Directory /workspace/41.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha384_vectors.1443335962
Short name T216
Test name
Test status
Simulation time 229592512164 ps
CPU time 1977.49 seconds
Started Jun 23 05:13:03 PM PDT 24
Finished Jun 23 05:46:01 PM PDT 24
Peak memory 216496 kb
Host smart-30d918d7-e6ee-4fe0-972c-77de8d7eb139
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1443335962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha384_vectors.1443335962
Directory /workspace/41.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha512_vectors.1031908561
Short name T410
Test name
Test status
Simulation time 151864993459 ps
CPU time 1922.34 seconds
Started Jun 23 05:13:00 PM PDT 24
Finished Jun 23 05:45:03 PM PDT 24
Peak memory 215984 kb
Host smart-b8728d3a-070f-497f-93d4-315e3484e9f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1031908561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha512_vectors.1031908561
Directory /workspace/41.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1477918638
Short name T580
Test name
Test status
Simulation time 1527313426 ps
CPU time 8.44 seconds
Started Jun 23 05:13:02 PM PDT 24
Finished Jun 23 05:13:10 PM PDT 24
Peak memory 200072 kb
Host smart-b64f3eaa-91bb-4bdc-a2cd-de3767cb87ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477918638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1477918638
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1386056620
Short name T419
Test name
Test status
Simulation time 11791997 ps
CPU time 0.59 seconds
Started Jun 23 05:13:05 PM PDT 24
Finished Jun 23 05:13:06 PM PDT 24
Peak memory 196016 kb
Host smart-d16fb7dc-f880-4fc7-96fa-09b788141464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386056620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1386056620
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3543579066
Short name T23
Test name
Test status
Simulation time 709657918 ps
CPU time 14.57 seconds
Started Jun 23 05:13:10 PM PDT 24
Finished Jun 23 05:13:25 PM PDT 24
Peak memory 200028 kb
Host smart-ea539670-66bc-4fde-986c-c09853c66935
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3543579066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3543579066
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1155768102
Short name T518
Test name
Test status
Simulation time 2195019472 ps
CPU time 16.91 seconds
Started Jun 23 05:13:03 PM PDT 24
Finished Jun 23 05:13:20 PM PDT 24
Peak memory 200132 kb
Host smart-6cfadad6-cef1-4025-be5d-29ac09721a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155768102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1155768102
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3170010985
Short name T370
Test name
Test status
Simulation time 8151063860 ps
CPU time 588.1 seconds
Started Jun 23 05:13:01 PM PDT 24
Finished Jun 23 05:22:49 PM PDT 24
Peak memory 717844 kb
Host smart-5eb8fe2c-4168-48bb-b4eb-596a21bd1c4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3170010985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3170010985
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.122676614
Short name T311
Test name
Test status
Simulation time 2727593815 ps
CPU time 150.57 seconds
Started Jun 23 05:13:07 PM PDT 24
Finished Jun 23 05:15:38 PM PDT 24
Peak memory 200132 kb
Host smart-fe27274b-342f-4bbe-a683-245c4d0f6a6b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122676614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.122676614
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1748712533
Short name T250
Test name
Test status
Simulation time 22502883612 ps
CPU time 118.35 seconds
Started Jun 23 05:13:04 PM PDT 24
Finished Jun 23 05:15:02 PM PDT 24
Peak memory 200124 kb
Host smart-30b063b5-1895-4582-9047-ec2e69561342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748712533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1748712533
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1682299799
Short name T471
Test name
Test status
Simulation time 169051788 ps
CPU time 7.66 seconds
Started Jun 23 05:13:05 PM PDT 24
Finished Jun 23 05:13:13 PM PDT 24
Peak memory 200112 kb
Host smart-dceab132-859d-430b-a7f8-b8c0c9fefebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682299799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1682299799
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.2931854784
Short name T172
Test name
Test status
Simulation time 204644250 ps
CPU time 1.27 seconds
Started Jun 23 05:13:06 PM PDT 24
Finished Jun 23 05:13:08 PM PDT 24
Peak memory 200044 kb
Host smart-30ec5e41-b060-44f5-b59c-25cf1b3e385f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931854784 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_hmac_vectors.2931854784
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha256_vectors.956951932
Short name T270
Test name
Test status
Simulation time 26930647138 ps
CPU time 495.13 seconds
Started Jun 23 05:13:07 PM PDT 24
Finished Jun 23 05:21:23 PM PDT 24
Peak memory 200156 kb
Host smart-5a663e36-2e10-4223-9d6a-80fed38810d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=956951932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha256_vectors.956951932
Directory /workspace/42.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha384_vectors.2820883439
Short name T542
Test name
Test status
Simulation time 58984997309 ps
CPU time 1602.24 seconds
Started Jun 23 05:13:07 PM PDT 24
Finished Jun 23 05:39:49 PM PDT 24
Peak memory 216176 kb
Host smart-ca737807-5a60-4db7-83d9-b3aea3d8910b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2820883439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha384_vectors.2820883439
Directory /workspace/42.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha512_vectors.1747138230
Short name T276
Test name
Test status
Simulation time 31693483380 ps
CPU time 1873.44 seconds
Started Jun 23 05:13:05 PM PDT 24
Finished Jun 23 05:44:19 PM PDT 24
Peak memory 216316 kb
Host smart-99703c4a-0c8d-4879-8434-bf28178856b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1747138230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha512_vectors.1747138230
Directory /workspace/42.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2061100753
Short name T609
Test name
Test status
Simulation time 1838292940 ps
CPU time 66.91 seconds
Started Jun 23 05:13:09 PM PDT 24
Finished Jun 23 05:14:16 PM PDT 24
Peak memory 200104 kb
Host smart-e135b16e-4e5e-426c-9297-e1488e1b59c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061100753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2061100753
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3073224276
Short name T200
Test name
Test status
Simulation time 13214576 ps
CPU time 0.59 seconds
Started Jun 23 05:13:14 PM PDT 24
Finished Jun 23 05:13:15 PM PDT 24
Peak memory 195724 kb
Host smart-8f50a6f9-8cf2-47fd-b8db-c83d9af021d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073224276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3073224276
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.901332840
Short name T616
Test name
Test status
Simulation time 1976436895 ps
CPU time 50.27 seconds
Started Jun 23 05:13:09 PM PDT 24
Finished Jun 23 05:14:00 PM PDT 24
Peak memory 200060 kb
Host smart-525cb068-29ee-4480-b250-306a6a092465
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=901332840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.901332840
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1046694234
Short name T448
Test name
Test status
Simulation time 777517666 ps
CPU time 23.27 seconds
Started Jun 23 05:13:07 PM PDT 24
Finished Jun 23 05:13:31 PM PDT 24
Peak memory 199984 kb
Host smart-919d495a-d324-4d7c-95f3-5db315d313a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046694234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1046694234
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.3705212145
Short name T354
Test name
Test status
Simulation time 2867526447 ps
CPU time 128.16 seconds
Started Jun 23 05:13:07 PM PDT 24
Finished Jun 23 05:15:16 PM PDT 24
Peak memory 597600 kb
Host smart-532eb807-a5cb-4cb3-8ea8-c2e04900e1e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3705212145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3705212145
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.4037253241
Short name T453
Test name
Test status
Simulation time 48602711471 ps
CPU time 100.98 seconds
Started Jun 23 05:13:08 PM PDT 24
Finished Jun 23 05:14:49 PM PDT 24
Peak memory 200112 kb
Host smart-7525acb1-16d9-4d55-995f-95731504cf86
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037253241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.4037253241
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.4142458541
Short name T444
Test name
Test status
Simulation time 17047771850 ps
CPU time 82.04 seconds
Started Jun 23 05:13:06 PM PDT 24
Finished Jun 23 05:14:29 PM PDT 24
Peak memory 200152 kb
Host smart-b4c1c091-c768-47d7-845c-bf3ea85863ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142458541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.4142458541
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.1490735443
Short name T545
Test name
Test status
Simulation time 783796189 ps
CPU time 4.43 seconds
Started Jun 23 05:13:06 PM PDT 24
Finished Jun 23 05:13:11 PM PDT 24
Peak memory 200108 kb
Host smart-89170e89-6252-4f1f-acea-110d05dd5932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490735443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1490735443
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.1020386836
Short name T590
Test name
Test status
Simulation time 28408049 ps
CPU time 1.15 seconds
Started Jun 23 05:13:11 PM PDT 24
Finished Jun 23 05:13:13 PM PDT 24
Peak memory 199820 kb
Host smart-5d268862-a60e-49af-9b00-5f15ceefb4bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020386836 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_hmac_vectors.1020386836
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha256_vectors.229305116
Short name T383
Test name
Test status
Simulation time 20255123395 ps
CPU time 404.69 seconds
Started Jun 23 05:13:07 PM PDT 24
Finished Jun 23 05:19:52 PM PDT 24
Peak memory 200332 kb
Host smart-c2624988-c775-491b-b002-1b1708ccc177
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=229305116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha256_vectors.229305116
Directory /workspace/43.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha384_vectors.2918405501
Short name T460
Test name
Test status
Simulation time 164931017132 ps
CPU time 2061.36 seconds
Started Jun 23 05:13:13 PM PDT 24
Finished Jun 23 05:47:35 PM PDT 24
Peak memory 216292 kb
Host smart-f11a8358-cfc0-47d0-a0c0-f7c4e1d486b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2918405501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha384_vectors.2918405501
Directory /workspace/43.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha512_vectors.1421925344
Short name T148
Test name
Test status
Simulation time 32745103222 ps
CPU time 1800.34 seconds
Started Jun 23 05:13:12 PM PDT 24
Finished Jun 23 05:43:12 PM PDT 24
Peak memory 215560 kb
Host smart-21aaabe9-23cd-45c2-af8f-ed1d1d65d290
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1421925344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha512_vectors.1421925344
Directory /workspace/43.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.4070313960
Short name T507
Test name
Test status
Simulation time 1614674369 ps
CPU time 54.78 seconds
Started Jun 23 05:13:08 PM PDT 24
Finished Jun 23 05:14:03 PM PDT 24
Peak memory 200076 kb
Host smart-0818530b-aeac-49bb-87c6-3fd40193782e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070313960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.4070313960
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1411423136
Short name T351
Test name
Test status
Simulation time 29860716 ps
CPU time 0.58 seconds
Started Jun 23 05:13:21 PM PDT 24
Finished Jun 23 05:13:21 PM PDT 24
Peak memory 196740 kb
Host smart-691b3ea8-9361-4e4f-b88f-88fa3b9bbd0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411423136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1411423136
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3755448638
Short name T267
Test name
Test status
Simulation time 40404866 ps
CPU time 2.54 seconds
Started Jun 23 05:13:11 PM PDT 24
Finished Jun 23 05:13:14 PM PDT 24
Peak memory 199976 kb
Host smart-d72e00d4-0b3d-4261-8c93-4972387da53f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3755448638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3755448638
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1233270184
Short name T221
Test name
Test status
Simulation time 155683270 ps
CPU time 8.3 seconds
Started Jun 23 05:13:13 PM PDT 24
Finished Jun 23 05:13:21 PM PDT 24
Peak memory 200072 kb
Host smart-1c45c4e0-3400-4498-8683-1afaef8444d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233270184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1233270184
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1144809964
Short name T246
Test name
Test status
Simulation time 2844718454 ps
CPU time 760.55 seconds
Started Jun 23 05:13:13 PM PDT 24
Finished Jun 23 05:25:54 PM PDT 24
Peak memory 703348 kb
Host smart-a2479182-024e-4a07-88b5-688df3da24dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1144809964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1144809964
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.2784559823
Short name T117
Test name
Test status
Simulation time 4942587386 ps
CPU time 142.87 seconds
Started Jun 23 05:13:18 PM PDT 24
Finished Jun 23 05:15:41 PM PDT 24
Peak memory 200132 kb
Host smart-fbf17546-ca95-4dbf-afbd-0eaa02cd6778
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784559823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2784559823
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.665054920
Short name T128
Test name
Test status
Simulation time 2217189883 ps
CPU time 46.2 seconds
Started Jun 23 05:13:14 PM PDT 24
Finished Jun 23 05:14:00 PM PDT 24
Peak memory 200180 kb
Host smart-e2d5f7b6-e2d6-48eb-8f8f-9efbb8acd82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665054920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.665054920
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3895672348
Short name T302
Test name
Test status
Simulation time 1346507293 ps
CPU time 9.26 seconds
Started Jun 23 05:13:12 PM PDT 24
Finished Jun 23 05:13:21 PM PDT 24
Peak memory 200052 kb
Host smart-16ab1f0d-6108-4f13-94ee-f9caf508e9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895672348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3895672348
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.2082611735
Short name T591
Test name
Test status
Simulation time 44632567 ps
CPU time 1.07 seconds
Started Jun 23 05:13:17 PM PDT 24
Finished Jun 23 05:13:19 PM PDT 24
Peak memory 199712 kb
Host smart-53285434-c63b-4848-adf4-8b20217218a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082611735 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_hmac_vectors.2082611735
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha256_vectors.1873068026
Short name T434
Test name
Test status
Simulation time 7830266622 ps
CPU time 418.91 seconds
Started Jun 23 05:13:18 PM PDT 24
Finished Jun 23 05:20:17 PM PDT 24
Peak memory 200304 kb
Host smart-16c96923-b7fc-4c74-b597-5699662b0401
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1873068026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha256_vectors.1873068026
Directory /workspace/44.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha384_vectors.2268948417
Short name T155
Test name
Test status
Simulation time 60918824760 ps
CPU time 1766.89 seconds
Started Jun 23 05:13:16 PM PDT 24
Finished Jun 23 05:42:43 PM PDT 24
Peak memory 216144 kb
Host smart-66901b27-9c77-401f-84f7-12ac92f1e958
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2268948417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha384_vectors.2268948417
Directory /workspace/44.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha512_vectors.150438480
Short name T166
Test name
Test status
Simulation time 455737138563 ps
CPU time 2003.93 seconds
Started Jun 23 05:13:18 PM PDT 24
Finished Jun 23 05:46:43 PM PDT 24
Peak memory 216428 kb
Host smart-4acc5cb3-f641-48e0-938a-cbc984676f3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=150438480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha512_vectors.150438480
Directory /workspace/44.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2933264365
Short name T334
Test name
Test status
Simulation time 804266923 ps
CPU time 11.98 seconds
Started Jun 23 05:13:17 PM PDT 24
Finished Jun 23 05:13:29 PM PDT 24
Peak memory 200072 kb
Host smart-f0247003-731a-4673-9a96-433ea0ce66e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933264365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2933264365
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.413484597
Short name T438
Test name
Test status
Simulation time 41706039 ps
CPU time 0.62 seconds
Started Jun 23 05:13:23 PM PDT 24
Finished Jun 23 05:13:24 PM PDT 24
Peak memory 195624 kb
Host smart-c3d54861-01b0-4d21-956d-8da6faee9f97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413484597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.413484597
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3672836771
Short name T504
Test name
Test status
Simulation time 193035963 ps
CPU time 8.78 seconds
Started Jun 23 05:13:18 PM PDT 24
Finished Jun 23 05:13:27 PM PDT 24
Peak memory 200028 kb
Host smart-165a6169-862a-4a3c-b77b-67ac9f9a9168
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3672836771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3672836771
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.1734896768
Short name T659
Test name
Test status
Simulation time 1333593448 ps
CPU time 18.61 seconds
Started Jun 23 05:13:17 PM PDT 24
Finished Jun 23 05:13:36 PM PDT 24
Peak memory 200048 kb
Host smart-dd815d21-a4ad-421d-bcaf-a8ada277da01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734896768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1734896768
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2985063177
Short name T168
Test name
Test status
Simulation time 4096493380 ps
CPU time 257.53 seconds
Started Jun 23 05:13:17 PM PDT 24
Finished Jun 23 05:17:35 PM PDT 24
Peak memory 656732 kb
Host smart-be50e83b-be08-4a81-84e2-7a5720a0ce7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2985063177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2985063177
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.2330120832
Short name T116
Test name
Test status
Simulation time 8016797021 ps
CPU time 154.51 seconds
Started Jun 23 05:13:17 PM PDT 24
Finished Jun 23 05:15:52 PM PDT 24
Peak memory 200116 kb
Host smart-b81bd6fc-2436-4a41-b725-3dd726c7f805
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330120832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2330120832
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.4115534530
Short name T319
Test name
Test status
Simulation time 18631705027 ps
CPU time 92.29 seconds
Started Jun 23 05:13:17 PM PDT 24
Finished Jun 23 05:14:49 PM PDT 24
Peak memory 200148 kb
Host smart-4b4cb70e-ce8c-4f02-a5a7-b97912546117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115534530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.4115534530
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1037246598
Short name T528
Test name
Test status
Simulation time 195001219 ps
CPU time 8.51 seconds
Started Jun 23 05:13:16 PM PDT 24
Finished Jun 23 05:13:25 PM PDT 24
Peak memory 200044 kb
Host smart-d71651b0-ec59-474b-b95a-79d022f50f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037246598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1037246598
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.3506146133
Short name T540
Test name
Test status
Simulation time 462077902 ps
CPU time 1.38 seconds
Started Jun 23 05:13:26 PM PDT 24
Finished Jun 23 05:13:27 PM PDT 24
Peak memory 200008 kb
Host smart-c3c1d605-4ea7-44fc-828c-820d96c62635
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506146133 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_hmac_vectors.3506146133
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha256_vectors.3704339600
Short name T77
Test name
Test status
Simulation time 47562342786 ps
CPU time 418.88 seconds
Started Jun 23 05:13:22 PM PDT 24
Finished Jun 23 05:20:22 PM PDT 24
Peak memory 200080 kb
Host smart-920b3cd7-e9f6-4617-bf8c-8b98da1d4393
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3704339600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha256_vectors.3704339600
Directory /workspace/45.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha384_vectors.379769215
Short name T236
Test name
Test status
Simulation time 195524052816 ps
CPU time 1747.31 seconds
Started Jun 23 05:13:21 PM PDT 24
Finished Jun 23 05:42:29 PM PDT 24
Peak memory 215500 kb
Host smart-e9c47b2d-8e8f-4f87-9755-880d3499a9b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=379769215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha384_vectors.379769215
Directory /workspace/45.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha512_vectors.125188680
Short name T551
Test name
Test status
Simulation time 963373913721 ps
CPU time 1889.2 seconds
Started Jun 23 05:13:24 PM PDT 24
Finished Jun 23 05:44:54 PM PDT 24
Peak memory 215976 kb
Host smart-c0b9ec1a-33b4-47c5-b9b0-6f49dd86c629
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=125188680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha512_vectors.125188680
Directory /workspace/45.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1034126099
Short name T289
Test name
Test status
Simulation time 15912216176 ps
CPU time 52.04 seconds
Started Jun 23 05:13:26 PM PDT 24
Finished Jun 23 05:14:18 PM PDT 24
Peak memory 200136 kb
Host smart-06d2ad0e-dd53-469f-a211-ade9dcfe4037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034126099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1034126099
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.2586869869
Short name T341
Test name
Test status
Simulation time 48098568 ps
CPU time 0.62 seconds
Started Jun 23 05:13:31 PM PDT 24
Finished Jun 23 05:13:32 PM PDT 24
Peak memory 196048 kb
Host smart-cf1d0791-f0c6-414f-b69a-719b02502042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586869869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2586869869
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1600946563
Short name T498
Test name
Test status
Simulation time 290552020 ps
CPU time 13.68 seconds
Started Jun 23 05:13:24 PM PDT 24
Finished Jun 23 05:13:38 PM PDT 24
Peak memory 200112 kb
Host smart-4a46def3-ae57-4325-baf3-d69598801a18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1600946563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1600946563
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.712864801
Short name T369
Test name
Test status
Simulation time 1878423094 ps
CPU time 36.75 seconds
Started Jun 23 05:13:23 PM PDT 24
Finished Jun 23 05:14:00 PM PDT 24
Peak memory 199948 kb
Host smart-9d438c7c-916b-4990-9e5a-589dc300b5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712864801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.712864801
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.1498295850
Short name T547
Test name
Test status
Simulation time 6118538830 ps
CPU time 223.32 seconds
Started Jun 23 05:13:22 PM PDT 24
Finished Jun 23 05:17:06 PM PDT 24
Peak memory 564128 kb
Host smart-1dc532df-a78e-45cb-8b2e-569717c45a74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1498295850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1498295850
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1910126383
Short name T536
Test name
Test status
Simulation time 3999078854 ps
CPU time 88.24 seconds
Started Jun 23 05:13:22 PM PDT 24
Finished Jun 23 05:14:51 PM PDT 24
Peak memory 200104 kb
Host smart-984010d5-9287-49d3-af8d-64da9a1c299f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910126383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1910126383
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.97845633
Short name T266
Test name
Test status
Simulation time 11640071576 ps
CPU time 108.19 seconds
Started Jun 23 05:13:22 PM PDT 24
Finished Jun 23 05:15:11 PM PDT 24
Peak memory 200180 kb
Host smart-41eaee15-ba8c-4ba5-806c-d82fcfcd8d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97845633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.97845633
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3800711698
Short name T9
Test name
Test status
Simulation time 325631219 ps
CPU time 6.4 seconds
Started Jun 23 05:13:22 PM PDT 24
Finished Jun 23 05:13:29 PM PDT 24
Peak memory 200040 kb
Host smart-360fa2ca-0d26-46ef-8bed-21e7d9b63206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800711698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3800711698
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.184866471
Short name T484
Test name
Test status
Simulation time 189082164 ps
CPU time 1.11 seconds
Started Jun 23 05:13:29 PM PDT 24
Finished Jun 23 05:13:31 PM PDT 24
Peak memory 199868 kb
Host smart-b695ec53-2069-4052-9cb4-a3fed364d73e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184866471 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_hmac_vectors.184866471
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha256_vectors.1962649810
Short name T530
Test name
Test status
Simulation time 56107083722 ps
CPU time 516.39 seconds
Started Jun 23 05:13:24 PM PDT 24
Finished Jun 23 05:22:01 PM PDT 24
Peak memory 200128 kb
Host smart-e59e3139-aadf-488c-a355-5661d886687a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1962649810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha256_vectors.1962649810
Directory /workspace/46.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha384_vectors.2133518598
Short name T362
Test name
Test status
Simulation time 43709106584 ps
CPU time 1636.19 seconds
Started Jun 23 05:13:23 PM PDT 24
Finished Jun 23 05:40:40 PM PDT 24
Peak memory 216036 kb
Host smart-4d1fdc48-cdb8-43a6-94fe-60b3d7f2f05d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2133518598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha384_vectors.2133518598
Directory /workspace/46.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha512_vectors.405020923
Short name T645
Test name
Test status
Simulation time 917415604024 ps
CPU time 1850.32 seconds
Started Jun 23 05:13:28 PM PDT 24
Finished Jun 23 05:44:19 PM PDT 24
Peak memory 215692 kb
Host smart-60886a15-2b30-46c4-9e60-92e3d2198ac7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=405020923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha512_vectors.405020923
Directory /workspace/46.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.604808134
Short name T550
Test name
Test status
Simulation time 14759641156 ps
CPU time 104.28 seconds
Started Jun 23 05:13:22 PM PDT 24
Finished Jun 23 05:15:06 PM PDT 24
Peak memory 200164 kb
Host smart-2866ac45-5adf-4b1a-953c-9deec9d35fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604808134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.604808134
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1398781214
Short name T320
Test name
Test status
Simulation time 44491836 ps
CPU time 0.61 seconds
Started Jun 23 05:13:29 PM PDT 24
Finished Jun 23 05:13:30 PM PDT 24
Peak memory 195916 kb
Host smart-faf90bad-dfa7-4ece-afcb-cf844a2172b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398781214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1398781214
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2640804788
Short name T510
Test name
Test status
Simulation time 922875887 ps
CPU time 13.12 seconds
Started Jun 23 05:13:31 PM PDT 24
Finished Jun 23 05:13:45 PM PDT 24
Peak memory 200036 kb
Host smart-ef505cd2-8e03-4f8d-b58f-a864bbaea3b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2640804788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2640804788
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.5677560
Short name T29
Test name
Test status
Simulation time 16156351314 ps
CPU time 61.56 seconds
Started Jun 23 05:13:26 PM PDT 24
Finished Jun 23 05:14:28 PM PDT 24
Peak memory 200148 kb
Host smart-a43ae3d7-5d36-437d-8e27-a5f9d032e4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5677560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.5677560
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2353771363
Short name T441
Test name
Test status
Simulation time 6061380453 ps
CPU time 376 seconds
Started Jun 23 05:13:28 PM PDT 24
Finished Jun 23 05:19:44 PM PDT 24
Peak memory 462992 kb
Host smart-41b234ef-491a-490f-826d-fcc4ae855611
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2353771363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2353771363
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1443232697
Short name T220
Test name
Test status
Simulation time 2479208270 ps
CPU time 68.68 seconds
Started Jun 23 05:13:27 PM PDT 24
Finished Jun 23 05:14:36 PM PDT 24
Peak memory 200152 kb
Host smart-99d52578-9a91-488a-a3e9-d86a0a704805
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443232697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1443232697
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2566255629
Short name T442
Test name
Test status
Simulation time 8675462129 ps
CPU time 38.53 seconds
Started Jun 23 05:13:28 PM PDT 24
Finished Jun 23 05:14:07 PM PDT 24
Peak memory 200200 kb
Host smart-a29ddfa9-45df-42b2-98d0-b9115bae3a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566255629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2566255629
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2767354035
Short name T303
Test name
Test status
Simulation time 902934424 ps
CPU time 9.13 seconds
Started Jun 23 05:13:27 PM PDT 24
Finished Jun 23 05:13:37 PM PDT 24
Peak memory 200072 kb
Host smart-20a4164d-1ef0-452b-97db-79b6b19b9065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767354035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2767354035
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2066064580
Short name T74
Test name
Test status
Simulation time 250288224 ps
CPU time 1.18 seconds
Started Jun 23 05:13:27 PM PDT 24
Finished Jun 23 05:13:29 PM PDT 24
Peak memory 200044 kb
Host smart-12b0ad79-aabc-4f48-afa4-4b8e74bba109
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066064580 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_hmac_vectors.2066064580
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha256_vectors.4025326911
Short name T164
Test name
Test status
Simulation time 81816117061 ps
CPU time 564.73 seconds
Started Jun 23 05:13:28 PM PDT 24
Finished Jun 23 05:22:53 PM PDT 24
Peak memory 200172 kb
Host smart-54e089ab-78ec-483f-9317-6b94d1605458
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4025326911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha256_vectors.4025326911
Directory /workspace/47.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha384_vectors.4219060825
Short name T316
Test name
Test status
Simulation time 846824120578 ps
CPU time 1970.46 seconds
Started Jun 23 05:13:28 PM PDT 24
Finished Jun 23 05:46:19 PM PDT 24
Peak memory 215572 kb
Host smart-17d728c4-5771-4710-a91b-c8c41ece35f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4219060825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha384_vectors.4219060825
Directory /workspace/47.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha512_vectors.1255882725
Short name T322
Test name
Test status
Simulation time 32322475358 ps
CPU time 1690.84 seconds
Started Jun 23 05:13:29 PM PDT 24
Finished Jun 23 05:41:41 PM PDT 24
Peak memory 216096 kb
Host smart-de61208b-3bf2-4339-a5e1-00f7beeb6ae3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1255882725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha512_vectors.1255882725
Directory /workspace/47.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1611551198
Short name T506
Test name
Test status
Simulation time 21521631018 ps
CPU time 60.27 seconds
Started Jun 23 05:13:28 PM PDT 24
Finished Jun 23 05:14:29 PM PDT 24
Peak memory 200064 kb
Host smart-c4db2cc1-e5df-4586-9d2e-a7d1410fef5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611551198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1611551198
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.4240330085
Short name T525
Test name
Test status
Simulation time 43185900 ps
CPU time 0.62 seconds
Started Jun 23 05:13:32 PM PDT 24
Finished Jun 23 05:13:33 PM PDT 24
Peak memory 196748 kb
Host smart-e2331a6d-ba36-4e55-b858-f9e68359c8c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240330085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.4240330085
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2758551541
Short name T146
Test name
Test status
Simulation time 223209012 ps
CPU time 5.03 seconds
Started Jun 23 05:13:32 PM PDT 24
Finished Jun 23 05:13:37 PM PDT 24
Peak memory 199948 kb
Host smart-c185139f-9c67-4954-8db1-e3bfcf4cd0e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2758551541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2758551541
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.684470707
Short name T144
Test name
Test status
Simulation time 4089857988 ps
CPU time 54.07 seconds
Started Jun 23 05:13:30 PM PDT 24
Finished Jun 23 05:14:25 PM PDT 24
Peak memory 200144 kb
Host smart-c57edba3-19b3-42a0-a7ce-6267fb917d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684470707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.684470707
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2482325185
Short name T130
Test name
Test status
Simulation time 3602599291 ps
CPU time 909.45 seconds
Started Jun 23 05:13:31 PM PDT 24
Finished Jun 23 05:28:41 PM PDT 24
Peak memory 772180 kb
Host smart-907416d9-a01c-4983-8e9b-b50988a732c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2482325185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2482325185
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.551581578
Short name T132
Test name
Test status
Simulation time 1721794721 ps
CPU time 5.83 seconds
Started Jun 23 05:13:32 PM PDT 24
Finished Jun 23 05:13:38 PM PDT 24
Peak memory 200192 kb
Host smart-0b77f994-0130-4371-a4c4-3cdb36030fcf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551581578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.551581578
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2030885752
Short name T142
Test name
Test status
Simulation time 7237564671 ps
CPU time 53.86 seconds
Started Jun 23 05:13:31 PM PDT 24
Finished Jun 23 05:14:26 PM PDT 24
Peak memory 200044 kb
Host smart-ca7d8119-59f6-490e-a6c1-b48f0e3a15d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030885752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2030885752
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1627303935
Short name T156
Test name
Test status
Simulation time 598570344 ps
CPU time 3.41 seconds
Started Jun 23 05:13:33 PM PDT 24
Finished Jun 23 05:13:37 PM PDT 24
Peak memory 198460 kb
Host smart-224c217d-f58d-456d-9edd-95a6373a2a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627303935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1627303935
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.3011124703
Short name T433
Test name
Test status
Simulation time 249977120 ps
CPU time 1.32 seconds
Started Jun 23 05:13:33 PM PDT 24
Finished Jun 23 05:13:34 PM PDT 24
Peak memory 199968 kb
Host smart-2c8f9141-bce1-4d5a-aa0d-7ee3e30a85bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011124703 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_hmac_vectors.3011124703
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha384_vectors.2202873790
Short name T313
Test name
Test status
Simulation time 158805249118 ps
CPU time 1977.01 seconds
Started Jun 23 05:13:32 PM PDT 24
Finished Jun 23 05:46:29 PM PDT 24
Peak memory 215636 kb
Host smart-00080b61-33c6-4d1a-84b0-9e439814fd13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2202873790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha384_vectors.2202873790
Directory /workspace/48.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha512_vectors.3623875238
Short name T601
Test name
Test status
Simulation time 31301269395 ps
CPU time 1738.49 seconds
Started Jun 23 05:13:32 PM PDT 24
Finished Jun 23 05:42:31 PM PDT 24
Peak memory 215548 kb
Host smart-dff0a9f8-06f8-4165-a117-dea5b80609d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3623875238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha512_vectors.3623875238
Directory /workspace/48.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.193722397
Short name T274
Test name
Test status
Simulation time 951118281 ps
CPU time 14.75 seconds
Started Jun 23 05:13:31 PM PDT 24
Finished Jun 23 05:13:47 PM PDT 24
Peak memory 200020 kb
Host smart-9abf90c9-21d0-4f85-ae35-b1c653a0dff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193722397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.193722397
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2909763905
Short name T170
Test name
Test status
Simulation time 12672832 ps
CPU time 0.61 seconds
Started Jun 23 05:13:50 PM PDT 24
Finished Jun 23 05:13:51 PM PDT 24
Peak memory 195040 kb
Host smart-cabb26be-f470-4674-abcb-b4d529540e1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909763905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2909763905
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.4124569587
Short name T627
Test name
Test status
Simulation time 3341161905 ps
CPU time 43.53 seconds
Started Jun 23 05:13:38 PM PDT 24
Finished Jun 23 05:14:22 PM PDT 24
Peak memory 200136 kb
Host smart-39811734-8ee0-45e0-9a94-13dfdb63dfbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4124569587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.4124569587
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1423436111
Short name T339
Test name
Test status
Simulation time 4225810890 ps
CPU time 66.8 seconds
Started Jun 23 05:13:36 PM PDT 24
Finished Jun 23 05:14:43 PM PDT 24
Peak memory 200136 kb
Host smart-c058321d-7944-4a21-a5c6-209c592c1c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423436111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1423436111
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.4052991376
Short name T526
Test name
Test status
Simulation time 642420101 ps
CPU time 134.32 seconds
Started Jun 23 05:13:38 PM PDT 24
Finished Jun 23 05:15:53 PM PDT 24
Peak memory 430516 kb
Host smart-81ac6306-5c8c-4c0a-a65e-106aa6c6a37f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4052991376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.4052991376
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3850004923
Short name T563
Test name
Test status
Simulation time 40588363088 ps
CPU time 173.65 seconds
Started Jun 23 05:13:38 PM PDT 24
Finished Jun 23 05:16:32 PM PDT 24
Peak memory 200112 kb
Host smart-83578a8e-6f6b-4fbf-8f12-5bda15620c90
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850004923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3850004923
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2895067880
Short name T174
Test name
Test status
Simulation time 131385782 ps
CPU time 7.97 seconds
Started Jun 23 05:13:37 PM PDT 24
Finished Jun 23 05:13:46 PM PDT 24
Peak memory 200076 kb
Host smart-ba7eeb74-1510-47f6-83bf-0a8fd6898c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895067880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2895067880
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3099217805
Short name T611
Test name
Test status
Simulation time 271738115 ps
CPU time 1.3 seconds
Started Jun 23 05:13:38 PM PDT 24
Finished Jun 23 05:13:40 PM PDT 24
Peak memory 200016 kb
Host smart-b0bae505-8f13-4012-9574-ae67f08e6ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099217805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3099217805
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.1792190522
Short name T398
Test name
Test status
Simulation time 66020682 ps
CPU time 1.39 seconds
Started Jun 23 05:13:38 PM PDT 24
Finished Jun 23 05:13:40 PM PDT 24
Peak memory 200076 kb
Host smart-21b6275f-a422-4415-971b-1502209ea2ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792190522 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_hmac_vectors.1792190522
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha256_vectors.2656160782
Short name T54
Test name
Test status
Simulation time 27474294970 ps
CPU time 495.04 seconds
Started Jun 23 05:13:37 PM PDT 24
Finished Jun 23 05:21:53 PM PDT 24
Peak memory 200100 kb
Host smart-3e3e210b-454c-48b0-aa88-bc32ed63dcfa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2656160782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha256_vectors.2656160782
Directory /workspace/49.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha384_vectors.503172864
Short name T359
Test name
Test status
Simulation time 386155808481 ps
CPU time 1968.83 seconds
Started Jun 23 05:13:37 PM PDT 24
Finished Jun 23 05:46:27 PM PDT 24
Peak memory 216260 kb
Host smart-e2b94176-b121-4c62-beb2-243ff2670c55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=503172864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha384_vectors.503172864
Directory /workspace/49.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha512_vectors.3896204275
Short name T232
Test name
Test status
Simulation time 104348813217 ps
CPU time 1979.23 seconds
Started Jun 23 05:13:36 PM PDT 24
Finished Jun 23 05:46:36 PM PDT 24
Peak memory 215556 kb
Host smart-a60bbcec-ab34-4ca4-b43e-aedbc1bfebde
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3896204275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha512_vectors.3896204275
Directory /workspace/49.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.4162203149
Short name T495
Test name
Test status
Simulation time 22662271242 ps
CPU time 95.29 seconds
Started Jun 23 05:13:36 PM PDT 24
Finished Jun 23 05:15:12 PM PDT 24
Peak memory 200160 kb
Host smart-b1941917-98ba-4f7c-b6b5-71dc74b935f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162203149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.4162203149
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.4266689043
Short name T625
Test name
Test status
Simulation time 20783434 ps
CPU time 0.6 seconds
Started Jun 23 05:11:12 PM PDT 24
Finished Jun 23 05:11:14 PM PDT 24
Peak memory 196064 kb
Host smart-995c5956-638c-43be-9886-cab89871f852
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266689043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.4266689043
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.104710290
Short name T5
Test name
Test status
Simulation time 172796111 ps
CPU time 9.32 seconds
Started Jun 23 05:11:12 PM PDT 24
Finished Jun 23 05:11:22 PM PDT 24
Peak memory 199976 kb
Host smart-2619f0f8-419f-4ba7-908a-207ae54592ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104710290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.104710290
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.479999497
Short name T265
Test name
Test status
Simulation time 3842619286 ps
CPU time 17.99 seconds
Started Jun 23 05:11:07 PM PDT 24
Finished Jun 23 05:11:25 PM PDT 24
Peak memory 200140 kb
Host smart-62d4fee2-1c8a-4603-83b4-bfcae29ba905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479999497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.479999497
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3247143392
Short name T628
Test name
Test status
Simulation time 11559628059 ps
CPU time 848.67 seconds
Started Jun 23 05:11:14 PM PDT 24
Finished Jun 23 05:25:24 PM PDT 24
Peak memory 775372 kb
Host smart-da287189-267e-4aa6-8339-20e26c0bc663
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3247143392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3247143392
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.2041927231
Short name T549
Test name
Test status
Simulation time 7186055616 ps
CPU time 28.79 seconds
Started Jun 23 05:11:05 PM PDT 24
Finished Jun 23 05:11:35 PM PDT 24
Peak memory 200136 kb
Host smart-9e818a8b-3b7b-40d3-82fe-f4d8d5486645
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041927231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2041927231
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3810282459
Short name T115
Test name
Test status
Simulation time 911853326 ps
CPU time 56.28 seconds
Started Jun 23 05:11:12 PM PDT 24
Finished Jun 23 05:12:09 PM PDT 24
Peak memory 200068 kb
Host smart-90f7d831-4d0f-4130-b5c6-4a44799a59d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810282459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3810282459
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.4227246801
Short name T523
Test name
Test status
Simulation time 3373736679 ps
CPU time 11.93 seconds
Started Jun 23 05:11:15 PM PDT 24
Finished Jun 23 05:11:27 PM PDT 24
Peak memory 200152 kb
Host smart-0a8aae9b-0097-4124-ad0a-e8d95023fd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227246801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.4227246801
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.1369362167
Short name T206
Test name
Test status
Simulation time 34853412 ps
CPU time 1.29 seconds
Started Jun 23 05:11:14 PM PDT 24
Finished Jun 23 05:11:16 PM PDT 24
Peak memory 199976 kb
Host smart-37d87a88-7bbf-40e8-a208-a0084ccb1f92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369362167 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_hmac_vectors.1369362167
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha256_vectors.745248999
Short name T356
Test name
Test status
Simulation time 27107074744 ps
CPU time 482.49 seconds
Started Jun 23 05:11:12 PM PDT 24
Finished Jun 23 05:19:15 PM PDT 24
Peak memory 200128 kb
Host smart-48694878-6077-48d2-8ca8-eb1d560ac401
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=745248999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha256_vectors.745248999
Directory /workspace/5.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha384_vectors.4142037314
Short name T286
Test name
Test status
Simulation time 103494915675 ps
CPU time 1770.79 seconds
Started Jun 23 05:11:14 PM PDT 24
Finished Jun 23 05:40:46 PM PDT 24
Peak memory 216188 kb
Host smart-b90fa9f1-f542-4dc9-be82-6b6e507c8e5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4142037314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha384_vectors.4142037314
Directory /workspace/5.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha512_vectors.3816377616
Short name T169
Test name
Test status
Simulation time 407044820144 ps
CPU time 1903.01 seconds
Started Jun 23 05:11:12 PM PDT 24
Finished Jun 23 05:42:56 PM PDT 24
Peak memory 216228 kb
Host smart-f42dced4-4856-4b97-a536-e4826a1de528
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3816377616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha512_vectors.3816377616
Directory /workspace/5.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.417067565
Short name T387
Test name
Test status
Simulation time 15642346395 ps
CPU time 62.39 seconds
Started Jun 23 05:11:06 PM PDT 24
Finished Jun 23 05:12:10 PM PDT 24
Peak memory 200140 kb
Host smart-50c526e7-99f5-4547-a054-5b235b0adc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417067565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.417067565
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1765413406
Short name T477
Test name
Test status
Simulation time 13452865 ps
CPU time 0.56 seconds
Started Jun 23 05:11:12 PM PDT 24
Finished Jun 23 05:11:14 PM PDT 24
Peak memory 194860 kb
Host smart-9104d123-4162-4feb-b7be-41328774495a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765413406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1765413406
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.1238128979
Short name T21
Test name
Test status
Simulation time 139625662 ps
CPU time 4.44 seconds
Started Jun 23 05:11:12 PM PDT 24
Finished Jun 23 05:11:17 PM PDT 24
Peak memory 200004 kb
Host smart-aae9840c-af0b-46b8-a624-295cacf6cbf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1238128979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.1238128979
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3601299791
Short name T602
Test name
Test status
Simulation time 1165760445 ps
CPU time 10.87 seconds
Started Jun 23 05:11:12 PM PDT 24
Finished Jun 23 05:11:24 PM PDT 24
Peak memory 200088 kb
Host smart-04014e9f-c53d-4310-ad36-7a0e85ce4c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601299791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3601299791
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2362866959
Short name T348
Test name
Test status
Simulation time 2193371020 ps
CPU time 540.53 seconds
Started Jun 23 05:11:11 PM PDT 24
Finished Jun 23 05:20:12 PM PDT 24
Peak memory 523380 kb
Host smart-0f08c520-ba60-4e06-b59c-c51158fd8621
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2362866959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2362866959
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1726976749
Short name T294
Test name
Test status
Simulation time 8477430067 ps
CPU time 13.1 seconds
Started Jun 23 05:11:15 PM PDT 24
Finished Jun 23 05:11:28 PM PDT 24
Peak memory 199952 kb
Host smart-dd6667ec-f12d-4f89-82b6-9081dd2e196f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726976749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1726976749
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.2632547040
Short name T502
Test name
Test status
Simulation time 4062482001 ps
CPU time 17.93 seconds
Started Jun 23 05:11:10 PM PDT 24
Finished Jun 23 05:11:29 PM PDT 24
Peak memory 200192 kb
Host smart-2090d958-b594-4bd3-ae19-f0c56513b572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632547040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2632547040
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.219354001
Short name T285
Test name
Test status
Simulation time 176630337 ps
CPU time 8.33 seconds
Started Jun 23 05:11:17 PM PDT 24
Finished Jun 23 05:11:27 PM PDT 24
Peak memory 200040 kb
Host smart-64224f11-6827-43a9-8f9e-9cbef2f28b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219354001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.219354001
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.109413344
Short name T229
Test name
Test status
Simulation time 490397631472 ps
CPU time 1834.41 seconds
Started Jun 23 05:11:14 PM PDT 24
Finished Jun 23 05:41:49 PM PDT 24
Peak memory 828856 kb
Host smart-8bc20b46-5cd1-4e79-81b6-8f7fc11af2b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109413344 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.109413344
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.1339586217
Short name T349
Test name
Test status
Simulation time 153890566 ps
CPU time 1.1 seconds
Started Jun 23 05:11:13 PM PDT 24
Finished Jun 23 05:11:15 PM PDT 24
Peak memory 200008 kb
Host smart-c51aa3db-1c2e-4bb5-941e-b24f914f55a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339586217 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_hmac_vectors.1339586217
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha256_vectors.2088794163
Short name T480
Test name
Test status
Simulation time 57885226161 ps
CPU time 487.8 seconds
Started Jun 23 05:11:12 PM PDT 24
Finished Jun 23 05:19:21 PM PDT 24
Peak memory 200120 kb
Host smart-ed222930-fcb7-4467-a78e-fdb49a475ffa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2088794163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha256_vectors.2088794163
Directory /workspace/6.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha384_vectors.493240895
Short name T403
Test name
Test status
Simulation time 29605060373 ps
CPU time 1620.35 seconds
Started Jun 23 05:11:16 PM PDT 24
Finished Jun 23 05:38:17 PM PDT 24
Peak memory 215012 kb
Host smart-4f18d0a5-ad39-4340-9738-9ee41782696a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=493240895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha384_vectors.493240895
Directory /workspace/6.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha512_vectors.824713818
Short name T344
Test name
Test status
Simulation time 728611181200 ps
CPU time 2028.88 seconds
Started Jun 23 05:11:12 PM PDT 24
Finished Jun 23 05:45:02 PM PDT 24
Peak memory 216456 kb
Host smart-7aa90785-525b-44a8-aeff-cee98e821271
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=824713818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha512_vectors.824713818
Directory /workspace/6.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2188148842
Short name T373
Test name
Test status
Simulation time 2836233969 ps
CPU time 45.88 seconds
Started Jun 23 05:11:13 PM PDT 24
Finished Jun 23 05:12:00 PM PDT 24
Peak memory 200176 kb
Host smart-f8408c2b-7a66-4db3-aa81-e0e57282eea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188148842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2188148842
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3064228167
Short name T252
Test name
Test status
Simulation time 13013459 ps
CPU time 0.59 seconds
Started Jun 23 05:11:17 PM PDT 24
Finished Jun 23 05:11:18 PM PDT 24
Peak memory 196072 kb
Host smart-d78c7586-a9e2-4d6c-a6d2-0382ea536cc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064228167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3064228167
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2380632803
Short name T400
Test name
Test status
Simulation time 6577265049 ps
CPU time 52.75 seconds
Started Jun 23 05:11:16 PM PDT 24
Finished Jun 23 05:12:09 PM PDT 24
Peak memory 216544 kb
Host smart-ad9b323f-4e40-4b49-9bdd-816292394e13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2380632803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2380632803
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2374573833
Short name T567
Test name
Test status
Simulation time 289315202 ps
CPU time 15.99 seconds
Started Jun 23 05:11:12 PM PDT 24
Finished Jun 23 05:11:29 PM PDT 24
Peak memory 200068 kb
Host smart-3c6417ca-03dd-48c3-b57d-a73adddd6c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374573833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2374573833
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2349251570
Short name T331
Test name
Test status
Simulation time 11825511495 ps
CPU time 805.33 seconds
Started Jun 23 05:11:13 PM PDT 24
Finished Jun 23 05:24:40 PM PDT 24
Peak memory 747560 kb
Host smart-a1f8a7dc-438c-46af-b739-284eb2904315
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2349251570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2349251570
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.3474391059
Short name T272
Test name
Test status
Simulation time 1966581580 ps
CPU time 118.06 seconds
Started Jun 23 05:11:12 PM PDT 24
Finished Jun 23 05:13:11 PM PDT 24
Peak memory 200024 kb
Host smart-32fb209f-ba82-427f-8421-e7434d5c9fd2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474391059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3474391059
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1266389945
Short name T222
Test name
Test status
Simulation time 24891935620 ps
CPU time 129.21 seconds
Started Jun 23 05:11:14 PM PDT 24
Finished Jun 23 05:13:24 PM PDT 24
Peak memory 216532 kb
Host smart-74b69dba-d6d2-4d71-ae80-f9410095f39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266389945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1266389945
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3125906313
Short name T653
Test name
Test status
Simulation time 121699755 ps
CPU time 5.37 seconds
Started Jun 23 05:11:13 PM PDT 24
Finished Jun 23 05:11:19 PM PDT 24
Peak memory 200064 kb
Host smart-23991d78-f756-438c-8bd5-39d284f347a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125906313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3125906313
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.144518825
Short name T27
Test name
Test status
Simulation time 47737967631 ps
CPU time 178.53 seconds
Started Jun 23 05:11:10 PM PDT 24
Finished Jun 23 05:14:09 PM PDT 24
Peak memory 200244 kb
Host smart-a6cd29b4-06cb-4cc6-ae60-709d65b42dee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144518825 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.144518825
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.1186688811
Short name T649
Test name
Test status
Simulation time 222819693 ps
CPU time 1.21 seconds
Started Jun 23 05:11:13 PM PDT 24
Finished Jun 23 05:11:15 PM PDT 24
Peak memory 199864 kb
Host smart-4b1f5dbf-e25e-4bcb-bb43-2650e347cdfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186688811 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_hmac_vectors.1186688811
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha256_vectors.803051156
Short name T456
Test name
Test status
Simulation time 28184612016 ps
CPU time 380.07 seconds
Started Jun 23 05:11:11 PM PDT 24
Finished Jun 23 05:17:32 PM PDT 24
Peak memory 200128 kb
Host smart-9db0f21a-a914-4448-b834-e2d267ddb5e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=803051156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha256_vectors.803051156
Directory /workspace/7.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha384_vectors.947772316
Short name T328
Test name
Test status
Simulation time 62521170795 ps
CPU time 1728.6 seconds
Started Jun 23 05:11:14 PM PDT 24
Finished Jun 23 05:40:04 PM PDT 24
Peak memory 216208 kb
Host smart-e16f0a02-9816-4341-9ae2-bc85830bc9f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=947772316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha384_vectors.947772316
Directory /workspace/7.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha512_vectors.487178226
Short name T295
Test name
Test status
Simulation time 225947817594 ps
CPU time 2006.41 seconds
Started Jun 23 05:11:14 PM PDT 24
Finished Jun 23 05:44:41 PM PDT 24
Peak memory 216384 kb
Host smart-06976d97-4ec6-463f-b474-bd7039fa492a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=487178226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha512_vectors.487178226
Directory /workspace/7.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.3841041295
Short name T113
Test name
Test status
Simulation time 32929850528 ps
CPU time 53.14 seconds
Started Jun 23 05:11:12 PM PDT 24
Finished Jun 23 05:12:05 PM PDT 24
Peak memory 199804 kb
Host smart-28866468-f5b6-4acc-ac2b-4e25611813cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841041295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3841041295
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2815743628
Short name T513
Test name
Test status
Simulation time 13222847 ps
CPU time 0.59 seconds
Started Jun 23 05:11:17 PM PDT 24
Finished Jun 23 05:11:19 PM PDT 24
Peak memory 194988 kb
Host smart-d27536fc-000b-43bb-b286-e0f01e6fecd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815743628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2815743628
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3925089448
Short name T468
Test name
Test status
Simulation time 514757060 ps
CPU time 24.27 seconds
Started Jun 23 05:11:13 PM PDT 24
Finished Jun 23 05:11:38 PM PDT 24
Peak memory 200064 kb
Host smart-3b976d00-2139-45cc-936d-921415f9348a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3925089448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3925089448
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3062801527
Short name T416
Test name
Test status
Simulation time 1846723216 ps
CPU time 33.38 seconds
Started Jun 23 05:11:12 PM PDT 24
Finished Jun 23 05:11:46 PM PDT 24
Peak memory 200072 kb
Host smart-6e12111f-79a5-478f-ad40-1cd47ee1f845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062801527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3062801527
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1182324061
Short name T256
Test name
Test status
Simulation time 2541508366 ps
CPU time 580.91 seconds
Started Jun 23 05:11:11 PM PDT 24
Finished Jun 23 05:20:52 PM PDT 24
Peak memory 696540 kb
Host smart-a4ccf04c-26c8-40df-a533-99cdcefb9d86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1182324061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1182324061
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3629181376
Short name T401
Test name
Test status
Simulation time 612966512 ps
CPU time 33.97 seconds
Started Jun 23 05:11:13 PM PDT 24
Finished Jun 23 05:11:48 PM PDT 24
Peak memory 200068 kb
Host smart-b6de06be-75b7-4c76-8edb-cded3e29c4a2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629181376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3629181376
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3050632592
Short name T271
Test name
Test status
Simulation time 782013848 ps
CPU time 15.11 seconds
Started Jun 23 05:11:11 PM PDT 24
Finished Jun 23 05:11:26 PM PDT 24
Peak memory 200108 kb
Host smart-fe4d0b96-6348-4721-a819-348d3b6a9336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050632592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3050632592
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1284731306
Short name T472
Test name
Test status
Simulation time 625163007 ps
CPU time 6.41 seconds
Started Jun 23 05:11:16 PM PDT 24
Finished Jun 23 05:11:23 PM PDT 24
Peak memory 200052 kb
Host smart-44883494-aac1-4b84-a19b-2d04b69bdbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284731306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1284731306
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.2229162803
Short name T336
Test name
Test status
Simulation time 29159930 ps
CPU time 1.05 seconds
Started Jun 23 05:11:16 PM PDT 24
Finished Jun 23 05:11:18 PM PDT 24
Peak memory 200012 kb
Host smart-876a4fbc-ccc0-443b-bf83-2b583474e6c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229162803 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_hmac_vectors.2229162803
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha256_vectors.732545057
Short name T149
Test name
Test status
Simulation time 107888927454 ps
CPU time 437.68 seconds
Started Jun 23 05:11:17 PM PDT 24
Finished Jun 23 05:18:36 PM PDT 24
Peak memory 200080 kb
Host smart-768c60ea-d225-40b5-b79a-0f63aa590302
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=732545057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha256_vectors.732545057
Directory /workspace/8.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha384_vectors.1507986727
Short name T167
Test name
Test status
Simulation time 151668084309 ps
CPU time 1919.53 seconds
Started Jun 23 05:11:16 PM PDT 24
Finished Jun 23 05:43:17 PM PDT 24
Peak memory 215476 kb
Host smart-41746853-fbe0-4c5c-bce6-8d7a0439ebe1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1507986727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha384_vectors.1507986727
Directory /workspace/8.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha512_vectors.1433176074
Short name T197
Test name
Test status
Simulation time 767793592944 ps
CPU time 1823.56 seconds
Started Jun 23 05:11:16 PM PDT 24
Finished Jun 23 05:41:40 PM PDT 24
Peak memory 215592 kb
Host smart-e8aca3a6-7023-4972-85bf-0cb381bfe819
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1433176074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha512_vectors.1433176074
Directory /workspace/8.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.4130574470
Short name T374
Test name
Test status
Simulation time 2879514979 ps
CPU time 56.07 seconds
Started Jun 23 05:11:12 PM PDT 24
Finished Jun 23 05:12:09 PM PDT 24
Peak memory 200068 kb
Host smart-288ff7e2-f10b-4320-8f0f-755e5a6e3e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130574470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.4130574470
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3251216497
Short name T241
Test name
Test status
Simulation time 34176182 ps
CPU time 0.58 seconds
Started Jun 23 05:11:15 PM PDT 24
Finished Jun 23 05:11:17 PM PDT 24
Peak memory 195640 kb
Host smart-e16c22ea-2f17-49f9-b0e6-7b28d9f77683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251216497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3251216497
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.4126215772
Short name T7
Test name
Test status
Simulation time 122541516 ps
CPU time 1.56 seconds
Started Jun 23 05:11:16 PM PDT 24
Finished Jun 23 05:11:18 PM PDT 24
Peak memory 200048 kb
Host smart-d74520c6-b4b3-4ebe-bcd7-f5814b2ca8d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4126215772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.4126215772
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.407139036
Short name T517
Test name
Test status
Simulation time 2556734648 ps
CPU time 34.36 seconds
Started Jun 23 05:11:17 PM PDT 24
Finished Jun 23 05:11:53 PM PDT 24
Peak memory 200080 kb
Host smart-69e5913d-b134-4444-bd7b-542941fd8f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407139036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.407139036
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3954184829
Short name T491
Test name
Test status
Simulation time 1503730800 ps
CPU time 386.46 seconds
Started Jun 23 05:11:17 PM PDT 24
Finished Jun 23 05:17:45 PM PDT 24
Peak memory 642184 kb
Host smart-f109a88a-553b-49ab-ac39-cfc60b9b6f55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3954184829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3954184829
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3030149311
Short name T244
Test name
Test status
Simulation time 34708446 ps
CPU time 0.87 seconds
Started Jun 23 05:11:15 PM PDT 24
Finished Jun 23 05:11:16 PM PDT 24
Peak memory 197540 kb
Host smart-9bc3d73f-56d1-42d4-9d64-7cdb2389d87f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030149311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3030149311
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_smoke.4292847046
Short name T570
Test name
Test status
Simulation time 151174336 ps
CPU time 7.02 seconds
Started Jun 23 05:11:17 PM PDT 24
Finished Jun 23 05:11:26 PM PDT 24
Peak memory 200092 kb
Host smart-2520d1f5-5801-432c-bfb8-b0f485a52bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292847046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.4292847046
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.2002907246
Short name T482
Test name
Test status
Simulation time 682274636 ps
CPU time 1.31 seconds
Started Jun 23 05:11:16 PM PDT 24
Finished Jun 23 05:11:18 PM PDT 24
Peak memory 200060 kb
Host smart-6c36c63b-3aee-4e8a-b6e3-1234a31b24d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002907246 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_hmac_vectors.2002907246
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha256_vectors.1227105110
Short name T154
Test name
Test status
Simulation time 32332838805 ps
CPU time 451.82 seconds
Started Jun 23 05:11:16 PM PDT 24
Finished Jun 23 05:18:48 PM PDT 24
Peak memory 200048 kb
Host smart-7219503d-55d1-4ef5-a687-a20c503cb08f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1227105110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha256_vectors.1227105110
Directory /workspace/9.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha384_vectors.436685765
Short name T185
Test name
Test status
Simulation time 166565789092 ps
CPU time 2183.05 seconds
Started Jun 23 05:11:14 PM PDT 24
Finished Jun 23 05:47:38 PM PDT 24
Peak memory 215588 kb
Host smart-2a5eaabe-11ba-4e51-ab1b-48c1fb0d750c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=436685765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha384_vectors.436685765
Directory /workspace/9.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha512_vectors.246472950
Short name T315
Test name
Test status
Simulation time 343623616448 ps
CPU time 1711.11 seconds
Started Jun 23 05:11:21 PM PDT 24
Finished Jun 23 05:39:53 PM PDT 24
Peak memory 216000 kb
Host smart-76f0b43a-b17c-4810-bccb-f0391fb26152
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=246472950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha512_vectors.246472950
Directory /workspace/9.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3134175206
Short name T395
Test name
Test status
Simulation time 4363026890 ps
CPU time 64.29 seconds
Started Jun 23 05:11:15 PM PDT 24
Finished Jun 23 05:12:20 PM PDT 24
Peak memory 200108 kb
Host smart-01411296-1e5e-4dcd-b9dd-cee41282fd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134175206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3134175206
Directory /workspace/9.hmac_wipe_secret/latest
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