Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	35196701	1			T1	5517		T2	76752		T3	2749
all_values[1]	35196701	1			T1	5517		T2	76752		T3	2749
all_values[2]	35196701	1			T1	5517		T2	76752		T3	2749

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

71501

1

T1

17

T3

569

T20

965

auto[1]

105518602

1

T1

16534

T2

230256

T3

7678

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87386382

1

T1

13644

T2

190626

T3

7022

auto[1]

18203721

1

T1

2907

T2

39630

T3

1225

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	24055	1			T6	2		T127	1		T22	4
all_values[0]	auto[0]	auto[1]	191	1			T127	2		T16	2		T128	2
all_values[0]	auto[1]	auto[0]	35120551	1			T1	5486		T2	76558		T3	2738
all_values[0]	auto[1]	auto[1]	51904	1			T1	31		T2	194		T3	11
all_values[1]	auto[0]	auto[0]	26789	1			T30	948		T127	3		T15	179
all_values[1]	auto[0]	auto[1]	90	1			T69	1		T70	4		T71	1
all_values[1]	auto[1]	auto[0]	35166641	1			T1	5516		T2	76752		T3	2749
all_values[1]	auto[1]	auto[1]	3181	1			T1	1		T5	118		T16	68
all_values[2]	auto[0]	auto[0]	6401	1			T1	2		T3	1		T20	495
all_values[2]	auto[0]	auto[1]	13975	1			T1	15		T3	568		T20	470
all_values[2]	auto[1]	auto[0]	17041945	1			T1	2640		T2	37316		T3	1534
all_values[2]	auto[1]	auto[1]	18134380	1			T1	2860		T2	39436		T3	646