Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	2	16	88.89
Crosses	32	8	24	75.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	1	14	93.33	100	1	1	0
msg_len_upper_cp	1	1	0	0.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	6	24	80.00	100	1	1	0
msg_len_upper_cross	2	2	0	0.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100292

1

T1

2212

T2

172

T3

16

auto[1]

59042

1

T1

2620

T3

4

T8

2

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	1	14	93.33

User Defined Bins for msg_len_lower_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_511	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	25628	1			T1	1036		T2	21		T3	3
len_1026_2046	18930	1			T1	894		T2	3		T3	2
len_514_1022	5210	1			T1	133		T2	2		T3	1
len_2_510	23710	1			T1	136		T2	59		T3	1
len_2049	2	1			T141	2		-	-		-	-
len_2048	30	1			T1	1		T15	1		T22	1
len_2047	2	1			T79	2		-	-		-	-
len_1025	2	1			T142	2		-	-		-	-
len_1024	53	1			T1	1		T13	1		T143	1
len_1023	1	1			T144	1		-	-		-	-
len_513	3	1			T145	3		-	-		-	-
len_512	47	1			T1	2		T13	1		T143	1
len_1	618	1			T2	1		T4	1		T12	1
len_0	5431	1			T1	213		T3	3		T4	2

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for msg_len_upper_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_upper	0	1	1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	6	24	80.00	6

Automatically Generated Cross Bins for msg_len_lower_cross

Uncovered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[len_2049]	0	1	1
[auto[0]]	[len_513]	0	1	1
[auto[0]]	[len_511]	0	1	1
[auto[1]]	[len_2047]	0	1	1
[auto[1]]	[len_1023]	0	1	1
[auto[1]]	[len_511]	0	1	1

Covered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	16352	1			T1	473		T2	21		T3	3
auto[0]	len_1026_2046	9258	1			T1	234		T2	3		T4	8
auto[0]	len_514_1022	2848	1			T1	120		T2	2		T3	1
auto[0]	len_2_510	19399	1			T1	124		T2	59		T3	1
auto[0]	len_2048	23	1			T15	1		T22	1		T146	1
auto[0]	len_2047	2	1			T79	2		-	-		-	-
auto[0]	len_1025	1	1			T142	1		-	-		-	-
auto[0]	len_1024	38	1			T1	1		T13	1		T143	1
auto[0]	len_1023	1	1			T144	1		-	-		-	-
auto[0]	len_512	32	1			T1	1		T13	1		T143	1
auto[0]	len_1	139	1			T2	1		T4	1		T12	1
auto[0]	len_0	2053	1			T1	153		T3	3		T4	2
auto[1]	len_2050_plus	9276	1			T1	563		T13	111		T14	5
auto[1]	len_1026_2046	9672	1			T1	660		T3	2		T13	217
auto[1]	len_514_1022	2362	1			T1	13		T13	5		T15	29
auto[1]	len_2_510	4311	1			T1	12		T8	1		T10	2
auto[1]	len_2049	2	1			T141	2		-	-		-	-
auto[1]	len_2048	7	1			T1	1		T147	1		T148	1
auto[1]	len_1025	1	1			T142	1		-	-		-	-
auto[1]	len_1024	15	1			T149	1		T150	1		T151	1
auto[1]	len_513	3	1			T145	3		-	-		-	-
auto[1]	len_512	15	1			T1	1		T147	1		T151	1
auto[1]	len_1	479	1			T32	17		T37	13		T152	14
auto[1]	len_0	3378	1			T1	60		T13	56		T20	4

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	2	0	0.00	2

Automatically Generated Cross Bins for msg_len_upper_cross

Uncovered bins

hmac_en	msg_len_upper_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	2