Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17127225

1

T1

6398

T2

37121

T3

1547

auto[1]

1392866

1

T1

10283

T3

1119

T13

2155

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1316091

1

T1

8586

T3

1083

T13

1928

auto[1]

17204000

1

T1

8095

T2

37121

T3

1583

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16519653

1

T1

9045

T2

37121

T3

2238

auto[1]

2000438

1

T1

7636

T3

428

T8

29

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	16186381	1			T1	6585		T2	24228		T3	2521
fifo_depth[1]	495080	1			T1	53		T2	2558		T3	57
fifo_depth[2]	373052	1			T1	133		T2	2361		T3	47
fifo_depth[3]	294556	1			T1	82		T2	1844		T3	23
fifo_depth[4]	227965	1			T1	217		T2	1470		T3	11
fifo_depth[5]	176157	1			T1	166		T2	1102		T3	6
fifo_depth[6]	152609	1			T1	161		T2	1049		T12	26
fifo_depth[7]	135394	1			T1	170		T2	836		T3	1

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2333710

1

T1

10096

T2

12893

T3

145

auto[1]

16186381

1

T1

6585

T2

24228

T3

2521

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18514751

1

T1

15505

T2

37121

T3

2666

auto[1]

5340

1

T1

1176

T5

2

T15

592

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

30702

1

T1

1087

T3

36

T13

82

auto[0]

auto[0]

auto[0]

auto[1]

38380

1

T1

2846

T13

128

T14

43

auto[0]

auto[0]

auto[1]

auto[0]

1932455

1

T1

1340

T2

12893

T3

47

auto[0]

auto[0]

auto[1]

auto[1]

36017

1

T1

2042

T3

33

T14

82

auto[0]

auto[1]

auto[0]

auto[0]

83977

1

T1

1677

T3

29

T14

20

auto[0]

auto[1]

auto[0]

auto[1]

57301

1

T1

1104

T14

6

T20

172

auto[0]

auto[1]

auto[1]

auto[0]

70393

1

T8

4

T10

13

T14

66

auto[0]

auto[1]

auto[1]

auto[1]

84485

1

T13

60

T14

24

T20

259

auto[1]

auto[0]

auto[0]

auto[0]

142191

1

T1

283

T3

381

T13

534

auto[1]

auto[0]

auto[0]

auto[1]

160621

1

T1

450

T3

239

T13

563

auto[1]

auto[0]

auto[1]

auto[0]

14022226

1

T1

373

T2

24228

T3

655

auto[1]

auto[0]

auto[1]

auto[1]

157061

1

T1

624

T3

847

T13

36

auto[1]

auto[1]

auto[0]

auto[0]

401696

1

T1

322

T3

398

T13

288

auto[1]

auto[1]

auto[0]

auto[1]

401223

1

T1

817

T13

333

T14

978

auto[1]

auto[1]

auto[1]

auto[0]

443585

1

T1

1316

T3

1

T8

25

auto[1]

auto[1]

auto[1]

auto[1]

457778

1

T1

2400

T13

1035

T14

2225

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

172536

1

T1

1296

T3

417

T13

616

auto[0]

auto[0]

auto[0]

auto[1]

197812

1

T1

2727

T3

239

T13

691

auto[0]

auto[0]

auto[1]

auto[0]

15953031

1

T1

1684

T2

37121

T3

702

auto[0]

auto[0]

auto[1]

auto[1]

192344

1

T1

2635

T3

880

T13

36

auto[0]

auto[1]

auto[0]

auto[0]

485423

1

T1

1992

T3

427

T13

288

auto[0]

auto[1]

auto[0]

auto[1]

457783

1

T1

1455

T13

333

T14

984

auto[0]

auto[1]

auto[1]

auto[0]

513727

1

T1

1316

T3

1

T8

29

auto[0]

auto[1]

auto[1]

auto[1]

542095

1

T1

2400

T13

1095

T14

2249

auto[1]

auto[0]

auto[0]

auto[0]

357

1

T1

74

T15

9

T24

1

auto[1]

auto[0]

auto[0]

auto[1]

1189

1

T1

569

T15

17

T38

1

auto[1]

auto[0]

auto[1]

auto[0]

1650

1

T1

29

T5

1

T27

1

auto[1]

auto[0]

auto[1]

auto[1]

734

1

T1

31

T15

432

T165

13

auto[1]

auto[1]

auto[0]

auto[0]

250

1

T1

7

T15

69

T24

1

auto[1]

auto[1]

auto[0]

auto[1]

741

1

T1

466

T5

1

T166

4

auto[1]

auto[1]

auto[1]

auto[0]

251

1

T38

9

T167

42

T151

14

auto[1]

auto[1]

auto[1]

auto[1]

168

1

T15

65

T28

1

T168

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	142191	1			T1	283		T3	381		T13	534
fifo_depth[0]	auto[0]	auto[0]	auto[1]	160621	1			T1	450		T3	239		T13	563
fifo_depth[0]	auto[0]	auto[1]	auto[0]	14022226	1			T1	373		T2	24228		T3	655
fifo_depth[0]	auto[0]	auto[1]	auto[1]	157061	1			T1	624		T3	847		T13	36
fifo_depth[0]	auto[1]	auto[0]	auto[0]	401696	1			T1	322		T3	398		T13	288
fifo_depth[0]	auto[1]	auto[0]	auto[1]	401223	1			T1	817		T13	333		T14	978
fifo_depth[0]	auto[1]	auto[1]	auto[0]	443585	1			T1	1316		T3	1		T8	25
fifo_depth[0]	auto[1]	auto[1]	auto[1]	457778	1			T1	2400		T13	1035		T14	2225
fifo_depth[1]	auto[0]	auto[0]	auto[0]	3297	1			T1	2		T3	14		T13	12
fifo_depth[1]	auto[0]	auto[0]	auto[1]	4147	1			T1	6		T13	4		T14	22
fifo_depth[1]	auto[0]	auto[1]	auto[0]	453412	1			T1	1		T2	2558		T3	21
fifo_depth[1]	auto[0]	auto[1]	auto[1]	4160	1			T1	41		T3	11		T14	57
fifo_depth[1]	auto[1]	auto[0]	auto[0]	7924	1			T1	3		T3	11		T14	13
fifo_depth[1]	auto[1]	auto[0]	auto[1]	6183	1			T14	3		T20	16		T19	24
fifo_depth[1]	auto[1]	auto[1]	auto[0]	7166	1			T8	2		T10	4		T14	36
fifo_depth[1]	auto[1]	auto[1]	auto[1]	8791	1			T13	6		T14	9		T20	37
fifo_depth[2]	auto[0]	auto[0]	auto[0]	2926	1			T1	13		T3	13		T13	32
fifo_depth[2]	auto[0]	auto[0]	auto[1]	3585	1			T1	32		T13	68		T14	13
fifo_depth[2]	auto[0]	auto[1]	auto[0]	335008	1			T1	13		T2	2361		T3	13
fifo_depth[2]	auto[0]	auto[1]	auto[1]	3434	1			T1	46		T3	11		T14	16
fifo_depth[2]	auto[1]	auto[0]	auto[0]	7484	1			T1	29		T3	10		T14	5
fifo_depth[2]	auto[1]	auto[0]	auto[1]	5708	1			T14	1		T20	19		T19	13
fifo_depth[2]	auto[1]	auto[1]	auto[0]	6671	1			T8	2		T10	4		T14	20
fifo_depth[2]	auto[1]	auto[1]	auto[1]	8236	1			T13	7		T14	6		T20	31
fifo_depth[3]	auto[0]	auto[0]	auto[0]	2115	1			T1	3		T3	6		T13	5
fifo_depth[3]	auto[0]	auto[0]	auto[1]	2559	1			T1	5		T13	1		T14	7
fifo_depth[3]	auto[0]	auto[1]	auto[0]	261306	1			T1	2		T2	1844		T3	8
fifo_depth[3]	auto[0]	auto[1]	auto[1]	2635	1			T1	39		T3	4		T14	8
fifo_depth[3]	auto[1]	auto[0]	auto[0]	6970	1			T1	31		T3	5		T14	1
fifo_depth[3]	auto[1]	auto[0]	auto[1]	5238	1			T1	2		T20	16		T19	15
fifo_depth[3]	auto[1]	auto[1]	auto[0]	6013	1			T10	1		T14	9		T20	6
fifo_depth[3]	auto[1]	auto[1]	auto[1]	7720	1			T13	10		T14	6		T20	27
fifo_depth[4]	auto[0]	auto[0]	auto[0]	2068	1			T1	13		T3	2		T13	12
fifo_depth[4]	auto[0]	auto[0]	auto[1]	2516	1			T1	38		T13	54		T14	1
fifo_depth[4]	auto[0]	auto[1]	auto[0]	195676	1			T1	16		T2	1470		T3	2
fifo_depth[4]	auto[0]	auto[1]	auto[1]	2382	1			T1	52		T3	4		T14	1
fifo_depth[4]	auto[1]	auto[0]	auto[0]	7045	1			T1	97		T3	3		T20	46
fifo_depth[4]	auto[1]	auto[0]	auto[1]	5001	1			T1	1		T14	1		T20	16
fifo_depth[4]	auto[1]	auto[1]	auto[0]	5900	1			T10	3		T14	1		T20	12
fifo_depth[4]	auto[1]	auto[1]	auto[1]	7377	1			T13	7		T14	1		T20	31
fifo_depth[5]	auto[0]	auto[0]	auto[0]	1748	1			T1	5		T3	1		T13	7
fifo_depth[5]	auto[0]	auto[0]	auto[1]	1798	1			T1	8		T20	36		T19	98
fifo_depth[5]	auto[0]	auto[1]	auto[0]	146726	1			T1	7		T2	1102		T3	3
fifo_depth[5]	auto[0]	auto[1]	auto[1]	1869	1			T1	52		T3	2		T20	18
fifo_depth[5]	auto[1]	auto[0]	auto[0]	6391	1			T1	93		T14	1		T20	39
fifo_depth[5]	auto[1]	auto[0]	auto[1]	4818	1			T1	1		T14	1		T20	12
fifo_depth[5]	auto[1]	auto[1]	auto[0]	5675	1			T10	1		T20	8		T19	2
fifo_depth[5]	auto[1]	auto[1]	auto[1]	7132	1			T13	8		T14	1		T20	31
fifo_depth[6]	auto[0]	auto[0]	auto[0]	1752	1			T1	10		T13	5		T20	44
fifo_depth[6]	auto[0]	auto[0]	auto[1]	1858	1			T1	32		T13	1		T20	36
fifo_depth[6]	auto[0]	auto[1]	auto[0]	123513	1			T1	18		T2	1049		T12	26
fifo_depth[6]	auto[0]	auto[1]	auto[1]	1782	1			T1	47		T20	17		T119	1
fifo_depth[6]	auto[1]	auto[0]	auto[0]	6517	1			T1	54		T20	42		T32	88
fifo_depth[6]	auto[1]	auto[0]	auto[1]	4758	1			T20	11		T19	14		T30	28
fifo_depth[6]	auto[1]	auto[1]	auto[0]	5441	1			T20	10		T61	4		T32	167
fifo_depth[6]	auto[1]	auto[1]	auto[1]	6988	1			T13	5		T14	1		T20	33
fifo_depth[7]	auto[0]	auto[0]	auto[0]	1579	1			T1	4		T13	2		T20	41
fifo_depth[7]	auto[0]	auto[0]	auto[1]	1739	1			T1	4		T20	39		T19	82
fifo_depth[7]	auto[0]	auto[1]	auto[0]	107689	1			T1	5		T2	836		T12	5
fifo_depth[7]	auto[0]	auto[1]	auto[1]	1705	1			T1	60		T3	1		T20	19
fifo_depth[7]	auto[1]	auto[0]	auto[0]	6113	1			T1	94		T20	48		T32	89
fifo_depth[7]	auto[1]	auto[0]	auto[1]	4550	1			T1	3		T20	10		T19	13
fifo_depth[7]	auto[1]	auto[1]	auto[0]	5281	1			T20	6		T61	3		T32	145
fifo_depth[7]	auto[1]	auto[1]	auto[1]	6738	1			T13	4		T20	26		T32	102