Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	35196701	1			T1	5517		T2	76752		T3	2749
all_pins[1]	35196701	1			T1	5517		T2	76752		T3	2749
all_pins[2]	35196701	1			T1	5517		T2	76752		T3	2749

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	87400078	1			T1	13652		T2	190626		T3	7589
values[0x1]	18190025	1			T1	2899		T2	39630		T3	658
transitions[0x0=>0x1]	18189849	1			T1	2899		T2	39630		T3	658
transitions[0x1=>0x0]	18189856	1			T1	2899		T2	39630		T3	658

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	35144319	1			T1	5480		T2	76558		T3	2737
all_pins[0]	values[0x1]	52382	1			T1	37		T2	194		T3	12
all_pins[0]	transitions[0x0=>0x1]	52349	1			T1	37		T2	194		T3	12
all_pins[0]	transitions[0x1=>0x0]	18134354	1			T1	2860		T2	39436		T3	646
all_pins[1]	values[0x0]	35193438	1			T1	5515		T2	76752		T3	2749
all_pins[1]	values[0x1]	3263	1			T1	2		T5	121		T16	70
all_pins[1]	transitions[0x0=>0x1]	3151	1			T1	2		T5	118		T16	66
all_pins[1]	transitions[0x1=>0x0]	52270	1			T1	37		T2	194		T3	12
all_pins[2]	values[0x0]	17062321	1			T1	2657		T2	37316		T3	2103
all_pins[2]	values[0x1]	18134380	1			T1	2860		T2	39436		T3	646
all_pins[2]	transitions[0x0=>0x1]	18134349	1			T1	2860		T2	39436		T3	646
all_pins[2]	transitions[0x1=>0x0]	3232	1			T1	2		T5	121		T16	70