Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 422 1 T69 7 T70 14 T71 11
all_values[1] 422 1 T69 7 T70 14 T71 11
all_values[2] 422 1 T69 7 T70 14 T71 11


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 697 1 T69 13 T70 28 T71 16
auto[1] 569 1 T69 8 T70 14 T71 17


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 463 1 T69 5 T70 11 T71 16
auto[1] 803 1 T69 16 T70 31 T71 17


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 726 1 T69 9 T70 22 T71 22
auto[1] 540 1 T69 12 T70 20 T71 11


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 106 1 T69 2 T70 6 T71 2
all_values[0] auto[0] auto[0] auto[1] 44 1 T70 2 T71 1 T153 1
all_values[0] auto[0] auto[1] auto[0] 72 1 T70 1 T71 4 T153 2
all_values[0] auto[0] auto[1] auto[1] 33 1 T69 1 T153 1 T154 1
all_values[0] auto[1] auto[0] auto[1] 90 1 T69 4 T70 3 T71 2
all_values[0] auto[1] auto[1] auto[1] 77 1 T70 2 T71 2 T153 2
all_values[1] auto[0] auto[0] auto[0] 85 1 T69 1 T70 2 T71 3
all_values[1] auto[0] auto[0] auto[1] 52 1 T69 1 T70 3 T71 1
all_values[1] auto[0] auto[1] auto[0] 57 1 T70 2 T71 2 T153 2
all_values[1] auto[0] auto[1] auto[1] 43 1 T69 2 T71 1 T153 1
all_values[1] auto[1] auto[0] auto[1] 99 1 T69 1 T70 6 T71 2
all_values[1] auto[1] auto[1] auto[1] 86 1 T69 2 T70 1 T71 2
all_values[2] auto[0] auto[0] auto[0] 89 1 T69 1 T71 3 T153 2
all_values[2] auto[0] auto[0] auto[1] 37 1 T70 2 T71 2 T153 2
all_values[2] auto[0] auto[1] auto[0] 54 1 T69 1 T71 2 T153 2
all_values[2] auto[0] auto[1] auto[1] 54 1 T70 4 T71 1 T75 1
all_values[2] auto[1] auto[0] auto[1] 95 1 T69 3 T70 4 T153 2
all_values[2] auto[1] auto[1] auto[1] 93 1 T69 2 T70 4 T71 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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