Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.47	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	2	18	90.00
Crosses	82	22	60	73.17

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	1	4	80.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	1	6	85.71	100	1	1	0
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	8	0	8	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	11	24	68.57	100	1	1	0
key_length_x_digest_size	35	11	24	68.57	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	1	4	80.00

User Defined Bins for digest_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
sha2_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_none	83	1			T30	1		T31	2		T34	1
sha2_512	20307	1			T1	7		T3	2		T12	386
sha2_384	19599	1			T1	10		T3	1		T13	3
sha2_256	11493	1			T1	6		T2	194		T3	4

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48751

1

T1

9

T2

194

T3

6

auto[1]

2731

1

T1

14

T3

1

T13

4

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2567

1

T1

14

T3

3

T13

7

auto[1]

48915

1

T1

9

T2

194

T3

4

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

2602

1

T1

5

T3

2

T8

4

disabled

48880

1

T1

18

T2

194

T3

5

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for key_length

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
key_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	1030	1			T1	6		T3	1		T14	6
key_1024	753	1			T1	6		T3	1		T14	3
key_512	945	1			T1	4		T14	4		T20	2
key_384	855	1			T1	3		T3	1		T13	4
key_256	47025	1			T1	3		T2	194		T3	2
key_128	874	1			T1	1		T3	2		T13	1

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

51274

1

T1

23

T2

194

T3

7

disabled

208

1

T19

2

T30

2

T31

4

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
enabled	auto[0]	auto[0]	595	1			T1	3		T3	1		T13	1
enabled	auto[0]	auto[1]	583	1			T1	2		T13	1		T14	2
enabled	auto[1]	auto[0]	790	1			T3	1		T8	4		T10	4
enabled	auto[1]	auto[1]	634	1			T13	2		T14	2		T20	1
disabled	auto[0]	auto[0]	650	1			T1	4		T3	2		T13	4
disabled	auto[0]	auto[1]	739	1			T1	5		T13	1		T14	2
disabled	auto[1]	auto[0]	46716	1			T1	2		T2	194		T3	2
disabled	auto[1]	auto[1]	775	1			T1	7		T3	1		T14	4

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

2507

1

T1

5

T3

2

T8

4

enabled

disabled

95

1

T30

1

T31

2

T34

1

disabled

disabled

113

1

T19

2

T30

1

T31

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

48767

1

T1

18

T2

194

T3

5

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	11	24	68.57	11
Automatically Generated Cross Bins	34	11	23	67.65	11
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid]	--	--	6

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_none	34	1			T30	1		T31	1		T34	1
key_none	sha2_512	332	1			T1	1		T14	2		T20	1
key_none	sha2_384	331	1			T1	3		T3	1		T14	2
key_none	sha2_256	333	1			T1	2		T14	2		T20	4
key_1024	sha2_none	8	1			T129	1		T130	1		T131	1
key_1024	sha2_512	304	1			T1	4		T3	1		T14	1
key_1024	sha2_384	308	1			T1	1		T14	1		T20	1
key_512	sha2_none	12	1			T31	1		T132	1		T133	2
key_512	sha2_512	306	1			T20	1		T5	1		T119	1
key_512	sha2_384	325	1			T1	4		T14	2		T19	1
key_512	sha2_256	302	1			T14	2		T20	1		T19	8
key_384	sha2_none	12	1			T134	1		T43	1		T135	1
key_384	sha2_512	303	1			T13	2		T14	3		T19	2
key_384	sha2_384	259	1			T1	1		T32	1		T6	1
key_384	sha2_256	281	1			T1	2		T3	1		T13	2
key_256	sha2_none	9	1			T136	1		T137	1		T138	1
key_256	sha2_512	18796	1			T1	2		T3	1		T12	386
key_256	sha2_384	18058	1			T1	1		T13	2		T14	3
key_256	sha2_256	10162	1			T2	194		T3	1		T4	194
key_128	sha2_none	8	1			T139	1		T131	1		T140	1
key_128	sha2_512	266	1			T14	1		T20	1		T19	1
key_128	sha2_384	318	1			T13	1		T5	1		T32	1
key_128	sha2_256	282	1			T1	1		T3	2		T20	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

133

1

T1

1

T14

1

T5

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	11	24	68.57	11

Automatically Generated Cross Bins for key_length_x_digest_size

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid]	--	--	6

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_none	34	1			T30	1		T31	1		T34	1
key_none	sha2_512	332	1			T1	1		T14	2		T20	1
key_none	sha2_384	331	1			T1	3		T3	1		T14	2
key_none	sha2_256	333	1			T1	2		T14	2		T20	4
key_1024	sha2_none	8	1			T129	1		T130	1		T131	1
key_1024	sha2_512	304	1			T1	4		T3	1		T14	1
key_1024	sha2_384	308	1			T1	1		T14	1		T20	1
key_1024	sha2_256	133	1			T1	1		T14	1		T5	1
key_512	sha2_none	12	1			T31	1		T132	1		T133	2
key_512	sha2_512	306	1			T20	1		T5	1		T119	1
key_512	sha2_384	325	1			T1	4		T14	2		T19	1
key_512	sha2_256	302	1			T14	2		T20	1		T19	8
key_384	sha2_none	12	1			T134	1		T43	1		T135	1
key_384	sha2_512	303	1			T13	2		T14	3		T19	2
key_384	sha2_384	259	1			T1	1		T32	1		T6	1
key_384	sha2_256	281	1			T1	2		T3	1		T13	2
key_256	sha2_none	9	1			T136	1		T137	1		T138	1
key_256	sha2_512	18796	1			T1	2		T3	1		T12	386
key_256	sha2_384	18058	1			T1	1		T13	2		T14	3
key_256	sha2_256	10162	1			T2	194		T3	1		T4	194
key_128	sha2_none	8	1			T139	1		T131	1		T140	1
key_128	sha2_512	266	1			T14	1		T20	1		T19	1
key_128	sha2_384	318	1			T13	1		T5	1		T32	1
key_128	sha2_256	282	1			T1	1		T3	2		T20	2