Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.58 95.85 92.94 100.00 74.36 91.89 99.49 93.58


Total test records in report: 775
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html
T155 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1609307253 Jun 24 05:36:28 PM PDT 24 Jun 24 05:36:33 PM PDT 24 154552283 ps
T754 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1996565848 Jun 24 05:36:19 PM PDT 24 Jun 24 05:36:21 PM PDT 24 64135186 ps
T755 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1733431988 Jun 24 05:36:31 PM PDT 24 Jun 24 05:36:34 PM PDT 24 15444263 ps
T756 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1101891898 Jun 24 05:36:30 PM PDT 24 Jun 24 05:36:33 PM PDT 24 12728656 ps
T757 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.273725494 Jun 24 05:36:30 PM PDT 24 Jun 24 05:36:35 PM PDT 24 836452084 ps
T156 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2853293226 Jun 24 05:36:13 PM PDT 24 Jun 24 05:36:17 PM PDT 24 301719360 ps
T758 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2799316417 Jun 24 05:36:26 PM PDT 24 Jun 24 05:36:32 PM PDT 24 454557635 ps
T759 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3962937882 Jun 24 05:36:24 PM PDT 24 Jun 24 05:36:33 PM PDT 24 831766737 ps
T760 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2681244613 Jun 24 05:36:33 PM PDT 24 Jun 24 05:36:40 PM PDT 24 236714531 ps
T761 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3401455230 Jun 24 05:36:33 PM PDT 24 Jun 24 05:36:50 PM PDT 24 615621353 ps
T762 /workspace/coverage/cover_reg_top/48.hmac_intr_test.977215324 Jun 24 05:36:35 PM PDT 24 Jun 24 05:36:40 PM PDT 24 44242516 ps
T763 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.438099403 Jun 24 05:36:29 PM PDT 24 Jun 24 05:44:58 PM PDT 24 51481568970 ps
T764 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3263085474 Jun 24 05:36:33 PM PDT 24 Jun 24 05:36:37 PM PDT 24 41498992 ps
T765 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.929832628 Jun 24 05:36:26 PM PDT 24 Jun 24 05:36:31 PM PDT 24 46275672 ps
T766 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1647351642 Jun 24 05:36:24 PM PDT 24 Jun 24 05:36:28 PM PDT 24 286499261 ps
T767 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1693553654 Jun 24 05:36:25 PM PDT 24 Jun 24 05:36:29 PM PDT 24 112863848 ps
T768 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.990833227 Jun 24 05:36:34 PM PDT 24 Jun 24 05:36:42 PM PDT 24 361214417 ps
T769 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.813321708 Jun 24 05:36:19 PM PDT 24 Jun 24 05:36:23 PM PDT 24 85260723 ps
T770 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.805006700 Jun 24 05:36:44 PM PDT 24 Jun 24 05:36:48 PM PDT 24 308359318 ps
T157 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.28040248 Jun 24 05:36:35 PM PDT 24 Jun 24 05:36:43 PM PDT 24 256574236 ps
T771 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3837453685 Jun 24 05:36:40 PM PDT 24 Jun 24 05:36:46 PM PDT 24 79646471 ps
T772 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.18647848 Jun 24 05:36:35 PM PDT 24 Jun 24 05:36:42 PM PDT 24 82366139 ps
T773 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1778670045 Jun 24 05:36:36 PM PDT 24 Jun 24 05:36:42 PM PDT 24 171509085 ps
T774 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3429726447 Jun 24 05:36:32 PM PDT 24 Jun 24 05:36:38 PM PDT 24 214623314 ps
T775 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3906232054 Jun 24 05:36:21 PM PDT 24 Jun 24 05:36:25 PM PDT 24 120208245 ps

Test location /workspace/coverage/default/3.hmac_burst_wr.89452973
Short name T1
Test name
Test status
Simulation time 8609857782 ps
CPU time 72.09 seconds
Started Jun 24 06:16:57 PM PDT 24
Finished Jun 24 06:18:11 PM PDT 24
Peak memory 200148 kb
Host smart-0dda1a24-2c6e-4b7b-8214-04b74d893293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89452973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.89452973
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_long_msg.778835028
Short name T14
Test name
Test status
Simulation time 15777881439 ps
CPU time 106.01 seconds
Started Jun 24 06:19:18 PM PDT 24
Finished Jun 24 06:21:04 PM PDT 24
Peak memory 200148 kb
Host smart-f8e00435-f39b-4d0a-8acc-a7fb446d3ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778835028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.778835028
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3410117337
Short name T67
Test name
Test status
Simulation time 228725195981 ps
CPU time 554.23 seconds
Started Jun 24 05:36:34 PM PDT 24
Finished Jun 24 05:45:52 PM PDT 24
Peak memory 215672 kb
Host smart-c8702e40-f5b3-45f6-9b75-ad6dba8ee45a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410117337 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3410117337
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1828404562
Short name T71
Test name
Test status
Simulation time 32043179675 ps
CPU time 1068.3 seconds
Started Jun 24 06:17:39 PM PDT 24
Finished Jun 24 06:35:29 PM PDT 24
Peak memory 728784 kb
Host smart-615c9b8f-802b-49f9-b139-a883775cfc6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828404562 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1828404562
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.539021904
Short name T90
Test name
Test status
Simulation time 150625133 ps
CPU time 3.16 seconds
Started Jun 24 05:36:32 PM PDT 24
Finished Jun 24 05:36:37 PM PDT 24
Peak memory 199592 kb
Host smart-a271f34f-ee27-40e3-a9b8-0e6f254c42eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539021904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.539021904
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1937793075
Short name T22
Test name
Test status
Simulation time 1288406296 ps
CPU time 62.36 seconds
Started Jun 24 06:17:29 PM PDT 24
Finished Jun 24 06:18:35 PM PDT 24
Peak memory 200100 kb
Host smart-d512eaec-5270-4abb-bd85-cbb996442155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937793075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1937793075
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3909386317
Short name T26
Test name
Test status
Simulation time 635741569 ps
CPU time 32.7 seconds
Started Jun 24 06:18:43 PM PDT 24
Finished Jun 24 06:19:18 PM PDT 24
Peak memory 200036 kb
Host smart-f3065258-6984-4f48-b210-0386a9744ea5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3909386317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3909386317
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_error.2888222968
Short name T19
Test name
Test status
Simulation time 4400747077 ps
CPU time 62.42 seconds
Started Jun 24 06:19:46 PM PDT 24
Finished Jun 24 06:20:49 PM PDT 24
Peak memory 200072 kb
Host smart-f4ea7523-6d9b-46d0-96a1-b6db8f2397ec
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888222968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2888222968
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_alert_test.659204036
Short name T197
Test name
Test status
Simulation time 12025760 ps
CPU time 0.59 seconds
Started Jun 24 06:17:37 PM PDT 24
Finished Jun 24 06:17:39 PM PDT 24
Peak memory 195804 kb
Host smart-c9254306-6e51-4f90-866a-b9be1ddae124
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659204036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.659204036
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3780414193
Short name T104
Test name
Test status
Simulation time 45314025 ps
CPU time 0.69 seconds
Started Jun 24 05:36:36 PM PDT 24
Finished Jun 24 05:36:41 PM PDT 24
Peak memory 197904 kb
Host smart-b01d1b94-b8f4-4e5e-9916-958c079a6408
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780414193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3780414193
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/default/11.hmac_error.973284112
Short name T134
Test name
Test status
Simulation time 4548331047 ps
CPU time 86.42 seconds
Started Jun 24 06:17:28 PM PDT 24
Finished Jun 24 06:18:58 PM PDT 24
Peak memory 200108 kb
Host smart-f202de33-2478-4d8e-a219-0514297144ef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973284112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.973284112
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_error.1437436946
Short name T498
Test name
Test status
Simulation time 10267306163 ps
CPU time 61.41 seconds
Started Jun 24 06:20:04 PM PDT 24
Finished Jun 24 06:21:06 PM PDT 24
Peak memory 200028 kb
Host smart-3d1eb0ec-560a-4fd3-9b2c-c36017f39fee
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437436946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1437436946
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.4286153155
Short name T51
Test name
Test status
Simulation time 147607294 ps
CPU time 0.83 seconds
Started Jun 24 06:16:49 PM PDT 24
Finished Jun 24 06:16:52 PM PDT 24
Peak memory 218244 kb
Host smart-f881480f-a3c2-49dc-8e25-2f8b60841ac9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286153155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.4286153155
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2853293226
Short name T156
Test name
Test status
Simulation time 301719360 ps
CPU time 3.08 seconds
Started Jun 24 05:36:13 PM PDT 24
Finished Jun 24 05:36:17 PM PDT 24
Peak memory 199612 kb
Host smart-4d1462b2-7bfc-425d-a6c4-1a83f5b0b693
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853293226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2853293226
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1805881851
Short name T32
Test name
Test status
Simulation time 40385951974 ps
CPU time 1442.08 seconds
Started Jun 24 06:18:36 PM PDT 24
Finished Jun 24 06:42:40 PM PDT 24
Peak memory 767464 kb
Host smart-d78af1e2-416e-46ad-a021-84d940413fbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1805881851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1805881851
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2299081447
Short name T162
Test name
Test status
Simulation time 160694592 ps
CPU time 4.21 seconds
Started Jun 24 05:36:33 PM PDT 24
Finished Jun 24 05:36:41 PM PDT 24
Peak memory 199680 kb
Host smart-1427bb8c-6511-4451-93e9-c1439da5e6a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299081447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2299081447
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.388626986
Short name T142
Test name
Test status
Simulation time 589760629 ps
CPU time 28.44 seconds
Started Jun 24 06:18:33 PM PDT 24
Finished Jun 24 06:19:03 PM PDT 24
Peak memory 200020 kb
Host smart-1d89da2b-f581-439b-853b-6ddc7690ac88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=388626986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.388626986
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2291380456
Short name T38
Test name
Test status
Simulation time 1407169463 ps
CPU time 37.58 seconds
Started Jun 24 06:17:29 PM PDT 24
Finished Jun 24 06:18:10 PM PDT 24
Peak memory 200028 kb
Host smart-b7225d70-2c6e-43bc-820e-7e6f0580f878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291380456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2291380456
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1443227197
Short name T154
Test name
Test status
Simulation time 16973981 ps
CPU time 0.59 seconds
Started Jun 24 05:36:36 PM PDT 24
Finished Jun 24 05:36:41 PM PDT 24
Peak memory 194428 kb
Host smart-5b821b14-a84d-4ebd-a8be-085143d0dce9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443227197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1443227197
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1534697852
Short name T144
Test name
Test status
Simulation time 2586195170 ps
CPU time 42.8 seconds
Started Jun 24 06:16:47 PM PDT 24
Finished Jun 24 06:17:31 PM PDT 24
Peak memory 200136 kb
Host smart-0c7586c3-e79b-4fb0-841a-f2481b784b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534697852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1534697852
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.332185162
Short name T145
Test name
Test status
Simulation time 8453938470 ps
CPU time 955.51 seconds
Started Jun 24 06:17:45 PM PDT 24
Finished Jun 24 06:33:42 PM PDT 24
Peak memory 739604 kb
Host smart-f115aa33-5404-4d17-afe7-0bf6776c8b3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=332185162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.332185162
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.369341683
Short name T141
Test name
Test status
Simulation time 8052618348 ps
CPU time 385.97 seconds
Started Jun 24 06:18:30 PM PDT 24
Finished Jun 24 06:24:57 PM PDT 24
Peak memory 642856 kb
Host smart-369649a3-ff30-4dab-a71c-99fc4a71ef9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=369341683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.369341683
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3900647812
Short name T79
Test name
Test status
Simulation time 2591885182 ps
CPU time 47.17 seconds
Started Jun 24 06:19:18 PM PDT 24
Finished Jun 24 06:20:06 PM PDT 24
Peak memory 200136 kb
Host smart-9e56f8fe-fff6-4780-b88b-8422dc289919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900647812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3900647812
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2948698504
Short name T117
Test name
Test status
Simulation time 140921054 ps
CPU time 1.08 seconds
Started Jun 24 05:36:28 PM PDT 24
Finished Jun 24 05:36:31 PM PDT 24
Peak memory 199208 kb
Host smart-3a55661b-2cec-40af-a865-ec64cde283e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948698504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2948698504
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.hmac_test_sha512_vectors.749538807
Short name T169
Test name
Test status
Simulation time 114951475332 ps
CPU time 1973.95 seconds
Started Jun 24 06:17:26 PM PDT 24
Finished Jun 24 06:50:22 PM PDT 24
Peak memory 215816 kb
Host smart-40671ef2-de92-42b0-acb2-7b516fdeecfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=749538807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha512_vectors.749538807
Directory /workspace/13.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.2493187395
Short name T250
Test name
Test status
Simulation time 627847110 ps
CPU time 30.56 seconds
Started Jun 24 06:17:51 PM PDT 24
Finished Jun 24 06:18:23 PM PDT 24
Peak memory 200056 kb
Host smart-c2e1029e-f6ee-4241-8c91-6d5d2a18e313
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2493187395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2493187395
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.273725494
Short name T757
Test name
Test status
Simulation time 836452084 ps
CPU time 3.38 seconds
Started Jun 24 05:36:30 PM PDT 24
Finished Jun 24 05:36:35 PM PDT 24
Peak memory 199356 kb
Host smart-20e33097-038c-4105-935e-1b67d039186a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273725494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.273725494
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3401455230
Short name T761
Test name
Test status
Simulation time 615621353 ps
CPU time 14.18 seconds
Started Jun 24 05:36:33 PM PDT 24
Finished Jun 24 05:36:50 PM PDT 24
Peak memory 198592 kb
Host smart-f199afee-8f22-4efb-a122-aeea0c4ed6f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401455230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3401455230
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1819198610
Short name T98
Test name
Test status
Simulation time 26170121 ps
CPU time 0.85 seconds
Started Jun 24 05:36:20 PM PDT 24
Finished Jun 24 05:36:23 PM PDT 24
Peak memory 198724 kb
Host smart-3f0bf110-cb44-4559-bf82-5153e9977220
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819198610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1819198610
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1365706442
Short name T45
Test name
Test status
Simulation time 228629356 ps
CPU time 1.64 seconds
Started Jun 24 05:36:20 PM PDT 24
Finished Jun 24 05:36:23 PM PDT 24
Peak memory 199876 kb
Host smart-c3ac8b8f-eaca-46d6-ab36-fb8fe565a7f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365706442 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1365706442
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.639330024
Short name T697
Test name
Test status
Simulation time 28003760 ps
CPU time 0.79 seconds
Started Jun 24 05:36:14 PM PDT 24
Finished Jun 24 05:36:15 PM PDT 24
Peak memory 198768 kb
Host smart-6c54d87a-6044-4f37-848f-84aafb90bd5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639330024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.639330024
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3052761501
Short name T670
Test name
Test status
Simulation time 14406964 ps
CPU time 0.64 seconds
Started Jun 24 05:36:13 PM PDT 24
Finished Jun 24 05:36:15 PM PDT 24
Peak memory 194412 kb
Host smart-450f556a-31bc-4625-a050-d234e9635112
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052761501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3052761501
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.347267538
Short name T691
Test name
Test status
Simulation time 212707822 ps
CPU time 1.15 seconds
Started Jun 24 05:36:32 PM PDT 24
Finished Jun 24 05:36:36 PM PDT 24
Peak memory 199580 kb
Host smart-593af1ba-c0a2-4899-93c7-918bb860168a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347267538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.347267538
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2774518636
Short name T747
Test name
Test status
Simulation time 99207194 ps
CPU time 1.55 seconds
Started Jun 24 05:36:27 PM PDT 24
Finished Jun 24 05:36:31 PM PDT 24
Peak memory 199564 kb
Host smart-8e599e5c-4460-4873-ba59-d2cae72ad1fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774518636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2774518636
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.66495332
Short name T47
Test name
Test status
Simulation time 212234573 ps
CPU time 1.88 seconds
Started Jun 24 05:36:19 PM PDT 24
Finished Jun 24 05:36:22 PM PDT 24
Peak memory 199596 kb
Host smart-8dfd848c-3b3e-406d-9b5f-ba54794cd7ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66495332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.66495332
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3962937882
Short name T759
Test name
Test status
Simulation time 831766737 ps
CPU time 6.08 seconds
Started Jun 24 05:36:24 PM PDT 24
Finished Jun 24 05:36:33 PM PDT 24
Peak memory 199600 kb
Host smart-d96f0317-0abd-4054-b4d0-f8b1c0e0f28e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962937882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3962937882
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1277140180
Short name T720
Test name
Test status
Simulation time 895672268 ps
CPU time 9.51 seconds
Started Jun 24 05:36:24 PM PDT 24
Finished Jun 24 05:36:36 PM PDT 24
Peak memory 199548 kb
Host smart-c6963524-b03e-45f4-9465-abc776e9682c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277140180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1277140180
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1924349883
Short name T73
Test name
Test status
Simulation time 23109555 ps
CPU time 0.79 seconds
Started Jun 24 05:36:21 PM PDT 24
Finished Jun 24 05:36:24 PM PDT 24
Peak memory 197872 kb
Host smart-e8cd80e2-eaf9-4615-9569-9e62da8babd1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924349883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1924349883
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.4235473782
Short name T746
Test name
Test status
Simulation time 203776562 ps
CPU time 3.49 seconds
Started Jun 24 05:36:25 PM PDT 24
Finished Jun 24 05:36:31 PM PDT 24
Peak memory 207868 kb
Host smart-35809782-8080-487e-ae0f-9d7fcf5dc416
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235473782 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.4235473782
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1693553654
Short name T767
Test name
Test status
Simulation time 112863848 ps
CPU time 0.97 seconds
Started Jun 24 05:36:25 PM PDT 24
Finished Jun 24 05:36:29 PM PDT 24
Peak memory 199256 kb
Host smart-c0f3d611-dd5a-4637-8a2f-6ad77ef73bff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693553654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1693553654
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1158896396
Short name T674
Test name
Test status
Simulation time 37612111 ps
CPU time 0.6 seconds
Started Jun 24 05:36:31 PM PDT 24
Finished Jun 24 05:36:34 PM PDT 24
Peak memory 194404 kb
Host smart-faf26b82-2ffa-4c2c-a14a-c89b6470b3a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158896396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1158896396
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.929832628
Short name T765
Test name
Test status
Simulation time 46275672 ps
CPU time 2.13 seconds
Started Jun 24 05:36:26 PM PDT 24
Finished Jun 24 05:36:31 PM PDT 24
Peak memory 199532 kb
Host smart-a1163b2b-a3af-43a8-a3b7-663eeb98353b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929832628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.929832628
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2367106054
Short name T751
Test name
Test status
Simulation time 990680058 ps
CPU time 1.87 seconds
Started Jun 24 05:36:33 PM PDT 24
Finished Jun 24 05:36:38 PM PDT 24
Peak memory 199572 kb
Host smart-33c089a0-1c4d-4eaf-ac59-e67e5ddd6c6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367106054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2367106054
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.4181696354
Short name T744
Test name
Test status
Simulation time 155532396 ps
CPU time 3.19 seconds
Started Jun 24 05:36:30 PM PDT 24
Finished Jun 24 05:36:35 PM PDT 24
Peak memory 199624 kb
Host smart-45ebb907-eaff-45dd-befb-e09954792237
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181696354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.4181696354
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2677068446
Short name T696
Test name
Test status
Simulation time 24713589 ps
CPU time 1.58 seconds
Started Jun 24 05:36:31 PM PDT 24
Finished Jun 24 05:36:35 PM PDT 24
Peak memory 199692 kb
Host smart-0e0031e1-869d-4a5c-9b9a-00a578df9b0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677068446 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2677068446
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.217256731
Short name T97
Test name
Test status
Simulation time 32817362 ps
CPU time 0.95 seconds
Started Jun 24 05:36:33 PM PDT 24
Finished Jun 24 05:36:38 PM PDT 24
Peak memory 199408 kb
Host smart-a23237f8-9e15-4267-862d-683c96de03a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217256731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.217256731
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2104663920
Short name T706
Test name
Test status
Simulation time 16844154 ps
CPU time 0.62 seconds
Started Jun 24 05:36:32 PM PDT 24
Finished Jun 24 05:36:36 PM PDT 24
Peak memory 194424 kb
Host smart-d8bebeda-c8ee-45a4-a211-3ad24a8c7906
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104663920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2104663920
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.83145604
Short name T712
Test name
Test status
Simulation time 888229434 ps
CPU time 2.58 seconds
Started Jun 24 05:36:32 PM PDT 24
Finished Jun 24 05:36:37 PM PDT 24
Peak memory 199584 kb
Host smart-16b38289-0942-4afc-93de-eb766bb75411
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83145604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.83145604
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.4226327213
Short name T163
Test name
Test status
Simulation time 51486046 ps
CPU time 1.74 seconds
Started Jun 24 05:36:33 PM PDT 24
Finished Jun 24 05:36:38 PM PDT 24
Peak memory 199608 kb
Host smart-f507747a-3d62-41c2-8dbf-17b7be2950f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226327213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.4226327213
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1195658992
Short name T721
Test name
Test status
Simulation time 87419233077 ps
CPU time 97.93 seconds
Started Jun 24 05:36:33 PM PDT 24
Finished Jun 24 05:38:15 PM PDT 24
Peak memory 216108 kb
Host smart-bb996f4d-fc48-4db8-b311-582e96d62f3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195658992 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1195658992
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2891635999
Short name T738
Test name
Test status
Simulation time 59397906 ps
CPU time 0.61 seconds
Started Jun 24 05:36:22 PM PDT 24
Finished Jun 24 05:36:25 PM PDT 24
Peak memory 194448 kb
Host smart-ceaa3f27-4dcd-4911-88ec-54c4e54a2257
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891635999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2891635999
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.156328099
Short name T714
Test name
Test status
Simulation time 370270477 ps
CPU time 1.8 seconds
Started Jun 24 05:36:27 PM PDT 24
Finished Jun 24 05:36:31 PM PDT 24
Peak memory 199424 kb
Host smart-0be9dde2-159d-4b42-b218-8c6b2cc3e317
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156328099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.156328099
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2471365314
Short name T708
Test name
Test status
Simulation time 718598869 ps
CPU time 3.92 seconds
Started Jun 24 05:36:28 PM PDT 24
Finished Jun 24 05:36:34 PM PDT 24
Peak memory 199624 kb
Host smart-273475a9-d422-4096-9186-72021d4dea9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471365314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2471365314
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3533448172
Short name T752
Test name
Test status
Simulation time 568319626 ps
CPU time 1.71 seconds
Started Jun 24 05:36:33 PM PDT 24
Finished Jun 24 05:36:39 PM PDT 24
Peak memory 199624 kb
Host smart-d200b486-813e-4934-86b9-1e12df60f8d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533448172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3533448172
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3306878877
Short name T701
Test name
Test status
Simulation time 53619339970 ps
CPU time 762.99 seconds
Started Jun 24 05:36:31 PM PDT 24
Finished Jun 24 05:49:17 PM PDT 24
Peak memory 215996 kb
Host smart-827334c5-4dce-4dd3-82e8-e262031aa17c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306878877 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3306878877
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2311094158
Short name T686
Test name
Test status
Simulation time 26243268 ps
CPU time 0.85 seconds
Started Jun 24 05:36:27 PM PDT 24
Finished Jun 24 05:36:31 PM PDT 24
Peak memory 198724 kb
Host smart-20b97767-45cf-4cb1-ae86-a88ed4c31fd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311094158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2311094158
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.772700297
Short name T742
Test name
Test status
Simulation time 119864850 ps
CPU time 0.63 seconds
Started Jun 24 05:36:35 PM PDT 24
Finished Jun 24 05:36:41 PM PDT 24
Peak memory 194508 kb
Host smart-9242eacf-312a-4900-85d8-2ca90798a7fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772700297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.772700297
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3818910659
Short name T687
Test name
Test status
Simulation time 24708600 ps
CPU time 1.06 seconds
Started Jun 24 05:36:35 PM PDT 24
Finished Jun 24 05:36:41 PM PDT 24
Peak memory 199448 kb
Host smart-12cad848-52a5-46c3-93be-50893170081d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818910659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3818910659
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1676249896
Short name T693
Test name
Test status
Simulation time 232396985 ps
CPU time 1.49 seconds
Started Jun 24 05:36:34 PM PDT 24
Finished Jun 24 05:36:39 PM PDT 24
Peak memory 199576 kb
Host smart-94277a49-6e23-40b4-9f81-3f5d707b0a63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676249896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1676249896
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.865565153
Short name T62
Test name
Test status
Simulation time 309351129 ps
CPU time 2.37 seconds
Started Jun 24 05:36:20 PM PDT 24
Finished Jun 24 05:36:24 PM PDT 24
Peak memory 215048 kb
Host smart-bf3dc1e5-2bb7-41e5-acd1-c679e5dc4612
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865565153 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.865565153
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2711283685
Short name T109
Test name
Test status
Simulation time 28352977 ps
CPU time 0.71 seconds
Started Jun 24 05:36:36 PM PDT 24
Finished Jun 24 05:36:41 PM PDT 24
Peak memory 197348 kb
Host smart-dc646f79-28ea-4667-9a32-5a14bd04ad96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711283685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2711283685
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1657553232
Short name T677
Test name
Test status
Simulation time 35474118 ps
CPU time 0.59 seconds
Started Jun 24 05:36:35 PM PDT 24
Finished Jun 24 05:36:40 PM PDT 24
Peak memory 194464 kb
Host smart-10653c0e-b6f6-4528-a5c7-a150aa285ec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657553232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1657553232
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.945514458
Short name T116
Test name
Test status
Simulation time 90074437 ps
CPU time 1.24 seconds
Started Jun 24 05:36:36 PM PDT 24
Finished Jun 24 05:36:42 PM PDT 24
Peak memory 199356 kb
Host smart-b4575f34-02c2-4a23-92eb-3773b3215816
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945514458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr
_outstanding.945514458
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.253957450
Short name T719
Test name
Test status
Simulation time 269097381 ps
CPU time 2.73 seconds
Started Jun 24 05:36:30 PM PDT 24
Finished Jun 24 05:36:43 PM PDT 24
Peak memory 199588 kb
Host smart-f4bda3af-a169-4f6d-810b-dc4ef2ee3dee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253957450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.253957450
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.18647848
Short name T772
Test name
Test status
Simulation time 82366139 ps
CPU time 1.78 seconds
Started Jun 24 05:36:35 PM PDT 24
Finished Jun 24 05:36:42 PM PDT 24
Peak memory 199592 kb
Host smart-2c9659f5-186a-4565-bb92-0d02648206db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18647848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.18647848
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2189949902
Short name T88
Test name
Test status
Simulation time 77533437 ps
CPU time 2.34 seconds
Started Jun 24 05:36:39 PM PDT 24
Finished Jun 24 05:36:45 PM PDT 24
Peak memory 199620 kb
Host smart-4646e1ca-d151-4d31-b827-38f729735734
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189949902 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2189949902
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.4198331410
Short name T106
Test name
Test status
Simulation time 44625734 ps
CPU time 0.85 seconds
Started Jun 24 05:36:23 PM PDT 24
Finished Jun 24 05:36:27 PM PDT 24
Peak memory 199184 kb
Host smart-e50b1c84-4b74-480f-93f8-387413e18020
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198331410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.4198331410
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1101891898
Short name T756
Test name
Test status
Simulation time 12728656 ps
CPU time 0.63 seconds
Started Jun 24 05:36:30 PM PDT 24
Finished Jun 24 05:36:33 PM PDT 24
Peak memory 194428 kb
Host smart-be6a6cdc-f5c0-4c2c-a1f8-67b22b2d9326
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101891898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1101891898
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2899655213
Short name T672
Test name
Test status
Simulation time 237978798 ps
CPU time 1.21 seconds
Started Jun 24 05:36:36 PM PDT 24
Finished Jun 24 05:36:42 PM PDT 24
Peak memory 199360 kb
Host smart-1cfb16be-4f9f-45a6-9bd9-3ffe459b3381
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899655213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2899655213
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3139028095
Short name T707
Test name
Test status
Simulation time 694436764 ps
CPU time 3.92 seconds
Started Jun 24 05:36:39 PM PDT 24
Finished Jun 24 05:36:48 PM PDT 24
Peak memory 199664 kb
Host smart-bf6cac3e-8447-4037-a732-630c03d62be8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139028095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3139028095
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.726621086
Short name T64
Test name
Test status
Simulation time 105719886 ps
CPU time 1.8 seconds
Started Jun 24 05:36:28 PM PDT 24
Finished Jun 24 05:36:32 PM PDT 24
Peak memory 199620 kb
Host smart-8680225b-0807-4b69-9e58-bcce374fd3b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726621086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.726621086
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.879533195
Short name T678
Test name
Test status
Simulation time 102428801 ps
CPU time 2.31 seconds
Started Jun 24 05:36:35 PM PDT 24
Finished Jun 24 05:36:42 PM PDT 24
Peak memory 199640 kb
Host smart-08955efd-3c75-4bc5-8082-f290e75eebe2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879533195 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.879533195
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.477300016
Short name T100
Test name
Test status
Simulation time 42950069 ps
CPU time 0.69 seconds
Started Jun 24 05:36:30 PM PDT 24
Finished Jun 24 05:36:33 PM PDT 24
Peak memory 197312 kb
Host smart-c7867e75-624b-4526-9485-f801dd63d3a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477300016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.477300016
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.4286237240
Short name T75
Test name
Test status
Simulation time 32440202 ps
CPU time 0.61 seconds
Started Jun 24 05:36:36 PM PDT 24
Finished Jun 24 05:36:45 PM PDT 24
Peak memory 194404 kb
Host smart-0ff7a763-5e6a-40a4-bb5a-39e389127997
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286237240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.4286237240
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2000339458
Short name T113
Test name
Test status
Simulation time 49200217 ps
CPU time 1.26 seconds
Started Jun 24 05:36:39 PM PDT 24
Finished Jun 24 05:36:45 PM PDT 24
Peak memory 199352 kb
Host smart-f80e47fa-ad6f-47ab-b635-b2998d36232f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000339458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2000339458
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3429726447
Short name T774
Test name
Test status
Simulation time 214623314 ps
CPU time 3 seconds
Started Jun 24 05:36:32 PM PDT 24
Finished Jun 24 05:36:38 PM PDT 24
Peak memory 199676 kb
Host smart-96dca372-f41d-453f-b53f-e30cb25c47b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429726447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3429726447
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2240974189
Short name T160
Test name
Test status
Simulation time 331278160 ps
CPU time 1.89 seconds
Started Jun 24 05:36:27 PM PDT 24
Finished Jun 24 05:36:31 PM PDT 24
Peak memory 199604 kb
Host smart-8e5a22b0-0b27-4303-96df-ad7e8c76f669
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240974189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2240974189
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.174259500
Short name T724
Test name
Test status
Simulation time 61572146 ps
CPU time 1.24 seconds
Started Jun 24 05:36:35 PM PDT 24
Finished Jun 24 05:36:40 PM PDT 24
Peak memory 199484 kb
Host smart-39646cbe-dcdf-4dd8-8c43-5e91c210f86f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174259500 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.174259500
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2612732836
Short name T101
Test name
Test status
Simulation time 78537194 ps
CPU time 0.83 seconds
Started Jun 24 05:36:38 PM PDT 24
Finished Jun 24 05:36:44 PM PDT 24
Peak memory 199192 kb
Host smart-5df30f24-cf6a-4085-ab1d-9e638913bcad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612732836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2612732836
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.4024857792
Short name T716
Test name
Test status
Simulation time 21059276 ps
CPU time 0.61 seconds
Started Jun 24 05:36:36 PM PDT 24
Finished Jun 24 05:36:42 PM PDT 24
Peak memory 194328 kb
Host smart-3b7db542-f2ef-41aa-80aa-1c3afe9b3548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024857792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.4024857792
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3954218563
Short name T689
Test name
Test status
Simulation time 425217981 ps
CPU time 1.81 seconds
Started Jun 24 05:36:53 PM PDT 24
Finished Jun 24 05:36:56 PM PDT 24
Peak memory 199392 kb
Host smart-bea66ac6-4a65-4d5a-b532-af5ad9bcad03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954218563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3954218563
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3837453685
Short name T771
Test name
Test status
Simulation time 79646471 ps
CPU time 1.77 seconds
Started Jun 24 05:36:40 PM PDT 24
Finished Jun 24 05:36:46 PM PDT 24
Peak memory 199808 kb
Host smart-9751b78b-3ac0-4049-b770-c7de0e68e369
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837453685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3837453685
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1375997959
Short name T695
Test name
Test status
Simulation time 64731193335 ps
CPU time 230.58 seconds
Started Jun 24 05:36:45 PM PDT 24
Finished Jun 24 05:40:37 PM PDT 24
Peak memory 215160 kb
Host smart-395239a6-009a-422b-bb0d-bc4a6c0208da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375997959 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1375997959
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.802439863
Short name T99
Test name
Test status
Simulation time 45256419 ps
CPU time 0.82 seconds
Started Jun 24 05:36:33 PM PDT 24
Finished Jun 24 05:36:37 PM PDT 24
Peak memory 199428 kb
Host smart-26c32ddf-b2ed-4500-b7e1-ab6c4dda0ea1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802439863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.802439863
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3967678997
Short name T74
Test name
Test status
Simulation time 51885067 ps
CPU time 0.59 seconds
Started Jun 24 05:36:34 PM PDT 24
Finished Jun 24 05:36:39 PM PDT 24
Peak memory 194424 kb
Host smart-af53c97b-783c-4eae-b1d4-d60f942cbabf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967678997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3967678997
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4064401511
Short name T736
Test name
Test status
Simulation time 268145646 ps
CPU time 2.04 seconds
Started Jun 24 05:36:33 PM PDT 24
Finished Jun 24 05:36:39 PM PDT 24
Peak memory 199612 kb
Host smart-8ae38f93-f1d7-46df-9588-8428b503c8cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064401511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.4064401511
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2121662113
Short name T725
Test name
Test status
Simulation time 147754095 ps
CPU time 3.22 seconds
Started Jun 24 05:36:34 PM PDT 24
Finished Jun 24 05:36:42 PM PDT 24
Peak memory 199612 kb
Host smart-bcc520c9-9011-4e11-8210-445fd1cb7669
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121662113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2121662113
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3331547091
Short name T91
Test name
Test status
Simulation time 299845498 ps
CPU time 3.06 seconds
Started Jun 24 05:36:34 PM PDT 24
Finished Jun 24 05:36:41 PM PDT 24
Peak memory 199676 kb
Host smart-74b88082-4d1f-4e7c-ab1d-27e834d85d96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331547091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3331547091
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.947385509
Short name T68
Test name
Test status
Simulation time 115674281 ps
CPU time 2.43 seconds
Started Jun 24 05:36:58 PM PDT 24
Finished Jun 24 05:37:02 PM PDT 24
Peak memory 199664 kb
Host smart-03ca9e6f-615b-4cc1-962b-cd694d00e1b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947385509 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.947385509
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1789805755
Short name T115
Test name
Test status
Simulation time 89380766 ps
CPU time 0.83 seconds
Started Jun 24 05:36:35 PM PDT 24
Finished Jun 24 05:36:40 PM PDT 24
Peak memory 199056 kb
Host smart-f5d777d9-5319-458b-8d14-a1adf41cf9ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789805755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1789805755
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2779030791
Short name T664
Test name
Test status
Simulation time 16682866 ps
CPU time 0.58 seconds
Started Jun 24 05:36:50 PM PDT 24
Finished Jun 24 05:36:58 PM PDT 24
Peak memory 194364 kb
Host smart-4cf17505-f2f9-4c8e-a81d-4aecc7156939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779030791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2779030791
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3202443374
Short name T750
Test name
Test status
Simulation time 166744485 ps
CPU time 1.1 seconds
Started Jun 24 05:36:33 PM PDT 24
Finished Jun 24 05:36:38 PM PDT 24
Peak memory 197988 kb
Host smart-840c4064-7a39-4fce-8c08-b9b3e629beaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202443374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3202443374
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2073532727
Short name T65
Test name
Test status
Simulation time 111243150 ps
CPU time 1.53 seconds
Started Jun 24 05:36:35 PM PDT 24
Finished Jun 24 05:36:41 PM PDT 24
Peak memory 199580 kb
Host smart-640f8832-2770-43a1-93b8-2ac5f42be47c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073532727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2073532727
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.28040248
Short name T157
Test name
Test status
Simulation time 256574236 ps
CPU time 4.07 seconds
Started Jun 24 05:36:35 PM PDT 24
Finished Jun 24 05:36:43 PM PDT 24
Peak memory 199628 kb
Host smart-692cc9d2-d37b-4e2f-8526-4075d0a80d48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28040248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.28040248
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.4140268518
Short name T111
Test name
Test status
Simulation time 31964563 ps
CPU time 0.91 seconds
Started Jun 24 05:36:41 PM PDT 24
Finished Jun 24 05:36:46 PM PDT 24
Peak memory 199100 kb
Host smart-d76efab6-f80c-4404-b460-2a62f010499b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140268518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.4140268518
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.659130963
Short name T753
Test name
Test status
Simulation time 28322374 ps
CPU time 0.62 seconds
Started Jun 24 05:36:33 PM PDT 24
Finished Jun 24 05:36:37 PM PDT 24
Peak memory 194416 kb
Host smart-f68a376b-92af-43b2-8a39-810c9cb711fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659130963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.659130963
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.805006700
Short name T770
Test name
Test status
Simulation time 308359318 ps
CPU time 1.76 seconds
Started Jun 24 05:36:44 PM PDT 24
Finished Jun 24 05:36:48 PM PDT 24
Peak memory 199664 kb
Host smart-1ebbb603-7f4a-445e-a1db-91f32d74ce84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805006700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.805006700
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1085488699
Short name T737
Test name
Test status
Simulation time 709059840 ps
CPU time 3.89 seconds
Started Jun 24 05:36:37 PM PDT 24
Finished Jun 24 05:36:46 PM PDT 24
Peak memory 199528 kb
Host smart-649d96ed-7ea1-4758-a458-0fc752e9230a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085488699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1085488699
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3750262760
Short name T46
Test name
Test status
Simulation time 165002911 ps
CPU time 3.08 seconds
Started Jun 24 05:36:41 PM PDT 24
Finished Jun 24 05:36:48 PM PDT 24
Peak memory 199672 kb
Host smart-0f8fd276-cffb-4e7a-86da-b9345b925e57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750262760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3750262760
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.717499269
Short name T103
Test name
Test status
Simulation time 153889376 ps
CPU time 8.08 seconds
Started Jun 24 05:36:31 PM PDT 24
Finished Jun 24 05:36:42 PM PDT 24
Peak memory 199528 kb
Host smart-c045a3a2-9319-4cb9-bb4b-b6a6c897d694
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717499269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.717499269
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3015460634
Short name T108
Test name
Test status
Simulation time 5693615779 ps
CPU time 15.16 seconds
Started Jun 24 05:36:29 PM PDT 24
Finished Jun 24 05:36:46 PM PDT 24
Peak memory 199016 kb
Host smart-b4ff2c14-a290-469a-893f-4ebb40c69b5d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015460634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3015460634
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3231184627
Short name T715
Test name
Test status
Simulation time 84795277 ps
CPU time 0.72 seconds
Started Jun 24 05:36:35 PM PDT 24
Finished Jun 24 05:36:40 PM PDT 24
Peak memory 197620 kb
Host smart-fe8e1688-03ba-4aee-9db6-22e597f85fdd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231184627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3231184627
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.240732197
Short name T718
Test name
Test status
Simulation time 37195034 ps
CPU time 2.42 seconds
Started Jun 24 05:36:25 PM PDT 24
Finished Jun 24 05:36:31 PM PDT 24
Peak memory 199660 kb
Host smart-9963855a-4fdf-4042-ae98-4960483384f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240732197 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.240732197
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1996565848
Short name T754
Test name
Test status
Simulation time 64135186 ps
CPU time 0.96 seconds
Started Jun 24 05:36:19 PM PDT 24
Finished Jun 24 05:36:21 PM PDT 24
Peak memory 199416 kb
Host smart-799a1358-3884-48bf-a88d-2db808270cbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996565848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1996565848
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.1136168825
Short name T668
Test name
Test status
Simulation time 46375818 ps
CPU time 0.58 seconds
Started Jun 24 05:36:21 PM PDT 24
Finished Jun 24 05:36:24 PM PDT 24
Peak memory 194516 kb
Host smart-90db5ce3-10d9-4659-b211-c7c01cf7e368
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136168825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1136168825
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.72725315
Short name T77
Test name
Test status
Simulation time 602503648 ps
CPU time 2.3 seconds
Started Jun 24 05:36:31 PM PDT 24
Finished Jun 24 05:36:36 PM PDT 24
Peak memory 199532 kb
Host smart-1c8a91d6-f1e6-4290-be53-b066e748eb92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72725315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_o
utstanding.72725315
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1607146492
Short name T63
Test name
Test status
Simulation time 276697008 ps
CPU time 3.76 seconds
Started Jun 24 05:36:21 PM PDT 24
Finished Jun 24 05:36:27 PM PDT 24
Peak memory 199828 kb
Host smart-58bc9ee2-17bc-421f-835f-74fa5f964711
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607146492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1607146492
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3423066160
Short name T161
Test name
Test status
Simulation time 709847302 ps
CPU time 3.17 seconds
Started Jun 24 05:36:20 PM PDT 24
Finished Jun 24 05:36:25 PM PDT 24
Peak memory 199592 kb
Host smart-2d84961e-fe40-4ad6-966f-053fd4208cec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423066160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3423066160
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2946994641
Short name T729
Test name
Test status
Simulation time 16816367 ps
CPU time 0.69 seconds
Started Jun 24 05:36:32 PM PDT 24
Finished Jun 24 05:36:35 PM PDT 24
Peak memory 194736 kb
Host smart-5e2ede94-5a8f-4313-ad52-4a8ec857efe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946994641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2946994641
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.827911176
Short name T709
Test name
Test status
Simulation time 12726291 ps
CPU time 0.64 seconds
Started Jun 24 05:36:34 PM PDT 24
Finished Jun 24 05:36:39 PM PDT 24
Peak memory 194476 kb
Host smart-f67effaa-dde2-4cc8-af27-2c11eb5eca88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827911176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.827911176
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.367876475
Short name T739
Test name
Test status
Simulation time 30186153 ps
CPU time 0.59 seconds
Started Jun 24 05:36:35 PM PDT 24
Finished Jun 24 05:36:40 PM PDT 24
Peak memory 194424 kb
Host smart-b54fc6d5-bfb7-4b5f-ade1-5d8ca94a2234
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367876475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.367876475
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1301861399
Short name T732
Test name
Test status
Simulation time 18925480 ps
CPU time 0.67 seconds
Started Jun 24 05:36:34 PM PDT 24
Finished Jun 24 05:36:39 PM PDT 24
Peak memory 194356 kb
Host smart-4e76a65a-76ac-4b9a-b840-c21e8eea3c01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301861399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1301861399
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2568468283
Short name T741
Test name
Test status
Simulation time 36076961 ps
CPU time 0.58 seconds
Started Jun 24 05:36:51 PM PDT 24
Finished Jun 24 05:36:53 PM PDT 24
Peak memory 194444 kb
Host smart-e90a0e09-ff33-4102-996f-239a6e29c661
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568468283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2568468283
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2166406078
Short name T682
Test name
Test status
Simulation time 22163149 ps
CPU time 0.67 seconds
Started Jun 24 05:36:33 PM PDT 24
Finished Jun 24 05:36:37 PM PDT 24
Peak memory 194528 kb
Host smart-e73fab33-38ce-4c2e-a0e1-0d51405d3cd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166406078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2166406078
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.181201405
Short name T710
Test name
Test status
Simulation time 57856843 ps
CPU time 0.63 seconds
Started Jun 24 05:36:38 PM PDT 24
Finished Jun 24 05:36:44 PM PDT 24
Peak memory 194404 kb
Host smart-0a1778d0-8249-413d-b93c-d95b3f589756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181201405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.181201405
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3755298423
Short name T703
Test name
Test status
Simulation time 23202277 ps
CPU time 0.63 seconds
Started Jun 24 05:36:41 PM PDT 24
Finished Jun 24 05:36:45 PM PDT 24
Peak memory 194432 kb
Host smart-b68471f1-7c50-4ff2-b1f2-633424ad54bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755298423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3755298423
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1260299797
Short name T713
Test name
Test status
Simulation time 11337767 ps
CPU time 0.61 seconds
Started Jun 24 05:36:36 PM PDT 24
Finished Jun 24 05:36:41 PM PDT 24
Peak memory 194444 kb
Host smart-2e21b249-3004-4357-8499-2fca4ac01046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260299797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1260299797
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1778670045
Short name T773
Test name
Test status
Simulation time 171509085 ps
CPU time 0.62 seconds
Started Jun 24 05:36:36 PM PDT 24
Finished Jun 24 05:36:42 PM PDT 24
Peak memory 194432 kb
Host smart-5df45c6f-b10b-4f8e-8778-91be04ac5214
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778670045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1778670045
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1478521788
Short name T110
Test name
Test status
Simulation time 164121787 ps
CPU time 8.12 seconds
Started Jun 24 05:36:20 PM PDT 24
Finished Jun 24 05:36:30 PM PDT 24
Peak memory 199612 kb
Host smart-d5219f61-1af2-4cad-af8e-23eb9ca083c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478521788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1478521788
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3110929324
Short name T723
Test name
Test status
Simulation time 734898491 ps
CPU time 5.59 seconds
Started Jun 24 05:36:21 PM PDT 24
Finished Jun 24 05:36:29 PM PDT 24
Peak memory 199556 kb
Host smart-5e847f71-d3de-4bb6-9080-4bda64431231
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110929324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3110929324
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.738841388
Short name T669
Test name
Test status
Simulation time 13952736 ps
CPU time 0.74 seconds
Started Jun 24 05:36:27 PM PDT 24
Finished Jun 24 05:36:30 PM PDT 24
Peak memory 197784 kb
Host smart-245b033c-bb66-4b97-817b-0ae05b9ee0cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738841388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.738841388
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.4019241982
Short name T688
Test name
Test status
Simulation time 29192435 ps
CPU time 1.67 seconds
Started Jun 24 05:36:18 PM PDT 24
Finished Jun 24 05:36:21 PM PDT 24
Peak memory 199668 kb
Host smart-30e5c20f-d0aa-4fa8-b368-eb49bfedcfc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019241982 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.4019241982
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1647351642
Short name T766
Test name
Test status
Simulation time 286499261 ps
CPU time 1.01 seconds
Started Jun 24 05:36:24 PM PDT 24
Finished Jun 24 05:36:28 PM PDT 24
Peak memory 199092 kb
Host smart-8ca7a830-09bd-4377-bceb-33e0b4aec773
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647351642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1647351642
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1214150527
Short name T692
Test name
Test status
Simulation time 16659441 ps
CPU time 0.63 seconds
Started Jun 24 05:36:20 PM PDT 24
Finished Jun 24 05:36:22 PM PDT 24
Peak memory 194444 kb
Host smart-2e4deaff-6170-4db1-af34-63e019da6544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214150527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1214150527
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.137613599
Short name T114
Test name
Test status
Simulation time 185130291 ps
CPU time 2.07 seconds
Started Jun 24 05:36:25 PM PDT 24
Finished Jun 24 05:36:30 PM PDT 24
Peak memory 199696 kb
Host smart-bafa483a-7667-4de1-8845-3d15b127c57d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137613599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.137613599
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.813321708
Short name T769
Test name
Test status
Simulation time 85260723 ps
CPU time 2.49 seconds
Started Jun 24 05:36:19 PM PDT 24
Finished Jun 24 05:36:23 PM PDT 24
Peak memory 199620 kb
Host smart-db056c77-fced-467c-a58a-559f90aa6ef5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813321708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.813321708
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2681244613
Short name T760
Test name
Test status
Simulation time 236714531 ps
CPU time 3.92 seconds
Started Jun 24 05:36:33 PM PDT 24
Finished Jun 24 05:36:40 PM PDT 24
Peak memory 199660 kb
Host smart-b4a0957f-6fac-4c98-9e0c-c51d5dadc783
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681244613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2681244613
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1923215446
Short name T711
Test name
Test status
Simulation time 10696380 ps
CPU time 0.58 seconds
Started Jun 24 05:36:34 PM PDT 24
Finished Jun 24 05:36:39 PM PDT 24
Peak memory 194464 kb
Host smart-e2be80d1-f274-4907-a2cb-21c77c897b7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923215446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1923215446
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2610672993
Short name T704
Test name
Test status
Simulation time 12954827 ps
CPU time 0.62 seconds
Started Jun 24 05:36:51 PM PDT 24
Finished Jun 24 05:36:53 PM PDT 24
Peak memory 194424 kb
Host smart-b277bf93-2662-4850-a91a-53c433fc1952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610672993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2610672993
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3565638302
Short name T717
Test name
Test status
Simulation time 208695435 ps
CPU time 0.59 seconds
Started Jun 24 05:36:38 PM PDT 24
Finished Jun 24 05:36:43 PM PDT 24
Peak memory 194388 kb
Host smart-696fc942-3928-4c0e-b951-e60a15353044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565638302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3565638302
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1692329168
Short name T681
Test name
Test status
Simulation time 13468744 ps
CPU time 0.61 seconds
Started Jun 24 05:36:47 PM PDT 24
Finished Jun 24 05:36:48 PM PDT 24
Peak memory 194416 kb
Host smart-7f7c3250-b843-4f78-bec4-6242440f9b79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692329168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1692329168
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2471526359
Short name T683
Test name
Test status
Simulation time 49605696 ps
CPU time 0.6 seconds
Started Jun 24 05:36:36 PM PDT 24
Finished Jun 24 05:36:41 PM PDT 24
Peak memory 194416 kb
Host smart-8eedfbde-a28d-45ae-9165-6d045b72017d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471526359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2471526359
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1401381112
Short name T694
Test name
Test status
Simulation time 18224105 ps
CPU time 0.61 seconds
Started Jun 24 05:36:52 PM PDT 24
Finished Jun 24 05:36:54 PM PDT 24
Peak memory 194416 kb
Host smart-dd7917fc-dd73-4532-8486-2ab7791bc7bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401381112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1401381112
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1535133798
Short name T728
Test name
Test status
Simulation time 14838896 ps
CPU time 0.62 seconds
Started Jun 24 05:36:35 PM PDT 24
Finished Jun 24 05:36:44 PM PDT 24
Peak memory 194428 kb
Host smart-e5b557a2-c411-4988-80e9-ceb222550b0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535133798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1535133798
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1822108682
Short name T743
Test name
Test status
Simulation time 13080515 ps
CPU time 0.57 seconds
Started Jun 24 05:36:36 PM PDT 24
Finished Jun 24 05:36:41 PM PDT 24
Peak memory 194352 kb
Host smart-052f6e5b-82e6-4a63-aa39-6aea9a7f632b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822108682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1822108682
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.997622353
Short name T705
Test name
Test status
Simulation time 75670729 ps
CPU time 0.62 seconds
Started Jun 24 05:36:37 PM PDT 24
Finished Jun 24 05:36:42 PM PDT 24
Peak memory 194432 kb
Host smart-d32908e5-5a0c-4e6e-80a9-37670fb1eef9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997622353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.997622353
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2147622775
Short name T702
Test name
Test status
Simulation time 166481244 ps
CPU time 3.34 seconds
Started Jun 24 05:36:24 PM PDT 24
Finished Jun 24 05:36:30 PM PDT 24
Peak memory 199524 kb
Host smart-ff880475-da7a-4a13-b689-df791e9d5abc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147622775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2147622775
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.970685066
Short name T105
Test name
Test status
Simulation time 477449194 ps
CPU time 14.7 seconds
Started Jun 24 05:36:24 PM PDT 24
Finished Jun 24 05:36:41 PM PDT 24
Peak memory 199584 kb
Host smart-3156920e-fddd-4ec8-a9cc-11ebbddf1745
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970685066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.970685066
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1832100594
Short name T667
Test name
Test status
Simulation time 37396875 ps
CPU time 1 seconds
Started Jun 24 05:36:15 PM PDT 24
Finished Jun 24 05:36:18 PM PDT 24
Peak memory 199448 kb
Host smart-e7d96d77-a87c-4ea0-9553-1ff89e7614fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832100594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1832100594
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3611620671
Short name T727
Test name
Test status
Simulation time 307875112 ps
CPU time 2.38 seconds
Started Jun 24 05:36:20 PM PDT 24
Finished Jun 24 05:36:24 PM PDT 24
Peak memory 199728 kb
Host smart-cb6a3724-87ab-46af-959e-97ea38130b4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611620671 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3611620671
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.602825059
Short name T112
Test name
Test status
Simulation time 48095603 ps
CPU time 0.85 seconds
Started Jun 24 05:36:21 PM PDT 24
Finished Jun 24 05:36:24 PM PDT 24
Peak memory 198900 kb
Host smart-f8f88afc-bd3f-4edc-a768-e576d440070f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602825059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.602825059
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2183451533
Short name T685
Test name
Test status
Simulation time 37004758 ps
CPU time 0.58 seconds
Started Jun 24 05:36:20 PM PDT 24
Finished Jun 24 05:36:22 PM PDT 24
Peak memory 194352 kb
Host smart-659dd7b6-87a0-4981-bad5-5f097d90e6d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183451533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2183451533
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1769587068
Short name T78
Test name
Test status
Simulation time 56217970 ps
CPU time 1.21 seconds
Started Jun 24 05:36:24 PM PDT 24
Finished Jun 24 05:36:28 PM PDT 24
Peak memory 199492 kb
Host smart-f8c0cddf-187b-480b-aae6-334c2a6ffe31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769587068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1769587068
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2799316417
Short name T758
Test name
Test status
Simulation time 454557635 ps
CPU time 2.36 seconds
Started Jun 24 05:36:26 PM PDT 24
Finished Jun 24 05:36:32 PM PDT 24
Peak memory 199612 kb
Host smart-4bee0013-cdd5-49b6-9ada-7bb11fb8186e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799316417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.2799316417
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1609307253
Short name T155
Test name
Test status
Simulation time 154552283 ps
CPU time 3.13 seconds
Started Jun 24 05:36:28 PM PDT 24
Finished Jun 24 05:36:33 PM PDT 24
Peak memory 199568 kb
Host smart-79bee690-1209-4691-a553-5263e4b78b34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609307253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1609307253
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3211157046
Short name T749
Test name
Test status
Simulation time 24472459 ps
CPU time 0.6 seconds
Started Jun 24 05:36:35 PM PDT 24
Finished Jun 24 05:36:41 PM PDT 24
Peak memory 194476 kb
Host smart-3905a2db-063d-43a1-947c-83feb94bcf9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211157046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3211157046
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3598518007
Short name T748
Test name
Test status
Simulation time 39708965 ps
CPU time 0.59 seconds
Started Jun 24 05:36:34 PM PDT 24
Finished Jun 24 05:36:38 PM PDT 24
Peak memory 194364 kb
Host smart-048c496f-5421-473d-9725-685fb978b95d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598518007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3598518007
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3263085474
Short name T764
Test name
Test status
Simulation time 41498992 ps
CPU time 0.6 seconds
Started Jun 24 05:36:33 PM PDT 24
Finished Jun 24 05:36:37 PM PDT 24
Peak memory 194420 kb
Host smart-f0f3b7e0-6a54-447c-bb68-e723b4be4fe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263085474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3263085474
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2283565342
Short name T673
Test name
Test status
Simulation time 70638162 ps
CPU time 0.62 seconds
Started Jun 24 05:36:42 PM PDT 24
Finished Jun 24 05:36:46 PM PDT 24
Peak memory 194420 kb
Host smart-ba32af89-9dd9-4ad6-85ca-42047f60a105
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283565342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2283565342
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2530720195
Short name T684
Test name
Test status
Simulation time 40187318 ps
CPU time 0.62 seconds
Started Jun 24 05:36:35 PM PDT 24
Finished Jun 24 05:36:40 PM PDT 24
Peak memory 194432 kb
Host smart-a953030d-2848-464c-89ee-61544e6a2b57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530720195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2530720195
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2628228299
Short name T680
Test name
Test status
Simulation time 81979819 ps
CPU time 0.61 seconds
Started Jun 24 05:36:31 PM PDT 24
Finished Jun 24 05:36:34 PM PDT 24
Peak memory 194476 kb
Host smart-7c0d150d-4894-4e94-8bc2-2e6dcaa06cd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628228299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2628228299
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1890937236
Short name T700
Test name
Test status
Simulation time 12220248 ps
CPU time 0.61 seconds
Started Jun 24 05:36:37 PM PDT 24
Finished Jun 24 05:36:42 PM PDT 24
Peak memory 194420 kb
Host smart-d442472b-040d-4f34-b2a0-83da7dee48c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890937236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1890937236
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2631820959
Short name T730
Test name
Test status
Simulation time 16578553 ps
CPU time 0.6 seconds
Started Jun 24 05:36:32 PM PDT 24
Finished Jun 24 05:36:35 PM PDT 24
Peak memory 194440 kb
Host smart-5ffd3cbb-05d4-447f-b165-395f49e49c22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631820959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2631820959
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.977215324
Short name T762
Test name
Test status
Simulation time 44242516 ps
CPU time 0.63 seconds
Started Jun 24 05:36:35 PM PDT 24
Finished Jun 24 05:36:40 PM PDT 24
Peak memory 194444 kb
Host smart-0c3db696-072b-4940-bf78-c73961e9b313
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977215324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.977215324
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.4130406828
Short name T675
Test name
Test status
Simulation time 47477846 ps
CPU time 0.63 seconds
Started Jun 24 05:36:32 PM PDT 24
Finished Jun 24 05:36:36 PM PDT 24
Peak memory 194440 kb
Host smart-c293f0a8-6961-45d2-a337-47c9c17bf9e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130406828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.4130406828
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2200304934
Short name T731
Test name
Test status
Simulation time 206396286 ps
CPU time 2.41 seconds
Started Jun 24 05:36:15 PM PDT 24
Finished Jun 24 05:36:19 PM PDT 24
Peak memory 199648 kb
Host smart-53cf7e97-1042-4142-a94a-fb200e6863a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200304934 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2200304934
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3890508524
Short name T699
Test name
Test status
Simulation time 15520381 ps
CPU time 0.77 seconds
Started Jun 24 05:36:26 PM PDT 24
Finished Jun 24 05:36:29 PM PDT 24
Peak memory 199400 kb
Host smart-ad49f7d9-4702-44ab-9607-62e02a3d3928
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890508524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3890508524
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2285224839
Short name T665
Test name
Test status
Simulation time 54405462 ps
CPU time 0.61 seconds
Started Jun 24 05:36:31 PM PDT 24
Finished Jun 24 05:36:33 PM PDT 24
Peak memory 194360 kb
Host smart-ba97ca27-d06d-47ec-addd-ef13cc0019c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285224839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2285224839
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3955468974
Short name T740
Test name
Test status
Simulation time 254890305 ps
CPU time 2.18 seconds
Started Jun 24 05:36:22 PM PDT 24
Finished Jun 24 05:36:27 PM PDT 24
Peak memory 199656 kb
Host smart-208e2acc-009d-4f62-8743-11ac5f61c766
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955468974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3955468974
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.4200000744
Short name T66
Test name
Test status
Simulation time 413253013 ps
CPU time 3.85 seconds
Started Jun 24 05:36:33 PM PDT 24
Finished Jun 24 05:36:40 PM PDT 24
Peak memory 199444 kb
Host smart-003e3d50-2113-4c3b-a854-60e810c99a02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200000744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.4200000744
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2234848208
Short name T690
Test name
Test status
Simulation time 41541838 ps
CPU time 1.31 seconds
Started Jun 24 05:36:23 PM PDT 24
Finished Jun 24 05:36:27 PM PDT 24
Peak memory 199612 kb
Host smart-83580acd-66b6-4548-aaea-f1706d2ef585
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234848208 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2234848208
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4200260450
Short name T102
Test name
Test status
Simulation time 126309100 ps
CPU time 0.69 seconds
Started Jun 24 05:36:33 PM PDT 24
Finished Jun 24 05:36:37 PM PDT 24
Peak memory 197260 kb
Host smart-004e0100-4b41-49e9-9e71-2e15a230b40c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200260450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.4200260450
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2516754889
Short name T676
Test name
Test status
Simulation time 13542442 ps
CPU time 0.61 seconds
Started Jun 24 05:36:10 PM PDT 24
Finished Jun 24 05:36:12 PM PDT 24
Peak memory 194376 kb
Host smart-3066972b-a341-435c-b096-f65103854f0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516754889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2516754889
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2676894555
Short name T76
Test name
Test status
Simulation time 51415974 ps
CPU time 1.22 seconds
Started Jun 24 05:36:32 PM PDT 24
Finished Jun 24 05:36:36 PM PDT 24
Peak memory 198204 kb
Host smart-860fa12e-e61c-4fb9-9a3d-9796a4e553f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676894555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2676894555
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3906232054
Short name T775
Test name
Test status
Simulation time 120208245 ps
CPU time 1.71 seconds
Started Jun 24 05:36:21 PM PDT 24
Finished Jun 24 05:36:25 PM PDT 24
Peak memory 199636 kb
Host smart-88a047df-95f6-46be-9e9f-eac5dca15da7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906232054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3906232054
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.9971688
Short name T92
Test name
Test status
Simulation time 347813142 ps
CPU time 2.88 seconds
Started Jun 24 05:36:35 PM PDT 24
Finished Jun 24 05:36:42 PM PDT 24
Peak memory 199620 kb
Host smart-40fe29af-625d-4d6f-ab5a-e224cdffa07a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9971688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.9971688
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.883256714
Short name T733
Test name
Test status
Simulation time 45852183 ps
CPU time 1.56 seconds
Started Jun 24 05:36:33 PM PDT 24
Finished Jun 24 05:36:38 PM PDT 24
Peak memory 199592 kb
Host smart-ddcd5608-f018-439c-b913-c83c56b56bc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883256714 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.883256714
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3298818103
Short name T722
Test name
Test status
Simulation time 81003499 ps
CPU time 0.84 seconds
Started Jun 24 05:36:25 PM PDT 24
Finished Jun 24 05:36:29 PM PDT 24
Peak memory 198832 kb
Host smart-31bbcc02-1a91-4299-be6e-fe4519c8675e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298818103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3298818103
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.511979900
Short name T666
Test name
Test status
Simulation time 38004807 ps
CPU time 0.59 seconds
Started Jun 24 05:36:24 PM PDT 24
Finished Jun 24 05:36:28 PM PDT 24
Peak memory 194332 kb
Host smart-cc8bbd67-bb96-47cc-9fd3-ecc5f7c60d15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511979900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.511979900
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2572117411
Short name T671
Test name
Test status
Simulation time 1168152190 ps
CPU time 2.3 seconds
Started Jun 24 05:36:23 PM PDT 24
Finished Jun 24 05:36:28 PM PDT 24
Peak memory 199628 kb
Host smart-32ee1d75-7aa5-4d12-990d-9bac6afe685a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572117411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2572117411
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1379430173
Short name T735
Test name
Test status
Simulation time 75486328 ps
CPU time 2.06 seconds
Started Jun 24 05:36:31 PM PDT 24
Finished Jun 24 05:36:35 PM PDT 24
Peak memory 199612 kb
Host smart-f9059baa-ff8c-4078-8175-6b3dba8c14e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379430173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1379430173
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3339982147
Short name T158
Test name
Test status
Simulation time 251915786 ps
CPU time 3.98 seconds
Started Jun 24 05:36:17 PM PDT 24
Finished Jun 24 05:36:22 PM PDT 24
Peak memory 199536 kb
Host smart-5919e8bb-bb65-4cf3-913d-935bdf4742c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339982147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3339982147
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.438099403
Short name T763
Test name
Test status
Simulation time 51481568970 ps
CPU time 506.8 seconds
Started Jun 24 05:36:29 PM PDT 24
Finished Jun 24 05:44:58 PM PDT 24
Peak memory 215420 kb
Host smart-023a820e-ce39-4635-b96e-69262a14be89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438099403 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.438099403
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1603636350
Short name T107
Test name
Test status
Simulation time 27166998 ps
CPU time 0.88 seconds
Started Jun 24 05:36:31 PM PDT 24
Finished Jun 24 05:36:35 PM PDT 24
Peak memory 199436 kb
Host smart-65e9246d-0e03-4e4b-97e6-118402b71356
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603636350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1603636350
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2218913051
Short name T726
Test name
Test status
Simulation time 252543718 ps
CPU time 0.62 seconds
Started Jun 24 05:36:30 PM PDT 24
Finished Jun 24 05:36:33 PM PDT 24
Peak memory 194456 kb
Host smart-18545e46-0d59-4b7a-b319-8ceea68589e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218913051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2218913051
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3308634629
Short name T745
Test name
Test status
Simulation time 76309009 ps
CPU time 1.14 seconds
Started Jun 24 05:36:31 PM PDT 24
Finished Jun 24 05:36:35 PM PDT 24
Peak memory 199524 kb
Host smart-8a0c6366-5a4f-426f-ab48-725888166b70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308634629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3308634629
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1176735293
Short name T72
Test name
Test status
Simulation time 209136130 ps
CPU time 3.89 seconds
Started Jun 24 05:36:40 PM PDT 24
Finished Jun 24 05:36:48 PM PDT 24
Peak memory 199604 kb
Host smart-157c7d67-966d-4a22-879e-32e6fc8dd5d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176735293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1176735293
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2347954638
Short name T734
Test name
Test status
Simulation time 385474439 ps
CPU time 1.86 seconds
Started Jun 24 05:36:30 PM PDT 24
Finished Jun 24 05:36:33 PM PDT 24
Peak memory 199588 kb
Host smart-92396343-5fda-48ad-b89c-7534e8768120
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347954638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2347954638
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.378422604
Short name T89
Test name
Test status
Simulation time 45927639 ps
CPU time 1.35 seconds
Started Jun 24 05:36:32 PM PDT 24
Finished Jun 24 05:36:36 PM PDT 24
Peak memory 199712 kb
Host smart-aeaf17c9-e5f3-4221-86af-cbbef14ecaa6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378422604 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.378422604
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1733431988
Short name T755
Test name
Test status
Simulation time 15444263 ps
CPU time 0.77 seconds
Started Jun 24 05:36:31 PM PDT 24
Finished Jun 24 05:36:34 PM PDT 24
Peak memory 199000 kb
Host smart-7bb203e4-3c91-4729-9315-1419ec173538
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733431988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1733431988
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1396454160
Short name T679
Test name
Test status
Simulation time 28841390 ps
CPU time 0.58 seconds
Started Jun 24 05:36:33 PM PDT 24
Finished Jun 24 05:36:36 PM PDT 24
Peak memory 194380 kb
Host smart-a239b1fe-1a44-45e6-8450-dc12cb790def
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396454160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1396454160
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.482603213
Short name T698
Test name
Test status
Simulation time 102590126 ps
CPU time 1.74 seconds
Started Jun 24 05:36:33 PM PDT 24
Finished Jun 24 05:36:39 PM PDT 24
Peak memory 199380 kb
Host smart-a5ab3b07-7906-48bb-86f3-df891d216977
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482603213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.482603213
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.990833227
Short name T768
Test name
Test status
Simulation time 361214417 ps
CPU time 3.85 seconds
Started Jun 24 05:36:34 PM PDT 24
Finished Jun 24 05:36:42 PM PDT 24
Peak memory 199608 kb
Host smart-2661cad1-8e48-4e1e-941b-3551b98681f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990833227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.990833227
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.419127054
Short name T159
Test name
Test status
Simulation time 54254791 ps
CPU time 1.68 seconds
Started Jun 24 05:36:32 PM PDT 24
Finished Jun 24 05:36:37 PM PDT 24
Peak memory 199604 kb
Host smart-880377d5-4203-4d94-966e-02bcc8ef6e3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419127054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.419127054
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3359642112
Short name T551
Test name
Test status
Simulation time 24751856 ps
CPU time 0.67 seconds
Started Jun 24 06:16:53 PM PDT 24
Finished Jun 24 06:16:54 PM PDT 24
Peak memory 196288 kb
Host smart-b8a18f93-2ff4-4b8b-870c-daacf727b78d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359642112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3359642112
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.1593738769
Short name T485
Test name
Test status
Simulation time 5543740972 ps
CPU time 23.98 seconds
Started Jun 24 06:16:48 PM PDT 24
Finished Jun 24 06:17:13 PM PDT 24
Peak memory 200056 kb
Host smart-1cb74754-795f-4fea-aa48-d1f68fea9916
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1593738769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1593738769
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.4060490912
Short name T383
Test name
Test status
Simulation time 395561170 ps
CPU time 3.33 seconds
Started Jun 24 06:16:50 PM PDT 24
Finished Jun 24 06:16:56 PM PDT 24
Peak memory 200052 kb
Host smart-152c34e0-885c-44e4-82da-23a27f6ad64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060490912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.4060490912
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1776711328
Short name T439
Test name
Test status
Simulation time 6389178736 ps
CPU time 277.61 seconds
Started Jun 24 06:16:49 PM PDT 24
Finished Jun 24 06:21:28 PM PDT 24
Peak memory 389288 kb
Host smart-ba8ad8c2-f517-4152-8912-94f01d500346
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1776711328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1776711328
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2924619041
Short name T531
Test name
Test status
Simulation time 3185692503 ps
CPU time 174.77 seconds
Started Jun 24 06:16:49 PM PDT 24
Finished Jun 24 06:19:46 PM PDT 24
Peak memory 200084 kb
Host smart-7b2115d8-b7fd-4df7-9160-7db2178c4f81
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924619041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2924619041
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3672123818
Short name T183
Test name
Test status
Simulation time 1506877885 ps
CPU time 19.4 seconds
Started Jun 24 06:16:50 PM PDT 24
Finished Jun 24 06:17:12 PM PDT 24
Peak memory 200096 kb
Host smart-2aa1d2b3-1db5-468f-9260-caa92e891608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672123818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3672123818
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.554474475
Short name T530
Test name
Test status
Simulation time 603960844 ps
CPU time 7.59 seconds
Started Jun 24 06:16:50 PM PDT 24
Finished Jun 24 06:16:59 PM PDT 24
Peak memory 200064 kb
Host smart-4dd96d42-41d1-4883-a9ef-58f196bba550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554474475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.554474475
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.282444689
Short name T320
Test name
Test status
Simulation time 50117339 ps
CPU time 1.11 seconds
Started Jun 24 06:17:00 PM PDT 24
Finished Jun 24 06:17:02 PM PDT 24
Peak memory 199604 kb
Host smart-36d31ef7-431d-42c8-99d7-b9d6bd2ace8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282444689 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac_vectors.282444689
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.3077301384
Short name T238
Test name
Test status
Simulation time 8043816423 ps
CPU time 459.9 seconds
Started Jun 24 06:16:51 PM PDT 24
Finished Jun 24 06:24:33 PM PDT 24
Peak memory 200120 kb
Host smart-144064d9-3b43-4a39-bd75-f27695947629
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3077301384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3077301384
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.4048524022
Short name T288
Test name
Test status
Simulation time 102611574767 ps
CPU time 1937.75 seconds
Started Jun 24 06:16:49 PM PDT 24
Finished Jun 24 06:49:07 PM PDT 24
Peak memory 215720 kb
Host smart-4602fc0f-ce0f-46dc-83cc-22444466bbbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4048524022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.4048524022
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.3056802998
Short name T618
Test name
Test status
Simulation time 152860563630 ps
CPU time 1961.4 seconds
Started Jun 24 06:16:50 PM PDT 24
Finished Jun 24 06:49:33 PM PDT 24
Peak memory 215524 kb
Host smart-9c8a2f3c-2384-42f6-9697-3a903a6716e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3056802998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.3056802998
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3054155855
Short name T438
Test name
Test status
Simulation time 3251102844 ps
CPU time 65.35 seconds
Started Jun 24 06:16:51 PM PDT 24
Finished Jun 24 06:17:58 PM PDT 24
Peak memory 200144 kb
Host smart-3f5bb8d0-5681-402c-ae52-4e0680c591a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054155855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3054155855
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3651850201
Short name T575
Test name
Test status
Simulation time 31384365 ps
CPU time 0.61 seconds
Started Jun 24 06:17:00 PM PDT 24
Finished Jun 24 06:17:01 PM PDT 24
Peak memory 196740 kb
Host smart-45020315-b9e1-4a36-a5d7-67cbf4b3d993
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651850201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3651850201
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3856132124
Short name T370
Test name
Test status
Simulation time 1240724301 ps
CPU time 29.56 seconds
Started Jun 24 06:16:49 PM PDT 24
Finished Jun 24 06:17:20 PM PDT 24
Peak memory 200064 kb
Host smart-f564c576-9d9d-4dfc-bf36-eb774e002724
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3856132124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3856132124
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.123840269
Short name T480
Test name
Test status
Simulation time 2364432092 ps
CPU time 12.13 seconds
Started Jun 24 06:16:56 PM PDT 24
Finished Jun 24 06:17:10 PM PDT 24
Peak memory 200104 kb
Host smart-86d02384-6fac-4a78-9f53-eea909db9025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123840269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.123840269
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2359507140
Short name T60
Test name
Test status
Simulation time 775164855 ps
CPU time 160.75 seconds
Started Jun 24 06:16:51 PM PDT 24
Finished Jun 24 06:19:33 PM PDT 24
Peak memory 384464 kb
Host smart-92c44a35-681b-4b37-a2a8-4f1e919221ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2359507140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2359507140
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.2701396511
Short name T130
Test name
Test status
Simulation time 2019520173 ps
CPU time 115.36 seconds
Started Jun 24 06:17:00 PM PDT 24
Finished Jun 24 06:18:56 PM PDT 24
Peak memory 200020 kb
Host smart-a56fd7ab-72bf-4fcf-920d-63be5f4c24ff
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701396511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2701396511
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1083585523
Short name T50
Test name
Test status
Simulation time 86271253 ps
CPU time 1.01 seconds
Started Jun 24 06:17:02 PM PDT 24
Finished Jun 24 06:17:04 PM PDT 24
Peak memory 219208 kb
Host smart-43734e28-ff54-43f9-8331-f13838286769
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083585523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1083585523
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.4159848232
Short name T233
Test name
Test status
Simulation time 580945869 ps
CPU time 7.61 seconds
Started Jun 24 06:16:49 PM PDT 24
Finished Jun 24 06:16:58 PM PDT 24
Peak memory 200256 kb
Host smart-279f5a88-661b-4e5f-b717-1cf492f04683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159848232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.4159848232
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2520656519
Short name T607
Test name
Test status
Simulation time 4643412099 ps
CPU time 141.68 seconds
Started Jun 24 06:17:00 PM PDT 24
Finished Jun 24 06:19:23 PM PDT 24
Peak memory 200120 kb
Host smart-7d7796eb-85cd-41a0-933d-c2eeb6c4fcfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520656519 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2520656519
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.977239446
Short name T463
Test name
Test status
Simulation time 63546078 ps
CPU time 1.43 seconds
Started Jun 24 06:17:01 PM PDT 24
Finished Jun 24 06:17:03 PM PDT 24
Peak memory 200088 kb
Host smart-cbd1c1d0-91ee-4ed9-bf6e-a4058e903a6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977239446 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac_vectors.977239446
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.189083077
Short name T431
Test name
Test status
Simulation time 30147394641 ps
CPU time 449.99 seconds
Started Jun 24 06:17:01 PM PDT 24
Finished Jun 24 06:24:32 PM PDT 24
Peak memory 200124 kb
Host smart-94e13639-0849-4453-a8a4-4c05d934db1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=189083077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.189083077
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.4082314838
Short name T182
Test name
Test status
Simulation time 110460178381 ps
CPU time 2017.72 seconds
Started Jun 24 06:16:56 PM PDT 24
Finished Jun 24 06:50:35 PM PDT 24
Peak memory 215620 kb
Host smart-c615d3fe-df4e-4f7b-bddc-35d32fed1919
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4082314838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.4082314838
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.2973589750
Short name T517
Test name
Test status
Simulation time 212618710750 ps
CPU time 1909.33 seconds
Started Jun 24 06:17:29 PM PDT 24
Finished Jun 24 06:49:22 PM PDT 24
Peak memory 215548 kb
Host smart-65d88eec-a64e-474c-8c84-04727a34ba56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2973589750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.2973589750
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3496770848
Short name T126
Test name
Test status
Simulation time 7603967970 ps
CPU time 102.1 seconds
Started Jun 24 06:16:58 PM PDT 24
Finished Jun 24 06:18:41 PM PDT 24
Peak memory 200120 kb
Host smart-b21a6ffd-6d78-4637-9cb6-b83aa0c1c548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496770848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3496770848
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2522456969
Short name T490
Test name
Test status
Simulation time 46956250 ps
CPU time 0.59 seconds
Started Jun 24 06:17:27 PM PDT 24
Finished Jun 24 06:17:30 PM PDT 24
Peak memory 195948 kb
Host smart-16322aa5-702b-4adf-997c-f00167965ff6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522456969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2522456969
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1705053523
Short name T549
Test name
Test status
Simulation time 835946800 ps
CPU time 12.86 seconds
Started Jun 24 06:17:18 PM PDT 24
Finished Jun 24 06:17:32 PM PDT 24
Peak memory 199992 kb
Host smart-0be8e947-4537-46bd-8245-ee246e3dd681
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1705053523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1705053523
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3089382625
Short name T165
Test name
Test status
Simulation time 3276015412 ps
CPU time 23.3 seconds
Started Jun 24 06:17:19 PM PDT 24
Finished Jun 24 06:17:43 PM PDT 24
Peak memory 200164 kb
Host smart-cd634573-adc0-4689-ab6e-40b1a53745ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089382625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3089382625
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.3765214297
Short name T479
Test name
Test status
Simulation time 12538797645 ps
CPU time 1513.28 seconds
Started Jun 24 06:17:17 PM PDT 24
Finished Jun 24 06:42:32 PM PDT 24
Peak memory 765944 kb
Host smart-a5e58e66-9b70-4254-affe-8e0b6bb55319
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3765214297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3765214297
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.4058788895
Short name T11
Test name
Test status
Simulation time 20109968 ps
CPU time 0.69 seconds
Started Jun 24 06:17:16 PM PDT 24
Finished Jun 24 06:17:18 PM PDT 24
Peak memory 196300 kb
Host smart-9212fdd8-a19d-4144-b1b9-0998c9db61a4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058788895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.4058788895
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.2606435575
Short name T164
Test name
Test status
Simulation time 5693027602 ps
CPU time 112.99 seconds
Started Jun 24 06:17:16 PM PDT 24
Finished Jun 24 06:19:10 PM PDT 24
Peak memory 200380 kb
Host smart-ff958980-9861-4db6-a3d8-819e8217afe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606435575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2606435575
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.503170982
Short name T354
Test name
Test status
Simulation time 1739158041 ps
CPU time 13.9 seconds
Started Jun 24 06:17:17 PM PDT 24
Finished Jun 24 06:17:32 PM PDT 24
Peak memory 200068 kb
Host smart-809b638b-f732-4b02-82db-3b13fc8c2e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503170982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.503170982
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.2141286652
Short name T506
Test name
Test status
Simulation time 300072150 ps
CPU time 1.37 seconds
Started Jun 24 06:17:19 PM PDT 24
Finished Jun 24 06:17:21 PM PDT 24
Peak memory 200068 kb
Host smart-82815042-56ed-409a-82f6-2e273d15e383
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141286652 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_hmac_vectors.2141286652
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha256_vectors.2173466686
Short name T302
Test name
Test status
Simulation time 741823771137 ps
CPU time 483.11 seconds
Started Jun 24 06:17:18 PM PDT 24
Finished Jun 24 06:25:22 PM PDT 24
Peak memory 200120 kb
Host smart-fce6f5d4-f808-40b0-9dbe-731d41ebe4c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2173466686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha256_vectors.2173466686
Directory /workspace/10.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha384_vectors.4191249145
Short name T347
Test name
Test status
Simulation time 415791255614 ps
CPU time 1934.89 seconds
Started Jun 24 06:17:15 PM PDT 24
Finished Jun 24 06:49:32 PM PDT 24
Peak memory 216528 kb
Host smart-cb549ba5-9c90-4e1c-82d9-3c25c14bfc6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4191249145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha384_vectors.4191249145
Directory /workspace/10.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha512_vectors.224794548
Short name T508
Test name
Test status
Simulation time 301201974291 ps
CPU time 1843.91 seconds
Started Jun 24 06:17:20 PM PDT 24
Finished Jun 24 06:48:05 PM PDT 24
Peak memory 215504 kb
Host smart-e45c1fa8-bc8a-4f5d-8144-aa221e4940fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=224794548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha512_vectors.224794548
Directory /workspace/10.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.84978800
Short name T323
Test name
Test status
Simulation time 7999747686 ps
CPU time 38.7 seconds
Started Jun 24 06:17:20 PM PDT 24
Finished Jun 24 06:17:59 PM PDT 24
Peak memory 200116 kb
Host smart-e416b672-c711-4e90-9355-6e05366e2360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84978800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.84978800
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1926196992
Short name T599
Test name
Test status
Simulation time 43074966 ps
CPU time 0.59 seconds
Started Jun 24 06:17:32 PM PDT 24
Finished Jun 24 06:17:34 PM PDT 24
Peak memory 194960 kb
Host smart-8645c486-5155-467b-9965-4de4c1be81e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926196992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1926196992
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.129980384
Short name T610
Test name
Test status
Simulation time 11507702458 ps
CPU time 43.65 seconds
Started Jun 24 06:17:27 PM PDT 24
Finished Jun 24 06:18:14 PM PDT 24
Peak memory 208328 kb
Host smart-db47c85f-ac7a-401d-8a05-a8277a2ee3bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=129980384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.129980384
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.4029950632
Short name T317
Test name
Test status
Simulation time 8034086372 ps
CPU time 34.36 seconds
Started Jun 24 06:17:28 PM PDT 24
Finished Jun 24 06:18:06 PM PDT 24
Peak memory 200104 kb
Host smart-1de75a25-e882-4e7d-916f-6ec5877abc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029950632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.4029950632
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2129558658
Short name T524
Test name
Test status
Simulation time 7405353308 ps
CPU time 492.64 seconds
Started Jun 24 06:17:27 PM PDT 24
Finished Jun 24 06:25:42 PM PDT 24
Peak memory 682256 kb
Host smart-d66b1694-59f6-47f4-9bd7-05ce215b9633
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2129558658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2129558658
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1157984410
Short name T397
Test name
Test status
Simulation time 6707216482 ps
CPU time 105.95 seconds
Started Jun 24 06:17:27 PM PDT 24
Finished Jun 24 06:19:15 PM PDT 24
Peak memory 200124 kb
Host smart-c51c419f-fa3e-4616-a039-bff2339b4076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157984410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1157984410
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3255549927
Short name T268
Test name
Test status
Simulation time 2478655927 ps
CPU time 17.9 seconds
Started Jun 24 06:17:29 PM PDT 24
Finished Jun 24 06:17:50 PM PDT 24
Peak memory 200144 kb
Host smart-85cad855-d617-4473-9549-4bf8c654f8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255549927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3255549927
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.442059598
Short name T10
Test name
Test status
Simulation time 32332435 ps
CPU time 1.24 seconds
Started Jun 24 06:17:27 PM PDT 24
Finished Jun 24 06:17:31 PM PDT 24
Peak memory 200108 kb
Host smart-635928cd-090e-4b74-8860-d9749d46172a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442059598 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_hmac_vectors.442059598
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha256_vectors.11626532
Short name T385
Test name
Test status
Simulation time 34739559700 ps
CPU time 450.5 seconds
Started Jun 24 06:17:26 PM PDT 24
Finished Jun 24 06:24:59 PM PDT 24
Peak memory 200068 kb
Host smart-41799e55-3bcf-4417-8ea2-5cc6dffd476f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=11626532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha256_vectors.11626532
Directory /workspace/11.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha384_vectors.3488409800
Short name T415
Test name
Test status
Simulation time 406901431060 ps
CPU time 1858.09 seconds
Started Jun 24 06:17:28 PM PDT 24
Finished Jun 24 06:48:30 PM PDT 24
Peak memory 216108 kb
Host smart-02b81c61-876d-41d1-ad71-8edf9d067127
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3488409800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha384_vectors.3488409800
Directory /workspace/11.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha512_vectors.1140753816
Short name T497
Test name
Test status
Simulation time 30018681599 ps
CPU time 1819.57 seconds
Started Jun 24 06:17:27 PM PDT 24
Finished Jun 24 06:47:49 PM PDT 24
Peak memory 215576 kb
Host smart-01531077-f5cd-44fe-8bd1-37cbc6956778
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1140753816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha512_vectors.1140753816
Directory /workspace/11.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.3548492571
Short name T601
Test name
Test status
Simulation time 20814007077 ps
CPU time 82.36 seconds
Started Jun 24 06:17:28 PM PDT 24
Finished Jun 24 06:18:54 PM PDT 24
Peak memory 200112 kb
Host smart-44d6806d-4f1a-48a0-9254-2d99204a37d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548492571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3548492571
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3452489771
Short name T261
Test name
Test status
Simulation time 31520371 ps
CPU time 0.58 seconds
Started Jun 24 06:17:25 PM PDT 24
Finished Jun 24 06:17:27 PM PDT 24
Peak memory 195048 kb
Host smart-d6303b16-65fd-4675-9839-248c60aabde8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452489771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3452489771
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.2540707937
Short name T231
Test name
Test status
Simulation time 740212806 ps
CPU time 37.4 seconds
Started Jun 24 06:17:27 PM PDT 24
Finished Jun 24 06:18:07 PM PDT 24
Peak memory 200036 kb
Host smart-520a4636-5299-4079-bf56-d7a115809e24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2540707937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2540707937
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3699825388
Short name T128
Test name
Test status
Simulation time 33617972 ps
CPU time 0.79 seconds
Started Jun 24 06:17:27 PM PDT 24
Finished Jun 24 06:17:31 PM PDT 24
Peak memory 198504 kb
Host smart-4e43db28-6a98-4eb7-a296-46c41d61f007
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3699825388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3699825388
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3804754887
Short name T136
Test name
Test status
Simulation time 1269557066 ps
CPU time 12.17 seconds
Started Jun 24 06:17:26 PM PDT 24
Finished Jun 24 06:17:39 PM PDT 24
Peak memory 200080 kb
Host smart-1030ad5f-87e6-46f2-9987-65b845956160
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804754887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3804754887
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3075209766
Short name T395
Test name
Test status
Simulation time 655393488 ps
CPU time 19.27 seconds
Started Jun 24 06:17:27 PM PDT 24
Finished Jun 24 06:17:49 PM PDT 24
Peak memory 200120 kb
Host smart-398af9d7-4a5d-48a9-8a79-6a5a5e7ecf47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075209766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3075209766
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3489449299
Short name T562
Test name
Test status
Simulation time 85868581 ps
CPU time 3.41 seconds
Started Jun 24 06:17:26 PM PDT 24
Finished Jun 24 06:17:32 PM PDT 24
Peak memory 200000 kb
Host smart-cb6eaa10-9487-41ff-9e94-61d30bc7f893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489449299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3489449299
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.2787175321
Short name T316
Test name
Test status
Simulation time 35561195 ps
CPU time 1.14 seconds
Started Jun 24 06:17:27 PM PDT 24
Finished Jun 24 06:17:30 PM PDT 24
Peak memory 200064 kb
Host smart-e3370fec-81f0-4bdb-a910-458bf89f2753
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787175321 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_hmac_vectors.2787175321
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha256_vectors.3023330728
Short name T454
Test name
Test status
Simulation time 26416476517 ps
CPU time 488.22 seconds
Started Jun 24 06:17:29 PM PDT 24
Finished Jun 24 06:25:41 PM PDT 24
Peak memory 200120 kb
Host smart-6733318b-78a7-4ee7-b49d-db454811abaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3023330728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha256_vectors.3023330728
Directory /workspace/12.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha512_vectors.908888322
Short name T520
Test name
Test status
Simulation time 447090333112 ps
CPU time 2011.96 seconds
Started Jun 24 06:17:28 PM PDT 24
Finished Jun 24 06:51:03 PM PDT 24
Peak memory 216504 kb
Host smart-144947c9-53c9-4b44-a621-fa1e2036b841
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=908888322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha512_vectors.908888322
Directory /workspace/12.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2881769362
Short name T55
Test name
Test status
Simulation time 1379097191 ps
CPU time 7.62 seconds
Started Jun 24 06:17:28 PM PDT 24
Finished Jun 24 06:17:38 PM PDT 24
Peak memory 200064 kb
Host smart-f11a5bd3-4551-4147-875b-ef42bf02520b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881769362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2881769362
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2536010970
Short name T436
Test name
Test status
Simulation time 40619913 ps
CPU time 0.58 seconds
Started Jun 24 06:17:27 PM PDT 24
Finished Jun 24 06:17:31 PM PDT 24
Peak memory 194972 kb
Host smart-f361c490-a433-4d42-83eb-3d4b7c7cc364
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536010970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2536010970
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3521846183
Short name T600
Test name
Test status
Simulation time 849041546 ps
CPU time 10 seconds
Started Jun 24 06:17:25 PM PDT 24
Finished Jun 24 06:17:36 PM PDT 24
Peak memory 200052 kb
Host smart-4b9a2b48-a5d5-4eee-b83a-9c7268ed4a7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3521846183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3521846183
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.3985307568
Short name T493
Test name
Test status
Simulation time 4858569649 ps
CPU time 39.14 seconds
Started Jun 24 06:17:26 PM PDT 24
Finished Jun 24 06:18:07 PM PDT 24
Peak memory 200132 kb
Host smart-078776f4-7598-4e87-b66e-f103cb1973ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985307568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3985307568
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2685219994
Short name T201
Test name
Test status
Simulation time 9876490230 ps
CPU time 937.78 seconds
Started Jun 24 06:17:28 PM PDT 24
Finished Jun 24 06:33:10 PM PDT 24
Peak memory 755256 kb
Host smart-5bd6c68e-3ebb-43e1-b8e9-c908f707066e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2685219994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2685219994
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.421640720
Short name T341
Test name
Test status
Simulation time 8056725566 ps
CPU time 147.66 seconds
Started Jun 24 06:17:27 PM PDT 24
Finished Jun 24 06:19:57 PM PDT 24
Peak memory 200104 kb
Host smart-9e73fb01-32aa-4ee4-a21c-8dd09e6e8a87
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421640720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.421640720
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.4128939629
Short name T319
Test name
Test status
Simulation time 5747393757 ps
CPU time 109.53 seconds
Started Jun 24 06:17:25 PM PDT 24
Finished Jun 24 06:19:16 PM PDT 24
Peak memory 200136 kb
Host smart-aae99b45-1a50-4401-8144-75f97e5017b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128939629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.4128939629
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.154154821
Short name T242
Test name
Test status
Simulation time 4916262234 ps
CPU time 21.61 seconds
Started Jun 24 06:17:27 PM PDT 24
Finished Jun 24 06:17:51 PM PDT 24
Peak memory 200120 kb
Host smart-ea440e02-113b-4022-acd8-b14ecd6444c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154154821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.154154821
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.2547414869
Short name T200
Test name
Test status
Simulation time 54612982 ps
CPU time 1.17 seconds
Started Jun 24 06:17:27 PM PDT 24
Finished Jun 24 06:17:30 PM PDT 24
Peak memory 200004 kb
Host smart-9a5cf2c7-8cbd-446f-8154-33cd0b31702a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547414869 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_hmac_vectors.2547414869
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha256_vectors.2411148077
Short name T232
Test name
Test status
Simulation time 28967256577 ps
CPU time 545.03 seconds
Started Jun 24 06:17:30 PM PDT 24
Finished Jun 24 06:26:38 PM PDT 24
Peak memory 200100 kb
Host smart-3caa5fda-14b6-4656-a7a9-9b66f89b04e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2411148077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha256_vectors.2411148077
Directory /workspace/13.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha384_vectors.4224554360
Short name T621
Test name
Test status
Simulation time 201011233786 ps
CPU time 1882.55 seconds
Started Jun 24 06:17:29 PM PDT 24
Finished Jun 24 06:48:55 PM PDT 24
Peak memory 215536 kb
Host smart-2701798c-aed0-404d-b448-f134179c728e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4224554360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha384_vectors.4224554360
Directory /workspace/13.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/14.hmac_alert_test.489195892
Short name T86
Test name
Test status
Simulation time 19071370 ps
CPU time 0.59 seconds
Started Jun 24 06:17:25 PM PDT 24
Finished Jun 24 06:17:27 PM PDT 24
Peak memory 195716 kb
Host smart-468a993d-858c-4058-ba49-7e15323d3311
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489195892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.489195892
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2533965939
Short name T416
Test name
Test status
Simulation time 684815847 ps
CPU time 17.4 seconds
Started Jun 24 06:17:26 PM PDT 24
Finished Jun 24 06:17:45 PM PDT 24
Peak memory 200024 kb
Host smart-dc433b94-4193-4782-a238-0e517b0eab8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533965939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2533965939
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2076782788
Short name T249
Test name
Test status
Simulation time 4661472603 ps
CPU time 33.38 seconds
Started Jun 24 06:17:29 PM PDT 24
Finished Jun 24 06:18:06 PM PDT 24
Peak memory 200152 kb
Host smart-8ba5209c-b232-4a35-8b59-37aba57e9fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076782788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2076782788
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.854770200
Short name T152
Test name
Test status
Simulation time 7325538146 ps
CPU time 1245.98 seconds
Started Jun 24 06:17:27 PM PDT 24
Finished Jun 24 06:38:16 PM PDT 24
Peak memory 764064 kb
Host smart-58c93703-7089-4a85-83b6-75573378aa72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=854770200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.854770200
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.955659451
Short name T403
Test name
Test status
Simulation time 5001115644 ps
CPU time 67.31 seconds
Started Jun 24 06:17:30 PM PDT 24
Finished Jun 24 06:18:40 PM PDT 24
Peak memory 200136 kb
Host smart-4a0a44a6-39e3-4482-b4a2-0d0f3c77c29e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955659451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.955659451
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2361139080
Short name T303
Test name
Test status
Simulation time 282857052 ps
CPU time 15.86 seconds
Started Jun 24 06:17:27 PM PDT 24
Finished Jun 24 06:17:45 PM PDT 24
Peak memory 200056 kb
Host smart-87953932-54cb-490c-a613-334aeacf3a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361139080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2361139080
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.371075111
Short name T371
Test name
Test status
Simulation time 1257987605 ps
CPU time 14.19 seconds
Started Jun 24 06:17:26 PM PDT 24
Finished Jun 24 06:17:42 PM PDT 24
Peak memory 200000 kb
Host smart-d6f85e7a-00a0-49e0-ba24-0eaa78af99e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371075111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.371075111
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.3602763225
Short name T577
Test name
Test status
Simulation time 60508819 ps
CPU time 1.44 seconds
Started Jun 24 06:17:24 PM PDT 24
Finished Jun 24 06:17:26 PM PDT 24
Peak memory 200044 kb
Host smart-39ddbe67-1202-495f-a8d9-938f293253fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602763225 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_hmac_vectors.3602763225
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha256_vectors.3325569595
Short name T533
Test name
Test status
Simulation time 7567989947 ps
CPU time 436.19 seconds
Started Jun 24 06:17:25 PM PDT 24
Finished Jun 24 06:24:43 PM PDT 24
Peak memory 200120 kb
Host smart-51efe917-2740-4c4e-974b-56ee58c8604b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3325569595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha256_vectors.3325569595
Directory /workspace/14.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha384_vectors.2694791333
Short name T430
Test name
Test status
Simulation time 112651006793 ps
CPU time 1990.7 seconds
Started Jun 24 06:17:26 PM PDT 24
Finished Jun 24 06:50:40 PM PDT 24
Peak memory 215808 kb
Host smart-486ec320-3d9a-42e9-abef-f82da81a344c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2694791333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha384_vectors.2694791333
Directory /workspace/14.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha512_vectors.1983834634
Short name T224
Test name
Test status
Simulation time 62413487477 ps
CPU time 1712.86 seconds
Started Jun 24 06:17:28 PM PDT 24
Finished Jun 24 06:46:05 PM PDT 24
Peak memory 215752 kb
Host smart-0379b52b-5050-48af-8ae8-13aa90b4f6bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1983834634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha512_vectors.1983834634
Directory /workspace/14.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.251694590
Short name T94
Test name
Test status
Simulation time 8094794748 ps
CPU time 52.31 seconds
Started Jun 24 06:17:27 PM PDT 24
Finished Jun 24 06:18:21 PM PDT 24
Peak memory 200132 kb
Host smart-889edf00-18ce-4542-aded-3a6662df84d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251694590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.251694590
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.4111641451
Short name T437
Test name
Test status
Simulation time 14351879 ps
CPU time 0.58 seconds
Started Jun 24 06:17:39 PM PDT 24
Finished Jun 24 06:17:41 PM PDT 24
Peak memory 195684 kb
Host smart-03f47094-aa54-4a88-9910-665f132fa803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111641451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.4111641451
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2828837020
Short name T259
Test name
Test status
Simulation time 756315079 ps
CPU time 35.14 seconds
Started Jun 24 06:17:28 PM PDT 24
Finished Jun 24 06:18:07 PM PDT 24
Peak memory 200056 kb
Host smart-6df6062c-017c-4b19-9b89-a5c2182a844a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2828837020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2828837020
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1615296234
Short name T521
Test name
Test status
Simulation time 3853919785 ps
CPU time 51.5 seconds
Started Jun 24 06:17:29 PM PDT 24
Finished Jun 24 06:18:23 PM PDT 24
Peak memory 200164 kb
Host smart-38d9d1b1-2d51-4679-9b06-8f18d7758725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615296234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1615296234
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3811645387
Short name T554
Test name
Test status
Simulation time 23733705338 ps
CPU time 548.95 seconds
Started Jun 24 06:17:27 PM PDT 24
Finished Jun 24 06:26:39 PM PDT 24
Peak memory 628212 kb
Host smart-7761ed6a-927a-42ba-9d59-8fc69e36e629
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3811645387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3811645387
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2209792796
Short name T31
Test name
Test status
Simulation time 9202208283 ps
CPU time 121.12 seconds
Started Jun 24 06:17:30 PM PDT 24
Finished Jun 24 06:19:34 PM PDT 24
Peak memory 200060 kb
Host smart-fb39a163-710c-45a6-bf53-a9a9ffb77e31
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209792796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2209792796
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3216153834
Short name T482
Test name
Test status
Simulation time 11510803270 ps
CPU time 41.63 seconds
Started Jun 24 06:17:28 PM PDT 24
Finished Jun 24 06:18:13 PM PDT 24
Peak memory 200140 kb
Host smart-11091000-7f76-45ed-903e-5dc5888596f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216153834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3216153834
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1687894442
Short name T632
Test name
Test status
Simulation time 2451663035 ps
CPU time 15.51 seconds
Started Jun 24 06:17:29 PM PDT 24
Finished Jun 24 06:17:48 PM PDT 24
Peak memory 200128 kb
Host smart-ded3b9c8-03b2-4c56-a8b4-cc99db44bc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687894442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1687894442
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.4194149872
Short name T351
Test name
Test status
Simulation time 653524341 ps
CPU time 1.39 seconds
Started Jun 24 06:17:29 PM PDT 24
Finished Jun 24 06:17:34 PM PDT 24
Peak memory 200016 kb
Host smart-b59da42e-0473-4516-bf04-914c94c37277
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194149872 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_hmac_vectors.4194149872
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha256_vectors.1026328882
Short name T190
Test name
Test status
Simulation time 40848553477 ps
CPU time 540.24 seconds
Started Jun 24 06:17:26 PM PDT 24
Finished Jun 24 06:26:29 PM PDT 24
Peak memory 200096 kb
Host smart-1f3fda71-60e9-4e16-bf32-a4dbf198ee6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1026328882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha256_vectors.1026328882
Directory /workspace/15.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha384_vectors.215773953
Short name T487
Test name
Test status
Simulation time 223107746530 ps
CPU time 2013.2 seconds
Started Jun 24 06:17:27 PM PDT 24
Finished Jun 24 06:51:04 PM PDT 24
Peak memory 215540 kb
Host smart-3188b168-520a-4b49-9d09-f230ee6985f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=215773953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha384_vectors.215773953
Directory /workspace/15.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha512_vectors.3379534443
Short name T446
Test name
Test status
Simulation time 134833035428 ps
CPU time 1836.42 seconds
Started Jun 24 06:17:29 PM PDT 24
Finished Jun 24 06:48:09 PM PDT 24
Peak memory 216544 kb
Host smart-28017160-37d5-4b88-85b2-bd6f503e1486
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3379534443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha512_vectors.3379534443
Directory /workspace/15.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1827142279
Short name T260
Test name
Test status
Simulation time 503968059 ps
CPU time 6.82 seconds
Started Jun 24 06:17:28 PM PDT 24
Finished Jun 24 06:17:38 PM PDT 24
Peak memory 200072 kb
Host smart-ab102e7f-14e5-4fe3-a79e-79007d6a4237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827142279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1827142279
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.3343386736
Short name T663
Test name
Test status
Simulation time 2025789096 ps
CPU time 26.66 seconds
Started Jun 24 06:17:40 PM PDT 24
Finished Jun 24 06:18:08 PM PDT 24
Peak memory 200036 kb
Host smart-d5016b28-e1bc-4886-87e9-ccd55a04a1bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3343386736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3343386736
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1319000968
Short name T567
Test name
Test status
Simulation time 2002283859 ps
CPU time 28.28 seconds
Started Jun 24 06:17:38 PM PDT 24
Finished Jun 24 06:18:07 PM PDT 24
Peak memory 200048 kb
Host smart-c502e823-fd27-4bbb-9c77-e89141cc6b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319000968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1319000968
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.1230773891
Short name T653
Test name
Test status
Simulation time 40131675385 ps
CPU time 679.24 seconds
Started Jun 24 06:17:39 PM PDT 24
Finished Jun 24 06:28:59 PM PDT 24
Peak memory 679744 kb
Host smart-a0870eff-88f1-46ed-8241-be4c6b3afd95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1230773891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1230773891
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.3355121619
Short name T137
Test name
Test status
Simulation time 10982402731 ps
CPU time 210.17 seconds
Started Jun 24 06:17:40 PM PDT 24
Finished Jun 24 06:21:12 PM PDT 24
Peak memory 200100 kb
Host smart-ffc12e76-354b-46f1-bb5c-463678aef378
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355121619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3355121619
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2043271376
Short name T391
Test name
Test status
Simulation time 13117970434 ps
CPU time 121.3 seconds
Started Jun 24 06:17:38 PM PDT 24
Finished Jun 24 06:19:40 PM PDT 24
Peak memory 200140 kb
Host smart-cd82b9b0-d4df-424f-9cd8-8cb0433ba1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043271376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2043271376
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.4143570993
Short name T386
Test name
Test status
Simulation time 465335997 ps
CPU time 9.15 seconds
Started Jun 24 06:17:39 PM PDT 24
Finished Jun 24 06:17:49 PM PDT 24
Peak memory 200036 kb
Host smart-be781c18-cd15-46e9-b249-f24b6c847d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143570993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.4143570993
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.1623488512
Short name T8
Test name
Test status
Simulation time 314708088 ps
CPU time 1.18 seconds
Started Jun 24 06:17:39 PM PDT 24
Finished Jun 24 06:17:41 PM PDT 24
Peak memory 200232 kb
Host smart-4007a082-3126-4a20-bfca-b106a09508e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623488512 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_hmac_vectors.1623488512
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha256_vectors.2420462308
Short name T619
Test name
Test status
Simulation time 56035141975 ps
CPU time 501.31 seconds
Started Jun 24 06:17:39 PM PDT 24
Finished Jun 24 06:26:01 PM PDT 24
Peak memory 200124 kb
Host smart-524e6785-48a1-4392-a269-967d8e94af5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2420462308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha256_vectors.2420462308
Directory /workspace/16.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha512_vectors.2455067855
Short name T558
Test name
Test status
Simulation time 213366705829 ps
CPU time 1859 seconds
Started Jun 24 06:17:37 PM PDT 24
Finished Jun 24 06:48:37 PM PDT 24
Peak memory 215572 kb
Host smart-09909484-cb7c-4027-b753-540bcf014eab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2455067855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha512_vectors.2455067855
Directory /workspace/16.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1866471876
Short name T406
Test name
Test status
Simulation time 7790704164 ps
CPU time 31.24 seconds
Started Jun 24 06:17:39 PM PDT 24
Finished Jun 24 06:18:12 PM PDT 24
Peak memory 200128 kb
Host smart-913985fa-f369-48f7-95f1-5d52f8dc3625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866471876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1866471876
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.385901231
Short name T297
Test name
Test status
Simulation time 12082446 ps
CPU time 0.64 seconds
Started Jun 24 06:17:39 PM PDT 24
Finished Jun 24 06:17:41 PM PDT 24
Peak memory 195628 kb
Host smart-ad0a387a-2fdf-4575-aa1b-3415055f9d5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385901231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.385901231
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.603143637
Short name T427
Test name
Test status
Simulation time 507744631 ps
CPU time 21.59 seconds
Started Jun 24 06:17:37 PM PDT 24
Finished Jun 24 06:18:00 PM PDT 24
Peak memory 200068 kb
Host smart-223df0a7-7019-4f83-9443-f8b6dabe6a32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=603143637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.603143637
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1134751435
Short name T307
Test name
Test status
Simulation time 1300401183 ps
CPU time 23.27 seconds
Started Jun 24 06:17:41 PM PDT 24
Finished Jun 24 06:18:05 PM PDT 24
Peak memory 200036 kb
Host smart-6951075f-e540-4aec-9287-18a62a2770c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134751435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1134751435
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3605758519
Short name T239
Test name
Test status
Simulation time 20416815230 ps
CPU time 458.08 seconds
Started Jun 24 06:17:38 PM PDT 24
Finished Jun 24 06:25:17 PM PDT 24
Peak memory 475360 kb
Host smart-80651bf1-d452-4d8d-bf46-d725a8aa5848
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3605758519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3605758519
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.2863030485
Short name T129
Test name
Test status
Simulation time 10522047109 ps
CPU time 128.46 seconds
Started Jun 24 06:17:41 PM PDT 24
Finished Jun 24 06:19:51 PM PDT 24
Peak memory 200104 kb
Host smart-66cf5f8a-822f-4859-b2ad-1109cef070d4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863030485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2863030485
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3366593317
Short name T321
Test name
Test status
Simulation time 1590211092 ps
CPU time 92.57 seconds
Started Jun 24 06:17:37 PM PDT 24
Finished Jun 24 06:19:11 PM PDT 24
Peak memory 200072 kb
Host smart-23a7f5cd-c10e-4b4a-8142-a84e7f6c60e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366593317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3366593317
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3696887744
Short name T532
Test name
Test status
Simulation time 2361402585 ps
CPU time 13.91 seconds
Started Jun 24 06:17:38 PM PDT 24
Finished Jun 24 06:17:53 PM PDT 24
Peak memory 200168 kb
Host smart-0e0949ac-8767-4d3e-98d6-ca7a32be2b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696887744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3696887744
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.3048497822
Short name T349
Test name
Test status
Simulation time 49476062 ps
CPU time 1.08 seconds
Started Jun 24 06:17:39 PM PDT 24
Finished Jun 24 06:17:41 PM PDT 24
Peak memory 199792 kb
Host smart-3dcada41-d106-467c-b4ac-84d5a3e88f90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048497822 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_hmac_vectors.3048497822
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha256_vectors.2254214081
Short name T379
Test name
Test status
Simulation time 8024802717 ps
CPU time 449.7 seconds
Started Jun 24 06:17:41 PM PDT 24
Finished Jun 24 06:25:12 PM PDT 24
Peak memory 200096 kb
Host smart-fef33e10-b22a-49db-812b-bf5b1a198275
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2254214081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha256_vectors.2254214081
Directory /workspace/17.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha384_vectors.3697963836
Short name T118
Test name
Test status
Simulation time 31000423482 ps
CPU time 1731.99 seconds
Started Jun 24 06:17:37 PM PDT 24
Finished Jun 24 06:46:30 PM PDT 24
Peak memory 216124 kb
Host smart-494a22cf-41bf-4311-b7fd-0ce083b22b65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3697963836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha384_vectors.3697963836
Directory /workspace/17.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha512_vectors.1536457182
Short name T405
Test name
Test status
Simulation time 29768027349 ps
CPU time 1762.14 seconds
Started Jun 24 06:17:38 PM PDT 24
Finished Jun 24 06:47:01 PM PDT 24
Peak memory 216060 kb
Host smart-7028c63e-21ec-4196-8ba8-26cdf2c55588
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1536457182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha512_vectors.1536457182
Directory /workspace/17.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1230907862
Short name T180
Test name
Test status
Simulation time 2937793368 ps
CPU time 27.96 seconds
Started Jun 24 06:17:38 PM PDT 24
Finished Jun 24 06:18:07 PM PDT 24
Peak memory 200108 kb
Host smart-4d038599-7407-428b-8472-0b5a8f9c7a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230907862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1230907862
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.4107160916
Short name T236
Test name
Test status
Simulation time 13786456 ps
CPU time 0.61 seconds
Started Jun 24 06:17:44 PM PDT 24
Finished Jun 24 06:17:46 PM PDT 24
Peak memory 195712 kb
Host smart-5df52c6e-4468-41f2-8ac2-b369e116373b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107160916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.4107160916
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2651988348
Short name T24
Test name
Test status
Simulation time 1038837380 ps
CPU time 46.81 seconds
Started Jun 24 06:17:39 PM PDT 24
Finished Jun 24 06:18:27 PM PDT 24
Peak memory 200064 kb
Host smart-7e4bef07-eb77-4d65-a854-ab24db4f7377
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2651988348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2651988348
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3720650920
Short name T194
Test name
Test status
Simulation time 202757749 ps
CPU time 11.11 seconds
Started Jun 24 06:17:41 PM PDT 24
Finished Jun 24 06:17:54 PM PDT 24
Peak memory 200060 kb
Host smart-3de147c3-1731-4a58-b92c-29ce780bafcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720650920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3720650920
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1420189245
Short name T581
Test name
Test status
Simulation time 18023374834 ps
CPU time 293.32 seconds
Started Jun 24 06:17:41 PM PDT 24
Finished Jun 24 06:22:35 PM PDT 24
Peak memory 586532 kb
Host smart-71338561-f357-4b11-8bfa-d9c5dd9a3e33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1420189245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1420189245
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2219904695
Short name T568
Test name
Test status
Simulation time 2602496050 ps
CPU time 129.84 seconds
Started Jun 24 06:17:41 PM PDT 24
Finished Jun 24 06:19:52 PM PDT 24
Peak memory 200128 kb
Host smart-81d4bf23-31eb-4435-af3b-a07a19b54932
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219904695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2219904695
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.3027303663
Short name T210
Test name
Test status
Simulation time 19069045091 ps
CPU time 91.95 seconds
Started Jun 24 06:17:39 PM PDT 24
Finished Jun 24 06:19:13 PM PDT 24
Peak memory 200124 kb
Host smart-fab34915-b040-4f3e-9b67-044429be288d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027303663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3027303663
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2333400965
Short name T329
Test name
Test status
Simulation time 3328011079 ps
CPU time 15.29 seconds
Started Jun 24 06:17:40 PM PDT 24
Finished Jun 24 06:17:56 PM PDT 24
Peak memory 200132 kb
Host smart-928e298e-9d3a-45bf-b6b8-410fccd3365f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333400965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2333400965
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.2296214205
Short name T518
Test name
Test status
Simulation time 159902658 ps
CPU time 1.4 seconds
Started Jun 24 06:17:40 PM PDT 24
Finished Jun 24 06:17:43 PM PDT 24
Peak memory 200060 kb
Host smart-5990b577-6504-4128-83d4-02bb7a564761
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296214205 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_hmac_vectors.2296214205
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha256_vectors.950243867
Short name T2
Test name
Test status
Simulation time 33163681838 ps
CPU time 444.85 seconds
Started Jun 24 06:17:41 PM PDT 24
Finished Jun 24 06:25:07 PM PDT 24
Peak memory 200128 kb
Host smart-16f801c7-64e3-4360-95d4-2bc17b415259
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=950243867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha256_vectors.950243867
Directory /workspace/18.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha384_vectors.3932447393
Short name T217
Test name
Test status
Simulation time 106704964544 ps
CPU time 1729.05 seconds
Started Jun 24 06:17:50 PM PDT 24
Finished Jun 24 06:46:40 PM PDT 24
Peak memory 215652 kb
Host smart-4d2f1606-db6a-4efd-8703-6687c333351d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3932447393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha384_vectors.3932447393
Directory /workspace/18.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha512_vectors.1932653295
Short name T185
Test name
Test status
Simulation time 29432942852 ps
CPU time 1600.22 seconds
Started Jun 24 06:17:39 PM PDT 24
Finished Jun 24 06:44:21 PM PDT 24
Peak memory 215988 kb
Host smart-73e7d40e-fdea-4771-8604-2402b3ad9a6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1932653295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha512_vectors.1932653295
Directory /workspace/18.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3665456261
Short name T477
Test name
Test status
Simulation time 112911058 ps
CPU time 3.36 seconds
Started Jun 24 06:17:42 PM PDT 24
Finished Jun 24 06:17:46 PM PDT 24
Peak memory 200068 kb
Host smart-1bc1bce7-3a5e-4874-b77c-743100db08a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665456261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3665456261
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1728035594
Short name T177
Test name
Test status
Simulation time 10397022 ps
CPU time 0.58 seconds
Started Jun 24 06:17:45 PM PDT 24
Finished Jun 24 06:17:47 PM PDT 24
Peak memory 194972 kb
Host smart-e9b88258-3c57-476f-8665-7cf0943f3580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728035594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1728035594
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3040673341
Short name T647
Test name
Test status
Simulation time 3552280846 ps
CPU time 42.5 seconds
Started Jun 24 06:17:39 PM PDT 24
Finished Jun 24 06:18:23 PM PDT 24
Peak memory 200084 kb
Host smart-80fc3d40-0d39-471c-910f-e74b9e74909b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3040673341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3040673341
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2743414488
Short name T366
Test name
Test status
Simulation time 568927060 ps
CPU time 5.78 seconds
Started Jun 24 06:17:41 PM PDT 24
Finished Jun 24 06:17:48 PM PDT 24
Peak memory 200056 kb
Host smart-9c8f7127-484a-446a-bb47-6177106c2b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743414488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2743414488
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_error.2913469080
Short name T172
Test name
Test status
Simulation time 1414679785 ps
CPU time 80.05 seconds
Started Jun 24 06:17:44 PM PDT 24
Finished Jun 24 06:19:05 PM PDT 24
Peak memory 200260 kb
Host smart-31bb6735-8f05-4813-b9ff-f31388c85e0c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913469080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2913469080
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.801486010
Short name T643
Test name
Test status
Simulation time 8557488348 ps
CPU time 123.5 seconds
Started Jun 24 06:17:41 PM PDT 24
Finished Jun 24 06:19:46 PM PDT 24
Peak memory 200324 kb
Host smart-049a0deb-dd7a-4509-a504-1d283ad6f19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801486010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.801486010
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.728775105
Short name T336
Test name
Test status
Simulation time 1015068141 ps
CPU time 11.96 seconds
Started Jun 24 06:17:43 PM PDT 24
Finished Jun 24 06:17:55 PM PDT 24
Peak memory 200108 kb
Host smart-56dfa75e-72a2-429e-a611-076f1785eb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728775105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.728775105
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.3753627556
Short name T388
Test name
Test status
Simulation time 155552821 ps
CPU time 1.42 seconds
Started Jun 24 06:17:46 PM PDT 24
Finished Jun 24 06:17:49 PM PDT 24
Peak memory 200056 kb
Host smart-a238067d-8038-484d-8622-99f0ab7392a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753627556 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_hmac_vectors.3753627556
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha256_vectors.3421692978
Short name T332
Test name
Test status
Simulation time 31125834266 ps
CPU time 577.37 seconds
Started Jun 24 06:17:40 PM PDT 24
Finished Jun 24 06:27:18 PM PDT 24
Peak memory 200104 kb
Host smart-a0f4a0cb-4870-4c12-b5a8-30c6ac3b8a16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3421692978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha256_vectors.3421692978
Directory /workspace/19.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha384_vectors.2743217994
Short name T82
Test name
Test status
Simulation time 99919843861 ps
CPU time 1579.64 seconds
Started Jun 24 06:17:47 PM PDT 24
Finished Jun 24 06:44:08 PM PDT 24
Peak memory 216504 kb
Host smart-1b59f59d-b264-4acd-87c5-a6037897e3af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2743217994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha384_vectors.2743217994
Directory /workspace/19.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha512_vectors.651485527
Short name T561
Test name
Test status
Simulation time 445648590280 ps
CPU time 2010.32 seconds
Started Jun 24 06:17:50 PM PDT 24
Finished Jun 24 06:51:21 PM PDT 24
Peak memory 216364 kb
Host smart-c2c3e8e8-7903-45df-a4ea-6d769025c2c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=651485527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha512_vectors.651485527
Directory /workspace/19.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.2842600131
Short name T546
Test name
Test status
Simulation time 11497875738 ps
CPU time 91.09 seconds
Started Jun 24 06:17:45 PM PDT 24
Finished Jun 24 06:19:17 PM PDT 24
Peak memory 200340 kb
Host smart-dc0a2a56-2620-4859-b23b-0070bdfbc05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842600131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2842600131
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1280414879
Short name T507
Test name
Test status
Simulation time 38942343 ps
CPU time 0.58 seconds
Started Jun 24 06:16:57 PM PDT 24
Finished Jun 24 06:17:00 PM PDT 24
Peak memory 195996 kb
Host smart-7eb6cf58-0ee7-45a4-a046-f5a20a593c77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280414879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1280414879
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.2649434542
Short name T481
Test name
Test status
Simulation time 1639916828 ps
CPU time 19.83 seconds
Started Jun 24 06:16:56 PM PDT 24
Finished Jun 24 06:17:18 PM PDT 24
Peak memory 200044 kb
Host smart-1076fab6-1401-4b64-a2eb-e1d8518e43a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2649434542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2649434542
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3641858967
Short name T591
Test name
Test status
Simulation time 518749784 ps
CPU time 7.25 seconds
Started Jun 24 06:16:58 PM PDT 24
Finished Jun 24 06:17:07 PM PDT 24
Peak memory 200052 kb
Host smart-5a92d89c-584b-4e3a-bfc8-5ed6ee598737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641858967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3641858967
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.515924997
Short name T414
Test name
Test status
Simulation time 10159633876 ps
CPU time 977.44 seconds
Started Jun 24 06:16:58 PM PDT 24
Finished Jun 24 06:33:17 PM PDT 24
Peak memory 717636 kb
Host smart-9c24ee76-5d06-484b-a19e-4a115d3f358f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=515924997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.515924997
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.846832065
Short name T30
Test name
Test status
Simulation time 2429816745 ps
CPU time 33.08 seconds
Started Jun 24 06:16:59 PM PDT 24
Finished Jun 24 06:17:33 PM PDT 24
Peak memory 200120 kb
Host smart-5e58b646-59c4-45fa-9481-f6b14b634c4a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846832065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.846832065
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3392955918
Short name T337
Test name
Test status
Simulation time 715634298 ps
CPU time 21.24 seconds
Started Jun 24 06:16:56 PM PDT 24
Finished Jun 24 06:17:19 PM PDT 24
Peak memory 200068 kb
Host smart-f2600032-9d65-4df9-888b-faa2a6cfbc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392955918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3392955918
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2079141239
Short name T49
Test name
Test status
Simulation time 235954467 ps
CPU time 0.86 seconds
Started Jun 24 06:17:00 PM PDT 24
Finished Jun 24 06:17:02 PM PDT 24
Peak memory 218172 kb
Host smart-3456c37f-d22c-4f98-9187-569e44c8e8d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079141239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2079141239
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2024445543
Short name T650
Test name
Test status
Simulation time 249915987 ps
CPU time 10.86 seconds
Started Jun 24 06:16:57 PM PDT 24
Finished Jun 24 06:17:09 PM PDT 24
Peak memory 200044 kb
Host smart-c317fea9-f863-4d0b-beef-ea7a13f15210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024445543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2024445543
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.3662422662
Short name T171
Test name
Test status
Simulation time 875608913 ps
CPU time 1.51 seconds
Started Jun 24 06:16:56 PM PDT 24
Finished Jun 24 06:16:59 PM PDT 24
Peak memory 200068 kb
Host smart-08c42314-5ebb-42c0-ab2e-b994e3033508
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662422662 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac_vectors.3662422662
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.1409550003
Short name T248
Test name
Test status
Simulation time 29930822824 ps
CPU time 576.53 seconds
Started Jun 24 06:16:55 PM PDT 24
Finished Jun 24 06:26:32 PM PDT 24
Peak memory 200388 kb
Host smart-36dc8c06-568e-47f7-8945-41aaca7b94ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1409550003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.1409550003
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.2365295784
Short name T578
Test name
Test status
Simulation time 648099928156 ps
CPU time 2057.1 seconds
Started Jun 24 06:17:04 PM PDT 24
Finished Jun 24 06:51:22 PM PDT 24
Peak memory 216500 kb
Host smart-0e92a59c-92c7-4675-8ccf-671cc7ecef4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2365295784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.2365295784
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.895186089
Short name T359
Test name
Test status
Simulation time 679685944155 ps
CPU time 2152.05 seconds
Started Jun 24 06:16:57 PM PDT 24
Finished Jun 24 06:52:51 PM PDT 24
Peak memory 216264 kb
Host smart-6f0004ae-043e-4431-b76d-4ca8fe99d4ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=895186089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.895186089
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3964192979
Short name T189
Test name
Test status
Simulation time 2378168989 ps
CPU time 48.79 seconds
Started Jun 24 06:16:59 PM PDT 24
Finished Jun 24 06:17:49 PM PDT 24
Peak memory 200132 kb
Host smart-3f96553e-6c04-44aa-b653-6d713a2a7be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964192979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3964192979
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2223444259
Short name T390
Test name
Test status
Simulation time 22354202 ps
CPU time 0.57 seconds
Started Jun 24 06:17:45 PM PDT 24
Finished Jun 24 06:17:47 PM PDT 24
Peak memory 195624 kb
Host smart-110592cf-04e5-4168-987e-7e791b013bc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223444259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2223444259
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.4074769108
Short name T298
Test name
Test status
Simulation time 458104219 ps
CPU time 20.48 seconds
Started Jun 24 06:17:47 PM PDT 24
Finished Jun 24 06:18:09 PM PDT 24
Peak memory 199972 kb
Host smart-294e84c3-870a-4041-aa2d-d0e0ee60c48a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4074769108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.4074769108
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2177445762
Short name T219
Test name
Test status
Simulation time 1868398114 ps
CPU time 31.5 seconds
Started Jun 24 06:17:47 PM PDT 24
Finished Jun 24 06:18:19 PM PDT 24
Peak memory 200056 kb
Host smart-50436df6-5049-444f-816c-aa7c9bd5e3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177445762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2177445762
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2054356334
Short name T264
Test name
Test status
Simulation time 3375878990 ps
CPU time 472.52 seconds
Started Jun 24 06:17:46 PM PDT 24
Finished Jun 24 06:25:40 PM PDT 24
Peak memory 690564 kb
Host smart-ae7bf0a6-05be-465a-891e-544e97e135e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2054356334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2054356334
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1208258858
Short name T138
Test name
Test status
Simulation time 7369846976 ps
CPU time 20.68 seconds
Started Jun 24 06:17:47 PM PDT 24
Finished Jun 24 06:18:09 PM PDT 24
Peak memory 199940 kb
Host smart-5159e0c0-4b31-4b86-9f8d-23ef67231ca2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208258858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1208258858
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2664490252
Short name T658
Test name
Test status
Simulation time 1095919248 ps
CPU time 13.31 seconds
Started Jun 24 06:17:49 PM PDT 24
Finished Jun 24 06:18:03 PM PDT 24
Peak memory 200084 kb
Host smart-60dbb2a9-285e-4819-89f8-53ce7de4eb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664490252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2664490252
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.812742769
Short name T292
Test name
Test status
Simulation time 215327443 ps
CPU time 3.18 seconds
Started Jun 24 06:17:52 PM PDT 24
Finished Jun 24 06:17:56 PM PDT 24
Peak memory 200032 kb
Host smart-ff955343-d91f-47ba-8fd9-e6efe6da0722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812742769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.812742769
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.1255620936
Short name T308
Test name
Test status
Simulation time 46992514 ps
CPU time 1.18 seconds
Started Jun 24 06:17:53 PM PDT 24
Finished Jun 24 06:17:56 PM PDT 24
Peak memory 200008 kb
Host smart-11cc23f3-1ac8-4198-880a-ea8a23ec73e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255620936 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_hmac_vectors.1255620936
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha256_vectors.281717572
Short name T660
Test name
Test status
Simulation time 8184692187 ps
CPU time 451.61 seconds
Started Jun 24 06:17:49 PM PDT 24
Finished Jun 24 06:25:21 PM PDT 24
Peak memory 200148 kb
Host smart-221afc40-e65f-4e52-9125-1a66d656ed7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=281717572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha256_vectors.281717572
Directory /workspace/20.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha384_vectors.1549829792
Short name T461
Test name
Test status
Simulation time 66914229558 ps
CPU time 1837 seconds
Started Jun 24 06:17:47 PM PDT 24
Finished Jun 24 06:48:25 PM PDT 24
Peak memory 216400 kb
Host smart-237073ac-1cc2-43ab-9829-d9bb7977af01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1549829792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha384_vectors.1549829792
Directory /workspace/20.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha512_vectors.474448406
Short name T120
Test name
Test status
Simulation time 72001558802 ps
CPU time 1685.05 seconds
Started Jun 24 06:17:48 PM PDT 24
Finished Jun 24 06:45:54 PM PDT 24
Peak memory 215736 kb
Host smart-a9978dcc-f6ea-4d5f-80f8-f67d5ddc5e4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=474448406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha512_vectors.474448406
Directory /workspace/20.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2270309586
Short name T381
Test name
Test status
Simulation time 16040015804 ps
CPU time 80.02 seconds
Started Jun 24 06:17:50 PM PDT 24
Finished Jun 24 06:19:11 PM PDT 24
Peak memory 200120 kb
Host smart-5a390863-1787-4cfd-aacc-3681b601aeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270309586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2270309586
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2791075867
Short name T256
Test name
Test status
Simulation time 14648380 ps
CPU time 0.59 seconds
Started Jun 24 06:17:51 PM PDT 24
Finished Jun 24 06:17:52 PM PDT 24
Peak memory 195040 kb
Host smart-4c6f7425-c0ce-46d3-b9ce-cf976758baa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791075867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2791075867
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2888055836
Short name T13
Test name
Test status
Simulation time 8326819119 ps
CPU time 30.75 seconds
Started Jun 24 06:17:49 PM PDT 24
Finished Jun 24 06:18:20 PM PDT 24
Peak memory 200096 kb
Host smart-7f66f4de-6b6f-401f-9d5e-2d45ab21d0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888055836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2888055836
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3019947650
Short name T540
Test name
Test status
Simulation time 1699384863 ps
CPU time 401.91 seconds
Started Jun 24 06:17:50 PM PDT 24
Finished Jun 24 06:24:33 PM PDT 24
Peak memory 638060 kb
Host smart-82cf005d-2a37-4624-81ff-23df85189cfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3019947650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3019947650
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.774227971
Short name T121
Test name
Test status
Simulation time 92904616842 ps
CPU time 103.99 seconds
Started Jun 24 06:17:53 PM PDT 24
Finished Jun 24 06:19:38 PM PDT 24
Peak memory 200112 kb
Host smart-2a5d553b-85aa-4c31-898c-6751c9685285
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774227971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.774227971
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1327872363
Short name T275
Test name
Test status
Simulation time 7658303549 ps
CPU time 100.6 seconds
Started Jun 24 06:17:45 PM PDT 24
Finished Jun 24 06:19:26 PM PDT 24
Peak memory 200144 kb
Host smart-f9bdbb95-e024-42b5-93a6-a7144c7440d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327872363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1327872363
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2615942980
Short name T243
Test name
Test status
Simulation time 2248982541 ps
CPU time 13.27 seconds
Started Jun 24 06:17:49 PM PDT 24
Finished Jun 24 06:18:03 PM PDT 24
Peak memory 200152 kb
Host smart-d08a93ac-363d-4374-b82c-ed1e6ddd131d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615942980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2615942980
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.3012374617
Short name T622
Test name
Test status
Simulation time 399442718 ps
CPU time 1.13 seconds
Started Jun 24 06:17:52 PM PDT 24
Finished Jun 24 06:17:54 PM PDT 24
Peak memory 199984 kb
Host smart-9bfa6df9-ba8c-4822-bd61-10181c189600
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012374617 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_hmac_vectors.3012374617
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha256_vectors.2575429916
Short name T605
Test name
Test status
Simulation time 7833029901 ps
CPU time 429.49 seconds
Started Jun 24 06:17:49 PM PDT 24
Finished Jun 24 06:24:59 PM PDT 24
Peak memory 200120 kb
Host smart-9f1526cb-5168-40eb-867b-e84148d27091
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2575429916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha256_vectors.2575429916
Directory /workspace/21.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha384_vectors.3975242055
Short name T486
Test name
Test status
Simulation time 404403097096 ps
CPU time 1998.92 seconds
Started Jun 24 06:17:46 PM PDT 24
Finished Jun 24 06:51:06 PM PDT 24
Peak memory 216256 kb
Host smart-a07e44ba-4a3b-4ec6-bd9b-ae8d868e64f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3975242055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha384_vectors.3975242055
Directory /workspace/21.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha512_vectors.3798650815
Short name T258
Test name
Test status
Simulation time 136059006019 ps
CPU time 1942.59 seconds
Started Jun 24 06:17:47 PM PDT 24
Finished Jun 24 06:50:11 PM PDT 24
Peak memory 216032 kb
Host smart-71627006-3145-455f-bea2-f3e9d2577663
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3798650815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha512_vectors.3798650815
Directory /workspace/21.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1191980421
Short name T289
Test name
Test status
Simulation time 14196669447 ps
CPU time 68.78 seconds
Started Jun 24 06:17:47 PM PDT 24
Finished Jun 24 06:18:57 PM PDT 24
Peak memory 200136 kb
Host smart-b62375ed-7e3e-43ba-8f83-1ddb6338c32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191980421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1191980421
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.4268018326
Short name T330
Test name
Test status
Simulation time 21428101 ps
CPU time 0.59 seconds
Started Jun 24 06:18:29 PM PDT 24
Finished Jun 24 06:18:31 PM PDT 24
Peak memory 195668 kb
Host smart-2113ea7b-af13-4f6c-b9e8-cbd9e4b91bb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268018326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.4268018326
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3180427441
Short name T448
Test name
Test status
Simulation time 278122409 ps
CPU time 10.84 seconds
Started Jun 24 06:17:49 PM PDT 24
Finished Jun 24 06:18:01 PM PDT 24
Peak memory 200044 kb
Host smart-90521836-805c-4149-927a-f574ec54c002
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3180427441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3180427441
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2444799797
Short name T286
Test name
Test status
Simulation time 1455930231 ps
CPU time 28.75 seconds
Started Jun 24 06:18:26 PM PDT 24
Finished Jun 24 06:18:56 PM PDT 24
Peak memory 200012 kb
Host smart-2e715339-2591-46f5-bce8-0c0b72de7138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444799797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2444799797
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3366790345
Short name T331
Test name
Test status
Simulation time 4002757879 ps
CPU time 534.23 seconds
Started Jun 24 06:17:46 PM PDT 24
Finished Jun 24 06:26:42 PM PDT 24
Peak memory 514972 kb
Host smart-e146b1dc-925b-4f3d-88c0-e795974ff69a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3366790345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3366790345
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.122239222
Short name T229
Test name
Test status
Simulation time 12191630152 ps
CPU time 39.79 seconds
Started Jun 24 06:18:26 PM PDT 24
Finished Jun 24 06:19:07 PM PDT 24
Peak memory 200140 kb
Host smart-db447653-5af0-49e3-bf97-6501601bf845
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122239222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.122239222
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1335330101
Short name T305
Test name
Test status
Simulation time 784649786 ps
CPU time 46.92 seconds
Started Jun 24 06:17:53 PM PDT 24
Finished Jun 24 06:18:40 PM PDT 24
Peak memory 200080 kb
Host smart-fb90d8b8-bf4b-40b1-abe1-205cc24b4dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335330101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1335330101
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1595062334
Short name T636
Test name
Test status
Simulation time 497837371 ps
CPU time 7.13 seconds
Started Jun 24 06:17:46 PM PDT 24
Finished Jun 24 06:17:54 PM PDT 24
Peak memory 199992 kb
Host smart-04b3382a-0c5d-44f3-a3fb-53ce99a03622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595062334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1595062334
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.710134464
Short name T254
Test name
Test status
Simulation time 294250064 ps
CPU time 1.13 seconds
Started Jun 24 06:18:25 PM PDT 24
Finished Jun 24 06:18:27 PM PDT 24
Peak memory 200024 kb
Host smart-2936e2b6-eb3f-4cc0-9dd6-394daf25be56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710134464 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_hmac_vectors.710134464
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha256_vectors.1402092361
Short name T615
Test name
Test status
Simulation time 42702813051 ps
CPU time 546.15 seconds
Started Jun 24 06:18:31 PM PDT 24
Finished Jun 24 06:27:39 PM PDT 24
Peak memory 200120 kb
Host smart-48999af3-3dab-4934-aef8-47d64437d0f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1402092361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha256_vectors.1402092361
Directory /workspace/22.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha384_vectors.735532914
Short name T253
Test name
Test status
Simulation time 83773256098 ps
CPU time 1731.98 seconds
Started Jun 24 06:18:26 PM PDT 24
Finished Jun 24 06:47:19 PM PDT 24
Peak memory 216004 kb
Host smart-a333aaed-4826-426f-a894-ba03c2f9789c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=735532914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha384_vectors.735532914
Directory /workspace/22.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha512_vectors.3574017785
Short name T542
Test name
Test status
Simulation time 28194405792 ps
CPU time 1690.21 seconds
Started Jun 24 06:18:26 PM PDT 24
Finished Jun 24 06:46:38 PM PDT 24
Peak memory 216196 kb
Host smart-93335b10-c3d6-4e86-941a-c5989681e877
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3574017785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha512_vectors.3574017785
Directory /workspace/22.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.467969584
Short name T401
Test name
Test status
Simulation time 6509414064 ps
CPU time 70.96 seconds
Started Jun 24 06:18:19 PM PDT 24
Finished Jun 24 06:19:30 PM PDT 24
Peak memory 200052 kb
Host smart-855954b0-419e-43e6-85c4-87715abe6e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467969584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.467969584
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.221523077
Short name T187
Test name
Test status
Simulation time 35204904 ps
CPU time 0.61 seconds
Started Jun 24 06:18:31 PM PDT 24
Finished Jun 24 06:18:33 PM PDT 24
Peak memory 196716 kb
Host smart-26c20b25-9295-4129-ad71-a2abcc0f8e94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221523077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.221523077
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.21635279
Short name T28
Test name
Test status
Simulation time 1903330643 ps
CPU time 22.75 seconds
Started Jun 24 06:18:25 PM PDT 24
Finished Jun 24 06:18:48 PM PDT 24
Peak memory 200064 kb
Host smart-cae24a39-3c4a-4391-9a53-3c27c7e59cdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=21635279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.21635279
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3723573547
Short name T327
Test name
Test status
Simulation time 397735984 ps
CPU time 21.57 seconds
Started Jun 24 06:18:26 PM PDT 24
Finished Jun 24 06:18:48 PM PDT 24
Peak memory 200056 kb
Host smart-e332b547-7ab8-4e92-8a9e-cf6ba888789b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723573547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3723573547
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.685860205
Short name T563
Test name
Test status
Simulation time 74783424 ps
CPU time 6.53 seconds
Started Jun 24 06:18:26 PM PDT 24
Finished Jun 24 06:18:34 PM PDT 24
Peak memory 200244 kb
Host smart-ab98927f-5dc5-4c7a-b7d5-6f5e10051878
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=685860205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.685860205
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.550260371
Short name T132
Test name
Test status
Simulation time 806638645 ps
CPU time 43.48 seconds
Started Jun 24 06:18:26 PM PDT 24
Finished Jun 24 06:19:12 PM PDT 24
Peak memory 199984 kb
Host smart-a409b797-8305-4dc1-8dfe-ffbfe123964d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550260371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.550260371
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3421104630
Short name T422
Test name
Test status
Simulation time 18626469480 ps
CPU time 140.07 seconds
Started Jun 24 06:18:28 PM PDT 24
Finished Jun 24 06:20:49 PM PDT 24
Peak memory 208356 kb
Host smart-cbb8adcb-a302-4ab3-8c60-dbda044d416a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421104630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3421104630
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3834164724
Short name T476
Test name
Test status
Simulation time 105034600 ps
CPU time 1.83 seconds
Started Jun 24 06:18:26 PM PDT 24
Finished Jun 24 06:18:30 PM PDT 24
Peak memory 200068 kb
Host smart-8044fbe1-9e14-4adc-b990-b8bea1483e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834164724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3834164724
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.3896429557
Short name T625
Test name
Test status
Simulation time 67722977 ps
CPU time 1.24 seconds
Started Jun 24 06:18:25 PM PDT 24
Finished Jun 24 06:18:28 PM PDT 24
Peak memory 199776 kb
Host smart-c8894818-d9bd-4e3c-976b-56491c006ce7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896429557 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_hmac_vectors.3896429557
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha256_vectors.2224271366
Short name T631
Test name
Test status
Simulation time 45901852625 ps
CPU time 470.9 seconds
Started Jun 24 06:18:27 PM PDT 24
Finished Jun 24 06:26:20 PM PDT 24
Peak memory 200116 kb
Host smart-4e078abf-9911-449f-a6bf-582eae2e555d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2224271366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha256_vectors.2224271366
Directory /workspace/23.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha384_vectors.907969479
Short name T501
Test name
Test status
Simulation time 32190950858 ps
CPU time 1802.81 seconds
Started Jun 24 06:18:23 PM PDT 24
Finished Jun 24 06:48:27 PM PDT 24
Peak memory 215692 kb
Host smart-18e7e366-5532-4faa-9d78-1ef4493d9176
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=907969479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha384_vectors.907969479
Directory /workspace/23.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha512_vectors.3660375530
Short name T235
Test name
Test status
Simulation time 258946778713 ps
CPU time 1881.85 seconds
Started Jun 24 06:18:25 PM PDT 24
Finished Jun 24 06:49:47 PM PDT 24
Peak memory 215392 kb
Host smart-9671181a-cbb3-437f-beb8-60b48caea94e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3660375530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha512_vectors.3660375530
Directory /workspace/23.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2187436378
Short name T462
Test name
Test status
Simulation time 91838332609 ps
CPU time 98.58 seconds
Started Jun 24 06:18:26 PM PDT 24
Finished Jun 24 06:20:06 PM PDT 24
Peak memory 200148 kb
Host smart-b83a8651-af9a-4dc0-9265-241b3a319b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187436378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2187436378
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3192042702
Short name T328
Test name
Test status
Simulation time 20230408 ps
CPU time 0.58 seconds
Started Jun 24 06:18:27 PM PDT 24
Finished Jun 24 06:18:29 PM PDT 24
Peak memory 195968 kb
Host smart-3cb0810c-215d-4fd9-9685-4da8230a35bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192042702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3192042702
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1121473499
Short name T499
Test name
Test status
Simulation time 1213897233 ps
CPU time 53.5 seconds
Started Jun 24 06:18:26 PM PDT 24
Finished Jun 24 06:19:20 PM PDT 24
Peak memory 200072 kb
Host smart-4a606cb5-ff50-45f0-9203-49463c15f234
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1121473499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1121473499
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.955604029
Short name T150
Test name
Test status
Simulation time 35695259296 ps
CPU time 47.78 seconds
Started Jun 24 06:18:27 PM PDT 24
Finished Jun 24 06:19:16 PM PDT 24
Peak memory 200136 kb
Host smart-a8a5ecd7-d53a-413a-8d12-19221dfb7007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955604029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.955604029
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1516256146
Short name T273
Test name
Test status
Simulation time 17505949198 ps
CPU time 1104.72 seconds
Started Jun 24 06:18:26 PM PDT 24
Finished Jun 24 06:36:52 PM PDT 24
Peak memory 785668 kb
Host smart-a689322f-d25b-43a3-8a5f-42ba06846847
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1516256146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1516256146
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3089508657
Short name T637
Test name
Test status
Simulation time 38818267679 ps
CPU time 126.15 seconds
Started Jun 24 06:18:25 PM PDT 24
Finished Jun 24 06:20:31 PM PDT 24
Peak memory 200108 kb
Host smart-89e4515d-7bac-48f8-84b0-66af9cd2f5e2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089508657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3089508657
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3090890159
Short name T207
Test name
Test status
Simulation time 2742692356 ps
CPU time 38.25 seconds
Started Jun 24 06:18:25 PM PDT 24
Finished Jun 24 06:19:05 PM PDT 24
Peak memory 200120 kb
Host smart-aa2cb517-43ee-4449-aec1-1c24304feae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090890159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3090890159
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.405246890
Short name T216
Test name
Test status
Simulation time 1744847252 ps
CPU time 7.56 seconds
Started Jun 24 06:18:25 PM PDT 24
Finished Jun 24 06:18:33 PM PDT 24
Peak memory 200072 kb
Host smart-9ea832bf-21db-433f-8c17-23f30e079990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405246890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.405246890
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.1021695089
Short name T409
Test name
Test status
Simulation time 48297043 ps
CPU time 1.18 seconds
Started Jun 24 06:18:26 PM PDT 24
Finished Jun 24 06:18:29 PM PDT 24
Peak memory 200024 kb
Host smart-5dc52395-4565-4877-baee-39434d329846
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021695089 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_hmac_vectors.1021695089
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha256_vectors.449510756
Short name T18
Test name
Test status
Simulation time 52315887400 ps
CPU time 481.93 seconds
Started Jun 24 06:18:25 PM PDT 24
Finished Jun 24 06:26:28 PM PDT 24
Peak memory 200088 kb
Host smart-282151f5-16b8-48d2-bdd8-0856d2dc0c87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=449510756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha256_vectors.449510756
Directory /workspace/24.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha384_vectors.2312957140
Short name T334
Test name
Test status
Simulation time 680374827914 ps
CPU time 1984.09 seconds
Started Jun 24 06:18:25 PM PDT 24
Finished Jun 24 06:51:30 PM PDT 24
Peak memory 216244 kb
Host smart-3693e7cb-e344-4e77-b322-42ba00f3218e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2312957140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha384_vectors.2312957140
Directory /workspace/24.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha512_vectors.953285006
Short name T12
Test name
Test status
Simulation time 140063509366 ps
CPU time 2055.64 seconds
Started Jun 24 06:18:30 PM PDT 24
Finished Jun 24 06:52:48 PM PDT 24
Peak memory 215576 kb
Host smart-c6cba0f8-0cce-4a40-a273-dcfab4ee9430
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=953285006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha512_vectors.953285006
Directory /workspace/24.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2189658314
Short name T204
Test name
Test status
Simulation time 473505411 ps
CPU time 9.43 seconds
Started Jun 24 06:18:26 PM PDT 24
Finished Jun 24 06:18:37 PM PDT 24
Peak memory 199992 kb
Host smart-7ab39ac3-192a-4256-ba72-97fefd614b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189658314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2189658314
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2083364650
Short name T435
Test name
Test status
Simulation time 12930103 ps
CPU time 0.58 seconds
Started Jun 24 06:18:30 PM PDT 24
Finished Jun 24 06:18:32 PM PDT 24
Peak memory 196748 kb
Host smart-9fa64916-92e6-47ea-9419-b9020365e480
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083364650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2083364650
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1300382750
Short name T5
Test name
Test status
Simulation time 1270009012 ps
CPU time 31.64 seconds
Started Jun 24 06:18:32 PM PDT 24
Finished Jun 24 06:19:05 PM PDT 24
Peak memory 200064 kb
Host smart-d83620e9-ba75-43c5-9300-0b536c2cdf33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1300382750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1300382750
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.4282890327
Short name T595
Test name
Test status
Simulation time 18004399784 ps
CPU time 54.27 seconds
Started Jun 24 06:18:29 PM PDT 24
Finished Jun 24 06:19:24 PM PDT 24
Peak memory 208528 kb
Host smart-4b4e7305-02f8-4d3c-89fb-24f56536bf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282890327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.4282890327
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2881624304
Short name T280
Test name
Test status
Simulation time 3053665713 ps
CPU time 542.34 seconds
Started Jun 24 06:18:32 PM PDT 24
Finished Jun 24 06:27:35 PM PDT 24
Peak memory 736788 kb
Host smart-67d26a9d-2324-43aa-a32a-e1ce5b7bb978
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2881624304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2881624304
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2656245272
Short name T449
Test name
Test status
Simulation time 557773049 ps
CPU time 3.06 seconds
Started Jun 24 06:18:30 PM PDT 24
Finished Jun 24 06:18:34 PM PDT 24
Peak memory 199992 kb
Host smart-a58206f8-a6e7-4eae-a156-3db3e9508eee
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656245272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2656245272
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.109003110
Short name T58
Test name
Test status
Simulation time 33233596439 ps
CPU time 70.4 seconds
Started Jun 24 06:18:28 PM PDT 24
Finished Jun 24 06:19:39 PM PDT 24
Peak memory 216536 kb
Host smart-7ffbb07a-05fd-4816-858e-ba497f297682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109003110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.109003110
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1024683485
Short name T584
Test name
Test status
Simulation time 36724630 ps
CPU time 1.96 seconds
Started Jun 24 06:18:29 PM PDT 24
Finished Jun 24 06:18:32 PM PDT 24
Peak memory 199996 kb
Host smart-4a7dcc51-263d-42fa-8007-cafdfff66abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024683485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1024683485
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.92957540
Short name T285
Test name
Test status
Simulation time 83685993 ps
CPU time 1.33 seconds
Started Jun 24 06:18:28 PM PDT 24
Finished Jun 24 06:18:30 PM PDT 24
Peak memory 200056 kb
Host smart-0282c04a-27fa-430b-bedb-0009978bc498
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92957540 -assert nopostpro
c +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_hmac_vectors.92957540
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha256_vectors.2044435408
Short name T196
Test name
Test status
Simulation time 70639609542 ps
CPU time 546.49 seconds
Started Jun 24 06:18:28 PM PDT 24
Finished Jun 24 06:27:36 PM PDT 24
Peak memory 200092 kb
Host smart-37322548-a5c5-41d7-843e-3ba956ba124b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2044435408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha256_vectors.2044435408
Directory /workspace/25.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha512_vectors.4209880941
Short name T193
Test name
Test status
Simulation time 112277864529 ps
CPU time 1940.9 seconds
Started Jun 24 06:18:32 PM PDT 24
Finished Jun 24 06:50:54 PM PDT 24
Peak memory 215544 kb
Host smart-46e21e16-203e-4fb9-8404-45fb074354db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4209880941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha512_vectors.4209880941
Directory /workspace/25.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2012961993
Short name T641
Test name
Test status
Simulation time 3615973125 ps
CPU time 56.55 seconds
Started Jun 24 06:18:34 PM PDT 24
Finished Jun 24 06:19:31 PM PDT 24
Peak memory 200068 kb
Host smart-90e785e0-dc30-469e-a110-45d6eab3a28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012961993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2012961993
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1097228730
Short name T460
Test name
Test status
Simulation time 16708288 ps
CPU time 0.56 seconds
Started Jun 24 06:18:31 PM PDT 24
Finished Jun 24 06:18:33 PM PDT 24
Peak memory 194952 kb
Host smart-fdd376f4-6a3f-4148-ab53-f80d889f3e84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097228730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1097228730
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.179268744
Short name T440
Test name
Test status
Simulation time 3771298338 ps
CPU time 54.91 seconds
Started Jun 24 06:18:29 PM PDT 24
Finished Jun 24 06:19:25 PM PDT 24
Peak memory 200104 kb
Host smart-385be417-d1da-4fc0-8cce-f269fb7486ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179268744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.179268744
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_error.2050843814
Short name T559
Test name
Test status
Simulation time 11811400253 ps
CPU time 88.5 seconds
Started Jun 24 06:18:30 PM PDT 24
Finished Jun 24 06:20:00 PM PDT 24
Peak memory 200132 kb
Host smart-f20593be-45a0-49eb-9430-16bdbd0997ce
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050843814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2050843814
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3718005428
Short name T271
Test name
Test status
Simulation time 33666536843 ps
CPU time 120.26 seconds
Started Jun 24 06:18:29 PM PDT 24
Finished Jun 24 06:20:30 PM PDT 24
Peak memory 200112 kb
Host smart-d087920b-1d01-4030-ace6-e9d29501e4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718005428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3718005428
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.1665355697
Short name T523
Test name
Test status
Simulation time 242528202 ps
CPU time 6.6 seconds
Started Jun 24 06:18:32 PM PDT 24
Finished Jun 24 06:18:40 PM PDT 24
Peak memory 200100 kb
Host smart-0a244967-3faf-4c21-9392-a687b03ce5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665355697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1665355697
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.671061477
Short name T380
Test name
Test status
Simulation time 3645617626 ps
CPU time 13.53 seconds
Started Jun 24 06:18:30 PM PDT 24
Finished Jun 24 06:18:44 PM PDT 24
Peak memory 200120 kb
Host smart-334ffb46-47e0-40d8-babf-0fdb003597ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671061477 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.671061477
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.2722107931
Short name T333
Test name
Test status
Simulation time 31271638 ps
CPU time 1.28 seconds
Started Jun 24 06:18:29 PM PDT 24
Finished Jun 24 06:18:31 PM PDT 24
Peak memory 200064 kb
Host smart-6562740e-0314-43c8-8097-b6c89a70d533
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722107931 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_hmac_vectors.2722107931
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha256_vectors.873909104
Short name T633
Test name
Test status
Simulation time 34657182229 ps
CPU time 508.61 seconds
Started Jun 24 06:18:30 PM PDT 24
Finished Jun 24 06:27:00 PM PDT 24
Peak memory 200120 kb
Host smart-962cdc17-3e3b-4197-b2e4-6ac50a7f8e5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=873909104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha256_vectors.873909104
Directory /workspace/26.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha384_vectors.3271536735
Short name T398
Test name
Test status
Simulation time 154151576376 ps
CPU time 1898.3 seconds
Started Jun 24 06:18:28 PM PDT 24
Finished Jun 24 06:50:08 PM PDT 24
Peak memory 216000 kb
Host smart-26d1a39f-ed27-46fc-91eb-f7e0cbc7bf95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3271536735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha384_vectors.3271536735
Directory /workspace/26.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha512_vectors.483097495
Short name T565
Test name
Test status
Simulation time 152233209186 ps
CPU time 1698.45 seconds
Started Jun 24 06:18:33 PM PDT 24
Finished Jun 24 06:46:52 PM PDT 24
Peak memory 216008 kb
Host smart-88ae2ce5-7f72-4e66-82ff-17a534815ab8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=483097495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha512_vectors.483097495
Directory /workspace/26.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1033188762
Short name T96
Test name
Test status
Simulation time 22382171753 ps
CPU time 71.94 seconds
Started Jun 24 06:18:26 PM PDT 24
Finished Jun 24 06:19:39 PM PDT 24
Peak memory 200172 kb
Host smart-06245d7b-3ded-42d0-ad7b-027f1148d4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033188762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1033188762
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.4233940653
Short name T504
Test name
Test status
Simulation time 14229097 ps
CPU time 0.59 seconds
Started Jun 24 06:18:33 PM PDT 24
Finished Jun 24 06:18:35 PM PDT 24
Peak memory 194964 kb
Host smart-f9fb5837-d7ca-4504-81b3-27f30b77407e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233940653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.4233940653
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.308696702
Short name T314
Test name
Test status
Simulation time 3142527023 ps
CPU time 41.12 seconds
Started Jun 24 06:18:30 PM PDT 24
Finished Jun 24 06:19:12 PM PDT 24
Peak memory 200140 kb
Host smart-5dd78dee-d465-4619-a7b9-d44af61ba77f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=308696702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.308696702
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.4135984898
Short name T640
Test name
Test status
Simulation time 7714461856 ps
CPU time 35.11 seconds
Started Jun 24 06:18:35 PM PDT 24
Finished Jun 24 06:19:11 PM PDT 24
Peak memory 200392 kb
Host smart-841011c8-0c26-447d-961f-a3d2ddcd39b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135984898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.4135984898
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.798108286
Short name T492
Test name
Test status
Simulation time 13828541836 ps
CPU time 1105.44 seconds
Started Jun 24 06:18:32 PM PDT 24
Finished Jun 24 06:36:59 PM PDT 24
Peak memory 684840 kb
Host smart-2a6b1d49-a5a9-496e-8a0d-3f0bd0ede82c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=798108286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.798108286
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2926942482
Short name T509
Test name
Test status
Simulation time 7971459841 ps
CPU time 104.47 seconds
Started Jun 24 06:18:35 PM PDT 24
Finished Jun 24 06:20:20 PM PDT 24
Peak memory 200108 kb
Host smart-557b7fe0-3dd1-4f4c-9e98-b4a6a617da6a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926942482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2926942482
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3085373503
Short name T616
Test name
Test status
Simulation time 4763596743 ps
CPU time 96.4 seconds
Started Jun 24 06:18:31 PM PDT 24
Finished Jun 24 06:20:09 PM PDT 24
Peak memory 216444 kb
Host smart-2ddc6ee0-4eb9-470d-9862-631a7c2a9df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085373503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3085373503
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3668926115
Short name T226
Test name
Test status
Simulation time 159804155 ps
CPU time 7.19 seconds
Started Jun 24 06:18:31 PM PDT 24
Finished Jun 24 06:18:39 PM PDT 24
Peak memory 200072 kb
Host smart-d21547f9-9cbd-46ad-990f-f15b9e5a0171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668926115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3668926115
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3130950217
Short name T425
Test name
Test status
Simulation time 6217834945 ps
CPU time 109.5 seconds
Started Jun 24 06:18:38 PM PDT 24
Finished Jun 24 06:20:28 PM PDT 24
Peak memory 200140 kb
Host smart-b17cd2dc-2e07-4da8-a60e-74334375cf99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130950217 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3130950217
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.204854765
Short name T311
Test name
Test status
Simulation time 63854812 ps
CPU time 1.27 seconds
Started Jun 24 06:18:34 PM PDT 24
Finished Jun 24 06:18:37 PM PDT 24
Peak memory 200004 kb
Host smart-0a808844-d9a1-4964-897a-ccc4a42593e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204854765 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_hmac_vectors.204854765
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha256_vectors.513300859
Short name T496
Test name
Test status
Simulation time 110550662818 ps
CPU time 435.91 seconds
Started Jun 24 06:18:31 PM PDT 24
Finished Jun 24 06:25:48 PM PDT 24
Peak memory 200156 kb
Host smart-b5f2382b-34c8-4047-b95d-7332fd302ab0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=513300859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha256_vectors.513300859
Directory /workspace/27.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha384_vectors.748297869
Short name T522
Test name
Test status
Simulation time 247823926029 ps
CPU time 1971.96 seconds
Started Jun 24 06:18:33 PM PDT 24
Finished Jun 24 06:51:26 PM PDT 24
Peak memory 216364 kb
Host smart-eeb7cef3-a8a5-48a7-b2ae-a5b5e7ac4093
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=748297869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha384_vectors.748297869
Directory /workspace/27.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha512_vectors.1741863166
Short name T174
Test name
Test status
Simulation time 196627688448 ps
CPU time 1802.59 seconds
Started Jun 24 06:18:34 PM PDT 24
Finished Jun 24 06:48:37 PM PDT 24
Peak memory 216528 kb
Host smart-ac97f208-952f-448b-99cc-3267252616c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1741863166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha512_vectors.1741863166
Directory /workspace/27.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.658639223
Short name T93
Test name
Test status
Simulation time 9020416274 ps
CPU time 74.47 seconds
Started Jun 24 06:18:34 PM PDT 24
Finished Jun 24 06:19:49 PM PDT 24
Peak memory 200128 kb
Host smart-cf342470-f79f-4b44-b082-25c70aeac85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658639223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.658639223
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2127015185
Short name T251
Test name
Test status
Simulation time 13606434 ps
CPU time 0.59 seconds
Started Jun 24 06:18:33 PM PDT 24
Finished Jun 24 06:18:34 PM PDT 24
Peak memory 195996 kb
Host smart-0c0dd8af-aad7-472e-91eb-5ded40a3d3b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127015185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2127015185
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3699332901
Short name T276
Test name
Test status
Simulation time 7446661404 ps
CPU time 22.43 seconds
Started Jun 24 06:18:32 PM PDT 24
Finished Jun 24 06:18:56 PM PDT 24
Peak memory 216500 kb
Host smart-a28178b9-8d88-4c00-959c-16e3c5d28f14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3699332901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3699332901
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3595873792
Short name T369
Test name
Test status
Simulation time 8919337459 ps
CPU time 46.6 seconds
Started Jun 24 06:18:34 PM PDT 24
Finished Jun 24 06:19:22 PM PDT 24
Peak memory 200408 kb
Host smart-cac98ba2-9ad4-43ac-b389-a471b182b3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595873792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3595873792
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1566027241
Short name T651
Test name
Test status
Simulation time 6038453623 ps
CPU time 413.22 seconds
Started Jun 24 06:18:38 PM PDT 24
Finished Jun 24 06:25:32 PM PDT 24
Peak memory 644140 kb
Host smart-864b077c-332c-4418-9819-7e8093d3063e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1566027241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1566027241
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.4258375569
Short name T227
Test name
Test status
Simulation time 985508686 ps
CPU time 55.41 seconds
Started Jun 24 06:18:37 PM PDT 24
Finished Jun 24 06:19:34 PM PDT 24
Peak memory 200060 kb
Host smart-c73576dc-b664-4b3f-86d1-8d9b0e867cc6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258375569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.4258375569
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2607060028
Short name T424
Test name
Test status
Simulation time 1003558453 ps
CPU time 59.73 seconds
Started Jun 24 06:18:36 PM PDT 24
Finished Jun 24 06:19:37 PM PDT 24
Peak memory 200092 kb
Host smart-79004cf2-1367-4765-9710-a1e5fd3a1058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607060028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2607060028
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2595637616
Short name T269
Test name
Test status
Simulation time 323684403 ps
CPU time 3.18 seconds
Started Jun 24 06:18:33 PM PDT 24
Finished Jun 24 06:18:37 PM PDT 24
Peak memory 200072 kb
Host smart-a3a1aa71-4716-4476-9789-3769f4baeab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595637616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2595637616
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3323385871
Short name T603
Test name
Test status
Simulation time 30811587232 ps
CPU time 285.9 seconds
Started Jun 24 06:18:38 PM PDT 24
Finished Jun 24 06:23:25 PM PDT 24
Peak memory 200116 kb
Host smart-6ee9a6cb-94b5-467f-a92b-2555a2f2d6a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323385871 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3323385871
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.1754174334
Short name T659
Test name
Test status
Simulation time 89913570 ps
CPU time 1.1 seconds
Started Jun 24 06:18:38 PM PDT 24
Finished Jun 24 06:18:40 PM PDT 24
Peak memory 200048 kb
Host smart-62291d09-e9eb-4173-a98a-859eb4d168cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754174334 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_hmac_vectors.1754174334
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha256_vectors.1404554963
Short name T277
Test name
Test status
Simulation time 28382423083 ps
CPU time 459.55 seconds
Started Jun 24 06:18:35 PM PDT 24
Finished Jun 24 06:26:16 PM PDT 24
Peak memory 200136 kb
Host smart-c9e2d06a-bb84-485e-9e67-a47a18abb8df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1404554963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha256_vectors.1404554963
Directory /workspace/28.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha384_vectors.885592656
Short name T630
Test name
Test status
Simulation time 566138301339 ps
CPU time 2152.61 seconds
Started Jun 24 06:18:31 PM PDT 24
Finished Jun 24 06:54:26 PM PDT 24
Peak memory 215648 kb
Host smart-40ee50f7-9bef-428b-a51b-7e642d15abc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=885592656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha384_vectors.885592656
Directory /workspace/28.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha512_vectors.2417387
Short name T652
Test name
Test status
Simulation time 404281046032 ps
CPU time 1770 seconds
Started Jun 24 06:18:34 PM PDT 24
Finished Jun 24 06:48:05 PM PDT 24
Peak memory 216380 kb
Host smart-db3fdff5-94c7-4888-8d1f-b39b2770c684
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2417387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha512_vectors.2417387
Directory /workspace/28.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.4144067994
Short name T20
Test name
Test status
Simulation time 3291074909 ps
CPU time 72.52 seconds
Started Jun 24 06:18:35 PM PDT 24
Finished Jun 24 06:19:48 PM PDT 24
Peak memory 200160 kb
Host smart-b98ed5b7-e060-4bb9-8a14-8a3dcba865d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144067994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.4144067994
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1566846213
Short name T426
Test name
Test status
Simulation time 128932120 ps
CPU time 0.57 seconds
Started Jun 24 06:18:26 PM PDT 24
Finished Jun 24 06:18:29 PM PDT 24
Peak memory 194996 kb
Host smart-c5a02d14-f9ac-41d9-a384-aea6592772f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566846213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1566846213
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3655455607
Short name T639
Test name
Test status
Simulation time 1816770529 ps
CPU time 25.82 seconds
Started Jun 24 06:18:42 PM PDT 24
Finished Jun 24 06:19:09 PM PDT 24
Peak memory 200064 kb
Host smart-28c0623f-5f60-4f72-9613-7e651cf40ee2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3655455607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3655455607
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1114647324
Short name T143
Test name
Test status
Simulation time 4454480544 ps
CPU time 64.82 seconds
Started Jun 24 06:18:40 PM PDT 24
Finished Jun 24 06:19:47 PM PDT 24
Peak memory 200088 kb
Host smart-4a2299bf-b6b3-4a67-aa7f-76a0155a1946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114647324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1114647324
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.2268901163
Short name T352
Test name
Test status
Simulation time 10608388477 ps
CPU time 753.4 seconds
Started Jun 24 06:18:40 PM PDT 24
Finished Jun 24 06:31:15 PM PDT 24
Peak memory 681456 kb
Host smart-a9544d0a-5138-4582-a93e-02c108299770
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2268901163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2268901163
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2099450397
Short name T417
Test name
Test status
Simulation time 2937024570 ps
CPU time 45.99 seconds
Started Jun 24 06:18:39 PM PDT 24
Finished Jun 24 06:19:27 PM PDT 24
Peak memory 200112 kb
Host smart-05779891-a83e-453a-a9a0-e6cbba7e7a18
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099450397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2099450397
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1659038482
Short name T638
Test name
Test status
Simulation time 6290191712 ps
CPU time 96.8 seconds
Started Jun 24 06:18:41 PM PDT 24
Finished Jun 24 06:20:19 PM PDT 24
Peak memory 208332 kb
Host smart-85415e27-38cd-4b18-a2ae-2d4647c2b0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659038482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1659038482
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.404685693
Short name T543
Test name
Test status
Simulation time 415936560 ps
CPU time 8.4 seconds
Started Jun 24 06:18:37 PM PDT 24
Finished Jun 24 06:18:46 PM PDT 24
Peak memory 200004 kb
Host smart-1b2c0985-a789-4d5b-bd1a-070c04c2df98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404685693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.404685693
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.825610823
Short name T179
Test name
Test status
Simulation time 46752010 ps
CPU time 1.1 seconds
Started Jun 24 06:18:38 PM PDT 24
Finished Jun 24 06:18:40 PM PDT 24
Peak memory 199796 kb
Host smart-ad405ee6-354c-466d-a492-8bbbc195af04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825610823 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_hmac_vectors.825610823
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha256_vectors.3277507663
Short name T552
Test name
Test status
Simulation time 34541724138 ps
CPU time 471.68 seconds
Started Jun 24 06:18:36 PM PDT 24
Finished Jun 24 06:26:29 PM PDT 24
Peak memory 200124 kb
Host smart-b28d8a29-7933-4b7c-8b47-63e68cb5f6e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3277507663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha256_vectors.3277507663
Directory /workspace/29.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha384_vectors.3278988256
Short name T589
Test name
Test status
Simulation time 28741572463 ps
CPU time 1721.8 seconds
Started Jun 24 06:18:38 PM PDT 24
Finished Jun 24 06:47:22 PM PDT 24
Peak memory 216088 kb
Host smart-e0159776-1cb8-47be-8624-b152c50429a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3278988256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha384_vectors.3278988256
Directory /workspace/29.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1526777876
Short name T505
Test name
Test status
Simulation time 14612504808 ps
CPU time 30.5 seconds
Started Jun 24 06:18:33 PM PDT 24
Finished Jun 24 06:19:05 PM PDT 24
Peak memory 200136 kb
Host smart-52da224e-c874-4704-b836-808a53785b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526777876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1526777876
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.4145087504
Short name T573
Test name
Test status
Simulation time 35184739 ps
CPU time 0.59 seconds
Started Jun 24 06:16:56 PM PDT 24
Finished Jun 24 06:16:58 PM PDT 24
Peak memory 196060 kb
Host smart-31dc614e-98a2-43e9-ba0b-755fc617da5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145087504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.4145087504
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.691511845
Short name T237
Test name
Test status
Simulation time 467903291 ps
CPU time 24.15 seconds
Started Jun 24 06:17:00 PM PDT 24
Finished Jun 24 06:17:25 PM PDT 24
Peak memory 200040 kb
Host smart-816d0872-6861-40de-8081-52dcc0fd02c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=691511845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.691511845
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2126868477
Short name T353
Test name
Test status
Simulation time 21301603449 ps
CPU time 913.72 seconds
Started Jun 24 06:16:56 PM PDT 24
Finished Jun 24 06:32:12 PM PDT 24
Peak memory 712268 kb
Host smart-f22766b8-b5da-434b-8be5-f5db4cb1d668
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2126868477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2126868477
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.906299376
Short name T429
Test name
Test status
Simulation time 29830382206 ps
CPU time 160.96 seconds
Started Jun 24 06:16:56 PM PDT 24
Finished Jun 24 06:19:39 PM PDT 24
Peak memory 200132 kb
Host smart-578b50cd-e143-4e85-b36d-53ff5f000097
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906299376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.906299376
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2713380126
Short name T566
Test name
Test status
Simulation time 16259153842 ps
CPU time 63.77 seconds
Started Jun 24 06:17:01 PM PDT 24
Finished Jun 24 06:18:06 PM PDT 24
Peak memory 200212 kb
Host smart-f9ac0cc4-0e72-493b-9a54-2261a428a6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713380126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2713380126
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1058989627
Short name T48
Test name
Test status
Simulation time 289011423 ps
CPU time 0.93 seconds
Started Jun 24 06:16:57 PM PDT 24
Finished Jun 24 06:16:59 PM PDT 24
Peak memory 218184 kb
Host smart-3671235c-c8e7-4e5a-875e-ec88f4635425
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058989627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1058989627
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.2845237217
Short name T471
Test name
Test status
Simulation time 446163278 ps
CPU time 6.91 seconds
Started Jun 24 06:16:56 PM PDT 24
Finished Jun 24 06:17:05 PM PDT 24
Peak memory 200100 kb
Host smart-5a005144-aae6-4bd4-8412-50266bd24e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845237217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2845237217
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.793593273
Short name T451
Test name
Test status
Simulation time 133717741 ps
CPU time 1.07 seconds
Started Jun 24 06:16:56 PM PDT 24
Finished Jun 24 06:16:59 PM PDT 24
Peak memory 199780 kb
Host smart-4dceda92-3762-4db1-b049-9385559943f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793593273 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac_vectors.793593273
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.575491174
Short name T35
Test name
Test status
Simulation time 152536226222 ps
CPU time 548.68 seconds
Started Jun 24 06:16:56 PM PDT 24
Finished Jun 24 06:26:07 PM PDT 24
Peak memory 200144 kb
Host smart-eff46cd9-61cb-445a-826b-82767c3f1c40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=575491174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.575491174
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.394510832
Short name T355
Test name
Test status
Simulation time 58880335780 ps
CPU time 1743.22 seconds
Started Jun 24 06:17:04 PM PDT 24
Finished Jun 24 06:46:08 PM PDT 24
Peak memory 215628 kb
Host smart-e5112838-5615-4eb8-a5ad-1244a18561af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=394510832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.394510832
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.2083529942
Short name T628
Test name
Test status
Simulation time 617370722716 ps
CPU time 1748.29 seconds
Started Jun 24 06:16:57 PM PDT 24
Finished Jun 24 06:46:07 PM PDT 24
Peak memory 215616 kb
Host smart-b00c3dd9-e601-4043-97ae-b24938926515
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2083529942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2083529942
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2871505028
Short name T203
Test name
Test status
Simulation time 980724320 ps
CPU time 6.24 seconds
Started Jun 24 06:17:00 PM PDT 24
Finished Jun 24 06:17:07 PM PDT 24
Peak memory 200012 kb
Host smart-ac258c9e-7ccd-47b7-b1ca-bf98e02a66e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871505028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2871505028
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1255471007
Short name T191
Test name
Test status
Simulation time 18416248 ps
CPU time 0.6 seconds
Started Jun 24 06:18:38 PM PDT 24
Finished Jun 24 06:18:40 PM PDT 24
Peak memory 196292 kb
Host smart-5f133efc-645f-4f3d-8cb3-23971d686dc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255471007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1255471007
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2854181714
Short name T25
Test name
Test status
Simulation time 97138736 ps
CPU time 5.52 seconds
Started Jun 24 06:18:45 PM PDT 24
Finished Jun 24 06:18:52 PM PDT 24
Peak memory 200048 kb
Host smart-8140ec6c-2f8c-4e60-bed4-a3c66581bf0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2854181714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2854181714
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.596300109
Short name T299
Test name
Test status
Simulation time 3278345482 ps
CPU time 56.92 seconds
Started Jun 24 06:18:34 PM PDT 24
Finished Jun 24 06:19:32 PM PDT 24
Peak memory 200132 kb
Host smart-3e7b9d92-a066-4585-97b8-ec372105472e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596300109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.596300109
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1376840331
Short name T81
Test name
Test status
Simulation time 11763911949 ps
CPU time 1334.9 seconds
Started Jun 24 06:18:37 PM PDT 24
Finished Jun 24 06:40:54 PM PDT 24
Peak memory 785396 kb
Host smart-22e6623d-8f0f-4892-b974-ea1a75352d32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1376840331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1376840331
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.700140153
Short name T582
Test name
Test status
Simulation time 80450183741 ps
CPU time 150.57 seconds
Started Jun 24 06:18:41 PM PDT 24
Finished Jun 24 06:21:13 PM PDT 24
Peak memory 200132 kb
Host smart-8dc986d6-3471-4377-b395-d1499cc98535
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700140153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.700140153
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3472639798
Short name T503
Test name
Test status
Simulation time 150659960 ps
CPU time 9.19 seconds
Started Jun 24 06:18:38 PM PDT 24
Finished Jun 24 06:18:48 PM PDT 24
Peak memory 200060 kb
Host smart-8f8de702-3133-446b-8088-5cfb97c451c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472639798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3472639798
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2155856782
Short name T287
Test name
Test status
Simulation time 1361891305 ps
CPU time 8.01 seconds
Started Jun 24 06:18:36 PM PDT 24
Finished Jun 24 06:18:45 PM PDT 24
Peak memory 200068 kb
Host smart-81668f43-11b6-4d70-8e48-2dcc0a855773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155856782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2155856782
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.2317019249
Short name T36
Test name
Test status
Simulation time 56515823 ps
CPU time 1.11 seconds
Started Jun 24 06:18:38 PM PDT 24
Finished Jun 24 06:18:41 PM PDT 24
Peak memory 199980 kb
Host smart-857324d7-58f7-4b13-b504-b63b50b593cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317019249 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_hmac_vectors.2317019249
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha256_vectors.2229616673
Short name T423
Test name
Test status
Simulation time 33830322747 ps
CPU time 455.21 seconds
Started Jun 24 06:18:40 PM PDT 24
Finished Jun 24 06:26:17 PM PDT 24
Peak memory 200132 kb
Host smart-267ed22b-7417-4115-9896-fd4b848bd57f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2229616673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha256_vectors.2229616673
Directory /workspace/30.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha384_vectors.136410371
Short name T263
Test name
Test status
Simulation time 448011112782 ps
CPU time 1986.1 seconds
Started Jun 24 06:18:38 PM PDT 24
Finished Jun 24 06:51:46 PM PDT 24
Peak memory 215612 kb
Host smart-f551feaf-4529-4eb9-8636-18f7d1f725a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=136410371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha384_vectors.136410371
Directory /workspace/30.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha512_vectors.3971236081
Short name T612
Test name
Test status
Simulation time 121048184786 ps
CPU time 1707.76 seconds
Started Jun 24 06:18:40 PM PDT 24
Finished Jun 24 06:47:10 PM PDT 24
Peak memory 216348 kb
Host smart-0a500504-1c22-4f88-a8f2-a1f9ed6da7d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3971236081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha512_vectors.3971236081
Directory /workspace/30.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3020652332
Short name T181
Test name
Test status
Simulation time 849386224 ps
CPU time 6.95 seconds
Started Jun 24 06:18:40 PM PDT 24
Finished Jun 24 06:18:48 PM PDT 24
Peak memory 200112 kb
Host smart-1e09cc34-267f-4b87-8d43-6e8800d26d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020652332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3020652332
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.4020528091
Short name T41
Test name
Test status
Simulation time 42112621 ps
CPU time 0.6 seconds
Started Jun 24 06:18:44 PM PDT 24
Finished Jun 24 06:18:46 PM PDT 24
Peak memory 195036 kb
Host smart-84cc27bd-5b16-4a9e-8e65-53ac64c106b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020528091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.4020528091
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.248499817
Short name T363
Test name
Test status
Simulation time 7875927664 ps
CPU time 20.96 seconds
Started Jun 24 06:18:38 PM PDT 24
Finished Jun 24 06:19:00 PM PDT 24
Peak memory 200172 kb
Host smart-074016ba-233d-46e6-9899-2ae73b072aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248499817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.248499817
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_error.2034411178
Short name T133
Test name
Test status
Simulation time 63697134043 ps
CPU time 148.81 seconds
Started Jun 24 06:18:42 PM PDT 24
Finished Jun 24 06:21:13 PM PDT 24
Peak memory 200100 kb
Host smart-3629d4c5-f5ea-46d0-89bc-147ac0ac4338
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034411178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2034411178
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1691704330
Short name T364
Test name
Test status
Simulation time 4733100337 ps
CPU time 76.78 seconds
Started Jun 24 06:18:36 PM PDT 24
Finished Jun 24 06:19:54 PM PDT 24
Peak memory 200116 kb
Host smart-571aca2f-c7c0-4e62-8220-4e28d09732a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691704330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1691704330
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2642720509
Short name T661
Test name
Test status
Simulation time 1807536811 ps
CPU time 9.85 seconds
Started Jun 24 06:18:38 PM PDT 24
Finished Jun 24 06:18:49 PM PDT 24
Peak memory 200064 kb
Host smart-948b2a73-dd88-4735-8ce5-9a6318132675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642720509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2642720509
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.3742625892
Short name T212
Test name
Test status
Simulation time 237329684 ps
CPU time 1.09 seconds
Started Jun 24 06:18:38 PM PDT 24
Finished Jun 24 06:18:40 PM PDT 24
Peak memory 200032 kb
Host smart-0a4c6dd1-e423-43e8-a145-62f2aed16d45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742625892 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_hmac_vectors.3742625892
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha256_vectors.210811556
Short name T252
Test name
Test status
Simulation time 239836881243 ps
CPU time 528.8 seconds
Started Jun 24 06:18:44 PM PDT 24
Finished Jun 24 06:27:34 PM PDT 24
Peak memory 200116 kb
Host smart-9dee7aad-b4f9-4144-8008-cd1d7008ae69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=210811556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha256_vectors.210811556
Directory /workspace/31.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha384_vectors.3684412304
Short name T608
Test name
Test status
Simulation time 123615647069 ps
CPU time 1715.8 seconds
Started Jun 24 06:18:38 PM PDT 24
Finished Jun 24 06:47:16 PM PDT 24
Peak memory 216540 kb
Host smart-748def48-f0c4-4455-8b14-60326f95226f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3684412304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha384_vectors.3684412304
Directory /workspace/31.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha512_vectors.2465674826
Short name T378
Test name
Test status
Simulation time 112749958457 ps
CPU time 1743.97 seconds
Started Jun 24 06:18:44 PM PDT 24
Finished Jun 24 06:47:49 PM PDT 24
Peak memory 215616 kb
Host smart-d8b8a5c8-fe48-47c8-962c-be5eb88db3cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2465674826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha512_vectors.2465674826
Directory /workspace/31.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1755404216
Short name T419
Test name
Test status
Simulation time 3507858590 ps
CPU time 13.59 seconds
Started Jun 24 06:18:44 PM PDT 24
Finished Jun 24 06:19:00 PM PDT 24
Peak memory 200156 kb
Host smart-8ba1efcc-38d4-4ac5-becb-9c637b83f3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755404216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1755404216
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1647020167
Short name T39
Test name
Test status
Simulation time 125145851 ps
CPU time 0.6 seconds
Started Jun 24 06:18:47 PM PDT 24
Finished Jun 24 06:18:48 PM PDT 24
Peak memory 194968 kb
Host smart-a5b70865-229c-4ec2-91c5-90ea1db69081
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647020167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1647020167
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3267127541
Short name T23
Test name
Test status
Simulation time 262449352 ps
CPU time 9.98 seconds
Started Jun 24 06:18:42 PM PDT 24
Finished Jun 24 06:18:54 PM PDT 24
Peak memory 200080 kb
Host smart-c2ab02f7-58a0-4e60-9a87-ed72e5e96f7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3267127541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3267127541
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.89792357
Short name T623
Test name
Test status
Simulation time 3447375420 ps
CPU time 41.78 seconds
Started Jun 24 06:18:41 PM PDT 24
Finished Jun 24 06:19:24 PM PDT 24
Peak memory 200080 kb
Host smart-fdf19d00-1126-453c-b6ad-c3eebb57c098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89792357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.89792357
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.975379550
Short name T54
Test name
Test status
Simulation time 4903759127 ps
CPU time 541.72 seconds
Started Jun 24 06:18:41 PM PDT 24
Finished Jun 24 06:27:44 PM PDT 24
Peak memory 682576 kb
Host smart-615d6d04-af6f-4399-835c-f6b2b9bf3c76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=975379550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.975379550
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.2384892668
Short name T335
Test name
Test status
Simulation time 8099726329 ps
CPU time 154.99 seconds
Started Jun 24 06:18:45 PM PDT 24
Finished Jun 24 06:21:21 PM PDT 24
Peak memory 200132 kb
Host smart-c940bf23-299c-430c-9a26-bfc32e701d63
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384892668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2384892668
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3698665070
Short name T291
Test name
Test status
Simulation time 1561426119 ps
CPU time 29.06 seconds
Started Jun 24 06:18:37 PM PDT 24
Finished Jun 24 06:19:07 PM PDT 24
Peak memory 200064 kb
Host smart-aca67d23-9075-4361-9c14-b8f9fcaf250c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698665070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3698665070
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.659435066
Short name T519
Test name
Test status
Simulation time 789199350 ps
CPU time 7.38 seconds
Started Jun 24 06:18:45 PM PDT 24
Finished Jun 24 06:18:53 PM PDT 24
Peak memory 199932 kb
Host smart-45ab869e-b809-4a9d-8536-31fb1070e51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659435066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.659435066
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.1090395824
Short name T255
Test name
Test status
Simulation time 92009067 ps
CPU time 1.49 seconds
Started Jun 24 06:18:42 PM PDT 24
Finished Jun 24 06:18:45 PM PDT 24
Peak memory 200008 kb
Host smart-4f956a29-5e68-438e-b685-75e2fdd60245
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090395824 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_hmac_vectors.1090395824
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha256_vectors.3329807404
Short name T315
Test name
Test status
Simulation time 31295309905 ps
CPU time 466.6 seconds
Started Jun 24 06:18:39 PM PDT 24
Finished Jun 24 06:26:27 PM PDT 24
Peak memory 200348 kb
Host smart-bae9d575-d77f-49b0-8c12-0f689caa6782
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3329807404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha256_vectors.3329807404
Directory /workspace/32.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha384_vectors.4253519703
Short name T602
Test name
Test status
Simulation time 488743430563 ps
CPU time 1840.12 seconds
Started Jun 24 06:18:45 PM PDT 24
Finished Jun 24 06:49:26 PM PDT 24
Peak memory 215452 kb
Host smart-3835e7d1-1ebf-4396-b0a8-bd5a2bff5c94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4253519703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha384_vectors.4253519703
Directory /workspace/32.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha512_vectors.2263495292
Short name T629
Test name
Test status
Simulation time 149639456226 ps
CPU time 2060.74 seconds
Started Jun 24 06:18:41 PM PDT 24
Finished Jun 24 06:53:04 PM PDT 24
Peak memory 215936 kb
Host smart-fb5dfd60-9e01-4186-a83e-7d6844ed59b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2263495292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha512_vectors.2263495292
Directory /workspace/32.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3544493332
Short name T512
Test name
Test status
Simulation time 1864558535 ps
CPU time 51.17 seconds
Started Jun 24 06:18:39 PM PDT 24
Finished Jun 24 06:19:32 PM PDT 24
Peak memory 200300 kb
Host smart-90bef3f5-4b00-4312-9c16-65bdac31a8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544493332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3544493332
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.3365883787
Short name T40
Test name
Test status
Simulation time 17490352 ps
CPU time 0.61 seconds
Started Jun 24 06:18:43 PM PDT 24
Finished Jun 24 06:18:45 PM PDT 24
Peak memory 195972 kb
Host smart-44785b67-20cb-4583-9ced-174a01de5284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365883787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3365883787
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3944036743
Short name T6
Test name
Test status
Simulation time 516072910 ps
CPU time 13.75 seconds
Started Jun 24 06:18:47 PM PDT 24
Finished Jun 24 06:19:01 PM PDT 24
Peak memory 200052 kb
Host smart-8e820666-e428-4c6d-bcab-c0b127474786
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3944036743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3944036743
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.657876271
Short name T598
Test name
Test status
Simulation time 1038091455 ps
CPU time 58.44 seconds
Started Jun 24 06:18:43 PM PDT 24
Finished Jun 24 06:19:43 PM PDT 24
Peak memory 200084 kb
Host smart-4e3c306f-1fd2-4520-857a-725be33e1f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657876271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.657876271
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2287261320
Short name T550
Test name
Test status
Simulation time 10074334908 ps
CPU time 712.34 seconds
Started Jun 24 06:18:43 PM PDT 24
Finished Jun 24 06:30:37 PM PDT 24
Peak memory 722676 kb
Host smart-93107058-f49b-43f3-81c0-190524d0205f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2287261320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2287261320
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1740493156
Short name T657
Test name
Test status
Simulation time 12517708663 ps
CPU time 231.56 seconds
Started Jun 24 06:18:41 PM PDT 24
Finished Jun 24 06:22:34 PM PDT 24
Peak memory 200120 kb
Host smart-c394cef0-c370-47db-8023-ad8d8c0c6d83
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740493156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1740493156
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.989167934
Short name T538
Test name
Test status
Simulation time 16145821211 ps
CPU time 105.27 seconds
Started Jun 24 06:18:43 PM PDT 24
Finished Jun 24 06:20:30 PM PDT 24
Peak memory 216536 kb
Host smart-71181d1e-bac8-4b05-9f3f-2e6356b78af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989167934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.989167934
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3754159296
Short name T529
Test name
Test status
Simulation time 269021390 ps
CPU time 3.43 seconds
Started Jun 24 06:18:47 PM PDT 24
Finished Jun 24 06:18:51 PM PDT 24
Peak memory 200072 kb
Host smart-765ab8cc-17b9-4cdf-9064-ae67c2a4ea80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754159296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3754159296
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.384881502
Short name T442
Test name
Test status
Simulation time 103906317 ps
CPU time 1.12 seconds
Started Jun 24 06:18:42 PM PDT 24
Finished Jun 24 06:18:45 PM PDT 24
Peak memory 200008 kb
Host smart-0c336c80-4ff8-4fac-b85d-0a5f68138337
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384881502 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_hmac_vectors.384881502
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha256_vectors.2201042571
Short name T338
Test name
Test status
Simulation time 8100844387 ps
CPU time 439.22 seconds
Started Jun 24 06:18:45 PM PDT 24
Finished Jun 24 06:26:06 PM PDT 24
Peak memory 200348 kb
Host smart-d961479a-1e4d-432c-8f1b-1bc5ba518b2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2201042571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha256_vectors.2201042571
Directory /workspace/33.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha384_vectors.1644957676
Short name T339
Test name
Test status
Simulation time 144691628678 ps
CPU time 1857.32 seconds
Started Jun 24 06:18:46 PM PDT 24
Finished Jun 24 06:49:44 PM PDT 24
Peak memory 215560 kb
Host smart-30bad0cc-7400-444d-b9d3-cca9584660b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1644957676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha384_vectors.1644957676
Directory /workspace/33.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha512_vectors.2226389961
Short name T214
Test name
Test status
Simulation time 79801470145 ps
CPU time 1773.21 seconds
Started Jun 24 06:18:41 PM PDT 24
Finished Jun 24 06:48:16 PM PDT 24
Peak memory 216536 kb
Host smart-7c93f4fc-2d86-4078-b8f5-519fd3b7c3b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2226389961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha512_vectors.2226389961
Directory /workspace/33.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3622058771
Short name T362
Test name
Test status
Simulation time 2306256014 ps
CPU time 66.78 seconds
Started Jun 24 06:18:46 PM PDT 24
Finished Jun 24 06:19:54 PM PDT 24
Peak memory 200136 kb
Host smart-81fc9a90-906e-4f30-a3d1-b0f2a1e41732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622058771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3622058771
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3673739424
Short name T613
Test name
Test status
Simulation time 39983531 ps
CPU time 0.59 seconds
Started Jun 24 06:18:54 PM PDT 24
Finished Jun 24 06:18:55 PM PDT 24
Peak memory 194956 kb
Host smart-51952016-6ed7-4c23-b382-b2e7b681b687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673739424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3673739424
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2064875340
Short name T27
Test name
Test status
Simulation time 445386784 ps
CPU time 11.8 seconds
Started Jun 24 06:18:41 PM PDT 24
Finished Jun 24 06:18:54 PM PDT 24
Peak memory 200032 kb
Host smart-f5df2dda-c261-4c8f-b36a-f3f0c3acb2e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2064875340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2064875340
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.565011114
Short name T166
Test name
Test status
Simulation time 2461736520 ps
CPU time 44.72 seconds
Started Jun 24 06:18:55 PM PDT 24
Finished Jun 24 06:19:40 PM PDT 24
Peak memory 200164 kb
Host smart-b113e60a-51df-4a9f-9fa8-f9b8233c5c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565011114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.565011114
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.4178315126
Short name T272
Test name
Test status
Simulation time 15147331383 ps
CPU time 1105.32 seconds
Started Jun 24 06:18:50 PM PDT 24
Finished Jun 24 06:37:16 PM PDT 24
Peak memory 750656 kb
Host smart-58b71bf1-5eaf-454f-9812-c00ce453acb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4178315126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.4178315126
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.4110770013
Short name T131
Test name
Test status
Simulation time 1421748450 ps
CPU time 77.67 seconds
Started Jun 24 06:18:50 PM PDT 24
Finished Jun 24 06:20:09 PM PDT 24
Peak memory 200072 kb
Host smart-cd530b85-334b-40bb-a908-cc22ed225f86
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110770013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.4110770013
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1948228957
Short name T304
Test name
Test status
Simulation time 10143375956 ps
CPU time 126.74 seconds
Started Jun 24 06:18:42 PM PDT 24
Finished Jun 24 06:20:51 PM PDT 24
Peak memory 200124 kb
Host smart-71bf4b42-2348-42c4-bb0b-5c31f00b3c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948228957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1948228957
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3696437309
Short name T443
Test name
Test status
Simulation time 619494268 ps
CPU time 9.09 seconds
Started Jun 24 06:18:44 PM PDT 24
Finished Jun 24 06:18:54 PM PDT 24
Peak memory 200072 kb
Host smart-14dfcd59-130a-4a13-a40c-861e3de6f6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696437309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3696437309
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.3962439682
Short name T642
Test name
Test status
Simulation time 265492542 ps
CPU time 1.01 seconds
Started Jun 24 06:18:50 PM PDT 24
Finished Jun 24 06:18:52 PM PDT 24
Peak memory 199780 kb
Host smart-e1bf6e48-32ae-4794-89ee-707cdbce4be1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962439682 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_hmac_vectors.3962439682
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha256_vectors.2946356371
Short name T283
Test name
Test status
Simulation time 126725731964 ps
CPU time 436.06 seconds
Started Jun 24 06:18:51 PM PDT 24
Finished Jun 24 06:26:07 PM PDT 24
Peak memory 200116 kb
Host smart-e2edbb94-283b-4daf-bfe7-23c33a870a6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2946356371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha256_vectors.2946356371
Directory /workspace/34.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha384_vectors.1019666403
Short name T211
Test name
Test status
Simulation time 141019903256 ps
CPU time 1846.92 seconds
Started Jun 24 06:18:56 PM PDT 24
Finished Jun 24 06:49:44 PM PDT 24
Peak memory 215532 kb
Host smart-c83313a6-367d-47ed-9186-a45d0c1f473f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1019666403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha384_vectors.1019666403
Directory /workspace/34.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2704272472
Short name T21
Test name
Test status
Simulation time 7725831098 ps
CPU time 32.12 seconds
Started Jun 24 06:18:51 PM PDT 24
Finished Jun 24 06:19:24 PM PDT 24
Peak memory 200108 kb
Host smart-72eb2032-aeac-4962-9a3f-0aa18f7a1411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704272472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2704272472
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.4148627430
Short name T564
Test name
Test status
Simulation time 20042926 ps
CPU time 0.58 seconds
Started Jun 24 06:19:01 PM PDT 24
Finished Jun 24 06:19:01 PM PDT 24
Peak memory 194952 kb
Host smart-4b1629ff-d7ab-481d-a8bc-d0829bee4f88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148627430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.4148627430
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3084746658
Short name T396
Test name
Test status
Simulation time 840323474 ps
CPU time 35.8 seconds
Started Jun 24 06:18:53 PM PDT 24
Finished Jun 24 06:19:30 PM PDT 24
Peak memory 200084 kb
Host smart-cd0de170-38f6-4447-bcbd-673404294130
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3084746658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3084746658
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3754300688
Short name T588
Test name
Test status
Simulation time 42881578 ps
CPU time 0.78 seconds
Started Jun 24 06:18:52 PM PDT 24
Finished Jun 24 06:18:53 PM PDT 24
Peak memory 196388 kb
Host smart-39bd7442-23e6-452a-a308-b000eda06ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754300688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3754300688
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3308676186
Short name T83
Test name
Test status
Simulation time 2708360528 ps
CPU time 718.54 seconds
Started Jun 24 06:18:49 PM PDT 24
Finished Jun 24 06:30:48 PM PDT 24
Peak memory 724976 kb
Host smart-a52bf073-da76-4912-b35d-285f1f268170
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3308676186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3308676186
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.104882760
Short name T579
Test name
Test status
Simulation time 16040921384 ps
CPU time 136.78 seconds
Started Jun 24 06:19:01 PM PDT 24
Finished Jun 24 06:21:19 PM PDT 24
Peak memory 200148 kb
Host smart-ecd50ee2-5748-4812-84c1-62a74d25b492
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104882760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.104882760
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.606740661
Short name T502
Test name
Test status
Simulation time 33168983222 ps
CPU time 112.6 seconds
Started Jun 24 06:18:56 PM PDT 24
Finished Jun 24 06:20:50 PM PDT 24
Peak memory 200044 kb
Host smart-8ddc799b-7bc6-431c-bba3-aab4615f88f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606740661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.606740661
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.1100400775
Short name T296
Test name
Test status
Simulation time 65203516 ps
CPU time 0.99 seconds
Started Jun 24 06:18:51 PM PDT 24
Finished Jun 24 06:18:53 PM PDT 24
Peak memory 199816 kb
Host smart-eb244fff-dd5e-425e-bd0f-0f22340f22b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100400775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1100400775
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.2335735303
Short name T69
Test name
Test status
Simulation time 13930125318 ps
CPU time 104.16 seconds
Started Jun 24 06:18:59 PM PDT 24
Finished Jun 24 06:20:44 PM PDT 24
Peak memory 200120 kb
Host smart-36150d9e-70f3-43f9-b3f3-184dac3883ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335735303 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2335735303
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.1056056620
Short name T222
Test name
Test status
Simulation time 108589215 ps
CPU time 1.23 seconds
Started Jun 24 06:19:08 PM PDT 24
Finished Jun 24 06:19:10 PM PDT 24
Peak memory 199976 kb
Host smart-c9ba0db8-a5dd-4547-9dbc-83e4f23dbfbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056056620 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_hmac_vectors.1056056620
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha256_vectors.2483603846
Short name T466
Test name
Test status
Simulation time 136733666598 ps
CPU time 454.38 seconds
Started Jun 24 06:19:01 PM PDT 24
Finished Jun 24 06:26:36 PM PDT 24
Peak memory 200124 kb
Host smart-9de88500-c7d1-4261-85c5-b19538d7ddf2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2483603846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha256_vectors.2483603846
Directory /workspace/35.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha384_vectors.1087787860
Short name T290
Test name
Test status
Simulation time 177064789114 ps
CPU time 2381.86 seconds
Started Jun 24 06:19:00 PM PDT 24
Finished Jun 24 06:58:42 PM PDT 24
Peak memory 216016 kb
Host smart-2cc4493d-4473-4738-bab9-c89cb431cab3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1087787860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha384_vectors.1087787860
Directory /workspace/35.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha512_vectors.3533394001
Short name T301
Test name
Test status
Simulation time 144290891477 ps
CPU time 1886.16 seconds
Started Jun 24 06:19:01 PM PDT 24
Finished Jun 24 06:50:28 PM PDT 24
Peak memory 216452 kb
Host smart-66929d90-bdc3-48ed-a809-10d5e1506c97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3533394001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha512_vectors.3533394001
Directory /workspace/35.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3583416943
Short name T593
Test name
Test status
Simulation time 9108093960 ps
CPU time 42.55 seconds
Started Jun 24 06:19:09 PM PDT 24
Finished Jun 24 06:19:53 PM PDT 24
Peak memory 200072 kb
Host smart-c170ac10-8ad9-4be7-8015-eaa255b0da93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583416943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3583416943
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3902411487
Short name T585
Test name
Test status
Simulation time 26264137 ps
CPU time 0.62 seconds
Started Jun 24 06:19:09 PM PDT 24
Finished Jun 24 06:19:11 PM PDT 24
Peak memory 196064 kb
Host smart-5cd019a1-ffb4-47af-9bfd-e09e2ced7432
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902411487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3902411487
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.514010366
Short name T484
Test name
Test status
Simulation time 1244872601 ps
CPU time 27.8 seconds
Started Jun 24 06:19:09 PM PDT 24
Finished Jun 24 06:19:37 PM PDT 24
Peak memory 199968 kb
Host smart-29088a46-d736-4a1b-b140-ce06d10892ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=514010366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.514010366
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.559190695
Short name T15
Test name
Test status
Simulation time 2968637738 ps
CPU time 57.99 seconds
Started Jun 24 06:19:08 PM PDT 24
Finished Jun 24 06:20:07 PM PDT 24
Peak memory 200128 kb
Host smart-af970273-45af-4dcd-a3ae-d47333f82f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559190695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.559190695
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2512342584
Short name T389
Test name
Test status
Simulation time 6302494517 ps
CPU time 374.81 seconds
Started Jun 24 06:19:01 PM PDT 24
Finished Jun 24 06:25:17 PM PDT 24
Peak memory 623692 kb
Host smart-1db9fb9c-6505-406d-962d-79187c842001
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2512342584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2512342584
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.160941328
Short name T34
Test name
Test status
Simulation time 1398727918 ps
CPU time 81.01 seconds
Started Jun 24 06:19:15 PM PDT 24
Finished Jun 24 06:20:37 PM PDT 24
Peak memory 199712 kb
Host smart-ca197a11-f44c-47f4-8ff7-62e5d624584d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160941328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.160941328
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.444403748
Short name T326
Test name
Test status
Simulation time 1603979488 ps
CPU time 97.38 seconds
Started Jun 24 06:19:09 PM PDT 24
Finished Jun 24 06:20:47 PM PDT 24
Peak memory 199984 kb
Host smart-baaad699-7f05-4dcc-8020-d9fa84f0b035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444403748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.444403748
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.3991890370
Short name T548
Test name
Test status
Simulation time 335352051 ps
CPU time 4.39 seconds
Started Jun 24 06:19:08 PM PDT 24
Finished Jun 24 06:19:13 PM PDT 24
Peak memory 199952 kb
Host smart-8e114896-75bc-4c74-bbfb-ebe97fc44f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991890370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3991890370
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.1147932551
Short name T594
Test name
Test status
Simulation time 327065471 ps
CPU time 1.27 seconds
Started Jun 24 06:19:08 PM PDT 24
Finished Jun 24 06:19:10 PM PDT 24
Peak memory 200008 kb
Host smart-7c3f42b3-deca-447a-9708-fb4d7cf92066
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147932551 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_hmac_vectors.1147932551
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha256_vectors.841805465
Short name T528
Test name
Test status
Simulation time 149069969006 ps
CPU time 493.25 seconds
Started Jun 24 06:19:08 PM PDT 24
Finished Jun 24 06:27:23 PM PDT 24
Peak memory 200124 kb
Host smart-6e1b8786-25cf-47e4-9f4c-08185c97f8b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=841805465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha256_vectors.841805465
Directory /workspace/36.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha384_vectors.1637068692
Short name T649
Test name
Test status
Simulation time 429259887834 ps
CPU time 1961.44 seconds
Started Jun 24 06:19:07 PM PDT 24
Finished Jun 24 06:51:49 PM PDT 24
Peak memory 215992 kb
Host smart-1ef3999f-0e59-4ae0-a22c-9ce8a624fa68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1637068692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha384_vectors.1637068692
Directory /workspace/36.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha512_vectors.2068988916
Short name T205
Test name
Test status
Simulation time 123237815268 ps
CPU time 1839.55 seconds
Started Jun 24 06:19:14 PM PDT 24
Finished Jun 24 06:49:54 PM PDT 24
Peak memory 216164 kb
Host smart-7618e04e-cff8-4f0e-b0b0-b647616d253d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2068988916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha512_vectors.2068988916
Directory /workspace/36.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.4001003354
Short name T473
Test name
Test status
Simulation time 4348051374 ps
CPU time 85.33 seconds
Started Jun 24 06:19:08 PM PDT 24
Finished Jun 24 06:20:34 PM PDT 24
Peak memory 200132 kb
Host smart-db356c36-7419-4c00-8368-5384d48485d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001003354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.4001003354
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2303387620
Short name T428
Test name
Test status
Simulation time 24558706 ps
CPU time 0.54 seconds
Started Jun 24 06:19:08 PM PDT 24
Finished Jun 24 06:19:09 PM PDT 24
Peak memory 194964 kb
Host smart-d39730af-16a5-4ded-b771-067b868685b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303387620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2303387620
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3652677771
Short name T241
Test name
Test status
Simulation time 988222604 ps
CPU time 47.8 seconds
Started Jun 24 06:19:09 PM PDT 24
Finished Jun 24 06:19:58 PM PDT 24
Peak memory 200064 kb
Host smart-0bcd19a3-df50-421a-96fd-874bb5f41284
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3652677771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3652677771
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3921939222
Short name T634
Test name
Test status
Simulation time 4645388422 ps
CPU time 24.73 seconds
Started Jun 24 06:19:10 PM PDT 24
Finished Jun 24 06:19:35 PM PDT 24
Peak memory 200116 kb
Host smart-9a0ecfdc-bdec-4e47-9ee0-e090d78f231c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921939222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3921939222
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3509851837
Short name T356
Test name
Test status
Simulation time 18061357200 ps
CPU time 701.17 seconds
Started Jun 24 06:19:05 PM PDT 24
Finished Jun 24 06:30:47 PM PDT 24
Peak memory 750068 kb
Host smart-666462a8-9f52-42f4-9932-e5d20fe6a7ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3509851837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3509851837
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1967203244
Short name T592
Test name
Test status
Simulation time 18263343887 ps
CPU time 117.12 seconds
Started Jun 24 06:19:09 PM PDT 24
Finished Jun 24 06:21:08 PM PDT 24
Peak memory 200100 kb
Host smart-a5b297f0-476a-4cb9-b473-c154fae64f22
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967203244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1967203244
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.426375755
Short name T586
Test name
Test status
Simulation time 1357515366 ps
CPU time 15.06 seconds
Started Jun 24 06:19:06 PM PDT 24
Finished Jun 24 06:19:22 PM PDT 24
Peak memory 200076 kb
Host smart-aa547287-1c9c-4af2-b6c6-e35aeec86fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426375755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.426375755
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1855720251
Short name T407
Test name
Test status
Simulation time 926052004 ps
CPU time 9.76 seconds
Started Jun 24 06:19:08 PM PDT 24
Finished Jun 24 06:19:19 PM PDT 24
Peak memory 200076 kb
Host smart-f50911d4-5131-4385-bcb5-20c28d219713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855720251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1855720251
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3138026636
Short name T44
Test name
Test status
Simulation time 20218733187 ps
CPU time 341.77 seconds
Started Jun 24 06:19:11 PM PDT 24
Finished Jun 24 06:24:53 PM PDT 24
Peak memory 664432 kb
Host smart-df7df7b0-78e5-4de6-8e18-5dc7a38293fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138026636 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3138026636
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.1079277271
Short name T59
Test name
Test status
Simulation time 113347066 ps
CPU time 1.05 seconds
Started Jun 24 06:19:15 PM PDT 24
Finished Jun 24 06:19:17 PM PDT 24
Peak memory 199596 kb
Host smart-b9c2c7d1-ab6a-4121-9c54-e340f8b0e10e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079277271 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_hmac_vectors.1079277271
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha256_vectors.2267126525
Short name T368
Test name
Test status
Simulation time 27183244880 ps
CPU time 398.38 seconds
Started Jun 24 06:19:07 PM PDT 24
Finished Jun 24 06:25:46 PM PDT 24
Peak memory 200104 kb
Host smart-6d1c578f-d222-40d8-a497-6f3424347759
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2267126525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha256_vectors.2267126525
Directory /workspace/37.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha384_vectors.671216974
Short name T312
Test name
Test status
Simulation time 107885910906 ps
CPU time 1853.35 seconds
Started Jun 24 06:19:09 PM PDT 24
Finished Jun 24 06:50:03 PM PDT 24
Peak memory 215988 kb
Host smart-330774a8-48eb-4b73-9eff-e58f4f2f20ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=671216974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha384_vectors.671216974
Directory /workspace/37.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha512_vectors.230081386
Short name T223
Test name
Test status
Simulation time 459490210829 ps
CPU time 2068.6 seconds
Started Jun 24 06:19:09 PM PDT 24
Finished Jun 24 06:53:39 PM PDT 24
Peak memory 215592 kb
Host smart-963b2829-b08f-4d4e-9591-048e2f2764a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=230081386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha512_vectors.230081386
Directory /workspace/37.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3754209805
Short name T279
Test name
Test status
Simulation time 292417229 ps
CPU time 4.86 seconds
Started Jun 24 06:19:09 PM PDT 24
Finished Jun 24 06:19:15 PM PDT 24
Peak memory 200020 kb
Host smart-3acf4523-c895-485f-a79a-fc831407c3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754209805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3754209805
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3134546817
Short name T444
Test name
Test status
Simulation time 43370082 ps
CPU time 0.61 seconds
Started Jun 24 06:19:19 PM PDT 24
Finished Jun 24 06:19:21 PM PDT 24
Peak memory 194968 kb
Host smart-d2cff81b-1688-43cb-ac8a-dd37d833b080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134546817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3134546817
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.859306665
Short name T382
Test name
Test status
Simulation time 379106214 ps
CPU time 17.12 seconds
Started Jun 24 06:19:16 PM PDT 24
Finished Jun 24 06:19:34 PM PDT 24
Peak memory 200096 kb
Host smart-92378aa2-ebc7-4af5-9472-07a97c441d0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=859306665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.859306665
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.2299023059
Short name T148
Test name
Test status
Simulation time 7682868197 ps
CPU time 59.79 seconds
Started Jun 24 06:19:20 PM PDT 24
Finished Jun 24 06:20:21 PM PDT 24
Peak memory 208172 kb
Host smart-54309573-b416-4fc9-8bcc-5bd785fd634e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299023059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2299023059
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.1139554138
Short name T489
Test name
Test status
Simulation time 2412582624 ps
CPU time 285.61 seconds
Started Jun 24 06:19:19 PM PDT 24
Finished Jun 24 06:24:05 PM PDT 24
Peak memory 601672 kb
Host smart-a6fbf947-0ef6-4f50-bbf6-a4d561ea7cb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1139554138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.1139554138
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.663078101
Short name T453
Test name
Test status
Simulation time 3503280048 ps
CPU time 43.92 seconds
Started Jun 24 06:19:20 PM PDT 24
Finished Jun 24 06:20:04 PM PDT 24
Peak memory 200132 kb
Host smart-23a26202-7964-4966-8a36-ce695905d8ef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663078101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.663078101
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1578553294
Short name T627
Test name
Test status
Simulation time 14553670950 ps
CPU time 35.61 seconds
Started Jun 24 06:19:10 PM PDT 24
Finished Jun 24 06:19:47 PM PDT 24
Peak memory 200128 kb
Host smart-14c883c6-984f-4e86-95c8-07c8c1630261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578553294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1578553294
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.677466540
Short name T525
Test name
Test status
Simulation time 81730034 ps
CPU time 1.26 seconds
Started Jun 24 06:19:08 PM PDT 24
Finished Jun 24 06:19:11 PM PDT 24
Peak memory 200320 kb
Host smart-7a119e4a-3288-4f23-867c-de49f035502e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677466540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.677466540
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1829533946
Short name T43
Test name
Test status
Simulation time 10403965594 ps
CPU time 303.38 seconds
Started Jun 24 06:19:18 PM PDT 24
Finished Jun 24 06:24:22 PM PDT 24
Peak memory 200108 kb
Host smart-beca91b0-20eb-4bbb-9a6d-4df6908e0284
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829533946 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1829533946
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.3077753181
Short name T61
Test name
Test status
Simulation time 189935106 ps
CPU time 1.11 seconds
Started Jun 24 06:19:18 PM PDT 24
Finished Jun 24 06:19:20 PM PDT 24
Peak memory 200064 kb
Host smart-e2f875b1-5c60-49e8-ad46-8654acbe42c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077753181 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_hmac_vectors.3077753181
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha256_vectors.666307256
Short name T387
Test name
Test status
Simulation time 15582613676 ps
CPU time 450.66 seconds
Started Jun 24 06:19:18 PM PDT 24
Finished Jun 24 06:26:50 PM PDT 24
Peak memory 200032 kb
Host smart-cc4ef6f9-e547-47d1-9496-94db0fed2734
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=666307256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha256_vectors.666307256
Directory /workspace/38.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha384_vectors.539626852
Short name T173
Test name
Test status
Simulation time 307341603375 ps
CPU time 2002.06 seconds
Started Jun 24 06:19:18 PM PDT 24
Finished Jun 24 06:52:41 PM PDT 24
Peak memory 216272 kb
Host smart-f9cf875e-9ead-41cf-ac38-83ee60706a58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=539626852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha384_vectors.539626852
Directory /workspace/38.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha512_vectors.4005724221
Short name T186
Test name
Test status
Simulation time 210887780418 ps
CPU time 1724.83 seconds
Started Jun 24 06:19:18 PM PDT 24
Finished Jun 24 06:48:04 PM PDT 24
Peak memory 216388 kb
Host smart-1e9768db-ad4c-4d63-8835-b5a94c2d9f49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4005724221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha512_vectors.4005724221
Directory /workspace/38.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.3225990
Short name T80
Test name
Test status
Simulation time 2243077029 ps
CPU time 32.32 seconds
Started Jun 24 06:19:18 PM PDT 24
Finished Jun 24 06:19:52 PM PDT 24
Peak memory 200156 kb
Host smart-279c1899-4667-45cf-a1db-581044a22dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.3225990
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.741804816
Short name T447
Test name
Test status
Simulation time 17085842 ps
CPU time 0.65 seconds
Started Jun 24 06:19:20 PM PDT 24
Finished Jun 24 06:19:21 PM PDT 24
Peak memory 196060 kb
Host smart-d6f566d5-e669-4df4-ab04-504f6f9f3a1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741804816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.741804816
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1223176187
Short name T84
Test name
Test status
Simulation time 2425003381 ps
CPU time 54.64 seconds
Started Jun 24 06:19:18 PM PDT 24
Finished Jun 24 06:20:14 PM PDT 24
Peak memory 200120 kb
Host smart-951039fc-eb8a-4c15-8af9-a7513816c950
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1223176187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1223176187
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2887823164
Short name T37
Test name
Test status
Simulation time 2152033304 ps
CPU time 523.18 seconds
Started Jun 24 06:19:18 PM PDT 24
Finished Jun 24 06:28:02 PM PDT 24
Peak memory 661764 kb
Host smart-417dd6ce-a238-4a0f-8028-3a86febb4032
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2887823164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2887823164
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1700067590
Short name T135
Test name
Test status
Simulation time 6692060683 ps
CPU time 93.99 seconds
Started Jun 24 06:19:18 PM PDT 24
Finished Jun 24 06:20:53 PM PDT 24
Peak memory 200100 kb
Host smart-be545855-e650-45de-a6d0-b894b4bbe0a3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700067590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1700067590
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_smoke.513175592
Short name T576
Test name
Test status
Simulation time 134595712 ps
CPU time 6.63 seconds
Started Jun 24 06:19:19 PM PDT 24
Finished Jun 24 06:19:26 PM PDT 24
Peak memory 200092 kb
Host smart-99dd18d4-be1c-483d-afbf-702f467f0cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513175592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.513175592
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.2428457527
Short name T358
Test name
Test status
Simulation time 29571089 ps
CPU time 1.13 seconds
Started Jun 24 06:19:17 PM PDT 24
Finished Jun 24 06:19:18 PM PDT 24
Peak memory 200076 kb
Host smart-bfa820d8-25c5-4c75-b70a-e2bff0162352
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428457527 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_hmac_vectors.2428457527
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha256_vectors.3025711123
Short name T367
Test name
Test status
Simulation time 47789108308 ps
CPU time 444.93 seconds
Started Jun 24 06:19:17 PM PDT 24
Finished Jun 24 06:26:43 PM PDT 24
Peak memory 200136 kb
Host smart-f364c30f-0159-4810-b945-6a6042c66500
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3025711123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha256_vectors.3025711123
Directory /workspace/39.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha384_vectors.1172972573
Short name T465
Test name
Test status
Simulation time 305242336218 ps
CPU time 1914.65 seconds
Started Jun 24 06:19:18 PM PDT 24
Finished Jun 24 06:51:14 PM PDT 24
Peak memory 215964 kb
Host smart-02b89999-4b6b-4656-aec3-dda92edffb07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1172972573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha384_vectors.1172972573
Directory /workspace/39.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha512_vectors.3521136376
Short name T590
Test name
Test status
Simulation time 113287524284 ps
CPU time 2105.25 seconds
Started Jun 24 06:19:19 PM PDT 24
Finished Jun 24 06:54:26 PM PDT 24
Peak memory 215816 kb
Host smart-ecde340b-adcf-4038-84b4-4e7a3650ff09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3521136376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha512_vectors.3521136376
Directory /workspace/39.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.715219302
Short name T394
Test name
Test status
Simulation time 1397293538 ps
CPU time 10.61 seconds
Started Jun 24 06:19:16 PM PDT 24
Finished Jun 24 06:19:27 PM PDT 24
Peak memory 200068 kb
Host smart-503f88c4-f6c9-4868-b431-b645914cee50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715219302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.715219302
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.4161025252
Short name T195
Test name
Test status
Simulation time 15198296 ps
CPU time 0.58 seconds
Started Jun 24 06:17:05 PM PDT 24
Finished Jun 24 06:17:07 PM PDT 24
Peak memory 194972 kb
Host smart-87b6658d-e6c8-45a2-a1c5-fa19677bf411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161025252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.4161025252
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1958581730
Short name T267
Test name
Test status
Simulation time 3816140111 ps
CPU time 35.61 seconds
Started Jun 24 06:17:00 PM PDT 24
Finished Jun 24 06:17:37 PM PDT 24
Peak memory 208348 kb
Host smart-9c3a6540-5d60-493d-aac8-63aed83bf241
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1958581730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1958581730
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2614620759
Short name T648
Test name
Test status
Simulation time 6204020146 ps
CPU time 58.46 seconds
Started Jun 24 06:16:59 PM PDT 24
Finished Jun 24 06:17:58 PM PDT 24
Peak memory 216472 kb
Host smart-f023cbd5-d793-445f-8776-39f1016f757c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614620759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2614620759
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2719638423
Short name T52
Test name
Test status
Simulation time 3645481342 ps
CPU time 971.33 seconds
Started Jun 24 06:16:56 PM PDT 24
Finished Jun 24 06:33:09 PM PDT 24
Peak memory 725504 kb
Host smart-6bde3ff5-9dfe-46dd-b0ec-c0015e39cfb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2719638423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2719638423
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3191531628
Short name T213
Test name
Test status
Simulation time 9644671885 ps
CPU time 113.38 seconds
Started Jun 24 06:17:03 PM PDT 24
Finished Jun 24 06:18:57 PM PDT 24
Peak memory 200112 kb
Host smart-3f3e1add-6cdd-4a99-b10e-eb32a872c3ee
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191531628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3191531628
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3312972410
Short name T376
Test name
Test status
Simulation time 2728725870 ps
CPU time 53.5 seconds
Started Jun 24 06:16:58 PM PDT 24
Finished Jun 24 06:17:53 PM PDT 24
Peak memory 200128 kb
Host smart-ae2322aa-01ab-4a21-b97a-2003c9394659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312972410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3312972410
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3050442740
Short name T42
Test name
Test status
Simulation time 35629880 ps
CPU time 0.81 seconds
Started Jun 24 06:17:09 PM PDT 24
Finished Jun 24 06:17:10 PM PDT 24
Peak memory 218236 kb
Host smart-5db9c803-4c9c-4531-810e-098fd2eab741
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050442740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3050442740
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.602695420
Short name T220
Test name
Test status
Simulation time 613124181 ps
CPU time 11.4 seconds
Started Jun 24 06:17:00 PM PDT 24
Finished Jun 24 06:17:12 PM PDT 24
Peak memory 200060 kb
Host smart-3f280abb-e8c4-42f3-82c1-e2bac7db6db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602695420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.602695420
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.1239040503
Short name T609
Test name
Test status
Simulation time 58069069 ps
CPU time 1.24 seconds
Started Jun 24 06:17:04 PM PDT 24
Finished Jun 24 06:17:05 PM PDT 24
Peak memory 200056 kb
Host smart-d0cdaa09-fcfb-47e8-8baf-16e229cb14d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239040503 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac_vectors.1239040503
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.2437564817
Short name T539
Test name
Test status
Simulation time 8075386498 ps
CPU time 462.82 seconds
Started Jun 24 06:17:00 PM PDT 24
Finished Jun 24 06:24:44 PM PDT 24
Peak memory 200088 kb
Host smart-7ab2f5f4-36fb-4192-880e-430ce174cd85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2437564817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2437564817
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.2639572068
Short name T33
Test name
Test status
Simulation time 123868259522 ps
CPU time 1696.28 seconds
Started Jun 24 06:17:07 PM PDT 24
Finished Jun 24 06:45:24 PM PDT 24
Peak memory 216360 kb
Host smart-d134793f-ea9f-4cd3-9c05-f9642df88dec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2639572068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.2639572068
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.1931249813
Short name T412
Test name
Test status
Simulation time 282412811587 ps
CPU time 1948.72 seconds
Started Jun 24 06:17:07 PM PDT 24
Finished Jun 24 06:49:37 PM PDT 24
Peak memory 215904 kb
Host smart-ab93d1d5-83b0-4b50-9a92-025e553786d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1931249813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.1931249813
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2750838298
Short name T411
Test name
Test status
Simulation time 2456021583 ps
CPU time 48.45 seconds
Started Jun 24 06:17:01 PM PDT 24
Finished Jun 24 06:17:50 PM PDT 24
Peak memory 200092 kb
Host smart-dc3e85e1-d1c6-4dd4-8cd8-108a91f24e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750838298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2750838298
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2527403325
Short name T309
Test name
Test status
Simulation time 43455261 ps
CPU time 0.58 seconds
Started Jun 24 06:19:27 PM PDT 24
Finished Jun 24 06:19:28 PM PDT 24
Peak memory 195036 kb
Host smart-b71dd941-30d1-43f6-8cd4-20313d73a660
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527403325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2527403325
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.106583269
Short name T571
Test name
Test status
Simulation time 2058383757 ps
CPU time 22.43 seconds
Started Jun 24 06:19:20 PM PDT 24
Finished Jun 24 06:19:43 PM PDT 24
Peak memory 199988 kb
Host smart-8965b544-342b-48e2-8866-bba6cef6dd74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106583269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.106583269
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1664576341
Short name T527
Test name
Test status
Simulation time 1780728543 ps
CPU time 18.55 seconds
Started Jun 24 06:19:19 PM PDT 24
Finished Jun 24 06:19:38 PM PDT 24
Peak memory 200076 kb
Host smart-381cff2b-ba35-42c1-94e9-1403d0d9eaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664576341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1664576341
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.4178370189
Short name T399
Test name
Test status
Simulation time 2273465245 ps
CPU time 164.22 seconds
Started Jun 24 06:19:20 PM PDT 24
Finished Jun 24 06:22:05 PM PDT 24
Peak memory 616896 kb
Host smart-88cef823-bfe3-44e4-8e65-f7e7f063f444
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4178370189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.4178370189
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.1864247516
Short name T325
Test name
Test status
Simulation time 608409959 ps
CPU time 36.02 seconds
Started Jun 24 06:19:18 PM PDT 24
Finished Jun 24 06:19:55 PM PDT 24
Peak memory 199932 kb
Host smart-43b12a17-4f59-4afa-8271-f33527f1231d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864247516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1864247516
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3427799830
Short name T513
Test name
Test status
Simulation time 1166102234 ps
CPU time 70.69 seconds
Started Jun 24 06:19:20 PM PDT 24
Finished Jun 24 06:20:31 PM PDT 24
Peak memory 200096 kb
Host smart-757fb991-62e1-4bb2-a892-43be5711a843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427799830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3427799830
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.4267034981
Short name T281
Test name
Test status
Simulation time 309322443 ps
CPU time 4.12 seconds
Started Jun 24 06:19:18 PM PDT 24
Finished Jun 24 06:19:22 PM PDT 24
Peak memory 200072 kb
Host smart-54ddee7e-3247-4ea5-8580-0291c28ecb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267034981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.4267034981
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.2580144614
Short name T572
Test name
Test status
Simulation time 211184567 ps
CPU time 1.28 seconds
Started Jun 24 06:19:27 PM PDT 24
Finished Jun 24 06:19:29 PM PDT 24
Peak memory 199992 kb
Host smart-3312b745-3079-4ce0-b917-807af7514a97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580144614 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_hmac_vectors.2580144614
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha256_vectors.179020608
Short name T580
Test name
Test status
Simulation time 53983852374 ps
CPU time 483.88 seconds
Started Jun 24 06:19:27 PM PDT 24
Finished Jun 24 06:27:32 PM PDT 24
Peak memory 200112 kb
Host smart-ddf06b72-c619-4bc4-b503-0031b352974a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=179020608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha256_vectors.179020608
Directory /workspace/40.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha384_vectors.359850005
Short name T421
Test name
Test status
Simulation time 66102562077 ps
CPU time 1882.66 seconds
Started Jun 24 06:19:30 PM PDT 24
Finished Jun 24 06:50:54 PM PDT 24
Peak memory 216120 kb
Host smart-e4735c73-447b-4293-bf3c-bd220fa7c713
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=359850005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha384_vectors.359850005
Directory /workspace/40.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha512_vectors.4167440350
Short name T56
Test name
Test status
Simulation time 165866801366 ps
CPU time 1868.27 seconds
Started Jun 24 06:19:28 PM PDT 24
Finished Jun 24 06:50:37 PM PDT 24
Peak memory 216508 kb
Host smart-197a065e-8d34-42f6-ae3d-5e1605102996
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4167440350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha512_vectors.4167440350
Directory /workspace/40.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.3949833861
Short name T274
Test name
Test status
Simulation time 29161940402 ps
CPU time 49.79 seconds
Started Jun 24 06:19:26 PM PDT 24
Finished Jun 24 06:20:16 PM PDT 24
Peak memory 200132 kb
Host smart-9b8de01f-135a-4339-88b8-cb5f3d6ea40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949833861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3949833861
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.349645735
Short name T345
Test name
Test status
Simulation time 11663903 ps
CPU time 0.58 seconds
Started Jun 24 06:19:24 PM PDT 24
Finished Jun 24 06:19:26 PM PDT 24
Peak memory 194964 kb
Host smart-98b8334e-38a0-40c3-9b60-42ec22a5e415
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349645735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.349645735
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.3203136319
Short name T16
Test name
Test status
Simulation time 348024067 ps
CPU time 17.33 seconds
Started Jun 24 06:19:29 PM PDT 24
Finished Jun 24 06:19:47 PM PDT 24
Peak memory 200032 kb
Host smart-fa9ad1ed-d108-4ad6-9376-0eb748b2f815
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3203136319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3203136319
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2570010513
Short name T393
Test name
Test status
Simulation time 33988819887 ps
CPU time 48.49 seconds
Started Jun 24 06:19:28 PM PDT 24
Finished Jun 24 06:20:17 PM PDT 24
Peak memory 200108 kb
Host smart-5e890d6a-69af-4425-acd3-31f5f021530b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570010513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2570010513
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1635369821
Short name T348
Test name
Test status
Simulation time 2438906432 ps
CPU time 378.49 seconds
Started Jun 24 06:19:28 PM PDT 24
Finished Jun 24 06:25:47 PM PDT 24
Peak memory 688216 kb
Host smart-167b2fb7-23c3-4109-9dc0-cd2ee37a4356
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1635369821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1635369821
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1464479604
Short name T140
Test name
Test status
Simulation time 226612127230 ps
CPU time 203.83 seconds
Started Jun 24 06:19:26 PM PDT 24
Finished Jun 24 06:22:51 PM PDT 24
Peak memory 200100 kb
Host smart-6574f359-f9b2-44b6-b5dc-717abc625e91
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464479604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1464479604
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.4264307162
Short name T474
Test name
Test status
Simulation time 2763954078 ps
CPU time 21.02 seconds
Started Jun 24 06:19:30 PM PDT 24
Finished Jun 24 06:19:52 PM PDT 24
Peak memory 200120 kb
Host smart-2b287790-00cf-49df-acf1-4a47f854cb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264307162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.4264307162
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3899262691
Short name T656
Test name
Test status
Simulation time 549252391 ps
CPU time 3.84 seconds
Started Jun 24 06:19:29 PM PDT 24
Finished Jun 24 06:19:33 PM PDT 24
Peak memory 200036 kb
Host smart-12ae1028-6e7f-4ebc-b592-4923c4b3c86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899262691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3899262691
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.3536988786
Short name T535
Test name
Test status
Simulation time 109331931 ps
CPU time 1.03 seconds
Started Jun 24 06:19:27 PM PDT 24
Finished Jun 24 06:19:29 PM PDT 24
Peak memory 199792 kb
Host smart-6622755a-ae36-48c8-8ab3-0aca1d4fe311
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536988786 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_hmac_vectors.3536988786
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha256_vectors.4021342683
Short name T569
Test name
Test status
Simulation time 37990622950 ps
CPU time 480.08 seconds
Started Jun 24 06:19:30 PM PDT 24
Finished Jun 24 06:27:31 PM PDT 24
Peak memory 200128 kb
Host smart-43b18ceb-44c6-4786-99c4-930a4c521940
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4021342683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha256_vectors.4021342683
Directory /workspace/41.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha384_vectors.1022523503
Short name T282
Test name
Test status
Simulation time 120313126277 ps
CPU time 1747.01 seconds
Started Jun 24 06:19:26 PM PDT 24
Finished Jun 24 06:48:34 PM PDT 24
Peak memory 215848 kb
Host smart-c7ae2b08-656e-40c6-9d4e-0cb254933d3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1022523503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha384_vectors.1022523503
Directory /workspace/41.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha512_vectors.739025124
Short name T491
Test name
Test status
Simulation time 64644995019 ps
CPU time 1860.04 seconds
Started Jun 24 06:19:28 PM PDT 24
Finished Jun 24 06:50:29 PM PDT 24
Peak memory 216528 kb
Host smart-ef0f10a3-252b-4530-846e-1c0a5e2297cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=739025124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha512_vectors.739025124
Directory /workspace/41.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3461106643
Short name T125
Test name
Test status
Simulation time 10589970302 ps
CPU time 78.04 seconds
Started Jun 24 06:19:28 PM PDT 24
Finished Jun 24 06:20:47 PM PDT 24
Peak memory 200136 kb
Host smart-981668ff-2f19-4218-a78b-e257f358d967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461106643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3461106643
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3228210345
Short name T198
Test name
Test status
Simulation time 35244450 ps
CPU time 0.61 seconds
Started Jun 24 06:19:36 PM PDT 24
Finished Jun 24 06:19:37 PM PDT 24
Peak memory 195992 kb
Host smart-9a01b32a-419c-494b-945a-cf3ffeb31582
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228210345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3228210345
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.281117732
Short name T85
Test name
Test status
Simulation time 2394724596 ps
CPU time 21.42 seconds
Started Jun 24 06:19:35 PM PDT 24
Finished Jun 24 06:19:57 PM PDT 24
Peak memory 200084 kb
Host smart-dd1c838a-8942-4265-a76e-233542e87b5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=281117732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.281117732
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.810308862
Short name T516
Test name
Test status
Simulation time 1334468707 ps
CPU time 18 seconds
Started Jun 24 06:19:36 PM PDT 24
Finished Jun 24 06:19:55 PM PDT 24
Peak memory 200048 kb
Host smart-7dc3a735-cbf7-4bbe-91ef-4231e51bf0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810308862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.810308862
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2564713160
Short name T472
Test name
Test status
Simulation time 6899888756 ps
CPU time 836.57 seconds
Started Jun 24 06:19:34 PM PDT 24
Finished Jun 24 06:33:32 PM PDT 24
Peak memory 741100 kb
Host smart-1a27dcfa-a25d-402e-8bec-56203b66c015
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2564713160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2564713160
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.1144167859
Short name T514
Test name
Test status
Simulation time 2656083706 ps
CPU time 71.36 seconds
Started Jun 24 06:19:35 PM PDT 24
Finished Jun 24 06:20:48 PM PDT 24
Peak memory 200112 kb
Host smart-9892c7fa-b7aa-4c6a-a6dd-b2e12e699c60
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144167859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1144167859
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3631195121
Short name T606
Test name
Test status
Simulation time 12208437831 ps
CPU time 76.6 seconds
Started Jun 24 06:19:27 PM PDT 24
Finished Jun 24 06:20:45 PM PDT 24
Peak memory 200124 kb
Host smart-96951130-332c-4370-aee1-8271bed13f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631195121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3631195121
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3198123680
Short name T202
Test name
Test status
Simulation time 536330201 ps
CPU time 8.61 seconds
Started Jun 24 06:19:27 PM PDT 24
Finished Jun 24 06:19:36 PM PDT 24
Peak memory 200036 kb
Host smart-3e913f8c-6f69-48b8-a9dd-fbad0179ff73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198123680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3198123680
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.687172128
Short name T176
Test name
Test status
Simulation time 225926634 ps
CPU time 1.26 seconds
Started Jun 24 06:19:36 PM PDT 24
Finished Jun 24 06:19:38 PM PDT 24
Peak memory 200024 kb
Host smart-8be37687-d986-4861-b4d0-bea3801e7dd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687172128 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_hmac_vectors.687172128
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha256_vectors.708700265
Short name T360
Test name
Test status
Simulation time 8525511476 ps
CPU time 493.43 seconds
Started Jun 24 06:19:34 PM PDT 24
Finished Jun 24 06:27:48 PM PDT 24
Peak memory 200120 kb
Host smart-3546166b-faaa-4477-8562-678cb4e59ba3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=708700265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha256_vectors.708700265
Directory /workspace/42.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha384_vectors.2930429019
Short name T300
Test name
Test status
Simulation time 144392839244 ps
CPU time 1821.01 seconds
Started Jun 24 06:19:34 PM PDT 24
Finished Jun 24 06:49:55 PM PDT 24
Peak memory 215980 kb
Host smart-984c5ec0-a87d-4cfe-a054-4c1222cfc990
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2930429019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha384_vectors.2930429019
Directory /workspace/42.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha512_vectors.2895693811
Short name T184
Test name
Test status
Simulation time 33455069443 ps
CPU time 1750.36 seconds
Started Jun 24 06:19:35 PM PDT 24
Finished Jun 24 06:48:46 PM PDT 24
Peak memory 216040 kb
Host smart-e404b3f7-9289-4643-a0ab-21625510cef5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2895693811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha512_vectors.2895693811
Directory /workspace/42.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.4276415128
Short name T87
Test name
Test status
Simulation time 5007493463 ps
CPU time 25.95 seconds
Started Jun 24 06:19:35 PM PDT 24
Finished Jun 24 06:20:02 PM PDT 24
Peak memory 200164 kb
Host smart-6ce6a402-a92b-40bf-ae7d-5e0cde34832d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276415128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.4276415128
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3847020681
Short name T611
Test name
Test status
Simulation time 19986738 ps
CPU time 0.58 seconds
Started Jun 24 06:19:44 PM PDT 24
Finished Jun 24 06:19:46 PM PDT 24
Peak memory 194968 kb
Host smart-edc3266f-d059-4af9-9c28-4680c28165dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847020681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3847020681
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3096355546
Short name T450
Test name
Test status
Simulation time 3767739250 ps
CPU time 48.58 seconds
Started Jun 24 06:19:35 PM PDT 24
Finished Jun 24 06:20:24 PM PDT 24
Peak memory 200092 kb
Host smart-58f66d1d-30de-4da8-9058-c841436b8594
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3096355546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3096355546
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2130886619
Short name T434
Test name
Test status
Simulation time 14789317638 ps
CPU time 22.9 seconds
Started Jun 24 06:19:35 PM PDT 24
Finished Jun 24 06:19:58 PM PDT 24
Peak memory 200064 kb
Host smart-4113f14a-24e7-41b1-9ece-0310eb021142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130886619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2130886619
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.448044034
Short name T534
Test name
Test status
Simulation time 11749884782 ps
CPU time 738.49 seconds
Started Jun 24 06:19:36 PM PDT 24
Finished Jun 24 06:31:56 PM PDT 24
Peak memory 721956 kb
Host smart-7672b61e-3996-49aa-8cf8-24f78e347d8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448044034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.448044034
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.1878024794
Short name T654
Test name
Test status
Simulation time 392264748 ps
CPU time 22.07 seconds
Started Jun 24 06:19:37 PM PDT 24
Finished Jun 24 06:20:00 PM PDT 24
Peak memory 199980 kb
Host smart-734264b5-3801-4fbd-8029-d301d4114bf4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878024794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1878024794
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.759739374
Short name T488
Test name
Test status
Simulation time 3931347758 ps
CPU time 73.12 seconds
Started Jun 24 06:19:36 PM PDT 24
Finished Jun 24 06:20:50 PM PDT 24
Peak memory 200132 kb
Host smart-7fca1155-8405-45ee-bda6-9cb29e6eb9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759739374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.759739374
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2486823944
Short name T361
Test name
Test status
Simulation time 900392777 ps
CPU time 12.31 seconds
Started Jun 24 06:19:35 PM PDT 24
Finished Jun 24 06:19:49 PM PDT 24
Peak memory 200072 kb
Host smart-3b71c8ce-a328-4fb9-8295-663b96501dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486823944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2486823944
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.3833277597
Short name T340
Test name
Test status
Simulation time 308778442 ps
CPU time 1.46 seconds
Started Jun 24 06:19:35 PM PDT 24
Finished Jun 24 06:19:38 PM PDT 24
Peak memory 200012 kb
Host smart-9f6089bd-95f1-4c45-b5ea-3927f8ccf393
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833277597 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_hmac_vectors.3833277597
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha256_vectors.1928904997
Short name T192
Test name
Test status
Simulation time 7269101812 ps
CPU time 403.21 seconds
Started Jun 24 06:19:34 PM PDT 24
Finished Jun 24 06:26:17 PM PDT 24
Peak memory 200108 kb
Host smart-6be713e3-6be2-4392-bc64-73790907fdb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1928904997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha256_vectors.1928904997
Directory /workspace/43.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha384_vectors.3365176525
Short name T626
Test name
Test status
Simulation time 31271783847 ps
CPU time 1842.71 seconds
Started Jun 24 06:19:35 PM PDT 24
Finished Jun 24 06:50:19 PM PDT 24
Peak memory 216308 kb
Host smart-58e5d316-38fe-47b0-b58a-6f03c497d872
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3365176525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha384_vectors.3365176525
Directory /workspace/43.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha512_vectors.534276613
Short name T570
Test name
Test status
Simulation time 368530452920 ps
CPU time 1769.86 seconds
Started Jun 24 06:19:36 PM PDT 24
Finished Jun 24 06:49:07 PM PDT 24
Peak memory 216528 kb
Host smart-3f3e4e3f-c029-41f5-bc43-43185ce86da4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=534276613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha512_vectors.534276613
Directory /workspace/43.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.4007380030
Short name T123
Test name
Test status
Simulation time 1775580087 ps
CPU time 64.55 seconds
Started Jun 24 06:19:36 PM PDT 24
Finished Jun 24 06:20:42 PM PDT 24
Peak memory 200072 kb
Host smart-51bb4e1f-a554-4636-940b-e3be5b8f04e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007380030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.4007380030
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.4241585839
Short name T483
Test name
Test status
Simulation time 14466940 ps
CPU time 0.59 seconds
Started Jun 24 06:19:45 PM PDT 24
Finished Jun 24 06:19:46 PM PDT 24
Peak memory 194952 kb
Host smart-53554882-ab33-46a6-8fa8-f2e4731eade5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241585839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.4241585839
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2639214160
Short name T7
Test name
Test status
Simulation time 6310103143 ps
CPU time 32.79 seconds
Started Jun 24 06:19:44 PM PDT 24
Finished Jun 24 06:20:17 PM PDT 24
Peak memory 200116 kb
Host smart-5fbf4efc-d285-44ea-a5ad-cc618b995a9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2639214160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2639214160
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1182326931
Short name T373
Test name
Test status
Simulation time 1972652229 ps
CPU time 25.96 seconds
Started Jun 24 06:19:46 PM PDT 24
Finished Jun 24 06:20:13 PM PDT 24
Peak memory 200236 kb
Host smart-71f94a13-b5ab-406b-a4d9-554e49e6a79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182326931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1182326931
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.18839912
Short name T322
Test name
Test status
Simulation time 2796752402 ps
CPU time 151.77 seconds
Started Jun 24 06:19:46 PM PDT 24
Finished Jun 24 06:22:19 PM PDT 24
Peak memory 459320 kb
Host smart-c7d89164-0636-4cf0-92f9-659c922242e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=18839912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.18839912
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_long_msg.3055962667
Short name T432
Test name
Test status
Simulation time 21732566048 ps
CPU time 76.98 seconds
Started Jun 24 06:19:45 PM PDT 24
Finished Jun 24 06:21:02 PM PDT 24
Peak memory 200036 kb
Host smart-669c88e8-5dca-4245-b963-720b4d30779f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055962667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3055962667
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.348721860
Short name T597
Test name
Test status
Simulation time 310214333 ps
CPU time 5.26 seconds
Started Jun 24 06:19:45 PM PDT 24
Finished Jun 24 06:19:51 PM PDT 24
Peak memory 200064 kb
Host smart-0aa3a7e2-1ad2-40de-aeba-187b08b04150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348721860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.348721860
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.1708568978
Short name T560
Test name
Test status
Simulation time 57112038 ps
CPU time 1.09 seconds
Started Jun 24 06:19:45 PM PDT 24
Finished Jun 24 06:19:47 PM PDT 24
Peak memory 199596 kb
Host smart-f5fd1b73-99a2-4598-8849-ea0c77e2945e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708568978 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_hmac_vectors.1708568978
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha256_vectors.1363179916
Short name T372
Test name
Test status
Simulation time 44027962977 ps
CPU time 431.72 seconds
Started Jun 24 06:19:44 PM PDT 24
Finished Jun 24 06:26:56 PM PDT 24
Peak memory 200120 kb
Host smart-bb75e118-41e5-45b9-a6de-e53767f3e191
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1363179916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha256_vectors.1363179916
Directory /workspace/44.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha384_vectors.1325589268
Short name T262
Test name
Test status
Simulation time 156832569701 ps
CPU time 1959.54 seconds
Started Jun 24 06:19:43 PM PDT 24
Finished Jun 24 06:52:23 PM PDT 24
Peak memory 215708 kb
Host smart-25f1ff73-f621-435e-a06b-a4660cb0ddb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1325589268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha384_vectors.1325589268
Directory /workspace/44.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha512_vectors.2947228245
Short name T547
Test name
Test status
Simulation time 70059069846 ps
CPU time 1893.11 seconds
Started Jun 24 06:19:44 PM PDT 24
Finished Jun 24 06:51:18 PM PDT 24
Peak memory 215620 kb
Host smart-22767ca9-1287-4d9f-8912-aec0821abc5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2947228245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha512_vectors.2947228245
Directory /workspace/44.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2479948568
Short name T408
Test name
Test status
Simulation time 1377480726 ps
CPU time 26.46 seconds
Started Jun 24 06:19:44 PM PDT 24
Finished Jun 24 06:20:11 PM PDT 24
Peak memory 200072 kb
Host smart-1b760338-6288-4751-9755-6e1e33668448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479948568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2479948568
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1217393945
Short name T206
Test name
Test status
Simulation time 15620798 ps
CPU time 0.63 seconds
Started Jun 24 06:19:56 PM PDT 24
Finished Jun 24 06:19:59 PM PDT 24
Peak memory 195632 kb
Host smart-877abefa-b84e-425a-b631-7d050abc3a72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217393945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1217393945
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.957425203
Short name T526
Test name
Test status
Simulation time 145969191 ps
CPU time 6.22 seconds
Started Jun 24 06:19:46 PM PDT 24
Finished Jun 24 06:19:53 PM PDT 24
Peak memory 200080 kb
Host smart-550c3803-f740-4dee-9095-f2200d04b5d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=957425203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.957425203
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.755531026
Short name T146
Test name
Test status
Simulation time 7885374934 ps
CPU time 40.66 seconds
Started Jun 24 06:19:54 PM PDT 24
Finished Jun 24 06:20:36 PM PDT 24
Peak memory 208588 kb
Host smart-d376da96-c45f-4976-8ebf-c7843ff056f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755531026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.755531026
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2142909021
Short name T557
Test name
Test status
Simulation time 39381871590 ps
CPU time 1057.34 seconds
Started Jun 24 06:19:56 PM PDT 24
Finished Jun 24 06:37:35 PM PDT 24
Peak memory 759100 kb
Host smart-279a905f-1106-4ab9-8d69-e05cc790d489
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2142909021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2142909021
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.4166341029
Short name T53
Test name
Test status
Simulation time 27273473609 ps
CPU time 85.25 seconds
Started Jun 24 06:19:54 PM PDT 24
Finished Jun 24 06:21:21 PM PDT 24
Peak memory 200016 kb
Host smart-9296b1ff-6d5a-4f80-9e19-ff57b494d4b3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166341029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.4166341029
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3306125593
Short name T3
Test name
Test status
Simulation time 1409847731 ps
CPU time 20.35 seconds
Started Jun 24 06:19:44 PM PDT 24
Finished Jun 24 06:20:05 PM PDT 24
Peak memory 200104 kb
Host smart-91358f74-cc33-49af-ac38-bff4dfe5b857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306125593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3306125593
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.808165271
Short name T375
Test name
Test status
Simulation time 166682770 ps
CPU time 8.55 seconds
Started Jun 24 06:19:46 PM PDT 24
Finished Jun 24 06:19:55 PM PDT 24
Peak memory 200076 kb
Host smart-c9e862b6-cbef-4eff-969c-1d2920cfd670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808165271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.808165271
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.1220014442
Short name T153
Test name
Test status
Simulation time 3601076593 ps
CPU time 180.15 seconds
Started Jun 24 06:19:56 PM PDT 24
Finished Jun 24 06:22:56 PM PDT 24
Peak memory 216424 kb
Host smart-816b5a2f-cecc-456e-b648-66be9391a445
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220014442 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1220014442
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.3814316066
Short name T343
Test name
Test status
Simulation time 123514419 ps
CPU time 1.23 seconds
Started Jun 24 06:19:57 PM PDT 24
Finished Jun 24 06:19:59 PM PDT 24
Peak memory 200268 kb
Host smart-90dd67fd-aaee-4a2e-92c6-5454c693927a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814316066 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_hmac_vectors.3814316066
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha256_vectors.307101899
Short name T57
Test name
Test status
Simulation time 36850473263 ps
CPU time 500.36 seconds
Started Jun 24 06:19:57 PM PDT 24
Finished Jun 24 06:28:19 PM PDT 24
Peak memory 200120 kb
Host smart-586740de-870d-449c-bb53-ae0d5800c3be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=307101899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha256_vectors.307101899
Directory /workspace/45.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha384_vectors.1299344414
Short name T257
Test name
Test status
Simulation time 444042798382 ps
CPU time 1962.45 seconds
Started Jun 24 06:19:57 PM PDT 24
Finished Jun 24 06:52:41 PM PDT 24
Peak memory 215660 kb
Host smart-76cf2966-74f3-44d8-9be1-1a3631714a0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1299344414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha384_vectors.1299344414
Directory /workspace/45.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha512_vectors.3692220914
Short name T400
Test name
Test status
Simulation time 52714921499 ps
CPU time 1501.99 seconds
Started Jun 24 06:19:53 PM PDT 24
Finished Jun 24 06:44:56 PM PDT 24
Peak memory 216088 kb
Host smart-d3b74eac-caaf-48d0-8fce-6f563d5ddd62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3692220914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha512_vectors.3692220914
Directory /workspace/45.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1321905582
Short name T410
Test name
Test status
Simulation time 3358933413 ps
CPU time 27.96 seconds
Started Jun 24 06:19:52 PM PDT 24
Finished Jun 24 06:20:20 PM PDT 24
Peak memory 200128 kb
Host smart-e40f4684-f472-4066-8385-cd19e57bd16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321905582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1321905582
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.261115153
Short name T617
Test name
Test status
Simulation time 12272720 ps
CPU time 0.59 seconds
Started Jun 24 06:19:53 PM PDT 24
Finished Jun 24 06:19:55 PM PDT 24
Peak memory 194968 kb
Host smart-0c1c64aa-5ae1-4971-a22d-6b61dab78296
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261115153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.261115153
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1006227802
Short name T635
Test name
Test status
Simulation time 431192401 ps
CPU time 19.22 seconds
Started Jun 24 06:19:52 PM PDT 24
Finished Jun 24 06:20:12 PM PDT 24
Peak memory 200056 kb
Host smart-39bfadf6-ec47-4bff-b72f-008e0ea6e986
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1006227802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1006227802
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.396391965
Short name T147
Test name
Test status
Simulation time 4195366650 ps
CPU time 63.6 seconds
Started Jun 24 06:19:53 PM PDT 24
Finished Jun 24 06:20:58 PM PDT 24
Peak memory 200120 kb
Host smart-b0302ec6-4e8e-400a-b7da-d5d070029261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396391965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.396391965
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2735563583
Short name T544
Test name
Test status
Simulation time 214871341 ps
CPU time 39.12 seconds
Started Jun 24 06:19:56 PM PDT 24
Finished Jun 24 06:20:37 PM PDT 24
Peak memory 313280 kb
Host smart-4397d1ca-e1a0-4ee7-8138-8d57f6c28850
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2735563583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2735563583
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.675099805
Short name T139
Test name
Test status
Simulation time 2064143281 ps
CPU time 62.45 seconds
Started Jun 24 06:19:53 PM PDT 24
Finished Jun 24 06:20:57 PM PDT 24
Peak memory 200036 kb
Host smart-cc1e6b27-845b-4b21-a49a-074d2a6e18c0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675099805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.675099805
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.3810269102
Short name T245
Test name
Test status
Simulation time 25643287853 ps
CPU time 106.23 seconds
Started Jun 24 06:19:53 PM PDT 24
Finished Jun 24 06:21:40 PM PDT 24
Peak memory 216440 kb
Host smart-04320c39-69ee-4074-a705-ea7f98158ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810269102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3810269102
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.44559879
Short name T265
Test name
Test status
Simulation time 315599688 ps
CPU time 4.4 seconds
Started Jun 24 06:19:56 PM PDT 24
Finished Jun 24 06:20:01 PM PDT 24
Peak memory 200068 kb
Host smart-2df7908d-912f-4f1e-ad1a-48dc2489131b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44559879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.44559879
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.305167759
Short name T228
Test name
Test status
Simulation time 61123515 ps
CPU time 1.22 seconds
Started Jun 24 06:19:52 PM PDT 24
Finished Jun 24 06:19:54 PM PDT 24
Peak memory 200064 kb
Host smart-6c976038-afa2-4ae2-905b-f86e72b4675d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305167759 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_hmac_vectors.305167759
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha256_vectors.86542741
Short name T404
Test name
Test status
Simulation time 53973127681 ps
CPU time 488.86 seconds
Started Jun 24 06:19:53 PM PDT 24
Finished Jun 24 06:28:03 PM PDT 24
Peak memory 200120 kb
Host smart-f8badaee-dd30-4acc-bd06-e272df976a3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=86542741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha256_vectors.86542741
Directory /workspace/46.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha384_vectors.1864560425
Short name T209
Test name
Test status
Simulation time 102844243377 ps
CPU time 1800.68 seconds
Started Jun 24 06:19:54 PM PDT 24
Finished Jun 24 06:49:56 PM PDT 24
Peak memory 215580 kb
Host smart-a6c9433a-d81d-4356-a5ad-d27f6470bb7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1864560425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha384_vectors.1864560425
Directory /workspace/46.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha512_vectors.3603089544
Short name T555
Test name
Test status
Simulation time 596791970580 ps
CPU time 1801.86 seconds
Started Jun 24 06:19:54 PM PDT 24
Finished Jun 24 06:49:57 PM PDT 24
Peak memory 216504 kb
Host smart-7b656b7c-bc4a-4568-950b-275acbebc0a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3603089544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha512_vectors.3603089544
Directory /workspace/46.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.3588343122
Short name T306
Test name
Test status
Simulation time 6295726400 ps
CPU time 24.26 seconds
Started Jun 24 06:19:57 PM PDT 24
Finished Jun 24 06:20:23 PM PDT 24
Peak memory 200128 kb
Host smart-2b9d6d22-e026-4e2f-a1ce-c58436bf59a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588343122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.3588343122
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2306040918
Short name T9
Test name
Test status
Simulation time 12509808 ps
CPU time 0.55 seconds
Started Jun 24 06:20:03 PM PDT 24
Finished Jun 24 06:20:04 PM PDT 24
Peak memory 194972 kb
Host smart-3aef3c11-b841-47b4-a79f-832ac2718a6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306040918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2306040918
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.3577388081
Short name T168
Test name
Test status
Simulation time 172174661 ps
CPU time 8.32 seconds
Started Jun 24 06:20:03 PM PDT 24
Finished Jun 24 06:20:12 PM PDT 24
Peak memory 199988 kb
Host smart-73de2e12-85a5-455b-abf6-cc496121cafc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3577388081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3577388081
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2482972924
Short name T149
Test name
Test status
Simulation time 9941080339 ps
CPU time 48.87 seconds
Started Jun 24 06:20:04 PM PDT 24
Finished Jun 24 06:20:54 PM PDT 24
Peak memory 208304 kb
Host smart-a912bdc6-ee7e-4c87-8ba9-852b99950122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482972924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2482972924
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3332755361
Short name T541
Test name
Test status
Simulation time 15112526790 ps
CPU time 813.2 seconds
Started Jun 24 06:20:04 PM PDT 24
Finished Jun 24 06:33:38 PM PDT 24
Peak memory 712572 kb
Host smart-83b2af72-5d7b-4f01-aeaf-bde69e6ac3d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3332755361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3332755361
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3561129984
Short name T596
Test name
Test status
Simulation time 143198322520 ps
CPU time 184.87 seconds
Started Jun 24 06:20:03 PM PDT 24
Finished Jun 24 06:23:09 PM PDT 24
Peak memory 200084 kb
Host smart-d038edbc-17c4-4ed3-966c-f03d09a7ae0a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561129984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3561129984
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1974884721
Short name T178
Test name
Test status
Simulation time 8046849057 ps
CPU time 111.47 seconds
Started Jun 24 06:20:03 PM PDT 24
Finished Jun 24 06:21:56 PM PDT 24
Peak memory 200156 kb
Host smart-a7758101-521e-4c36-8bc3-6b6e48e6c392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974884721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1974884721
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.4040034778
Short name T244
Test name
Test status
Simulation time 118992395 ps
CPU time 2.75 seconds
Started Jun 24 06:19:54 PM PDT 24
Finished Jun 24 06:19:58 PM PDT 24
Peak memory 200052 kb
Host smart-5b18f492-e74c-4646-b080-ddb532f2a75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040034778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.4040034778
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2190890769
Short name T500
Test name
Test status
Simulation time 122439386 ps
CPU time 1.24 seconds
Started Jun 24 06:20:03 PM PDT 24
Finished Jun 24 06:20:05 PM PDT 24
Peak memory 200020 kb
Host smart-acf3b1fb-33d7-4b85-be5a-2586ea8372f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190890769 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_hmac_vectors.2190890769
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha256_vectors.2473863185
Short name T295
Test name
Test status
Simulation time 36666339044 ps
CPU time 479.86 seconds
Started Jun 24 06:20:05 PM PDT 24
Finished Jun 24 06:28:06 PM PDT 24
Peak memory 200144 kb
Host smart-8474317a-d21d-4329-b3d8-01794e967bf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2473863185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha256_vectors.2473863185
Directory /workspace/47.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha384_vectors.4291977047
Short name T188
Test name
Test status
Simulation time 121365775964 ps
CPU time 1755.71 seconds
Started Jun 24 06:20:04 PM PDT 24
Finished Jun 24 06:49:21 PM PDT 24
Peak memory 215720 kb
Host smart-36f6c25a-5af8-4919-8981-546e371bd28f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4291977047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha384_vectors.4291977047
Directory /workspace/47.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha512_vectors.959963409
Short name T29
Test name
Test status
Simulation time 500035680034 ps
CPU time 1821.92 seconds
Started Jun 24 06:20:01 PM PDT 24
Finished Jun 24 06:50:24 PM PDT 24
Peak memory 216372 kb
Host smart-b2508132-5464-41cf-8194-0b3d06881f79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=959963409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha512_vectors.959963409
Directory /workspace/47.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.2287073318
Short name T278
Test name
Test status
Simulation time 3212225076 ps
CPU time 55.13 seconds
Started Jun 24 06:20:03 PM PDT 24
Finished Jun 24 06:20:59 PM PDT 24
Peak memory 200084 kb
Host smart-039954c5-d7a7-4eb7-a0bd-383caec61185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287073318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2287073318
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.2426981584
Short name T464
Test name
Test status
Simulation time 33078314 ps
CPU time 0.58 seconds
Started Jun 24 06:20:13 PM PDT 24
Finished Jun 24 06:20:14 PM PDT 24
Peak memory 195976 kb
Host smart-e3c65ace-3d12-4011-9d0a-4355d95ef93d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426981584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2426981584
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.390289283
Short name T266
Test name
Test status
Simulation time 2249068218 ps
CPU time 32.49 seconds
Started Jun 24 06:20:05 PM PDT 24
Finished Jun 24 06:20:38 PM PDT 24
Peak memory 200116 kb
Host smart-b516b3d1-8713-4fe0-9f91-fdbd438bb4be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=390289283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.390289283
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3609938188
Short name T151
Test name
Test status
Simulation time 4253744727 ps
CPU time 58.8 seconds
Started Jun 24 06:20:02 PM PDT 24
Finished Jun 24 06:21:02 PM PDT 24
Peak memory 200156 kb
Host smart-1b41fc9a-cf56-4886-9897-1a139e539632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609938188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3609938188
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.74459152
Short name T208
Test name
Test status
Simulation time 7235704777 ps
CPU time 1065.24 seconds
Started Jun 24 06:20:05 PM PDT 24
Finished Jun 24 06:37:51 PM PDT 24
Peak memory 753992 kb
Host smart-60017118-8881-449c-968a-5a0c1421d3e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=74459152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.74459152
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1058706253
Short name T457
Test name
Test status
Simulation time 5072830235 ps
CPU time 98 seconds
Started Jun 24 06:20:08 PM PDT 24
Finished Jun 24 06:21:47 PM PDT 24
Peak memory 200136 kb
Host smart-6cca94f1-02bc-42a9-8a37-879e1e204585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058706253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1058706253
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1056311587
Short name T545
Test name
Test status
Simulation time 474651804 ps
CPU time 2.67 seconds
Started Jun 24 06:20:03 PM PDT 24
Finished Jun 24 06:20:07 PM PDT 24
Peak memory 200068 kb
Host smart-39804116-e3e8-412f-a3a5-7d52d71c971d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056311587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1056311587
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.2910279983
Short name T646
Test name
Test status
Simulation time 78797525 ps
CPU time 1.45 seconds
Started Jun 24 06:20:17 PM PDT 24
Finished Jun 24 06:20:18 PM PDT 24
Peak memory 200324 kb
Host smart-224bdbe5-fc9c-44f4-be2e-0b3d44ba9578
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910279983 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_hmac_vectors.2910279983
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha256_vectors.1605112147
Short name T662
Test name
Test status
Simulation time 38021804936 ps
CPU time 520.72 seconds
Started Jun 24 06:20:01 PM PDT 24
Finished Jun 24 06:28:43 PM PDT 24
Peak memory 200120 kb
Host smart-2582016e-dad4-4911-8cd2-173ed4002fe7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1605112147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha256_vectors.1605112147
Directory /workspace/48.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha512_vectors.1661453469
Short name T452
Test name
Test status
Simulation time 709935908881 ps
CPU time 2229.52 seconds
Started Jun 24 06:20:02 PM PDT 24
Finished Jun 24 06:57:12 PM PDT 24
Peak memory 215528 kb
Host smart-be67716f-989e-40a5-81c4-ce252bc431c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1661453469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha512_vectors.1661453469
Directory /workspace/48.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3927393688
Short name T458
Test name
Test status
Simulation time 15019637686 ps
CPU time 52.55 seconds
Started Jun 24 06:20:04 PM PDT 24
Finished Jun 24 06:20:57 PM PDT 24
Peak memory 200160 kb
Host smart-68776757-59e6-4444-adf2-7ee15018e376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927393688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3927393688
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.46554428
Short name T475
Test name
Test status
Simulation time 59498203 ps
CPU time 0.59 seconds
Started Jun 24 06:20:13 PM PDT 24
Finished Jun 24 06:20:15 PM PDT 24
Peak memory 196068 kb
Host smart-a0a743d0-3dad-4248-b0df-2c020c0cb0ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46554428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.46554428
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.647142844
Short name T624
Test name
Test status
Simulation time 139387208 ps
CPU time 4.67 seconds
Started Jun 24 06:20:14 PM PDT 24
Finished Jun 24 06:20:20 PM PDT 24
Peak memory 200060 kb
Host smart-47672c74-dfc7-471b-acd3-36ed502aec43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=647142844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.647142844
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.4155952035
Short name T445
Test name
Test status
Simulation time 2144107939 ps
CPU time 62.71 seconds
Started Jun 24 06:20:13 PM PDT 24
Finished Jun 24 06:21:16 PM PDT 24
Peak memory 200044 kb
Host smart-0f9fa021-10f5-42ce-bedd-5de88fc943ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155952035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.4155952035
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3871295252
Short name T218
Test name
Test status
Simulation time 3594293164 ps
CPU time 257.44 seconds
Started Jun 24 06:20:13 PM PDT 24
Finished Jun 24 06:24:32 PM PDT 24
Peak memory 662824 kb
Host smart-abc951f8-b98a-45c3-8efe-a84592822139
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3871295252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3871295252
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2286761894
Short name T604
Test name
Test status
Simulation time 9498438786 ps
CPU time 107.95 seconds
Started Jun 24 06:20:13 PM PDT 24
Finished Jun 24 06:22:02 PM PDT 24
Peak memory 200132 kb
Host smart-740a8491-3cae-46e8-811f-f47feaef2887
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286761894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2286761894
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.565322583
Short name T553
Test name
Test status
Simulation time 5802624138 ps
CPU time 56.91 seconds
Started Jun 24 06:20:13 PM PDT 24
Finished Jun 24 06:21:10 PM PDT 24
Peak memory 200128 kb
Host smart-36639ad1-d850-450d-971f-6de834fe5e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565322583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.565322583
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3303919936
Short name T433
Test name
Test status
Simulation time 1597269312 ps
CPU time 14.67 seconds
Started Jun 24 06:20:14 PM PDT 24
Finished Jun 24 06:20:30 PM PDT 24
Peak memory 200064 kb
Host smart-17da807d-7990-43e0-b275-2a0b6ff21564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303919936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3303919936
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.4045677396
Short name T175
Test name
Test status
Simulation time 171062853 ps
CPU time 1.15 seconds
Started Jun 24 06:20:13 PM PDT 24
Finished Jun 24 06:20:15 PM PDT 24
Peak memory 200008 kb
Host smart-79f130cc-d0ae-4575-8eca-df385a35213c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045677396 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_hmac_vectors.4045677396
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha256_vectors.2565535293
Short name T478
Test name
Test status
Simulation time 7413471155 ps
CPU time 391.66 seconds
Started Jun 24 06:20:14 PM PDT 24
Finished Jun 24 06:26:47 PM PDT 24
Peak memory 200108 kb
Host smart-4e76505c-0514-4c97-a21a-1d5bcf9a1fd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2565535293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha256_vectors.2565535293
Directory /workspace/49.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha384_vectors.2686864648
Short name T17
Test name
Test status
Simulation time 196235004564 ps
CPU time 1769.05 seconds
Started Jun 24 06:20:14 PM PDT 24
Finished Jun 24 06:49:44 PM PDT 24
Peak memory 216492 kb
Host smart-2907ad1c-d716-445b-832c-e90188da6890
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2686864648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha384_vectors.2686864648
Directory /workspace/49.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha512_vectors.3881445943
Short name T225
Test name
Test status
Simulation time 333473211033 ps
CPU time 2218.16 seconds
Started Jun 24 06:20:12 PM PDT 24
Finished Jun 24 06:57:12 PM PDT 24
Peak memory 215592 kb
Host smart-66a184a6-d655-452d-b004-e011baa6f7b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3881445943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha512_vectors.3881445943
Directory /workspace/49.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.2111762080
Short name T124
Test name
Test status
Simulation time 4826333709 ps
CPU time 48.43 seconds
Started Jun 24 06:20:13 PM PDT 24
Finished Jun 24 06:21:02 PM PDT 24
Peak memory 200132 kb
Host smart-a0515bbb-3f44-4623-9e7d-4f1b760563b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111762080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2111762080
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1752402293
Short name T377
Test name
Test status
Simulation time 31215453 ps
CPU time 0.57 seconds
Started Jun 24 06:17:07 PM PDT 24
Finished Jun 24 06:17:09 PM PDT 24
Peak memory 195692 kb
Host smart-c6746325-602f-4e99-9c49-5399a29bf306
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752402293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1752402293
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.163765887
Short name T620
Test name
Test status
Simulation time 863767339 ps
CPU time 36.38 seconds
Started Jun 24 06:17:06 PM PDT 24
Finished Jun 24 06:17:44 PM PDT 24
Peak memory 200064 kb
Host smart-5a891776-c173-450f-b57e-fe303322bee8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=163765887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.163765887
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2265310869
Short name T418
Test name
Test status
Simulation time 1663126208 ps
CPU time 30.38 seconds
Started Jun 24 06:17:05 PM PDT 24
Finished Jun 24 06:17:37 PM PDT 24
Peak memory 199996 kb
Host smart-4ad9edb7-0c41-4ed3-90ef-f43019c49bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265310869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2265310869
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2525833655
Short name T293
Test name
Test status
Simulation time 382680435 ps
CPU time 40.93 seconds
Started Jun 24 06:17:07 PM PDT 24
Finished Jun 24 06:17:49 PM PDT 24
Peak memory 242712 kb
Host smart-528f9d8f-7eb0-431f-9a2a-75e963f3f471
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2525833655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2525833655
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1455432013
Short name T459
Test name
Test status
Simulation time 2150598826 ps
CPU time 120.85 seconds
Started Jun 24 06:17:06 PM PDT 24
Finished Jun 24 06:19:08 PM PDT 24
Peak memory 200124 kb
Host smart-a5280d39-fbc5-4c8c-9f8b-164579771eca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455432013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1455432013
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.2575536451
Short name T318
Test name
Test status
Simulation time 4044752493 ps
CPU time 66.15 seconds
Started Jun 24 06:17:04 PM PDT 24
Finished Jun 24 06:18:11 PM PDT 24
Peak memory 216400 kb
Host smart-f34d3f83-d2a5-40c1-b817-0a331b280719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575536451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2575536451
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3966694226
Short name T294
Test name
Test status
Simulation time 477555245 ps
CPU time 7.84 seconds
Started Jun 24 06:17:05 PM PDT 24
Finished Jun 24 06:17:14 PM PDT 24
Peak memory 200068 kb
Host smart-1caed301-5c71-47e7-835b-8c6ca04d8273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966694226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3966694226
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3498837947
Short name T70
Test name
Test status
Simulation time 24971060547 ps
CPU time 939.2 seconds
Started Jun 24 06:17:04 PM PDT 24
Finished Jun 24 06:32:44 PM PDT 24
Peak memory 724720 kb
Host smart-f753ec1c-ba1c-416c-beb5-79f8a820741c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498837947 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3498837947
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.1537864110
Short name T384
Test name
Test status
Simulation time 112875228 ps
CPU time 1.18 seconds
Started Jun 24 06:17:07 PM PDT 24
Finished Jun 24 06:17:09 PM PDT 24
Peak memory 200000 kb
Host smart-57b6e984-c20e-4c43-9c73-a4f7f753e6e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537864110 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_hmac_vectors.1537864110
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha256_vectors.1925739845
Short name T402
Test name
Test status
Simulation time 53778645507 ps
CPU time 505.29 seconds
Started Jun 24 06:17:10 PM PDT 24
Finished Jun 24 06:25:36 PM PDT 24
Peak memory 200348 kb
Host smart-7b92e399-bfef-4357-8cac-8f0965512dac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1925739845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha256_vectors.1925739845
Directory /workspace/5.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha384_vectors.3394766406
Short name T536
Test name
Test status
Simulation time 116982021790 ps
CPU time 2115.22 seconds
Started Jun 24 06:17:08 PM PDT 24
Finished Jun 24 06:52:25 PM PDT 24
Peak memory 215548 kb
Host smart-7044648f-24f4-4002-95cf-bf2fa836ffcb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3394766406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha384_vectors.3394766406
Directory /workspace/5.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha512_vectors.3043969035
Short name T467
Test name
Test status
Simulation time 479481524282 ps
CPU time 2082.98 seconds
Started Jun 24 06:17:06 PM PDT 24
Finished Jun 24 06:51:51 PM PDT 24
Peak memory 215484 kb
Host smart-6bff09a0-56af-4a8a-a1f2-2d12afe5cb47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3043969035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha512_vectors.3043969035
Directory /workspace/5.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.1859720672
Short name T587
Test name
Test status
Simulation time 1009831757 ps
CPU time 14.52 seconds
Started Jun 24 06:17:05 PM PDT 24
Finished Jun 24 06:17:21 PM PDT 24
Peak memory 200056 kb
Host smart-7bf4c819-4664-43a1-892f-06a76d978593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859720672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1859720672
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.4283735655
Short name T246
Test name
Test status
Simulation time 50148681 ps
CPU time 0.59 seconds
Started Jun 24 06:17:05 PM PDT 24
Finished Jun 24 06:17:07 PM PDT 24
Peak memory 195628 kb
Host smart-23e39ad8-3f8b-41e4-ab84-0f6e56e33352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283735655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.4283735655
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2566603085
Short name T270
Test name
Test status
Simulation time 901467924 ps
CPU time 40.11 seconds
Started Jun 24 06:17:10 PM PDT 24
Finished Jun 24 06:17:51 PM PDT 24
Peak memory 200292 kb
Host smart-00fe515d-df15-460e-9c42-b962341fe5e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2566603085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2566603085
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.249802580
Short name T365
Test name
Test status
Simulation time 9807270165 ps
CPU time 49.87 seconds
Started Jun 24 06:17:06 PM PDT 24
Finished Jun 24 06:17:57 PM PDT 24
Peak memory 208328 kb
Host smart-e342591d-5ce2-42a6-bf69-9ff8f69d9ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249802580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.249802580
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3939382558
Short name T420
Test name
Test status
Simulation time 3913614962 ps
CPU time 1026.94 seconds
Started Jun 24 06:17:07 PM PDT 24
Finished Jun 24 06:34:15 PM PDT 24
Peak memory 726596 kb
Host smart-8fac92a1-0aed-4eed-bf69-ebf7fc6116e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3939382558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3939382558
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1040784364
Short name T127
Test name
Test status
Simulation time 937188533 ps
CPU time 51.6 seconds
Started Jun 24 06:17:08 PM PDT 24
Finished Jun 24 06:18:01 PM PDT 24
Peak memory 200080 kb
Host smart-fe7a450e-74a7-4840-abc3-c30ee5e0fada
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040784364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1040784364
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.552706572
Short name T247
Test name
Test status
Simulation time 1866500759 ps
CPU time 109.57 seconds
Started Jun 24 06:17:07 PM PDT 24
Finished Jun 24 06:18:57 PM PDT 24
Peak memory 200048 kb
Host smart-1a741775-aebb-4cbb-b6f5-a2f7cb9347a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552706572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.552706572
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.101918856
Short name T510
Test name
Test status
Simulation time 500666921 ps
CPU time 4.57 seconds
Started Jun 24 06:17:06 PM PDT 24
Finished Jun 24 06:17:11 PM PDT 24
Peak memory 200068 kb
Host smart-53262402-04b8-4032-a334-86270068027f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101918856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.101918856
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.2682308208
Short name T324
Test name
Test status
Simulation time 51120539 ps
CPU time 1.13 seconds
Started Jun 24 06:17:05 PM PDT 24
Finished Jun 24 06:17:08 PM PDT 24
Peak memory 200040 kb
Host smart-f5a7c487-cfa7-4605-86aa-e3e56ba10097
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682308208 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_hmac_vectors.2682308208
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha256_vectors.501754349
Short name T468
Test name
Test status
Simulation time 24072653901 ps
CPU time 446.53 seconds
Started Jun 24 06:17:09 PM PDT 24
Finished Jun 24 06:24:37 PM PDT 24
Peak memory 200124 kb
Host smart-33a06bc8-aa74-4415-936d-04e7296fef5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=501754349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha256_vectors.501754349
Directory /workspace/6.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha384_vectors.4088114225
Short name T170
Test name
Test status
Simulation time 619986100147 ps
CPU time 2018.85 seconds
Started Jun 24 06:17:09 PM PDT 24
Finished Jun 24 06:50:49 PM PDT 24
Peak memory 215484 kb
Host smart-2a015a8f-f640-4321-ac34-7a460a2639ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4088114225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha384_vectors.4088114225
Directory /workspace/6.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha512_vectors.3202656247
Short name T556
Test name
Test status
Simulation time 595164656216 ps
CPU time 1981.38 seconds
Started Jun 24 06:17:07 PM PDT 24
Finished Jun 24 06:50:10 PM PDT 24
Peak memory 216184 kb
Host smart-a0a643e4-1010-436c-804f-f73bc6722947
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3202656247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha512_vectors.3202656247
Directory /workspace/6.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1361212974
Short name T495
Test name
Test status
Simulation time 66774016243 ps
CPU time 102.1 seconds
Started Jun 24 06:17:05 PM PDT 24
Finished Jun 24 06:18:49 PM PDT 24
Peak memory 200124 kb
Host smart-be209f3f-18e9-4932-92d6-f658a4eac1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361212974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1361212974
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1164322733
Short name T574
Test name
Test status
Simulation time 58654663 ps
CPU time 0.6 seconds
Started Jun 24 06:17:16 PM PDT 24
Finished Jun 24 06:17:17 PM PDT 24
Peak memory 196084 kb
Host smart-b43edb1b-a100-40e9-9531-7832d3eb9463
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164322733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1164322733
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2467461919
Short name T346
Test name
Test status
Simulation time 218745137 ps
CPU time 12.27 seconds
Started Jun 24 06:17:05 PM PDT 24
Finished Jun 24 06:17:19 PM PDT 24
Peak memory 200080 kb
Host smart-d93c73cd-3e81-4b35-bd13-03d9cdddceb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2467461919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2467461919
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3035123759
Short name T655
Test name
Test status
Simulation time 209967792 ps
CPU time 11.63 seconds
Started Jun 24 06:17:05 PM PDT 24
Finished Jun 24 06:17:18 PM PDT 24
Peak memory 200060 kb
Host smart-e9e0374d-6da9-4a1a-b5db-c5a23045a764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035123759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3035123759
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2768841081
Short name T583
Test name
Test status
Simulation time 3510608347 ps
CPU time 807.03 seconds
Started Jun 24 06:17:06 PM PDT 24
Finished Jun 24 06:30:35 PM PDT 24
Peak memory 609852 kb
Host smart-b65a8843-90a7-4ce0-be75-d8004a3c78c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2768841081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2768841081
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.3440916137
Short name T644
Test name
Test status
Simulation time 1178315886 ps
CPU time 67.53 seconds
Started Jun 24 06:17:18 PM PDT 24
Finished Jun 24 06:18:27 PM PDT 24
Peak memory 200264 kb
Host smart-547d0b44-583c-4a47-897f-6d82d4026298
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440916137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3440916137
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1999903005
Short name T230
Test name
Test status
Simulation time 2455527495 ps
CPU time 145.54 seconds
Started Jun 24 06:17:06 PM PDT 24
Finished Jun 24 06:19:32 PM PDT 24
Peak memory 200168 kb
Host smart-bff4968b-f075-4464-bd79-01cb69a78287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999903005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1999903005
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1234601736
Short name T344
Test name
Test status
Simulation time 13836908241 ps
CPU time 47.32 seconds
Started Jun 24 06:17:05 PM PDT 24
Finished Jun 24 06:17:53 PM PDT 24
Peak memory 200156 kb
Host smart-de779f69-d8cf-416b-a1fa-03eb4ebda31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234601736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1234601736
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.283394610
Short name T215
Test name
Test status
Simulation time 125113266 ps
CPU time 1.43 seconds
Started Jun 24 06:17:18 PM PDT 24
Finished Jun 24 06:17:21 PM PDT 24
Peak memory 200068 kb
Host smart-465b1e1f-c685-411d-94ad-bd694dfd6986
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283394610 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_hmac_vectors.283394610
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha256_vectors.33701198
Short name T4
Test name
Test status
Simulation time 168698030751 ps
CPU time 550.7 seconds
Started Jun 24 06:17:14 PM PDT 24
Finished Jun 24 06:26:25 PM PDT 24
Peak memory 200156 kb
Host smart-8838380a-a38c-42e1-bbff-1ea8dc4c0af6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=33701198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha256_vectors.33701198
Directory /workspace/7.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha384_vectors.2698804440
Short name T413
Test name
Test status
Simulation time 110042575717 ps
CPU time 1881.62 seconds
Started Jun 24 06:17:20 PM PDT 24
Finished Jun 24 06:48:43 PM PDT 24
Peak memory 216020 kb
Host smart-9f199963-ed09-4efd-a21a-1b7bd3c57547
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2698804440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha384_vectors.2698804440
Directory /workspace/7.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha512_vectors.1896556324
Short name T614
Test name
Test status
Simulation time 228090810713 ps
CPU time 1989.07 seconds
Started Jun 24 06:17:13 PM PDT 24
Finished Jun 24 06:50:23 PM PDT 24
Peak memory 216176 kb
Host smart-c92463a2-7cc2-4388-a11e-92f57798d71d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1896556324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha512_vectors.1896556324
Directory /workspace/7.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1103977732
Short name T537
Test name
Test status
Simulation time 1075986651 ps
CPU time 4.8 seconds
Started Jun 24 06:17:18 PM PDT 24
Finished Jun 24 06:17:24 PM PDT 24
Peak memory 200056 kb
Host smart-60db6213-40c0-4cc1-8a09-046421a641a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103977732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1103977732
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1000539697
Short name T234
Test name
Test status
Simulation time 40752330 ps
CPU time 0.6 seconds
Started Jun 24 06:17:15 PM PDT 24
Finished Jun 24 06:17:17 PM PDT 24
Peak memory 194968 kb
Host smart-d224b1c3-e4f7-4f1c-b1ff-6d56825c99cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000539697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1000539697
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3342390945
Short name T441
Test name
Test status
Simulation time 149830681 ps
CPU time 4.03 seconds
Started Jun 24 06:17:15 PM PDT 24
Finished Jun 24 06:17:20 PM PDT 24
Peak memory 200036 kb
Host smart-4d25f68b-5362-46b3-9261-618fdeaee146
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3342390945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3342390945
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3258861089
Short name T167
Test name
Test status
Simulation time 331822107 ps
CPU time 9.38 seconds
Started Jun 24 06:17:16 PM PDT 24
Finished Jun 24 06:17:27 PM PDT 24
Peak memory 199996 kb
Host smart-51e723e5-daf4-443d-97ce-5ca82258f4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258861089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3258861089
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1141284535
Short name T455
Test name
Test status
Simulation time 20292460433 ps
CPU time 1011.91 seconds
Started Jun 24 06:17:29 PM PDT 24
Finished Jun 24 06:34:24 PM PDT 24
Peak memory 698856 kb
Host smart-7506dc34-2d19-4b7d-a90f-0f4f32ade812
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1141284535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1141284535
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.772000878
Short name T342
Test name
Test status
Simulation time 608992361 ps
CPU time 34.28 seconds
Started Jun 24 06:17:17 PM PDT 24
Finished Jun 24 06:17:53 PM PDT 24
Peak memory 200048 kb
Host smart-c6e178d5-cef8-4ff4-8c6c-ba2e105270cc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772000878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.772000878
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.115356135
Short name T515
Test name
Test status
Simulation time 2219747805 ps
CPU time 29.45 seconds
Started Jun 24 06:17:17 PM PDT 24
Finished Jun 24 06:17:48 PM PDT 24
Peak memory 200080 kb
Host smart-fedcea58-de4c-4e48-98fa-72344a1442f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115356135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.115356135
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3031948382
Short name T119
Test name
Test status
Simulation time 377566683 ps
CPU time 4.02 seconds
Started Jun 24 06:17:16 PM PDT 24
Finished Jun 24 06:17:22 PM PDT 24
Peak memory 200052 kb
Host smart-da65cbc5-3d35-42d1-9408-200b0d1e9e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031948382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3031948382
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2278172270
Short name T456
Test name
Test status
Simulation time 84704298615 ps
CPU time 1045.99 seconds
Started Jun 24 06:17:17 PM PDT 24
Finished Jun 24 06:34:45 PM PDT 24
Peak memory 618252 kb
Host smart-7ae743d1-4cab-43a1-b29b-340a61384ff1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278172270 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2278172270
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.352828256
Short name T350
Test name
Test status
Simulation time 49261569 ps
CPU time 1.17 seconds
Started Jun 24 06:17:14 PM PDT 24
Finished Jun 24 06:17:16 PM PDT 24
Peak memory 200008 kb
Host smart-92e07aa9-9f34-42fd-82c3-7e5b26263ba3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352828256 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_hmac_vectors.352828256
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha256_vectors.3793767635
Short name T374
Test name
Test status
Simulation time 36577525117 ps
CPU time 510.84 seconds
Started Jun 24 06:17:16 PM PDT 24
Finished Jun 24 06:25:48 PM PDT 24
Peak memory 200120 kb
Host smart-9c83a188-b4bd-40b7-96ab-463071f7a150
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3793767635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha256_vectors.3793767635
Directory /workspace/8.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha384_vectors.1165440408
Short name T392
Test name
Test status
Simulation time 116844140480 ps
CPU time 1736.56 seconds
Started Jun 24 06:17:16 PM PDT 24
Finished Jun 24 06:46:14 PM PDT 24
Peak memory 215600 kb
Host smart-43c8396c-f64f-4bad-8c05-c0e436ace968
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1165440408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha384_vectors.1165440408
Directory /workspace/8.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha512_vectors.860710501
Short name T469
Test name
Test status
Simulation time 465033039996 ps
CPU time 1894.76 seconds
Started Jun 24 06:17:17 PM PDT 24
Finished Jun 24 06:48:54 PM PDT 24
Peak memory 216480 kb
Host smart-6d42150e-e0d8-4426-b0fc-4136b6856687
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=860710501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha512_vectors.860710501
Directory /workspace/8.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2319832579
Short name T95
Test name
Test status
Simulation time 6226261347 ps
CPU time 36.77 seconds
Started Jun 24 06:17:15 PM PDT 24
Finished Jun 24 06:17:52 PM PDT 24
Peak memory 200148 kb
Host smart-53b8d8ab-7a2f-42c6-ac26-6976c88043fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319832579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2319832579
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2694223242
Short name T313
Test name
Test status
Simulation time 11751535 ps
CPU time 0.6 seconds
Started Jun 24 06:17:19 PM PDT 24
Finished Jun 24 06:17:20 PM PDT 24
Peak memory 196008 kb
Host smart-40ff4660-bc73-426f-a555-13978724ca1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694223242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2694223242
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2316531756
Short name T645
Test name
Test status
Simulation time 3382422610 ps
CPU time 47.7 seconds
Started Jun 24 06:17:19 PM PDT 24
Finished Jun 24 06:18:07 PM PDT 24
Peak memory 200324 kb
Host smart-658d9c3a-b613-4723-8e6d-0b032790bd3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2316531756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2316531756
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2491444053
Short name T240
Test name
Test status
Simulation time 16064035085 ps
CPU time 60.57 seconds
Started Jun 24 06:17:17 PM PDT 24
Finished Jun 24 06:18:19 PM PDT 24
Peak memory 200136 kb
Host smart-6975592b-7a0f-4226-9748-82c7cff7eadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491444053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2491444053
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1627241240
Short name T494
Test name
Test status
Simulation time 1948650678 ps
CPU time 481.58 seconds
Started Jun 24 06:17:15 PM PDT 24
Finished Jun 24 06:25:18 PM PDT 24
Peak memory 695828 kb
Host smart-3a2547d1-2b24-438f-a1cf-e88f1e5c4d85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1627241240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1627241240
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2985367458
Short name T284
Test name
Test status
Simulation time 20685904 ps
CPU time 0.81 seconds
Started Jun 24 06:17:18 PM PDT 24
Finished Jun 24 06:17:20 PM PDT 24
Peak memory 197848 kb
Host smart-3be49782-bb59-4e1a-aa9b-fdc8449ec205
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985367458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2985367458
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.713327356
Short name T470
Test name
Test status
Simulation time 1921213671 ps
CPU time 113.6 seconds
Started Jun 24 06:17:16 PM PDT 24
Finished Jun 24 06:19:11 PM PDT 24
Peak memory 200080 kb
Host smart-5275ad71-958e-4ec1-9a59-cc3ce548c830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713327356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.713327356
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3867538410
Short name T310
Test name
Test status
Simulation time 765129800 ps
CPU time 7.22 seconds
Started Jun 24 06:17:16 PM PDT 24
Finished Jun 24 06:17:25 PM PDT 24
Peak memory 200108 kb
Host smart-18bd98aa-0a3e-41af-98f0-e7634a8601e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867538410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3867538410
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.635027229
Short name T221
Test name
Test status
Simulation time 166860016 ps
CPU time 1.11 seconds
Started Jun 24 06:17:15 PM PDT 24
Finished Jun 24 06:17:16 PM PDT 24
Peak memory 200092 kb
Host smart-7d33db6b-fb72-47c8-91e9-66ef005ebca1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635027229 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_hmac_vectors.635027229
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha256_vectors.2462744612
Short name T357
Test name
Test status
Simulation time 20591087910 ps
CPU time 423.25 seconds
Started Jun 24 06:17:15 PM PDT 24
Finished Jun 24 06:24:19 PM PDT 24
Peak memory 200116 kb
Host smart-12353859-778b-4924-bf64-b6f281ae0c85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2462744612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha256_vectors.2462744612
Directory /workspace/9.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha384_vectors.2772177131
Short name T511
Test name
Test status
Simulation time 81884359319 ps
CPU time 1896.68 seconds
Started Jun 24 06:17:16 PM PDT 24
Finished Jun 24 06:48:54 PM PDT 24
Peak memory 215672 kb
Host smart-b27b1516-08fa-4a2a-83c9-f2d029ee4614
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2772177131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha384_vectors.2772177131
Directory /workspace/9.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha512_vectors.1960354745
Short name T199
Test name
Test status
Simulation time 133847591045 ps
CPU time 1687.03 seconds
Started Jun 24 06:17:19 PM PDT 24
Finished Jun 24 06:45:27 PM PDT 24
Peak memory 216100 kb
Host smart-ea91f5e2-3df4-4ad0-9fdb-d9524550a604
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1960354745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha512_vectors.1960354745
Directory /workspace/9.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3632653282
Short name T122
Test name
Test status
Simulation time 3849600940 ps
CPU time 70.69 seconds
Started Jun 24 06:17:18 PM PDT 24
Finished Jun 24 06:18:30 PM PDT 24
Peak memory 200132 kb
Host smart-7cc6595b-079f-43bd-a289-e6f8367ad389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632653282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3632653282
Directory /workspace/9.hmac_wipe_secret/latest
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