Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	36150238	1			T1	22864		T2	14123		T3	424
all_values[1]	36150238	1			T1	22864		T2	14123		T3	424
all_values[2]	36150238	1			T1	22864		T2	14123		T3	424

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81596

1

T1

1956

T5

734

T6

3

auto[1]

108369118

1

T1

66636

T2

42369

T3

1272

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

89715303

1

T1

51451

T2

32725

T3

1091

auto[1]

18735411

1

T1

17141

T2

9644

T3

181

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	33829	1			T5	505		T7	2		T31	1183
all_values[0]	auto[0]	auto[1]	165	1			T5	2		T31	2		T22	2
all_values[0]	auto[1]	auto[0]	36062893	1			T1	22856		T2	14105		T3	411
all_values[0]	auto[1]	auto[1]	53351	1			T1	8		T2	18		T3	13
all_values[1]	auto[0]	auto[0]	21241	1			T5	224		T14	3		T7	2
all_values[1]	auto[0]	auto[1]	76	1			T37	1		T62	6		T67	1
all_values[1]	auto[1]	auto[0]	36124682	1			T1	22864		T2	14123		T3	424
all_values[1]	auto[1]	auto[1]	4239	1			T7	144		T8	34		T20	84
all_values[2]	auto[0]	auto[0]	11803	1			T5	3		T6	3		T14	1
all_values[2]	auto[0]	auto[1]	14482	1			T1	1956		T14	2		T19	505
all_values[2]	auto[1]	auto[0]	17460855	1			T1	5731		T2	4497		T3	256
all_values[2]	auto[1]	auto[1]	18663098	1			T1	15177		T2	9626		T3	168