Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
74.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33
Crosses	32	10	22	68.75

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	2	13	86.67	100	1	1	0
msg_len_upper_cp	1	1	0	0.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	8	22	73.33	100	1	1	0
msg_len_upper_cross	2	2	0	0.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101890

1

T3

18

T4

28

T5

32

auto[1]

59284

1

T1

24

T2

38

T3

10

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	2	13	86.67

User Defined Bins for msg_len_lower_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_1023	0	1	1
len_511	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	26302	1			T1	6		T2	3		T4	13
len_1026_2046	16936	1			T5	13		T11	6		T12	6
len_514_1022	4664	1			T2	1		T11	4		T12	4
len_2_510	24392	1			T2	1		T3	9		T9	2
len_2049	7	1			T117	4		T50	3		-	-
len_2048	38	1			T118	3		T119	1		T120	3
len_2047	3	1			T115	2		T121	1		-	-
len_1025	3	1			T18	2		T50	1		-	-
len_1024	50	1			T15	2		T30	2		T118	3
len_513	3	1			T122	2		T123	1		-	-
len_512	67	1			T15	1		T30	2		T118	1
len_1	806	1			T1	5		T2	14		T11	2
len_0	7316	1			T1	1		T3	5		T4	11

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for msg_len_upper_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_upper	0	1	1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	8	22	73.33	8

Automatically Generated Cross Bins for msg_len_lower_cross

Uncovered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[len_2049]	0	1	1
[auto[0]]	[len_2047 , len_1025]	--	--	2
[auto[0]]	[len_1023 , len_513]	--	--	2
[auto[0]]	[len_511]	0	1	1
[auto[1]]	[len_1023]	0	1	1
[auto[1]]	[len_511]	0	1	1

Covered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	16196	1			T4	7		T5	6		T11	22
auto[0]	len_1026_2046	8147	1			T5	6		T11	6		T12	6
auto[0]	len_514_1022	2943	1			T11	4		T12	4		T16	3
auto[0]	len_2_510	19923	1			T3	5		T5	3		T11	74
auto[0]	len_2048	24	1			T118	1		T119	1		T120	3
auto[0]	len_1024	33	1			T30	2		T118	2		T120	2
auto[0]	len_512	43	1			T30	2		T118	1		T124	1
auto[0]	len_1	138	1			T11	2		T12	1		T16	1
auto[0]	len_0	3498	1			T3	4		T4	7		T5	1
auto[1]	len_2050_plus	10106	1			T1	6		T2	3		T4	6
auto[1]	len_1026_2046	8789	1			T5	7		T14	2		T15	162
auto[1]	len_514_1022	1721	1			T2	1		T15	38		T30	27
auto[1]	len_2_510	4469	1			T2	1		T3	4		T9	2
auto[1]	len_2049	7	1			T117	4		T50	3		-	-
auto[1]	len_2048	14	1			T118	2		T125	1		T126	2
auto[1]	len_2047	3	1			T115	2		T121	1		-	-
auto[1]	len_1025	3	1			T18	2		T50	1		-	-
auto[1]	len_1024	17	1			T15	2		T118	1		T127	1
auto[1]	len_513	3	1			T122	2		T123	1		-	-
auto[1]	len_512	24	1			T15	1		T128	1		T129	1
auto[1]	len_1	668	1			T1	5		T2	14		T14	20
auto[1]	len_0	3818	1			T1	1		T3	1		T4	4

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	2	0	0.00	2

Automatically Generated Cross Bins for msg_len_upper_cross

Uncovered bins

hmac_en	msg_len_upper_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	2