Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17589534

1

T1

10819

T2

5003

T3

132

auto[1]

1331612

1

T1

11853

T2

8861

T3

221

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1367910

1

T1

9239

T2

2542

T3

233

auto[1]

17553236

1

T1

13433

T2

11322

T3

120

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16904980

1

T3

222

T4

5851

T5

5646

auto[1]

2016166

1

T1

22672

T2

13864

T3

131

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	16790620	1			T1	19997		T2	11746		T3	341
fifo_depth[1]	471865	1			T1	258		T2	227		T3	7
fifo_depth[2]	342200	1			T1	255		T2	214		T3	4
fifo_depth[3]	264366	1			T1	272		T2	209		T3	1
fifo_depth[4]	202522	1			T1	247		T2	194		T9	2
fifo_depth[5]	157515	1			T1	272		T2	197		T10	2
fifo_depth[6]	136706	1			T1	255		T2	209		T4	2
fifo_depth[7]	122384	1			T1	254		T2	180		T10	2

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2130526

1

T1

2675

T2

2118

T3

12

auto[1]

16790620

1

T1

19997

T2

11746

T3

341

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18915284

1

T1

22672

T2

13864

T3

353

auto[1]

5862

1

T15

261

T7

1

T8

2

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

34049

1

T3

2

T5

144

T15

808

auto[0]

auto[0]

auto[0]

auto[1]

26195

1

T3

2

T4

127

T15

196

auto[0]

auto[0]

auto[1]

auto[0]

1748265

1

T4

22

T5

177

T11

1220

auto[0]

auto[0]

auto[1]

auto[1]

24947

1

T5

68

T7

5

T31

161

auto[0]

auto[1]

auto[0]

auto[0]

68110

1

T1

767

T5

89

T14

1022

auto[0]

auto[1]

auto[0]

auto[1]

78945

1

T2

625

T3

5

T4

11

auto[0]

auto[1]

auto[1]

auto[0]

76340

1

T2

263

T9

9

T10

19

auto[0]

auto[1]

auto[1]

auto[1]

73675

1

T1

1908

T2

1230

T3

3

auto[1]

auto[0]

auto[0]

auto[0]

167200

1

T3

70

T4

2617

T5

1902

auto[1]

auto[0]

auto[0]

auto[1]

122301

1

T3

90

T4

1492

T5

250

auto[1]

auto[0]

auto[1]

auto[0]

14639288

1

T3

17

T4

1590

T5

2362

auto[1]

auto[0]

auto[1]

auto[1]

142735

1

T3

41

T4

3

T5

743

auto[1]

auto[1]

auto[0]

auto[0]

424015

1

T1

1113

T2

1417

T3

26

auto[1]

auto[1]

auto[0]

auto[1]

447095

1

T1

7359

T2

500

T3

38

auto[1]

auto[1]

auto[1]

auto[0]

432267

1

T1

8939

T2

3323

T3

17

auto[1]

auto[1]

auto[1]

auto[1]

415719

1

T1

2586

T2

6506

T3

42

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

200592

1

T3

72

T4

2617

T5

2046

auto[0]

auto[0]

auto[0]

auto[1]

147657

1

T3

92

T4

1619

T5

250

auto[0]

auto[0]

auto[1]

auto[0]

16386105

1

T3

17

T4

1612

T5

2539

auto[0]

auto[0]

auto[1]

auto[1]

167511

1

T3

41

T4

3

T5

811

auto[0]

auto[1]

auto[0]

auto[0]

491976

1

T1

1880

T2

1417

T3

26

auto[0]

auto[1]

auto[0]

auto[1]

524041

1

T1

7359

T2

1125

T3

43

auto[0]

auto[1]

auto[1]

auto[0]

508121

1

T1

8939

T2

3586

T3

17

auto[0]

auto[1]

auto[1]

auto[1]

489281

1

T1

4494

T2

7736

T3

45

auto[1]

auto[0]

auto[0]

auto[0]

657

1

T15

1

T7

1

T21

1

auto[1]

auto[0]

auto[0]

auto[1]

839

1

T22

1

T150

4

T151

6

auto[1]

auto[0]

auto[1]

auto[0]

1448

1

T150

147

T152

1

T53

452

auto[1]

auto[0]

auto[1]

auto[1]

171

1

T8

1

T20

1

T22

1

auto[1]

auto[1]

auto[0]

auto[0]

149

1

T15

8

T22

1

T24

1

auto[1]

auto[1]

auto[0]

auto[1]

1999

1

T15

56

T8

1

T25

1

auto[1]

auto[1]

auto[1]

auto[0]

486

1

T15

196

T23

1

T150

1

auto[1]

auto[1]

auto[1]

auto[1]

113

1

T22

1

T150

37

T151

4

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	167200	1			T3	70		T4	2617		T5	1902
fifo_depth[0]	auto[0]	auto[0]	auto[1]	122301	1			T3	90		T4	1492		T5	250
fifo_depth[0]	auto[0]	auto[1]	auto[0]	14639288	1			T3	17		T4	1590		T5	2362
fifo_depth[0]	auto[0]	auto[1]	auto[1]	142735	1			T3	41		T4	3		T5	743
fifo_depth[0]	auto[1]	auto[0]	auto[0]	424015	1			T1	1113		T2	1417		T3	26
fifo_depth[0]	auto[1]	auto[0]	auto[1]	447095	1			T1	7359		T2	500		T3	38
fifo_depth[0]	auto[1]	auto[1]	auto[0]	432267	1			T1	8939		T2	3323		T3	17
fifo_depth[0]	auto[1]	auto[1]	auto[1]	415719	1			T1	2586		T2	6506		T3	42
fifo_depth[1]	auto[0]	auto[0]	auto[0]	3965	1			T3	2		T5	47		T15	1
fifo_depth[1]	auto[0]	auto[0]	auto[1]	2894	1			T3	2		T4	61		T15	7
fifo_depth[1]	auto[0]	auto[1]	auto[0]	431434	1			T4	22		T5	71		T11	909
fifo_depth[1]	auto[0]	auto[1]	auto[1]	3435	1			T5	23		T31	31		T18	23
fifo_depth[1]	auto[1]	auto[0]	auto[0]	7254	1			T1	75		T5	38		T14	89
fifo_depth[1]	auto[1]	auto[0]	auto[1]	7551	1			T2	66		T3	2		T4	11
fifo_depth[1]	auto[1]	auto[1]	auto[0]	7809	1			T2	24		T9	4		T10	3
fifo_depth[1]	auto[1]	auto[1]	auto[1]	7523	1			T1	183		T2	137		T3	1
fifo_depth[2]	auto[0]	auto[0]	auto[0]	3371	1			T5	45		T15	11		T30	2
fifo_depth[2]	auto[0]	auto[0]	auto[1]	2409	1			T4	38		T15	2		T30	12
fifo_depth[2]	auto[0]	auto[1]	auto[0]	305946	1			T5	54		T11	257		T12	2402
fifo_depth[2]	auto[0]	auto[1]	auto[1]	2819	1			T5	22		T31	25		T18	14
fifo_depth[2]	auto[1]	auto[0]	auto[0]	6496	1			T1	62		T5	28		T14	90
fifo_depth[2]	auto[1]	auto[0]	auto[1]	6975	1			T2	56		T3	2		T5	23
fifo_depth[2]	auto[1]	auto[1]	auto[0]	7083	1			T2	25		T9	3		T10	3
fifo_depth[2]	auto[1]	auto[1]	auto[1]	7101	1			T1	193		T2	133		T3	2
fifo_depth[3]	auto[0]	auto[0]	auto[0]	2541	1			T5	28		T15	11		T30	3
fifo_depth[3]	auto[0]	auto[0]	auto[1]	1783	1			T4	17		T15	9		T30	7
fifo_depth[3]	auto[0]	auto[1]	auto[0]	232176	1			T5	30		T11	44		T12	1979
fifo_depth[3]	auto[0]	auto[1]	auto[1]	2100	1			T5	19		T31	27		T18	4
fifo_depth[3]	auto[1]	auto[0]	auto[0]	5877	1			T1	63		T5	8		T14	93
fifo_depth[3]	auto[1]	auto[0]	auto[1]	6478	1			T2	61		T3	1		T5	9
fifo_depth[3]	auto[1]	auto[1]	auto[0]	6803	1			T2	32		T10	2		T5	8
fifo_depth[3]	auto[1]	auto[1]	auto[1]	6608	1			T1	209		T2	116		T5	11
fifo_depth[4]	auto[0]	auto[0]	auto[0]	2481	1			T5	15		T15	42		T30	4
fifo_depth[4]	auto[0]	auto[0]	auto[1]	1807	1			T4	9		T15	1		T30	5
fifo_depth[4]	auto[0]	auto[1]	auto[0]	171203	1			T5	15		T11	8		T12	1559
fifo_depth[4]	auto[0]	auto[1]	auto[1]	1971	1			T5	3		T31	17		T18	2
fifo_depth[4]	auto[1]	auto[0]	auto[0]	5698	1			T1	57		T5	11		T14	87
fifo_depth[4]	auto[1]	auto[0]	auto[1]	6281	1			T2	63		T5	3		T14	227
fifo_depth[4]	auto[1]	auto[1]	auto[0]	6472	1			T2	24		T9	2		T10	3
fifo_depth[4]	auto[1]	auto[1]	auto[1]	6609	1			T1	190		T2	107		T5	5
fifo_depth[5]	auto[0]	auto[0]	auto[0]	1965	1			T5	6		T15	42		T30	2
fifo_depth[5]	auto[0]	auto[0]	auto[1]	1300	1			T15	10		T30	3		T19	41
fifo_depth[5]	auto[0]	auto[1]	auto[0]	128509	1			T5	7		T11	2		T12	1184
fifo_depth[5]	auto[0]	auto[1]	auto[1]	1556	1			T31	11		T18	1		T19	11
fifo_depth[5]	auto[1]	auto[0]	auto[0]	5509	1			T1	79		T5	4		T14	94
fifo_depth[5]	auto[1]	auto[0]	auto[1]	6192	1			T2	57		T5	2		T14	236
fifo_depth[5]	auto[1]	auto[1]	auto[0]	6226	1			T2	30		T10	2		T14	141
fifo_depth[5]	auto[1]	auto[1]	auto[1]	6258	1			T1	193		T2	110		T14	113
fifo_depth[6]	auto[0]	auto[0]	auto[0]	1938	1			T5	2		T15	44		T30	1
fifo_depth[6]	auto[0]	auto[0]	auto[1]	1493	1			T4	2		T30	1		T19	39
fifo_depth[6]	auto[0]	auto[1]	auto[0]	107855	1			T12	1060		T16	9		T17	2452
fifo_depth[6]	auto[0]	auto[1]	auto[1]	1538	1			T5	1		T31	7		T19	10
fifo_depth[6]	auto[1]	auto[0]	auto[0]	5256	1			T1	69		T14	88		T15	38
fifo_depth[6]	auto[1]	auto[0]	auto[1]	6013	1			T2	63		T14	245		T18	1
fifo_depth[6]	auto[1]	auto[1]	auto[0]	6301	1			T2	28		T10	2		T14	127
fifo_depth[6]	auto[1]	auto[1]	auto[1]	6312	1			T1	186		T2	118		T14	96
fifo_depth[7]	auto[0]	auto[0]	auto[0]	1801	1			T15	73		T31	7		T19	75
fifo_depth[7]	auto[0]	auto[0]	auto[1]	1334	1			T15	7		T30	1		T19	45
fifo_depth[7]	auto[0]	auto[1]	auto[0]	94517	1			T12	815		T16	1		T17	2232
fifo_depth[7]	auto[0]	auto[1]	auto[1]	1412	1			T31	8		T19	10		T118	1
fifo_depth[7]	auto[1]	auto[0]	auto[0]	5333	1			T1	72		T14	90		T15	52
fifo_depth[7]	auto[1]	auto[0]	auto[1]	5953	1			T2	55		T14	241		T15	4
fifo_depth[7]	auto[1]	auto[1]	auto[0]	6077	1			T2	23		T10	2		T14	128
fifo_depth[7]	auto[1]	auto[1]	auto[1]	5957	1			T1	182		T2	102		T14	100