Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	36150238	1			T1	22864		T2	14123		T3	424
all_pins[1]	36150238	1			T1	22864		T2	14123		T3	424
all_pins[2]	36150238	1			T1	22864		T2	14123		T3	424

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	89729393	1			T1	53405		T2	32723		T3	1090
values[0x1]	18721321	1			T1	15187		T2	9646		T3	182
transitions[0x0=>0x1]	18721103	1			T1	15187		T2	9646		T3	182
transitions[0x1=>0x0]	18721119	1			T1	15187		T2	9646		T3	182

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	36096362	1			T1	22854		T2	14103		T3	410
all_pins[0]	values[0x1]	53876	1			T1	10		T2	20		T3	14
all_pins[0]	transitions[0x0=>0x1]	53833	1			T1	10		T2	20		T3	14
all_pins[0]	transitions[0x1=>0x0]	18663071	1			T1	15177		T2	9626		T3	168
all_pins[1]	values[0x0]	36145891	1			T1	22864		T2	14123		T3	424
all_pins[1]	values[0x1]	4347	1			T7	148		T8	35		T20	86
all_pins[1]	transitions[0x0=>0x1]	4189	1			T7	142		T8	33		T20	83
all_pins[1]	transitions[0x1=>0x0]	53718	1			T1	10		T2	20		T3	14
all_pins[2]	values[0x0]	17487140	1			T1	7687		T2	4497		T3	256
all_pins[2]	values[0x1]	18663098	1			T1	15177		T2	9626		T3	168
all_pins[2]	transitions[0x0=>0x1]	18663081	1			T1	15177		T2	9626		T3	168
all_pins[2]	transitions[0x1=>0x0]	4330	1			T7	148		T8	35		T20	86