Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 421 1 T5 4 T37 7 T62 44
all_values[1] 421 1 T5 4 T37 7 T62 44
all_values[2] 421 1 T5 4 T37 7 T62 44


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 689 1 T5 7 T37 12 T62 66
auto[1] 574 1 T5 5 T37 9 T62 66


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 481 1 T5 9 T37 7 T62 42
auto[1] 782 1 T5 3 T37 14 T62 90


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 729 1 T5 10 T37 12 T62 73
auto[1] 534 1 T5 2 T37 9 T62 59


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 87 1 T37 1 T62 5 T137 2
all_values[0] auto[0] auto[0] auto[1] 32 1 T37 1 T62 8 T67 1
all_values[0] auto[0] auto[1] auto[0] 86 1 T5 1 T37 2 T62 9
all_values[0] auto[0] auto[1] auto[1] 33 1 T5 1 T62 2 T137 1
all_values[0] auto[1] auto[0] auto[1] 108 1 T5 2 T37 3 T62 12
all_values[0] auto[1] auto[1] auto[1] 75 1 T62 8 T67 2 T69 1
all_values[1] auto[0] auto[0] auto[0] 97 1 T5 1 T37 1 T62 7
all_values[1] auto[0] auto[0] auto[1] 51 1 T37 1 T62 4 T67 1
all_values[1] auto[0] auto[1] auto[0] 60 1 T5 3 T62 9 T67 1
all_values[1] auto[0] auto[1] auto[1] 49 1 T37 2 T62 6 T137 3
all_values[1] auto[1] auto[0] auto[1] 88 1 T37 1 T62 6 T67 2
all_values[1] auto[1] auto[1] auto[1] 76 1 T37 2 T62 12 T137 3
all_values[2] auto[0] auto[0] auto[0] 81 1 T5 4 T37 1 T62 6
all_values[2] auto[0] auto[0] auto[1] 43 1 T37 1 T62 6 T137 1
all_values[2] auto[0] auto[1] auto[0] 70 1 T37 2 T62 6 T67 4
all_values[2] auto[0] auto[1] auto[1] 40 1 T62 5 T67 1 T137 2
all_values[2] auto[1] auto[0] auto[1] 102 1 T37 2 T62 12 T137 4
all_values[2] auto[1] auto[1] auto[1] 85 1 T37 1 T62 9 T67 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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