Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.47	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	2	18	90.00
Crosses	82	22	60	73.17

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	1	4	80.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	1	6	85.71	100	1	1	0
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	8	0	8	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	11	24	68.57	100	1	1	0
key_length_x_digest_size	35	11	24	68.57	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	1	4	80.00

User Defined Bins for digest_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
sha2_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_none	91	1			T4	3		T31	1		T33	4
sha2_512	20395	1			T1	3		T2	7		T3	4
sha2_384	20901	1			T1	2		T2	4		T3	3
sha2_256	11558	1			T1	1		T2	4		T3	2

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50201

1

T1

2

T2

4

T3

5

auto[1]

2744

1

T1

4

T2

11

T3

4

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2820

1

T1

4

T2

8

T3

7

auto[1]

50125

1

T1

2

T2

7

T3

2

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

2856

1

T1

6

T2

15

T3

4

disabled

50089

1

T3

5

T4

24

T5

13

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for key_length

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
key_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	1002	1			T3	2		T4	1		T5	1
key_1024	801	1			T1	2		T2	1		T3	1
key_512	977	1			T2	2		T3	1		T4	2
key_384	946	1			T2	1		T3	2		T4	11
key_256	48281	1			T1	3		T2	5		T3	2
key_128	938	1			T1	1		T2	6		T3	1

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

52736

1

T1

6

T2

15

T3

9

disabled

209

1

T4

8

T31

2

T33

6

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
enabled	auto[0]	auto[0]	610	1			T1	2		T3	1		T4	2
enabled	auto[0]	auto[1]	751	1			T1	2		T2	8		T3	2
enabled	auto[1]	auto[0]	843	1			T2	4		T9	4		T4	1
enabled	auto[1]	auto[1]	652	1			T1	2		T2	3		T3	1
disabled	auto[0]	auto[0]	796	1			T3	3		T5	4		T15	1
disabled	auto[0]	auto[1]	663	1			T3	1		T4	11		T15	2
disabled	auto[1]	auto[0]	47952	1			T3	1		T4	12		T5	6
disabled	auto[1]	auto[1]	678	1			T4	1		T5	3		T15	1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

2747

1

T1

6

T2

15

T3

4

enabled

disabled

109

1

T4

3

T33

4

T130

2

disabled

disabled

100

1

T4

5

T31

2

T33

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

49989

1

T3

5

T4

19

T5

13

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	11	24	68.57	11
Automatically Generated Cross Bins	34	11	23	67.65	11
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid]	--	--	6

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_none	36	1			T31	1		T33	1		T77	1
key_none	sha2_512	373	1			T3	1		T5	1		T15	1
key_none	sha2_384	302	1			T4	1		T15	1		T30	3
key_none	sha2_256	291	1			T3	1		T15	1		T7	4
key_1024	sha2_none	11	1			T33	2		T131	2		T62	2
key_1024	sha2_512	314	1			T1	1		T2	1		T4	11
key_1024	sha2_384	331	1			T1	1		T15	1		T7	1
key_512	sha2_none	15	1			T4	1		T33	1		T131	2
key_512	sha2_512	318	1			T2	1		T3	1		T5	1
key_512	sha2_384	331	1			T5	2		T14	2		T15	1
key_512	sha2_256	313	1			T2	1		T4	1		T15	1
key_384	sha2_none	16	1			T4	1		T130	1		T132	1
key_384	sha2_512	261	1			T3	2		T5	2		T14	1
key_384	sha2_384	377	1			T2	1		T5	1		T6	1
key_384	sha2_256	292	1			T4	10		T5	3		T14	1
key_256	sha2_none	4	1			T4	1		T133	2		T134	1
key_256	sha2_512	18829	1			T1	1		T2	2		T17	386
key_256	sha2_384	19244	1			T1	1		T2	2		T3	2
key_256	sha2_256	10204	1			T1	1		T2	1		T9	4
key_128	sha2_none	9	1			T135	1		T62	1		T136	1
key_128	sha2_512	300	1			T1	1		T2	3		T5	2
key_128	sha2_384	316	1			T2	1		T3	1		T4	10
key_128	sha2_256	313	1			T2	2		T4	1		T5	3

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

145

1

T3

1

T5

1

T7

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	11	24	68.57	11

Automatically Generated Cross Bins for key_length_x_digest_size

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid]	--	--	6

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_none	36	1			T31	1		T33	1		T77	1
key_none	sha2_512	373	1			T3	1		T5	1		T15	1
key_none	sha2_384	302	1			T4	1		T15	1		T30	3
key_none	sha2_256	291	1			T3	1		T15	1		T7	4
key_1024	sha2_none	11	1			T33	2		T131	2		T62	2
key_1024	sha2_512	314	1			T1	1		T2	1		T4	11
key_1024	sha2_384	331	1			T1	1		T15	1		T7	1
key_1024	sha2_256	145	1			T3	1		T5	1		T7	1
key_512	sha2_none	15	1			T4	1		T33	1		T131	2
key_512	sha2_512	318	1			T2	1		T3	1		T5	1
key_512	sha2_384	331	1			T5	2		T14	2		T15	1
key_512	sha2_256	313	1			T2	1		T4	1		T15	1
key_384	sha2_none	16	1			T4	1		T130	1		T132	1
key_384	sha2_512	261	1			T3	2		T5	2		T14	1
key_384	sha2_384	377	1			T2	1		T5	1		T6	1
key_384	sha2_256	292	1			T4	10		T5	3		T14	1
key_256	sha2_none	4	1			T4	1		T133	2		T134	1
key_256	sha2_512	18829	1			T1	1		T2	2		T17	386
key_256	sha2_384	19244	1			T1	1		T2	2		T3	2
key_256	sha2_256	10204	1			T1	1		T2	1		T9	4
key_128	sha2_none	9	1			T135	1		T62	1		T136	1
key_128	sha2_512	300	1			T1	1		T2	3		T5	2
key_128	sha2_384	316	1			T2	1		T3	1		T4	10
key_128	sha2_256	313	1			T2	2		T4	1		T5	3