Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.51 95.85 92.94 100.00 74.36 91.89 99.49 93.06


Total test records in report: 779
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html
T752 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3132744618 Jun 25 05:26:06 PM PDT 24 Jun 25 05:26:09 PM PDT 24 93028857 ps
T753 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.823023527 Jun 25 05:26:20 PM PDT 24 Jun 25 05:26:23 PM PDT 24 19138103 ps
T754 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1313996235 Jun 25 05:26:33 PM PDT 24 Jun 25 05:26:36 PM PDT 24 36429070 ps
T755 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1989044489 Jun 25 05:26:08 PM PDT 24 Jun 25 05:26:12 PM PDT 24 86788690 ps
T756 /workspace/coverage/cover_reg_top/36.hmac_intr_test.1310998291 Jun 25 05:26:21 PM PDT 24 Jun 25 05:26:23 PM PDT 24 16911360 ps
T757 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.94149608 Jun 25 05:26:31 PM PDT 24 Jun 25 05:26:34 PM PDT 24 274822066 ps
T758 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.702544231 Jun 25 05:26:05 PM PDT 24 Jun 25 05:26:15 PM PDT 24 565708510 ps
T759 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.744087236 Jun 25 05:26:13 PM PDT 24 Jun 25 05:26:16 PM PDT 24 62135999 ps
T760 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1230124865 Jun 25 05:26:16 PM PDT 24 Jun 25 05:26:27 PM PDT 24 597972837 ps
T761 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1265898758 Jun 25 05:26:27 PM PDT 24 Jun 25 05:26:30 PM PDT 24 47555241 ps
T762 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.738162546 Jun 25 05:26:29 PM PDT 24 Jun 25 05:26:32 PM PDT 24 49863555 ps
T763 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2052257483 Jun 25 05:26:09 PM PDT 24 Jun 25 05:26:15 PM PDT 24 168368541 ps
T764 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.391740956 Jun 25 05:26:19 PM PDT 24 Jun 25 05:26:27 PM PDT 24 745044694 ps
T765 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2377131534 Jun 25 05:26:16 PM PDT 24 Jun 25 05:26:18 PM PDT 24 11275345 ps
T766 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1335853018 Jun 25 05:26:21 PM PDT 24 Jun 25 05:26:24 PM PDT 24 139379253 ps
T767 /workspace/coverage/cover_reg_top/3.hmac_intr_test.836139779 Jun 25 05:26:21 PM PDT 24 Jun 25 05:26:23 PM PDT 24 17503728 ps
T768 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2460636565 Jun 25 05:26:15 PM PDT 24 Jun 25 05:26:18 PM PDT 24 70269169 ps
T769 /workspace/coverage/cover_reg_top/13.hmac_intr_test.52335063 Jun 25 05:26:44 PM PDT 24 Jun 25 05:26:47 PM PDT 24 55324308 ps
T770 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2414934527 Jun 25 05:26:35 PM PDT 24 Jun 25 05:26:38 PM PDT 24 80611415 ps
T771 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1924323836 Jun 25 05:26:15 PM PDT 24 Jun 25 05:26:17 PM PDT 24 18919538 ps
T772 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1051831039 Jun 25 05:26:08 PM PDT 24 Jun 25 05:26:13 PM PDT 24 888727459 ps
T773 /workspace/coverage/cover_reg_top/35.hmac_intr_test.66440064 Jun 25 05:26:22 PM PDT 24 Jun 25 05:26:24 PM PDT 24 34301415 ps
T774 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2810461144 Jun 25 05:26:10 PM PDT 24 Jun 25 05:26:14 PM PDT 24 33292152 ps
T775 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2874944497 Jun 25 05:26:16 PM PDT 24 Jun 25 05:26:22 PM PDT 24 287595603 ps
T144 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2374078657 Jun 25 05:26:18 PM PDT 24 Jun 25 05:26:22 PM PDT 24 729600993 ps
T776 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2666995052 Jun 25 05:26:11 PM PDT 24 Jun 25 05:26:14 PM PDT 24 48434787 ps
T777 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.778661069 Jun 25 05:26:28 PM PDT 24 Jun 25 05:26:33 PM PDT 24 58736404 ps
T778 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2104120400 Jun 25 05:26:21 PM PDT 24 Jun 25 05:26:23 PM PDT 24 276767169 ps
T779 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3997583340 Jun 25 05:26:16 PM PDT 24 Jun 25 05:26:21 PM PDT 24 356681612 ps

Test location /workspace/coverage/default/6.hmac_smoke.4072253241
Short name T3
Test name
Test status
Simulation time 1260059544 ps
CPU time 6.5 seconds
Started Jun 25 05:29:08 PM PDT 24
Finished Jun 25 05:29:15 PM PDT 24
Peak memory 199964 kb
Host smart-efae6a9c-ed11-4962-95c0-5ef00bd95a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072253241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.4072253241
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1775587674
Short name T15
Test name
Test status
Simulation time 2570606226 ps
CPU time 34.82 seconds
Started Jun 25 05:30:10 PM PDT 24
Finished Jun 25 05:30:46 PM PDT 24
Peak memory 200040 kb
Host smart-a2f4114d-3a18-401c-abe9-8a6cbb3c9db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775587674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1775587674
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.526991284
Short name T39
Test name
Test status
Simulation time 190321366236 ps
CPU time 2085.3 seconds
Started Jun 25 05:26:50 PM PDT 24
Finished Jun 25 06:01:38 PM PDT 24
Peak memory 228344 kb
Host smart-fc476385-aa7b-480f-96fb-7bd739d4c3fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526991284 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.526991284
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/31.hmac_stress_all.973244829
Short name T5
Test name
Test status
Simulation time 24439609504 ps
CPU time 80.8 seconds
Started Jun 25 05:29:35 PM PDT 24
Finished Jun 25 05:30:58 PM PDT 24
Peak memory 200064 kb
Host smart-32692993-8e14-4326-8425-cfd82359f8f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973244829 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.973244829
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all.237285408
Short name T62
Test name
Test status
Simulation time 137413632079 ps
CPU time 633.65 seconds
Started Jun 25 05:28:57 PM PDT 24
Finished Jun 25 05:39:33 PM PDT 24
Peak memory 216456 kb
Host smart-bd6e32b5-7cba-4b33-8b2f-94fd9c54a239
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237285408 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.237285408
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1800895916
Short name T58
Test name
Test status
Simulation time 880893379 ps
CPU time 4.41 seconds
Started Jun 25 05:26:10 PM PDT 24
Finished Jun 25 05:26:17 PM PDT 24
Peak memory 199688 kb
Host smart-29464c2a-1d32-4ca3-a0b9-1143105b8f36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800895916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1800895916
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2201886921
Short name T22
Test name
Test status
Simulation time 1195482062 ps
CPU time 53.04 seconds
Started Jun 25 05:29:23 PM PDT 24
Finished Jun 25 05:30:17 PM PDT 24
Peak memory 200088 kb
Host smart-7e114913-3ca2-4c13-8a9b-778e632cbbcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2201886921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2201886921
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3900370545
Short name T34
Test name
Test status
Simulation time 12819345 ps
CPU time 0.61 seconds
Started Jun 25 05:30:23 PM PDT 24
Finished Jun 25 05:30:25 PM PDT 24
Peak memory 195756 kb
Host smart-cf0a5b3b-0e44-4d90-b061-74540b248133
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900370545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3900370545
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_error.559966707
Short name T4
Test name
Test status
Simulation time 45694826605 ps
CPU time 185.75 seconds
Started Jun 25 05:29:38 PM PDT 24
Finished Jun 25 05:32:46 PM PDT 24
Peak memory 200104 kb
Host smart-dffbcd0d-26ad-4ebb-9006-98083a020425
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559966707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.559966707
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3180531723
Short name T91
Test name
Test status
Simulation time 1659217326 ps
CPU time 16.57 seconds
Started Jun 25 05:26:21 PM PDT 24
Finished Jun 25 05:26:39 PM PDT 24
Peak memory 199640 kb
Host smart-bc2f8bde-b49c-4dc6-8480-4fe5f6ed4c39
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180531723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3180531723
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3614681090
Short name T14
Test name
Test status
Simulation time 5591785580 ps
CPU time 844.94 seconds
Started Jun 25 05:29:00 PM PDT 24
Finished Jun 25 05:43:08 PM PDT 24
Peak memory 690748 kb
Host smart-c6d97aa7-a417-4315-a5ff-6099fd7296f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3614681090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3614681090
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.61399458
Short name T44
Test name
Test status
Simulation time 578481769 ps
CPU time 0.88 seconds
Started Jun 25 05:28:47 PM PDT 24
Finished Jun 25 05:28:49 PM PDT 24
Peak memory 218212 kb
Host smart-dca746af-9592-4645-971a-b6b31d8b1890
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61399458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.61399458
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.750365743
Short name T118
Test name
Test status
Simulation time 34577297540 ps
CPU time 75.1 seconds
Started Jun 25 05:29:34 PM PDT 24
Finished Jun 25 05:30:52 PM PDT 24
Peak memory 200124 kb
Host smart-e7e4af7e-0391-46c6-9d37-6a7be503a446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750365743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.750365743
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1278807741
Short name T50
Test name
Test status
Simulation time 15395375245 ps
CPU time 582.02 seconds
Started Jun 25 05:28:58 PM PDT 24
Finished Jun 25 05:38:43 PM PDT 24
Peak memory 697044 kb
Host smart-175e5063-3e69-4a13-8ff5-b7a63dd94706
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1278807741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1278807741
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1727073610
Short name T732
Test name
Test status
Simulation time 1715397911 ps
CPU time 4.37 seconds
Started Jun 25 05:26:16 PM PDT 24
Finished Jun 25 05:26:22 PM PDT 24
Peak memory 199696 kb
Host smart-d6fea13e-985d-459d-a93c-8ccc774155e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727073610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1727073610
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/26.hmac_test_sha384_vectors.2074468959
Short name T110
Test name
Test status
Simulation time 691124144362 ps
CPU time 1888.73 seconds
Started Jun 25 05:29:29 PM PDT 24
Finished Jun 25 06:00:59 PM PDT 24
Peak memory 215492 kb
Host smart-cbf35ebf-f8c7-4c31-8226-7d6527011bc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2074468959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha384_vectors.2074468959
Directory /workspace/26.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2374078657
Short name T144
Test name
Test status
Simulation time 729600993 ps
CPU time 3.2 seconds
Started Jun 25 05:26:18 PM PDT 24
Finished Jun 25 05:26:22 PM PDT 24
Peak memory 199728 kb
Host smart-215228a8-74e1-4a6d-84be-7f08ac5a38b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374078657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2374078657
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_long_msg.549314177
Short name T121
Test name
Test status
Simulation time 8861422585 ps
CPU time 107.76 seconds
Started Jun 25 05:28:40 PM PDT 24
Finished Jun 25 05:30:30 PM PDT 24
Peak memory 200100 kb
Host smart-554d91d2-57a5-4f55-961a-33b961062344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549314177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.549314177
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.309826625
Short name T123
Test name
Test status
Simulation time 16276506265 ps
CPU time 1052.71 seconds
Started Jun 25 05:29:17 PM PDT 24
Finished Jun 25 05:46:53 PM PDT 24
Peak memory 708680 kb
Host smart-54405a05-a2ec-4856-bb1d-8afaf750a874
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=309826625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.309826625
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.4022137818
Short name T89
Test name
Test status
Simulation time 12336005 ps
CPU time 0.68 seconds
Started Jun 25 05:26:11 PM PDT 24
Finished Jun 25 05:26:14 PM PDT 24
Peak memory 197308 kb
Host smart-50569f8d-bc3b-4e44-92f1-f0b40011f295
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022137818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.4022137818
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3600712540
Short name T152
Test name
Test status
Simulation time 2228615486 ps
CPU time 31.74 seconds
Started Jun 25 05:28:58 PM PDT 24
Finished Jun 25 05:29:32 PM PDT 24
Peak memory 200076 kb
Host smart-502fe641-25d3-4d8d-bfb1-abfcde76333f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3600712540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3600712540
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.724728916
Short name T96
Test name
Test status
Simulation time 161045047 ps
CPU time 7.74 seconds
Started Jun 25 05:26:18 PM PDT 24
Finished Jun 25 05:26:28 PM PDT 24
Peak memory 199596 kb
Host smart-917074ae-32fd-4936-9831-c311cc1134bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724728916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.724728916
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.22283108
Short name T744
Test name
Test status
Simulation time 2201438647 ps
CPU time 15.78 seconds
Started Jun 25 05:26:10 PM PDT 24
Finished Jun 25 05:26:28 PM PDT 24
Peak memory 198776 kb
Host smart-02355627-5253-436e-ba4f-b5526e6aa597
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22283108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.22283108
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3757214572
Short name T741
Test name
Test status
Simulation time 31501375 ps
CPU time 0.89 seconds
Started Jun 25 05:26:11 PM PDT 24
Finished Jun 25 05:26:14 PM PDT 24
Peak memory 198896 kb
Host smart-363acf5b-647e-4af5-ba83-352d411c41af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757214572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3757214572
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2666995052
Short name T776
Test name
Test status
Simulation time 48434787 ps
CPU time 1.29 seconds
Started Jun 25 05:26:11 PM PDT 24
Finished Jun 25 05:26:14 PM PDT 24
Peak memory 199564 kb
Host smart-c16c05b0-a73d-457d-995e-8f161b49c484
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666995052 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2666995052
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2180882482
Short name T725
Test name
Test status
Simulation time 12073954 ps
CPU time 0.62 seconds
Started Jun 25 05:26:12 PM PDT 24
Finished Jun 25 05:26:14 PM PDT 24
Peak memory 194496 kb
Host smart-5d2c04c5-1837-4f0f-a95e-1a94cffa51e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180882482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2180882482
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.667778630
Short name T68
Test name
Test status
Simulation time 369973972 ps
CPU time 1.74 seconds
Started Jun 25 05:26:00 PM PDT 24
Finished Jun 25 05:26:03 PM PDT 24
Peak memory 199692 kb
Host smart-e6605682-3f6f-4420-ab89-19e43073c021
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667778630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.667778630
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1338790474
Short name T61
Test name
Test status
Simulation time 66311437 ps
CPU time 1.81 seconds
Started Jun 25 05:26:08 PM PDT 24
Finished Jun 25 05:26:12 PM PDT 24
Peak memory 199712 kb
Host smart-51ea5a12-a34e-4f32-8e29-4cac585f1f67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338790474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1338790474
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2449586032
Short name T148
Test name
Test status
Simulation time 195551085 ps
CPU time 1.69 seconds
Started Jun 25 05:26:06 PM PDT 24
Finished Jun 25 05:26:10 PM PDT 24
Peak memory 199688 kb
Host smart-f7ef1d28-bda7-4777-879f-e4a5abb9886f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449586032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2449586032
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.702544231
Short name T758
Test name
Test status
Simulation time 565708510 ps
CPU time 9.13 seconds
Started Jun 25 05:26:05 PM PDT 24
Finished Jun 25 05:26:15 PM PDT 24
Peak memory 199616 kb
Host smart-c4918372-868a-4c91-9d61-bd3c320c96d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702544231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.702544231
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1426452901
Short name T88
Test name
Test status
Simulation time 53478733 ps
CPU time 0.73 seconds
Started Jun 25 05:26:17 PM PDT 24
Finished Jun 25 05:26:19 PM PDT 24
Peak memory 197496 kb
Host smart-355d3396-9c9f-4d3b-a3b3-f45675f3e2a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426452901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1426452901
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1171963758
Short name T733
Test name
Test status
Simulation time 187854949563 ps
CPU time 503.09 seconds
Started Jun 25 05:26:12 PM PDT 24
Finished Jun 25 05:34:37 PM PDT 24
Peak memory 215832 kb
Host smart-63c50407-58bc-482f-a375-1ea4f747a06f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171963758 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1171963758
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.4045991171
Short name T93
Test name
Test status
Simulation time 61105066 ps
CPU time 0.99 seconds
Started Jun 25 05:26:05 PM PDT 24
Finished Jun 25 05:26:07 PM PDT 24
Peak memory 199264 kb
Host smart-15b81e8d-7cdf-4664-aafa-fbbd8d7b9848
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045991171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.4045991171
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2268960103
Short name T706
Test name
Test status
Simulation time 60750803 ps
CPU time 0.63 seconds
Started Jun 25 05:26:15 PM PDT 24
Finished Jun 25 05:26:16 PM PDT 24
Peak memory 194456 kb
Host smart-385ca9ec-705a-4240-8375-4ef3520e7c9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268960103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2268960103
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2810461144
Short name T774
Test name
Test status
Simulation time 33292152 ps
CPU time 1.64 seconds
Started Jun 25 05:26:10 PM PDT 24
Finished Jun 25 05:26:14 PM PDT 24
Peak memory 199684 kb
Host smart-c39ddd1b-5c95-4d7a-a5e3-f8bac71fea01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810461144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2810461144
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2609058840
Short name T678
Test name
Test status
Simulation time 69752831 ps
CPU time 1.54 seconds
Started Jun 25 05:26:18 PM PDT 24
Finished Jun 25 05:26:22 PM PDT 24
Peak memory 199648 kb
Host smart-ee3ee1a0-e524-4c7a-a6ef-263e0d0c6db0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609058840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2609058840
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.939274293
Short name T59
Test name
Test status
Simulation time 50952554 ps
CPU time 1.75 seconds
Started Jun 25 05:26:17 PM PDT 24
Finished Jun 25 05:26:20 PM PDT 24
Peak memory 199620 kb
Host smart-86c984b3-9725-49e7-9573-bc796af86dd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939274293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.939274293
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3446008041
Short name T703
Test name
Test status
Simulation time 80779094 ps
CPU time 1.6 seconds
Started Jun 25 05:26:05 PM PDT 24
Finished Jun 25 05:26:08 PM PDT 24
Peak memory 199752 kb
Host smart-14cbe722-4262-41bb-8514-749c1a464d2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446008041 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3446008041
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.4184618216
Short name T92
Test name
Test status
Simulation time 16482316 ps
CPU time 0.94 seconds
Started Jun 25 05:26:08 PM PDT 24
Finished Jun 25 05:26:11 PM PDT 24
Peak memory 199408 kb
Host smart-c88c60f5-ed0b-4c06-95db-e17e905388bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184618216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.4184618216
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3003291876
Short name T699
Test name
Test status
Simulation time 63286313 ps
CPU time 0.59 seconds
Started Jun 25 05:26:08 PM PDT 24
Finished Jun 25 05:26:11 PM PDT 24
Peak memory 194432 kb
Host smart-f4272f9a-0d4d-4d05-810d-972b8a667fb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003291876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3003291876
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2122976691
Short name T708
Test name
Test status
Simulation time 46758487 ps
CPU time 1.22 seconds
Started Jun 25 05:26:19 PM PDT 24
Finished Jun 25 05:26:23 PM PDT 24
Peak memory 198360 kb
Host smart-441fbd40-768f-41ed-b05c-2e5ae2ce41a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122976691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2122976691
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2290255699
Short name T691
Test name
Test status
Simulation time 152297333 ps
CPU time 3.2 seconds
Started Jun 25 05:26:19 PM PDT 24
Finished Jun 25 05:26:24 PM PDT 24
Peak memory 199932 kb
Host smart-83ba07a3-61bf-444f-be7c-de67797b839e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290255699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2290255699
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.708451173
Short name T684
Test name
Test status
Simulation time 138878658 ps
CPU time 1.82 seconds
Started Jun 25 05:26:19 PM PDT 24
Finished Jun 25 05:26:23 PM PDT 24
Peak memory 199872 kb
Host smart-db5796d6-5c6e-4c40-899a-e21504c56057
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708451173 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.708451173
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2236197071
Short name T95
Test name
Test status
Simulation time 17848707 ps
CPU time 0.97 seconds
Started Jun 25 05:26:33 PM PDT 24
Finished Jun 25 05:26:37 PM PDT 24
Peak memory 199220 kb
Host smart-39ca0003-c8de-42e7-bb56-5f9fe56ab143
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236197071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2236197071
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.687032831
Short name T702
Test name
Test status
Simulation time 38012451 ps
CPU time 0.62 seconds
Started Jun 25 05:26:16 PM PDT 24
Finished Jun 25 05:26:18 PM PDT 24
Peak memory 194588 kb
Host smart-b385d1c4-57b2-4eb3-916f-84238a3f63e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687032831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.687032831
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2251238235
Short name T99
Test name
Test status
Simulation time 287961611 ps
CPU time 1.09 seconds
Started Jun 25 05:26:26 PM PDT 24
Finished Jun 25 05:26:29 PM PDT 24
Peak memory 197928 kb
Host smart-7a65dfa6-95c6-4c4b-8dd8-312d4616a925
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251238235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2251238235
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2878024461
Short name T681
Test name
Test status
Simulation time 223966234 ps
CPU time 1.5 seconds
Started Jun 25 05:26:33 PM PDT 24
Finished Jun 25 05:26:36 PM PDT 24
Peak memory 199596 kb
Host smart-6283b52a-8c68-4e89-ba7f-d3f914e0e438
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878024461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2878024461
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2874944497
Short name T775
Test name
Test status
Simulation time 287595603 ps
CPU time 4.45 seconds
Started Jun 25 05:26:16 PM PDT 24
Finished Jun 25 05:26:22 PM PDT 24
Peak memory 199784 kb
Host smart-1aa318ca-7862-469f-81b3-8246331a17d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874944497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2874944497
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1335853018
Short name T766
Test name
Test status
Simulation time 139379253 ps
CPU time 1.21 seconds
Started Jun 25 05:26:21 PM PDT 24
Finished Jun 25 05:26:24 PM PDT 24
Peak memory 199548 kb
Host smart-3722a6c5-80b1-4a93-826e-a73a173867bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335853018 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1335853018
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.882720491
Short name T730
Test name
Test status
Simulation time 47930929 ps
CPU time 0.81 seconds
Started Jun 25 05:26:37 PM PDT 24
Finished Jun 25 05:26:42 PM PDT 24
Peak memory 198912 kb
Host smart-42422b8c-aa13-41a9-9e55-364b03fde00b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882720491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.882720491
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2377131534
Short name T765
Test name
Test status
Simulation time 11275345 ps
CPU time 0.59 seconds
Started Jun 25 05:26:16 PM PDT 24
Finished Jun 25 05:26:18 PM PDT 24
Peak memory 194504 kb
Host smart-e38b19ad-1b14-4b48-a3a1-01910f912e7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377131534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2377131534
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3084482183
Short name T103
Test name
Test status
Simulation time 41203789 ps
CPU time 1.18 seconds
Started Jun 25 05:26:25 PM PDT 24
Finished Jun 25 05:26:27 PM PDT 24
Peak memory 199788 kb
Host smart-ff352618-b6c2-4441-a07b-9c7cbf4f14e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084482183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3084482183
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.714162294
Short name T731
Test name
Test status
Simulation time 397102610 ps
CPU time 2.94 seconds
Started Jun 25 05:26:17 PM PDT 24
Finished Jun 25 05:26:22 PM PDT 24
Peak memory 199676 kb
Host smart-83f31127-ab1a-4228-9e59-2e20bc210fd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714162294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.714162294
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3877496259
Short name T713
Test name
Test status
Simulation time 93089169 ps
CPU time 1.85 seconds
Started Jun 25 05:26:19 PM PDT 24
Finished Jun 25 05:26:23 PM PDT 24
Peak memory 199648 kb
Host smart-22098107-52ba-41f5-ac38-75523bc205a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877496259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3877496259
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2943283797
Short name T704
Test name
Test status
Simulation time 35277015984 ps
CPU time 539.59 seconds
Started Jun 25 05:26:29 PM PDT 24
Finished Jun 25 05:35:30 PM PDT 24
Peak memory 215156 kb
Host smart-eaae8525-3888-460b-b342-26a09c4d81d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943283797 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2943283797
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.4195569916
Short name T98
Test name
Test status
Simulation time 58508116 ps
CPU time 0.84 seconds
Started Jun 25 05:26:33 PM PDT 24
Finished Jun 25 05:26:36 PM PDT 24
Peak memory 199148 kb
Host smart-0e7a7c76-8940-4900-bc5e-49300d0d4de5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195569916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.4195569916
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.52335063
Short name T769
Test name
Test status
Simulation time 55324308 ps
CPU time 0.62 seconds
Started Jun 25 05:26:44 PM PDT 24
Finished Jun 25 05:26:47 PM PDT 24
Peak memory 194456 kb
Host smart-19634b88-1471-4b73-9c67-6bce16ca1bec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52335063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.52335063
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.525033
Short name T724
Test name
Test status
Simulation time 71707764 ps
CPU time 1.14 seconds
Started Jun 25 05:26:26 PM PDT 24
Finished Jun 25 05:26:29 PM PDT 24
Peak memory 199440 kb
Host smart-0be8d7f9-4ddc-44c3-a9e1-5bd15802dfa5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr_ou
tstanding.525033
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3997583340
Short name T779
Test name
Test status
Simulation time 356681612 ps
CPU time 3.28 seconds
Started Jun 25 05:26:16 PM PDT 24
Finished Jun 25 05:26:21 PM PDT 24
Peak memory 199684 kb
Host smart-425afe95-caac-4363-b53e-28b19a21f2d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997583340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3997583340
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.4170396160
Short name T146
Test name
Test status
Simulation time 574076524 ps
CPU time 4.61 seconds
Started Jun 25 05:26:18 PM PDT 24
Finished Jun 25 05:26:25 PM PDT 24
Peak memory 199700 kb
Host smart-2ea686d4-fe62-4d1a-bbc0-ea07c2bc0a5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170396160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.4170396160
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.861451213
Short name T64
Test name
Test status
Simulation time 80117331 ps
CPU time 2.69 seconds
Started Jun 25 05:26:34 PM PDT 24
Finished Jun 25 05:26:40 PM PDT 24
Peak memory 199880 kb
Host smart-c8694289-d4ab-487a-bb3d-ca1f62d9fd8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861451213 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.861451213
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1972401420
Short name T86
Test name
Test status
Simulation time 47376824 ps
CPU time 0.86 seconds
Started Jun 25 05:26:26 PM PDT 24
Finished Jun 25 05:26:28 PM PDT 24
Peak memory 199160 kb
Host smart-a123e75e-0a53-4746-afdb-107fc1f45ba1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972401420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1972401420
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.3882697499
Short name T717
Test name
Test status
Simulation time 16357643 ps
CPU time 0.63 seconds
Started Jun 25 05:26:16 PM PDT 24
Finished Jun 25 05:26:18 PM PDT 24
Peak memory 194532 kb
Host smart-2c05b20e-6930-403e-941f-6e372a572238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882697499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3882697499
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3844845435
Short name T693
Test name
Test status
Simulation time 49455780 ps
CPU time 1.16 seconds
Started Jun 25 05:26:28 PM PDT 24
Finished Jun 25 05:26:31 PM PDT 24
Peak memory 198156 kb
Host smart-12f34bcb-45e9-40ec-96ff-36e6ad6a838b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844845435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3844845435
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.596107665
Short name T680
Test name
Test status
Simulation time 401716259 ps
CPU time 2.06 seconds
Started Jun 25 05:26:34 PM PDT 24
Finished Jun 25 05:26:39 PM PDT 24
Peak memory 199696 kb
Host smart-0ccc5489-34c4-4425-953f-a655d7a9c154
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596107665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.596107665
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.853654566
Short name T149
Test name
Test status
Simulation time 441041588 ps
CPU time 2.98 seconds
Started Jun 25 05:26:19 PM PDT 24
Finished Jun 25 05:26:24 PM PDT 24
Peak memory 199704 kb
Host smart-72ce0a3d-3b7b-4c56-933f-161910a5df25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853654566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.853654566
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3662551651
Short name T739
Test name
Test status
Simulation time 34020500 ps
CPU time 1.45 seconds
Started Jun 25 05:26:16 PM PDT 24
Finished Jun 25 05:26:18 PM PDT 24
Peak memory 199736 kb
Host smart-f54bfb39-cf9b-4307-a3c3-5e72949ff93a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662551651 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3662551651
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.738162546
Short name T762
Test name
Test status
Simulation time 49863555 ps
CPU time 0.76 seconds
Started Jun 25 05:26:29 PM PDT 24
Finished Jun 25 05:26:32 PM PDT 24
Peak memory 198424 kb
Host smart-3a19b690-abe6-4c6d-bf77-626626f5c74d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738162546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.738162546
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2414934527
Short name T770
Test name
Test status
Simulation time 80611415 ps
CPU time 0.62 seconds
Started Jun 25 05:26:35 PM PDT 24
Finished Jun 25 05:26:38 PM PDT 24
Peak memory 194532 kb
Host smart-e81d8b00-7e35-4d76-b85c-8cf61095bfd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414934527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2414934527
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2252029619
Short name T694
Test name
Test status
Simulation time 46887248 ps
CPU time 2.21 seconds
Started Jun 25 05:26:25 PM PDT 24
Finished Jun 25 05:26:29 PM PDT 24
Peak memory 199680 kb
Host smart-207fa804-acc3-4267-988c-257189786e2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252029619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2252029619
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1862151583
Short name T711
Test name
Test status
Simulation time 375484658 ps
CPU time 3.41 seconds
Started Jun 25 05:26:18 PM PDT 24
Finished Jun 25 05:26:24 PM PDT 24
Peak memory 199684 kb
Host smart-3dc2d9ed-59de-4d8b-873b-57b4c35a0f00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862151583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1862151583
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1830705117
Short name T147
Test name
Test status
Simulation time 461389930 ps
CPU time 4.73 seconds
Started Jun 25 05:26:26 PM PDT 24
Finished Jun 25 05:26:32 PM PDT 24
Peak memory 199728 kb
Host smart-ce86353a-c40a-4eca-9c75-84027f505b16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830705117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1830705117
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2002403074
Short name T742
Test name
Test status
Simulation time 363655006 ps
CPU time 2.53 seconds
Started Jun 25 05:26:24 PM PDT 24
Finished Jun 25 05:26:27 PM PDT 24
Peak memory 199800 kb
Host smart-3a4c77ed-fe64-4e73-9bc4-f6406c0ae18c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002403074 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2002403074
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1228613868
Short name T83
Test name
Test status
Simulation time 41332056 ps
CPU time 0.74 seconds
Started Jun 25 05:26:35 PM PDT 24
Finished Jun 25 05:26:39 PM PDT 24
Peak memory 197532 kb
Host smart-100fa5b1-71d6-4426-9d0e-ef213b3d607c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228613868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1228613868
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.639389850
Short name T751
Test name
Test status
Simulation time 69478372 ps
CPU time 0.59 seconds
Started Jun 25 05:26:35 PM PDT 24
Finished Jun 25 05:26:39 PM PDT 24
Peak memory 194424 kb
Host smart-3f8bb88b-f87d-4093-9a4b-3cf36a7d9cd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639389850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.639389850
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1048187745
Short name T740
Test name
Test status
Simulation time 1180201964 ps
CPU time 2.55 seconds
Started Jun 25 05:26:36 PM PDT 24
Finished Jun 25 05:26:42 PM PDT 24
Peak memory 199380 kb
Host smart-5ae97252-f540-4c19-9672-07144e311ba1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048187745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1048187745
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3683262033
Short name T41
Test name
Test status
Simulation time 298884058 ps
CPU time 2.04 seconds
Started Jun 25 05:26:37 PM PDT 24
Finished Jun 25 05:26:48 PM PDT 24
Peak memory 199684 kb
Host smart-e58c11da-74c3-4e8d-9a8b-3546609b7f5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683262033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3683262033
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2104120400
Short name T778
Test name
Test status
Simulation time 276767169 ps
CPU time 0.72 seconds
Started Jun 25 05:26:21 PM PDT 24
Finished Jun 25 05:26:23 PM PDT 24
Peak memory 197900 kb
Host smart-6805121a-528b-47b0-81de-ca08ba5cacad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104120400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2104120400
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3810638519
Short name T692
Test name
Test status
Simulation time 39470393 ps
CPU time 0.63 seconds
Started Jun 25 05:26:27 PM PDT 24
Finished Jun 25 05:26:30 PM PDT 24
Peak memory 194508 kb
Host smart-bf369144-e8b7-454f-a105-a0a313b8e9c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810638519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3810638519
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2782782727
Short name T100
Test name
Test status
Simulation time 23600528 ps
CPU time 1.06 seconds
Started Jun 25 05:26:21 PM PDT 24
Finished Jun 25 05:26:23 PM PDT 24
Peak memory 199652 kb
Host smart-6be1c303-2739-422e-9d62-111b475d8d67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782782727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2782782727
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.94149608
Short name T757
Test name
Test status
Simulation time 274822066 ps
CPU time 1.69 seconds
Started Jun 25 05:26:31 PM PDT 24
Finished Jun 25 05:26:34 PM PDT 24
Peak memory 199700 kb
Host smart-f3aae853-ac0d-4b46-bea6-65c74a117da5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94149608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.94149608
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2420456896
Short name T142
Test name
Test status
Simulation time 369174875 ps
CPU time 2.87 seconds
Started Jun 25 05:26:33 PM PDT 24
Finished Jun 25 05:26:39 PM PDT 24
Peak memory 199756 kb
Host smart-7fe2d78c-1034-469b-ade3-dfe73ac1e08e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420456896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2420456896
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3668586689
Short name T679
Test name
Test status
Simulation time 87115661 ps
CPU time 2.5 seconds
Started Jun 25 05:26:27 PM PDT 24
Finished Jun 25 05:26:32 PM PDT 24
Peak memory 199872 kb
Host smart-20487e7b-97d2-497a-8542-b21868bbed19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668586689 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3668586689
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1722237120
Short name T734
Test name
Test status
Simulation time 29921180 ps
CPU time 0.94 seconds
Started Jun 25 05:26:32 PM PDT 24
Finished Jun 25 05:26:34 PM PDT 24
Peak memory 199268 kb
Host smart-282f1c24-2b10-4e6d-a70c-7f91b2e7008c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722237120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1722237120
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1640720051
Short name T70
Test name
Test status
Simulation time 22293956 ps
CPU time 0.59 seconds
Started Jun 25 05:26:28 PM PDT 24
Finished Jun 25 05:26:31 PM PDT 24
Peak memory 194520 kb
Host smart-57edfe45-d5a1-4f0e-919e-b53379d778cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640720051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1640720051
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.323370916
Short name T737
Test name
Test status
Simulation time 123526739 ps
CPU time 2.27 seconds
Started Jun 25 05:26:28 PM PDT 24
Finished Jun 25 05:26:32 PM PDT 24
Peak memory 199656 kb
Host smart-91a87829-7182-4594-bf40-241f6de24af3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323370916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.323370916
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.778661069
Short name T777
Test name
Test status
Simulation time 58736404 ps
CPU time 3.1 seconds
Started Jun 25 05:26:28 PM PDT 24
Finished Jun 25 05:26:33 PM PDT 24
Peak memory 199604 kb
Host smart-b0fa0e5f-b378-4e08-b3c1-e7e133dfd366
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778661069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.778661069
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1640027952
Short name T141
Test name
Test status
Simulation time 345878892 ps
CPU time 3.08 seconds
Started Jun 25 05:26:27 PM PDT 24
Finished Jun 25 05:26:32 PM PDT 24
Peak memory 199628 kb
Host smart-6bbd6187-95eb-4643-9450-cb42a932e4f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640027952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.1640027952
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.427576302
Short name T722
Test name
Test status
Simulation time 70501765 ps
CPU time 2.11 seconds
Started Jun 25 05:26:27 PM PDT 24
Finished Jun 25 05:26:31 PM PDT 24
Peak memory 199864 kb
Host smart-97c60b36-25f6-4bb6-bd61-9f4b94ff65c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427576302 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.427576302
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2399459326
Short name T709
Test name
Test status
Simulation time 53299111 ps
CPU time 0.84 seconds
Started Jun 25 05:26:19 PM PDT 24
Finished Jun 25 05:26:22 PM PDT 24
Peak memory 198920 kb
Host smart-061436db-e167-47fb-993e-9007d2a32b69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399459326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2399459326
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1313996235
Short name T754
Test name
Test status
Simulation time 36429070 ps
CPU time 0.59 seconds
Started Jun 25 05:26:33 PM PDT 24
Finished Jun 25 05:26:36 PM PDT 24
Peak memory 194408 kb
Host smart-e7400837-0dff-4f90-af54-cf9b68f5a9a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313996235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1313996235
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.449560733
Short name T738
Test name
Test status
Simulation time 37301482 ps
CPU time 1.71 seconds
Started Jun 25 05:26:33 PM PDT 24
Finished Jun 25 05:26:37 PM PDT 24
Peak memory 199656 kb
Host smart-c867a36e-3f44-452a-9ef4-4ea7cc909ea9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449560733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.449560733
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2460636565
Short name T768
Test name
Test status
Simulation time 70269169 ps
CPU time 1.48 seconds
Started Jun 25 05:26:15 PM PDT 24
Finished Jun 25 05:26:18 PM PDT 24
Peak memory 199668 kb
Host smart-243c8ef7-8cb7-44f4-9c5a-0c467c218db8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460636565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2460636565
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.748859550
Short name T145
Test name
Test status
Simulation time 52043573 ps
CPU time 1.8 seconds
Started Jun 25 05:26:16 PM PDT 24
Finished Jun 25 05:26:19 PM PDT 24
Peak memory 199716 kb
Host smart-6b60c845-80fd-471e-a28b-c548029a7ef9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748859550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.748859550
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2458516885
Short name T94
Test name
Test status
Simulation time 216981929 ps
CPU time 3.14 seconds
Started Jun 25 05:26:08 PM PDT 24
Finished Jun 25 05:26:13 PM PDT 24
Peak memory 199688 kb
Host smart-d1414961-2433-4395-a3a7-6504f758ecf9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458516885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2458516885
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3527206526
Short name T84
Test name
Test status
Simulation time 222449099 ps
CPU time 9.95 seconds
Started Jun 25 05:26:17 PM PDT 24
Finished Jun 25 05:26:28 PM PDT 24
Peak memory 199568 kb
Host smart-24d0005a-0373-4bee-85cb-dfc73fcc453a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527206526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3527206526
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1924323836
Short name T771
Test name
Test status
Simulation time 18919538 ps
CPU time 0.74 seconds
Started Jun 25 05:26:15 PM PDT 24
Finished Jun 25 05:26:17 PM PDT 24
Peak memory 197584 kb
Host smart-0912f171-4f8a-46f6-8632-dc2f21e79e5b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924323836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1924323836
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1419617093
Short name T707
Test name
Test status
Simulation time 162076957 ps
CPU time 1.29 seconds
Started Jun 25 05:26:14 PM PDT 24
Finished Jun 25 05:26:17 PM PDT 24
Peak memory 199628 kb
Host smart-0e71008e-8d3d-419f-b05c-68527f2b4501
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419617093 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1419617093
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.357777759
Short name T90
Test name
Test status
Simulation time 50245937 ps
CPU time 0.84 seconds
Started Jun 25 05:26:10 PM PDT 24
Finished Jun 25 05:26:12 PM PDT 24
Peak memory 198756 kb
Host smart-6eedf106-a818-4417-ae10-a2931fda7db4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357777759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.357777759
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.4131308934
Short name T683
Test name
Test status
Simulation time 10431869 ps
CPU time 0.57 seconds
Started Jun 25 05:26:09 PM PDT 24
Finished Jun 25 05:26:11 PM PDT 24
Peak memory 194548 kb
Host smart-686a60fd-be5d-4e27-9b0c-801835380b07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131308934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.4131308934
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3132744618
Short name T752
Test name
Test status
Simulation time 93028857 ps
CPU time 1.18 seconds
Started Jun 25 05:26:06 PM PDT 24
Finished Jun 25 05:26:09 PM PDT 24
Peak memory 199496 kb
Host smart-a124e4f1-f24b-448b-919b-5f98bb5e4d80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132744618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3132744618
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2057013714
Short name T746
Test name
Test status
Simulation time 111978405 ps
CPU time 2.47 seconds
Started Jun 25 05:26:07 PM PDT 24
Finished Jun 25 05:26:11 PM PDT 24
Peak memory 199692 kb
Host smart-1d9d8251-65eb-4276-a4c2-b9144b4be9d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057013714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2057013714
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.612806963
Short name T140
Test name
Test status
Simulation time 1810110558 ps
CPU time 3.38 seconds
Started Jun 25 05:26:25 PM PDT 24
Finished Jun 25 05:26:30 PM PDT 24
Peak memory 199696 kb
Host smart-e59fb93c-2994-403e-aa09-7842871bc4df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612806963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.612806963
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3916535528
Short name T672
Test name
Test status
Simulation time 41258305 ps
CPU time 0.59 seconds
Started Jun 25 05:26:32 PM PDT 24
Finished Jun 25 05:26:33 PM PDT 24
Peak memory 194648 kb
Host smart-0287541f-9653-4af9-bc8d-08fb6688c5b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916535528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3916535528
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2499110329
Short name T670
Test name
Test status
Simulation time 21395824 ps
CPU time 0.6 seconds
Started Jun 25 05:26:34 PM PDT 24
Finished Jun 25 05:26:38 PM PDT 24
Peak memory 194560 kb
Host smart-13f0cfdd-bce2-49ed-b704-fa2404130fdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499110329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2499110329
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.2258010317
Short name T685
Test name
Test status
Simulation time 12376044 ps
CPU time 0.59 seconds
Started Jun 25 05:26:26 PM PDT 24
Finished Jun 25 05:26:28 PM PDT 24
Peak memory 194496 kb
Host smart-f6a08787-2054-4829-8c32-52a78edcd4f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258010317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2258010317
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2778777802
Short name T674
Test name
Test status
Simulation time 58108632 ps
CPU time 0.63 seconds
Started Jun 25 05:26:27 PM PDT 24
Finished Jun 25 05:26:30 PM PDT 24
Peak memory 194496 kb
Host smart-b21e77e9-a3df-4ac5-8214-5ab21c78f2a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778777802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2778777802
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2399433218
Short name T720
Test name
Test status
Simulation time 14239424 ps
CPU time 0.6 seconds
Started Jun 25 05:26:21 PM PDT 24
Finished Jun 25 05:26:23 PM PDT 24
Peak memory 194576 kb
Host smart-7db11e60-06f7-4bbb-932c-02dc94d98189
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399433218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2399433218
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.82207731
Short name T687
Test name
Test status
Simulation time 43011287 ps
CPU time 0.59 seconds
Started Jun 25 05:26:37 PM PDT 24
Finished Jun 25 05:26:42 PM PDT 24
Peak memory 194508 kb
Host smart-c82456ec-4a03-4a51-a3fc-de9ce28925d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82207731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.82207731
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3561852589
Short name T71
Test name
Test status
Simulation time 14016901 ps
CPU time 0.59 seconds
Started Jun 25 05:26:53 PM PDT 24
Finished Jun 25 05:26:55 PM PDT 24
Peak memory 194456 kb
Host smart-a496cdd1-1ea5-48e7-93c7-138d9a2fe500
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561852589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3561852589
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2698828989
Short name T715
Test name
Test status
Simulation time 12814321 ps
CPU time 0.58 seconds
Started Jun 25 05:26:32 PM PDT 24
Finished Jun 25 05:26:34 PM PDT 24
Peak memory 194408 kb
Host smart-6f4b14a5-b037-49b3-83b3-6d1f551a413d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698828989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2698828989
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.3482101676
Short name T682
Test name
Test status
Simulation time 19160087 ps
CPU time 0.64 seconds
Started Jun 25 05:26:29 PM PDT 24
Finished Jun 25 05:26:32 PM PDT 24
Peak memory 194520 kb
Host smart-8156ea93-d5ca-47b7-a24c-d9b09c18d863
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482101676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3482101676
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3423446038
Short name T729
Test name
Test status
Simulation time 23090333 ps
CPU time 0.6 seconds
Started Jun 25 05:26:28 PM PDT 24
Finished Jun 25 05:26:31 PM PDT 24
Peak memory 194484 kb
Host smart-7f50ca2a-fab4-40a3-9ffc-c45095caed22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423446038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3423446038
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1230124865
Short name T760
Test name
Test status
Simulation time 597972837 ps
CPU time 9.67 seconds
Started Jun 25 05:26:16 PM PDT 24
Finished Jun 25 05:26:27 PM PDT 24
Peak memory 199640 kb
Host smart-9428d8bd-a181-40b2-91dc-736ab728a781
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230124865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1230124865
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.391740956
Short name T764
Test name
Test status
Simulation time 745044694 ps
CPU time 5.83 seconds
Started Jun 25 05:26:19 PM PDT 24
Finished Jun 25 05:26:27 PM PDT 24
Peak memory 198564 kb
Host smart-b06e5b0b-eae0-456e-93ee-0bb65eb8da04
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391740956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.391740956
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.512109149
Short name T85
Test name
Test status
Simulation time 22081937 ps
CPU time 1.03 seconds
Started Jun 25 05:26:07 PM PDT 24
Finished Jun 25 05:26:10 PM PDT 24
Peak memory 199396 kb
Host smart-cc02729b-5c15-4a8e-9634-4323da850f0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512109149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.512109149
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3299072570
Short name T40
Test name
Test status
Simulation time 125501419 ps
CPU time 1.64 seconds
Started Jun 25 05:26:16 PM PDT 24
Finished Jun 25 05:26:19 PM PDT 24
Peak memory 199868 kb
Host smart-d297f44b-3009-49af-82c5-afc18acd4863
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299072570 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.3299072570
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.726793335
Short name T82
Test name
Test status
Simulation time 178485168 ps
CPU time 0.82 seconds
Started Jun 25 05:26:12 PM PDT 24
Finished Jun 25 05:26:15 PM PDT 24
Peak memory 198900 kb
Host smart-97984374-0983-46cf-b91d-c81f8eb28d81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726793335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.726793335
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.836139779
Short name T767
Test name
Test status
Simulation time 17503728 ps
CPU time 0.65 seconds
Started Jun 25 05:26:21 PM PDT 24
Finished Jun 25 05:26:23 PM PDT 24
Peak memory 194512 kb
Host smart-0be62045-032d-47f3-bbfd-530ba49cd437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836139779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.836139779
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3881493522
Short name T688
Test name
Test status
Simulation time 44101619 ps
CPU time 1.17 seconds
Started Jun 25 05:26:17 PM PDT 24
Finished Jun 25 05:26:20 PM PDT 24
Peak memory 199668 kb
Host smart-27d82448-c5cf-4ec3-8049-c123d6353853
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881493522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3881493522
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3562553630
Short name T721
Test name
Test status
Simulation time 133826861 ps
CPU time 2.73 seconds
Started Jun 25 05:26:08 PM PDT 24
Finished Jun 25 05:26:13 PM PDT 24
Peak memory 199660 kb
Host smart-246506a2-07b8-4c62-8870-86c5038c981d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562553630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3562553630
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1265898758
Short name T761
Test name
Test status
Simulation time 47555241 ps
CPU time 0.68 seconds
Started Jun 25 05:26:27 PM PDT 24
Finished Jun 25 05:26:30 PM PDT 24
Peak memory 194544 kb
Host smart-96ca8dfd-a4d9-47d1-ae68-0dad0bc98863
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265898758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1265898758
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.814629068
Short name T736
Test name
Test status
Simulation time 75230079 ps
CPU time 0.61 seconds
Started Jun 25 05:26:35 PM PDT 24
Finished Jun 25 05:26:38 PM PDT 24
Peak memory 194496 kb
Host smart-0df19649-960c-42d8-b2e6-16f615871b42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814629068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.814629068
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1543841477
Short name T735
Test name
Test status
Simulation time 128450898 ps
CPU time 0.6 seconds
Started Jun 25 05:26:18 PM PDT 24
Finished Jun 25 05:26:20 PM PDT 24
Peak memory 194532 kb
Host smart-b7264e13-552b-4601-bb57-563cd3c732e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543841477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1543841477
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2089660023
Short name T686
Test name
Test status
Simulation time 29606839 ps
CPU time 0.62 seconds
Started Jun 25 05:26:29 PM PDT 24
Finished Jun 25 05:26:31 PM PDT 24
Peak memory 194476 kb
Host smart-af3391c4-770e-45bc-a7c5-7bc111671220
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089660023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2089660023
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3268021069
Short name T745
Test name
Test status
Simulation time 73340392 ps
CPU time 0.62 seconds
Started Jun 25 05:26:26 PM PDT 24
Finished Jun 25 05:26:28 PM PDT 24
Peak memory 194572 kb
Host smart-d171ce2f-eefd-4616-a5d4-1102dbfd3008
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268021069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3268021069
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.66440064
Short name T773
Test name
Test status
Simulation time 34301415 ps
CPU time 0.61 seconds
Started Jun 25 05:26:22 PM PDT 24
Finished Jun 25 05:26:24 PM PDT 24
Peak memory 194732 kb
Host smart-02f1c854-ec27-47ad-8432-b7777abdb061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66440064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.66440064
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1310998291
Short name T756
Test name
Test status
Simulation time 16911360 ps
CPU time 0.63 seconds
Started Jun 25 05:26:21 PM PDT 24
Finished Jun 25 05:26:23 PM PDT 24
Peak memory 194536 kb
Host smart-b184a2bf-0bd9-46a1-b878-a5b25ced422f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310998291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1310998291
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.214899920
Short name T695
Test name
Test status
Simulation time 88420441 ps
CPU time 0.6 seconds
Started Jun 25 05:26:40 PM PDT 24
Finished Jun 25 05:26:49 PM PDT 24
Peak memory 194456 kb
Host smart-64802ce3-9418-423f-8426-25ab92ac4727
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214899920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.214899920
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3740957695
Short name T69
Test name
Test status
Simulation time 16879065 ps
CPU time 0.63 seconds
Started Jun 25 05:26:26 PM PDT 24
Finished Jun 25 05:26:27 PM PDT 24
Peak memory 194512 kb
Host smart-55e72d09-8a87-43ba-b4e2-3b83f2e575c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740957695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3740957695
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1150500356
Short name T716
Test name
Test status
Simulation time 15581794 ps
CPU time 0.62 seconds
Started Jun 25 05:26:48 PM PDT 24
Finished Jun 25 05:26:51 PM PDT 24
Peak memory 194528 kb
Host smart-a396bafa-2d82-42ed-8128-f4c3a33c5e52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150500356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1150500356
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3020937599
Short name T689
Test name
Test status
Simulation time 1246082497 ps
CPU time 6.1 seconds
Started Jun 25 05:26:06 PM PDT 24
Finished Jun 25 05:26:14 PM PDT 24
Peak memory 199644 kb
Host smart-0eeda32d-3490-403c-9041-f25b51cc825e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020937599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3020937599
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1551056358
Short name T675
Test name
Test status
Simulation time 1195016840 ps
CPU time 5.38 seconds
Started Jun 25 05:26:14 PM PDT 24
Finished Jun 25 05:26:20 PM PDT 24
Peak memory 199524 kb
Host smart-d939d598-7fd0-4647-ac0c-5d75e8c74145
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551056358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1551056358
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.743876471
Short name T710
Test name
Test status
Simulation time 19722228 ps
CPU time 0.85 seconds
Started Jun 25 05:26:12 PM PDT 24
Finished Jun 25 05:26:14 PM PDT 24
Peak memory 198712 kb
Host smart-81e87326-c907-4a8e-885d-62d21fdb0acb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743876471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.743876471
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1895462987
Short name T63
Test name
Test status
Simulation time 1246774740597 ps
CPU time 877.14 seconds
Started Jun 25 05:26:19 PM PDT 24
Finished Jun 25 05:40:59 PM PDT 24
Peak memory 216232 kb
Host smart-175eb132-cc5a-4081-80e4-f052924834f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895462987 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1895462987
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2877898884
Short name T87
Test name
Test status
Simulation time 76325235 ps
CPU time 0.85 seconds
Started Jun 25 05:26:12 PM PDT 24
Finished Jun 25 05:26:15 PM PDT 24
Peak memory 199440 kb
Host smart-0e405482-2d5c-4e57-905d-6f5932549908
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877898884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2877898884
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.4257985149
Short name T697
Test name
Test status
Simulation time 24121770 ps
CPU time 0.62 seconds
Started Jun 25 05:26:08 PM PDT 24
Finished Jun 25 05:26:11 PM PDT 24
Peak memory 194524 kb
Host smart-e4fe340c-e639-43aa-9d73-db2a6e754eaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257985149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.4257985149
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1537878538
Short name T727
Test name
Test status
Simulation time 178327501 ps
CPU time 1.72 seconds
Started Jun 25 05:26:18 PM PDT 24
Finished Jun 25 05:26:21 PM PDT 24
Peak memory 199684 kb
Host smart-05e6fa91-098f-46f3-9a39-cf376798415f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537878538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1537878538
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1051831039
Short name T772
Test name
Test status
Simulation time 888727459 ps
CPU time 3.11 seconds
Started Jun 25 05:26:08 PM PDT 24
Finished Jun 25 05:26:13 PM PDT 24
Peak memory 199708 kb
Host smart-6395994f-03ac-4062-ab52-8eba881b81cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051831039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1051831039
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.151771859
Short name T57
Test name
Test status
Simulation time 179713063 ps
CPU time 1.84 seconds
Started Jun 25 05:26:04 PM PDT 24
Finished Jun 25 05:26:07 PM PDT 24
Peak memory 199624 kb
Host smart-522b36f6-69e3-4150-9dc4-22672cbb2d47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151771859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.151771859
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1171870411
Short name T743
Test name
Test status
Simulation time 14577325 ps
CPU time 0.61 seconds
Started Jun 25 05:26:35 PM PDT 24
Finished Jun 25 05:26:39 PM PDT 24
Peak memory 194496 kb
Host smart-babad657-4364-45d3-99a0-50e69ed4e47c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171870411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1171870411
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3265390008
Short name T728
Test name
Test status
Simulation time 13745262 ps
CPU time 0.6 seconds
Started Jun 25 05:26:36 PM PDT 24
Finished Jun 25 05:26:40 PM PDT 24
Peak memory 194560 kb
Host smart-337c72bb-0661-47b7-b42f-6a64f0b3ccff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265390008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3265390008
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2746491865
Short name T701
Test name
Test status
Simulation time 33837261 ps
CPU time 0.59 seconds
Started Jun 25 05:26:43 PM PDT 24
Finished Jun 25 05:26:47 PM PDT 24
Peak memory 194420 kb
Host smart-c8163116-b7cc-4e67-8420-d0c97027f0f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746491865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2746491865
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.11308578
Short name T696
Test name
Test status
Simulation time 55014541 ps
CPU time 0.65 seconds
Started Jun 25 05:26:45 PM PDT 24
Finished Jun 25 05:26:48 PM PDT 24
Peak memory 194620 kb
Host smart-2975ec95-f160-41a4-bd46-0a8e035392a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11308578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.11308578
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.1799599379
Short name T671
Test name
Test status
Simulation time 30379944 ps
CPU time 0.64 seconds
Started Jun 25 05:26:34 PM PDT 24
Finished Jun 25 05:26:37 PM PDT 24
Peak memory 194588 kb
Host smart-310e1651-a9e4-4f21-97d4-cf5ac0650a63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799599379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1799599379
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.694604216
Short name T667
Test name
Test status
Simulation time 16518632 ps
CPU time 0.65 seconds
Started Jun 25 05:26:30 PM PDT 24
Finished Jun 25 05:26:32 PM PDT 24
Peak memory 194516 kb
Host smart-2b7494c6-3d58-49fb-8d1e-356da3c463f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694604216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.694604216
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3263963822
Short name T726
Test name
Test status
Simulation time 25849339 ps
CPU time 0.64 seconds
Started Jun 25 05:26:33 PM PDT 24
Finished Jun 25 05:26:36 PM PDT 24
Peak memory 194604 kb
Host smart-e49c381a-9a98-4e95-adc9-e69eba23d612
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263963822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3263963822
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.1417541021
Short name T700
Test name
Test status
Simulation time 38551268 ps
CPU time 0.59 seconds
Started Jun 25 05:26:33 PM PDT 24
Finished Jun 25 05:26:36 PM PDT 24
Peak memory 194476 kb
Host smart-d312e7cf-7b7f-4c0f-8ddd-ad389d15f5d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417541021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1417541021
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2162964284
Short name T137
Test name
Test status
Simulation time 13850731 ps
CPU time 0.63 seconds
Started Jun 25 05:26:36 PM PDT 24
Finished Jun 25 05:26:40 PM PDT 24
Peak memory 194640 kb
Host smart-584e0670-217f-43bb-b66a-2722f5e994c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162964284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2162964284
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3647764318
Short name T723
Test name
Test status
Simulation time 15408172 ps
CPU time 0.6 seconds
Started Jun 25 05:26:45 PM PDT 24
Finished Jun 25 05:26:48 PM PDT 24
Peak memory 194428 kb
Host smart-e11805e5-394f-42a0-aa5a-bdb5528439fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647764318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3647764318
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.180318993
Short name T712
Test name
Test status
Simulation time 72959665 ps
CPU time 1.46 seconds
Started Jun 25 05:26:17 PM PDT 24
Finished Jun 25 05:26:20 PM PDT 24
Peak memory 199748 kb
Host smart-97f49c2c-e377-4b4d-9516-1dd08fa26c5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180318993 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.180318993
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.170385577
Short name T97
Test name
Test status
Simulation time 16820024 ps
CPU time 0.81 seconds
Started Jun 25 05:26:18 PM PDT 24
Finished Jun 25 05:26:20 PM PDT 24
Peak memory 199440 kb
Host smart-11b63c79-6ad0-465d-88ce-bbd4c246cc55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170385577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.170385577
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1723083213
Short name T750
Test name
Test status
Simulation time 34057321 ps
CPU time 0.68 seconds
Started Jun 25 05:26:04 PM PDT 24
Finished Jun 25 05:26:06 PM PDT 24
Peak memory 194524 kb
Host smart-3f7fa2d0-a670-428f-81ad-a76a34f294d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723083213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1723083213
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3412621928
Short name T101
Test name
Test status
Simulation time 42789882 ps
CPU time 1.11 seconds
Started Jun 25 05:26:07 PM PDT 24
Finished Jun 25 05:26:10 PM PDT 24
Peak memory 199432 kb
Host smart-8bd81656-cb36-4a74-be63-3556e5cdb3e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412621928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3412621928
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2052257483
Short name T763
Test name
Test status
Simulation time 168368541 ps
CPU time 3.41 seconds
Started Jun 25 05:26:09 PM PDT 24
Finished Jun 25 05:26:15 PM PDT 24
Peak memory 199744 kb
Host smart-bc1e8ded-2803-4ac1-b231-2a90c3f68a18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052257483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2052257483
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2475823248
Short name T143
Test name
Test status
Simulation time 1365005672 ps
CPU time 4.47 seconds
Started Jun 25 05:26:13 PM PDT 24
Finished Jun 25 05:26:19 PM PDT 24
Peak memory 199712 kb
Host smart-c8566731-52df-4c97-a77a-9fa1feb6bd49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475823248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2475823248
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3197579169
Short name T718
Test name
Test status
Simulation time 85085892 ps
CPU time 1.66 seconds
Started Jun 25 05:26:13 PM PDT 24
Finished Jun 25 05:26:16 PM PDT 24
Peak memory 199608 kb
Host smart-3e705f69-d628-4926-a66d-71f43a3c9be1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197579169 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3197579169
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2323432674
Short name T748
Test name
Test status
Simulation time 17834336 ps
CPU time 0.69 seconds
Started Jun 25 05:26:19 PM PDT 24
Finished Jun 25 05:26:21 PM PDT 24
Peak memory 197448 kb
Host smart-fec9e7f6-49f7-4641-8c39-2f726ad19e92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323432674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2323432674
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1176046817
Short name T668
Test name
Test status
Simulation time 11128884 ps
CPU time 0.6 seconds
Started Jun 25 05:26:13 PM PDT 24
Finished Jun 25 05:26:15 PM PDT 24
Peak memory 194472 kb
Host smart-4e355e52-ea37-4892-8fd4-80707523b0ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176046817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1176046817
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3844651069
Short name T719
Test name
Test status
Simulation time 154909065 ps
CPU time 2.22 seconds
Started Jun 25 05:26:15 PM PDT 24
Finished Jun 25 05:26:18 PM PDT 24
Peak memory 199604 kb
Host smart-cb3728f5-1ca7-47b9-8908-8928cb48f05d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844651069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3844651069
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2604643621
Short name T673
Test name
Test status
Simulation time 672371667 ps
CPU time 1.65 seconds
Started Jun 25 05:26:05 PM PDT 24
Finished Jun 25 05:26:08 PM PDT 24
Peak memory 199688 kb
Host smart-24e5b6df-70c0-4872-91f2-1fcbac12c05f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604643621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2604643621
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1355255772
Short name T676
Test name
Test status
Simulation time 52256370 ps
CPU time 1.84 seconds
Started Jun 25 05:26:19 PM PDT 24
Finished Jun 25 05:26:23 PM PDT 24
Peak memory 199644 kb
Host smart-eb517254-2f79-4744-bc45-c316385d1c64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355255772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1355255772
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1168322892
Short name T66
Test name
Test status
Simulation time 179223031 ps
CPU time 2.8 seconds
Started Jun 25 05:26:18 PM PDT 24
Finished Jun 25 05:26:23 PM PDT 24
Peak memory 199672 kb
Host smart-39d06ddd-d830-4486-9b9c-48aec68b800a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168322892 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1168322892
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3455769703
Short name T747
Test name
Test status
Simulation time 25036678 ps
CPU time 0.83 seconds
Started Jun 25 05:26:07 PM PDT 24
Finished Jun 25 05:26:09 PM PDT 24
Peak memory 198520 kb
Host smart-f02566a9-96e4-41ed-a8fd-d6c9b1fd9592
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455769703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3455769703
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.987241817
Short name T669
Test name
Test status
Simulation time 47135887 ps
CPU time 0.6 seconds
Started Jun 25 05:26:08 PM PDT 24
Finished Jun 25 05:26:10 PM PDT 24
Peak memory 194428 kb
Host smart-3da1f7db-6bfe-4212-88af-81dd9dd283bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987241817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.987241817
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.744087236
Short name T759
Test name
Test status
Simulation time 62135999 ps
CPU time 1.2 seconds
Started Jun 25 05:26:13 PM PDT 24
Finished Jun 25 05:26:16 PM PDT 24
Peak memory 199336 kb
Host smart-80174dba-dc75-4bac-8f9d-673473b07402
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744087236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_
outstanding.744087236
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2873491209
Short name T714
Test name
Test status
Simulation time 776963209 ps
CPU time 3.62 seconds
Started Jun 25 05:26:18 PM PDT 24
Finished Jun 25 05:26:23 PM PDT 24
Peak memory 199680 kb
Host smart-e66beb8d-29b5-4504-8a6f-67d954a6d433
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873491209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2873491209
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.773070148
Short name T138
Test name
Test status
Simulation time 183225654 ps
CPU time 1.81 seconds
Started Jun 25 05:26:08 PM PDT 24
Finished Jun 25 05:26:12 PM PDT 24
Peak memory 199620 kb
Host smart-dfb2973b-7363-42f4-98dd-e88cd92ed00b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773070148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.773070148
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.837820470
Short name T65
Test name
Test status
Simulation time 89279815 ps
CPU time 2.26 seconds
Started Jun 25 05:26:19 PM PDT 24
Finished Jun 25 05:26:24 PM PDT 24
Peak memory 199768 kb
Host smart-d00e6e68-0916-4b15-94af-b619ff109792
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837820470 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.837820470
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.823023527
Short name T753
Test name
Test status
Simulation time 19138103 ps
CPU time 0.7 seconds
Started Jun 25 05:26:20 PM PDT 24
Finished Jun 25 05:26:23 PM PDT 24
Peak memory 197640 kb
Host smart-42d57e7a-ac77-4401-bf27-18b0df747009
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823023527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.823023527
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.468378596
Short name T677
Test name
Test status
Simulation time 63206560 ps
CPU time 0.58 seconds
Started Jun 25 05:26:20 PM PDT 24
Finished Jun 25 05:26:22 PM PDT 24
Peak memory 194480 kb
Host smart-ce283526-d9b8-4f2d-85e5-4af410c681b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468378596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.468378596
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2247756474
Short name T102
Test name
Test status
Simulation time 54868551 ps
CPU time 1.2 seconds
Started Jun 25 05:26:15 PM PDT 24
Finished Jun 25 05:26:17 PM PDT 24
Peak memory 199480 kb
Host smart-801b284d-9bca-4af8-aefa-83899973ecd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247756474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2247756474
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.530784390
Short name T60
Test name
Test status
Simulation time 1009465366 ps
CPU time 4.57 seconds
Started Jun 25 05:26:15 PM PDT 24
Finished Jun 25 05:26:21 PM PDT 24
Peak memory 199680 kb
Host smart-9266b4cb-1ebc-48f8-bd84-accc1787ee68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530784390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.530784390
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.494160742
Short name T705
Test name
Test status
Simulation time 1245025227 ps
CPU time 4.02 seconds
Started Jun 25 05:26:20 PM PDT 24
Finished Jun 25 05:26:26 PM PDT 24
Peak memory 199664 kb
Host smart-1d325249-2d9a-4b26-9862-44103b758a90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494160742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.494160742
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3024471572
Short name T72
Test name
Test status
Simulation time 384369597 ps
CPU time 2.45 seconds
Started Jun 25 05:26:08 PM PDT 24
Finished Jun 25 05:26:12 PM PDT 24
Peak memory 199760 kb
Host smart-8ebfaf31-09ec-4afe-8b05-3810534aa056
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024471572 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3024471572
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2616722499
Short name T698
Test name
Test status
Simulation time 32498884 ps
CPU time 0.95 seconds
Started Jun 25 05:26:18 PM PDT 24
Finished Jun 25 05:26:21 PM PDT 24
Peak memory 199400 kb
Host smart-11f30048-3523-40e1-94fe-155773b6ab18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616722499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2616722499
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1292374091
Short name T749
Test name
Test status
Simulation time 16269926 ps
CPU time 0.64 seconds
Started Jun 25 05:26:15 PM PDT 24
Finished Jun 25 05:26:17 PM PDT 24
Peak memory 194588 kb
Host smart-049c405f-43a9-4115-8dab-f04030661147
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292374091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1292374091
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1989044489
Short name T755
Test name
Test status
Simulation time 86788690 ps
CPU time 1.2 seconds
Started Jun 25 05:26:08 PM PDT 24
Finished Jun 25 05:26:12 PM PDT 24
Peak memory 199644 kb
Host smart-4262eb25-177b-48ef-b801-2c39242ca20a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989044489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.1989044489
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2245485598
Short name T690
Test name
Test status
Simulation time 295420023 ps
CPU time 3.56 seconds
Started Jun 25 05:26:19 PM PDT 24
Finished Jun 25 05:26:24 PM PDT 24
Peak memory 199676 kb
Host smart-691c830d-c5ad-4ee2-91b2-98542aec196c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245485598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2245485598
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3909832410
Short name T139
Test name
Test status
Simulation time 107294062 ps
CPU time 2.89 seconds
Started Jun 25 05:26:15 PM PDT 24
Finished Jun 25 05:26:19 PM PDT 24
Peak memory 199692 kb
Host smart-4074c235-1915-4935-b9b6-54ea4789bd84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909832410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3909832410
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.985296061
Short name T590
Test name
Test status
Simulation time 40770578 ps
CPU time 0.59 seconds
Started Jun 25 05:28:38 PM PDT 24
Finished Jun 25 05:28:41 PM PDT 24
Peak memory 195796 kb
Host smart-d771f7e3-2e5a-430c-8358-f91a2e13c1c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985296061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.985296061
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2566612243
Short name T8
Test name
Test status
Simulation time 1535132680 ps
CPU time 36.86 seconds
Started Jun 25 05:29:10 PM PDT 24
Finished Jun 25 05:29:48 PM PDT 24
Peak memory 200044 kb
Host smart-167bc59d-6dda-42e5-ad30-1f95e0382163
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2566612243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2566612243
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.4112366927
Short name T640
Test name
Test status
Simulation time 855160367 ps
CPU time 12.13 seconds
Started Jun 25 05:28:57 PM PDT 24
Finished Jun 25 05:29:11 PM PDT 24
Peak memory 200056 kb
Host smart-cf2e243f-7103-4e35-a97f-7a41973f9599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112366927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.4112366927
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.2432386844
Short name T423
Test name
Test status
Simulation time 16244944459 ps
CPU time 790.57 seconds
Started Jun 25 05:28:43 PM PDT 24
Finished Jun 25 05:41:56 PM PDT 24
Peak memory 694088 kb
Host smart-9285cf29-45b1-4780-9fba-eeb0d042033e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2432386844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2432386844
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1787056579
Short name T503
Test name
Test status
Simulation time 7313340287 ps
CPU time 130.25 seconds
Started Jun 25 05:29:04 PM PDT 24
Finished Jun 25 05:31:16 PM PDT 24
Peak memory 200068 kb
Host smart-62127731-500a-47b6-a192-96e32b216bd7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787056579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1787056579
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_smoke.1324543408
Short name T252
Test name
Test status
Simulation time 907351760 ps
CPU time 13.25 seconds
Started Jun 25 05:28:49 PM PDT 24
Finished Jun 25 05:29:03 PM PDT 24
Peak memory 199988 kb
Host smart-99e6668b-b7f7-467d-a4d1-aa59bf37857f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324543408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1324543408
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.3046608557
Short name T224
Test name
Test status
Simulation time 104940267 ps
CPU time 1.09 seconds
Started Jun 25 05:28:49 PM PDT 24
Finished Jun 25 05:28:51 PM PDT 24
Peak memory 199816 kb
Host smart-a2f9557b-2bc3-400b-a81f-49eb91559ea7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046608557 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac_vectors.3046608557
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.3297039565
Short name T258
Test name
Test status
Simulation time 27467552494 ps
CPU time 495.65 seconds
Started Jun 25 05:28:57 PM PDT 24
Finished Jun 25 05:37:15 PM PDT 24
Peak memory 200092 kb
Host smart-53aeb46b-6249-4925-a442-a47ac3fe83da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3297039565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3297039565
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.2930649097
Short name T568
Test name
Test status
Simulation time 33721253665 ps
CPU time 1877.75 seconds
Started Jun 25 05:29:00 PM PDT 24
Finished Jun 25 06:00:21 PM PDT 24
Peak memory 216416 kb
Host smart-0ba852c2-530c-4cb7-8805-cafd51267d57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2930649097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.2930649097
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.3097806855
Short name T217
Test name
Test status
Simulation time 119162925849 ps
CPU time 1910.62 seconds
Started Jun 25 05:29:04 PM PDT 24
Finished Jun 25 06:00:57 PM PDT 24
Peak memory 215700 kb
Host smart-11bb46c6-3a80-42e5-94d9-5afb8ebe3a08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3097806855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.3097806855
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1856940875
Short name T493
Test name
Test status
Simulation time 10356878701 ps
CPU time 36.72 seconds
Started Jun 25 05:28:40 PM PDT 24
Finished Jun 25 05:29:20 PM PDT 24
Peak memory 200124 kb
Host smart-eb6ffdbe-51c7-4f09-bfe0-82008b2aed7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856940875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1856940875
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2350685474
Short name T657
Test name
Test status
Simulation time 20841897 ps
CPU time 0.57 seconds
Started Jun 25 05:28:48 PM PDT 24
Finished Jun 25 05:28:49 PM PDT 24
Peak memory 196096 kb
Host smart-a450eb24-08c3-43b2-a93d-5704a389b8d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350685474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2350685474
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.47316257
Short name T126
Test name
Test status
Simulation time 4735786410 ps
CPU time 41.33 seconds
Started Jun 25 05:28:57 PM PDT 24
Finished Jun 25 05:29:40 PM PDT 24
Peak memory 200116 kb
Host smart-ddb925a0-a99a-443b-9f9f-f77e9cca5ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47316257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.47316257
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.503398075
Short name T231
Test name
Test status
Simulation time 79714998 ps
CPU time 4.15 seconds
Started Jun 25 05:28:52 PM PDT 24
Finished Jun 25 05:28:57 PM PDT 24
Peak memory 199964 kb
Host smart-97de8d90-ad57-4b24-b1d2-c65a5e05caee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=503398075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.503398075
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.17375611
Short name T487
Test name
Test status
Simulation time 16313781758 ps
CPU time 64.28 seconds
Started Jun 25 05:28:45 PM PDT 24
Finished Jun 25 05:29:51 PM PDT 24
Peak memory 200080 kb
Host smart-b8342f01-40c9-49a3-b231-d68b4e8d8ce5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17375611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.17375611
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.585444140
Short name T643
Test name
Test status
Simulation time 3635959392 ps
CPU time 118.38 seconds
Started Jun 25 05:28:41 PM PDT 24
Finished Jun 25 05:30:42 PM PDT 24
Peak memory 200240 kb
Host smart-45ff89d5-11d9-48fa-94b1-faca484c0c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585444140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.585444140
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3850874420
Short name T42
Test name
Test status
Simulation time 92545324 ps
CPU time 1.02 seconds
Started Jun 25 05:28:50 PM PDT 24
Finished Jun 25 05:28:52 PM PDT 24
Peak memory 219232 kb
Host smart-f42344ae-9aa1-49cf-91ba-3061add1be45
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850874420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3850874420
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.1606156081
Short name T416
Test name
Test status
Simulation time 184026240 ps
CPU time 8.52 seconds
Started Jun 25 05:28:37 PM PDT 24
Finished Jun 25 05:28:47 PM PDT 24
Peak memory 200064 kb
Host smart-d873d03b-b090-4200-9757-0d5c9282ddda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606156081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1606156081
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.4259607390
Short name T348
Test name
Test status
Simulation time 39226119609 ps
CPU time 1548.04 seconds
Started Jun 25 05:28:53 PM PDT 24
Finished Jun 25 05:54:42 PM PDT 24
Peak memory 761048 kb
Host smart-31a6ed8b-97c1-4a66-8704-f45b8c6ccc98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259607390 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.4259607390
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.3351017481
Short name T294
Test name
Test status
Simulation time 201889980 ps
CPU time 1.18 seconds
Started Jun 25 05:29:00 PM PDT 24
Finished Jun 25 05:29:03 PM PDT 24
Peak memory 199996 kb
Host smart-a06d6288-bb21-4e3a-804e-1c50e1f7b2af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351017481 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac_vectors.3351017481
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.3230011549
Short name T473
Test name
Test status
Simulation time 159430031312 ps
CPU time 531.92 seconds
Started Jun 25 05:28:45 PM PDT 24
Finished Jun 25 05:37:39 PM PDT 24
Peak memory 200072 kb
Host smart-cadff350-b66b-4691-b2b2-de50c2232d2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3230011549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.3230011549
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.42804074
Short name T453
Test name
Test status
Simulation time 429337763216 ps
CPU time 1808.57 seconds
Started Jun 25 05:28:54 PM PDT 24
Finished Jun 25 05:59:04 PM PDT 24
Peak memory 215556 kb
Host smart-67621a4b-0591-4d6b-a597-f8d71e6223a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=42804074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.42804074
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.3254902548
Short name T351
Test name
Test status
Simulation time 99947591556 ps
CPU time 1751.88 seconds
Started Jun 25 05:28:53 PM PDT 24
Finished Jun 25 05:58:06 PM PDT 24
Peak memory 215620 kb
Host smart-e6239b8d-388f-48d1-b837-103a047f3f4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3254902548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.3254902548
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.359579636
Short name T560
Test name
Test status
Simulation time 2699708869 ps
CPU time 58.87 seconds
Started Jun 25 05:28:52 PM PDT 24
Finished Jun 25 05:29:51 PM PDT 24
Peak memory 200088 kb
Host smart-ccac27a1-a0e3-420e-9163-2420b3870e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359579636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.359579636
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1485088027
Short name T301
Test name
Test status
Simulation time 16024346 ps
CPU time 0.63 seconds
Started Jun 25 05:29:01 PM PDT 24
Finished Jun 25 05:29:04 PM PDT 24
Peak memory 196172 kb
Host smart-228b9779-27bd-4ba1-ad1b-d331b985214c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485088027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1485088027
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1647081419
Short name T264
Test name
Test status
Simulation time 1508228418 ps
CPU time 5.74 seconds
Started Jun 25 05:29:00 PM PDT 24
Finished Jun 25 05:29:08 PM PDT 24
Peak memory 199968 kb
Host smart-cabe9231-1c03-46a7-9077-67c10dcf3730
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647081419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1647081419
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3445975005
Short name T614
Test name
Test status
Simulation time 146265102 ps
CPU time 8.39 seconds
Started Jun 25 05:28:53 PM PDT 24
Finished Jun 25 05:29:02 PM PDT 24
Peak memory 199928 kb
Host smart-84682cc2-9e48-47be-89cb-fc741c8965c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445975005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3445975005
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.831342564
Short name T177
Test name
Test status
Simulation time 44922863178 ps
CPU time 629.64 seconds
Started Jun 25 05:29:15 PM PDT 24
Finished Jun 25 05:39:48 PM PDT 24
Peak memory 678756 kb
Host smart-7e6e5636-74a9-44b0-8160-f04b850be6ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=831342564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.831342564
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.499354887
Short name T133
Test name
Test status
Simulation time 11291139058 ps
CPU time 210.18 seconds
Started Jun 25 05:29:02 PM PDT 24
Finished Jun 25 05:32:34 PM PDT 24
Peak memory 200096 kb
Host smart-18758c83-80a6-4ecb-a495-5e8619eaae1e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499354887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.499354887
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.2624279393
Short name T346
Test name
Test status
Simulation time 770941345 ps
CPU time 12.58 seconds
Started Jun 25 05:29:04 PM PDT 24
Finished Jun 25 05:29:18 PM PDT 24
Peak memory 199988 kb
Host smart-769d7608-0f0b-4a2d-aef6-5e7ba4c30646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624279393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2624279393
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1681459383
Short name T185
Test name
Test status
Simulation time 5971501873 ps
CPU time 20.77 seconds
Started Jun 25 05:29:11 PM PDT 24
Finished Jun 25 05:29:33 PM PDT 24
Peak memory 200108 kb
Host smart-2d3a482d-4041-45d6-af17-6d17d1dbbab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681459383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1681459383
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.65829968
Short name T75
Test name
Test status
Simulation time 708346215 ps
CPU time 1.21 seconds
Started Jun 25 05:28:59 PM PDT 24
Finished Jun 25 05:29:03 PM PDT 24
Peak memory 200012 kb
Host smart-7402c71d-ba65-4d5e-a22d-7e4738a95099
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65829968 -assert nopostpro
c +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_hmac_vectors.65829968
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha256_vectors.324198763
Short name T247
Test name
Test status
Simulation time 157029662823 ps
CPU time 517.38 seconds
Started Jun 25 05:29:12 PM PDT 24
Finished Jun 25 05:37:50 PM PDT 24
Peak memory 200008 kb
Host smart-75c45130-c7d4-448b-8a85-dccdf57bc46a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=324198763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha256_vectors.324198763
Directory /workspace/10.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha384_vectors.690146365
Short name T187
Test name
Test status
Simulation time 140587549927 ps
CPU time 1874.95 seconds
Started Jun 25 05:29:09 PM PDT 24
Finished Jun 25 06:00:25 PM PDT 24
Peak memory 215672 kb
Host smart-75ae213b-0eea-449e-bfdf-529423073549
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=690146365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha384_vectors.690146365
Directory /workspace/10.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha512_vectors.158683053
Short name T601
Test name
Test status
Simulation time 531744362099 ps
CPU time 1824.74 seconds
Started Jun 25 05:28:57 PM PDT 24
Finished Jun 25 05:59:23 PM PDT 24
Peak memory 216020 kb
Host smart-1cbea196-cffb-4834-9203-75230cb08c69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=158683053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha512_vectors.158683053
Directory /workspace/10.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1797451349
Short name T344
Test name
Test status
Simulation time 612997157 ps
CPU time 33.58 seconds
Started Jun 25 05:29:01 PM PDT 24
Finished Jun 25 05:29:37 PM PDT 24
Peak memory 200052 kb
Host smart-31d1ccb7-662e-44aa-804d-f350f8c5fab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797451349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1797451349
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1592901725
Short name T299
Test name
Test status
Simulation time 42779363 ps
CPU time 0.58 seconds
Started Jun 25 05:29:04 PM PDT 24
Finished Jun 25 05:29:06 PM PDT 24
Peak memory 194976 kb
Host smart-b87cd19a-2b48-4384-997a-e08f91e702d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592901725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1592901725
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1274208545
Short name T54
Test name
Test status
Simulation time 4824812556 ps
CPU time 42.32 seconds
Started Jun 25 05:29:12 PM PDT 24
Finished Jun 25 05:29:56 PM PDT 24
Peak memory 208280 kb
Host smart-8d511652-b363-40fd-a4a2-4204990ad98c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1274208545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1274208545
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1620962498
Short name T474
Test name
Test status
Simulation time 4657740266 ps
CPU time 46.96 seconds
Started Jun 25 05:29:09 PM PDT 24
Finished Jun 25 05:29:57 PM PDT 24
Peak memory 200156 kb
Host smart-666b937a-3e45-4c39-859e-243716a1117a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620962498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1620962498
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3352402776
Short name T427
Test name
Test status
Simulation time 1166660693 ps
CPU time 84.39 seconds
Started Jun 25 05:29:13 PM PDT 24
Finished Jun 25 05:30:39 PM PDT 24
Peak memory 450888 kb
Host smart-516c5879-b193-44ee-91a9-be7bd8e9a4e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3352402776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3352402776
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.3070692311
Short name T613
Test name
Test status
Simulation time 7738988471 ps
CPU time 145.09 seconds
Started Jun 25 05:29:11 PM PDT 24
Finished Jun 25 05:31:37 PM PDT 24
Peak memory 200028 kb
Host smart-d8506d8b-37bd-41cd-8d60-512b2a722872
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070692311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3070692311
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1200889304
Short name T580
Test name
Test status
Simulation time 947232574 ps
CPU time 58.99 seconds
Started Jun 25 05:29:08 PM PDT 24
Finished Jun 25 05:30:08 PM PDT 24
Peak memory 199476 kb
Host smart-92bc785d-a085-40cf-8ecd-0e4ec73b1248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200889304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1200889304
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.4046434212
Short name T492
Test name
Test status
Simulation time 624430190 ps
CPU time 9.32 seconds
Started Jun 25 05:29:14 PM PDT 24
Finished Jun 25 05:29:26 PM PDT 24
Peak memory 200044 kb
Host smart-722ec084-674a-4a84-b472-5da71778d531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046434212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.4046434212
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.412579122
Short name T267
Test name
Test status
Simulation time 76737051 ps
CPU time 1.51 seconds
Started Jun 25 05:29:16 PM PDT 24
Finished Jun 25 05:29:21 PM PDT 24
Peak memory 199896 kb
Host smart-ddbf3613-a2f5-41a9-858b-8ea07d3272c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412579122 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_hmac_vectors.412579122
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha256_vectors.690856345
Short name T214
Test name
Test status
Simulation time 33951064248 ps
CPU time 570.46 seconds
Started Jun 25 05:29:12 PM PDT 24
Finished Jun 25 05:38:44 PM PDT 24
Peak memory 200040 kb
Host smart-b5913a27-1b71-4ca8-bdb9-2556b2770077
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=690856345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha256_vectors.690856345
Directory /workspace/11.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha384_vectors.806896483
Short name T664
Test name
Test status
Simulation time 232075768229 ps
CPU time 1951.98 seconds
Started Jun 25 05:29:11 PM PDT 24
Finished Jun 25 06:01:45 PM PDT 24
Peak memory 216404 kb
Host smart-c00c4ceb-e607-4e2c-a76b-77307e1f8016
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=806896483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha384_vectors.806896483
Directory /workspace/11.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha512_vectors.1431518875
Short name T633
Test name
Test status
Simulation time 196691989515 ps
CPU time 1741.93 seconds
Started Jun 25 05:28:57 PM PDT 24
Finished Jun 25 05:58:01 PM PDT 24
Peak memory 216428 kb
Host smart-3a41c97a-e4c8-4dca-8b96-00e5c50a9e79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1431518875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha512_vectors.1431518875
Directory /workspace/11.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2579735662
Short name T424
Test name
Test status
Simulation time 30972237841 ps
CPU time 87.37 seconds
Started Jun 25 05:29:02 PM PDT 24
Finished Jun 25 05:30:31 PM PDT 24
Peak memory 200008 kb
Host smart-1681644a-3bc2-44b7-aa3d-6292e0e09d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579735662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2579735662
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2864634359
Short name T47
Test name
Test status
Simulation time 12023950 ps
CPU time 0.59 seconds
Started Jun 25 05:29:09 PM PDT 24
Finished Jun 25 05:29:11 PM PDT 24
Peak memory 195728 kb
Host smart-aadee90d-e3f5-4f43-9765-7a8c1eee6ca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864634359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2864634359
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3259084767
Short name T465
Test name
Test status
Simulation time 1164763774 ps
CPU time 57.2 seconds
Started Jun 25 05:29:16 PM PDT 24
Finished Jun 25 05:30:17 PM PDT 24
Peak memory 199936 kb
Host smart-d073c395-6350-4c74-9339-27c8f4b5bac2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3259084767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3259084767
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2073408753
Short name T489
Test name
Test status
Simulation time 1867927930 ps
CPU time 37.54 seconds
Started Jun 25 05:29:08 PM PDT 24
Finished Jun 25 05:29:47 PM PDT 24
Peak memory 199996 kb
Host smart-0ad9433c-e5a5-41ab-a31a-eb04f9ab295b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073408753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2073408753
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1306767932
Short name T438
Test name
Test status
Simulation time 3663213937 ps
CPU time 978.37 seconds
Started Jun 25 05:29:14 PM PDT 24
Finished Jun 25 05:45:35 PM PDT 24
Peak memory 689592 kb
Host smart-3f78ef98-9fd7-4000-8f4a-c1ac50fc1f2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1306767932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1306767932
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1078825919
Short name T136
Test name
Test status
Simulation time 24269351636 ps
CPU time 111.62 seconds
Started Jun 25 05:29:00 PM PDT 24
Finished Jun 25 05:30:54 PM PDT 24
Peak memory 200124 kb
Host smart-d629cc65-3bff-4405-bae3-8fbe43e6e9ca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078825919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1078825919
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.292666294
Short name T532
Test name
Test status
Simulation time 203411872 ps
CPU time 11.62 seconds
Started Jun 25 05:28:58 PM PDT 24
Finished Jun 25 05:29:12 PM PDT 24
Peak memory 200076 kb
Host smart-aad71a7c-6225-4bab-81ca-59706388e98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292666294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.292666294
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2338104358
Short name T606
Test name
Test status
Simulation time 563425636 ps
CPU time 7.09 seconds
Started Jun 25 05:28:59 PM PDT 24
Finished Jun 25 05:29:08 PM PDT 24
Peak memory 199984 kb
Host smart-94bf0c86-2ae0-4de3-9be2-61502b2354fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338104358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2338104358
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.1298129460
Short name T584
Test name
Test status
Simulation time 196315096 ps
CPU time 1.2 seconds
Started Jun 25 05:28:59 PM PDT 24
Finished Jun 25 05:29:02 PM PDT 24
Peak memory 199992 kb
Host smart-6f8f79a0-b0e3-42ca-889b-b6a9580f14d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298129460 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_hmac_vectors.1298129460
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha256_vectors.2052357073
Short name T327
Test name
Test status
Simulation time 84565587386 ps
CPU time 416.08 seconds
Started Jun 25 05:29:12 PM PDT 24
Finished Jun 25 05:36:10 PM PDT 24
Peak memory 200036 kb
Host smart-3e2e24d7-af5b-48f4-b3c2-7e5b2d74282d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2052357073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha256_vectors.2052357073
Directory /workspace/12.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha384_vectors.1431727160
Short name T582
Test name
Test status
Simulation time 31254775971 ps
CPU time 1720.79 seconds
Started Jun 25 05:29:07 PM PDT 24
Finished Jun 25 05:57:49 PM PDT 24
Peak memory 216108 kb
Host smart-32f84c79-bc73-42bc-a63c-18f457660685
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1431727160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha384_vectors.1431727160
Directory /workspace/12.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha512_vectors.2599649011
Short name T314
Test name
Test status
Simulation time 29477122140 ps
CPU time 1626.08 seconds
Started Jun 25 05:29:06 PM PDT 24
Finished Jun 25 05:56:14 PM PDT 24
Peak memory 215752 kb
Host smart-fcf84e2d-e552-404e-80d3-39a4108f88f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2599649011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha512_vectors.2599649011
Directory /workspace/12.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2729981854
Short name T370
Test name
Test status
Simulation time 3666969794 ps
CPU time 53.36 seconds
Started Jun 25 05:29:08 PM PDT 24
Finished Jun 25 05:30:03 PM PDT 24
Peak memory 200060 kb
Host smart-e4c9b353-72e1-425e-9213-7ce2731830a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729981854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2729981854
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3135225705
Short name T594
Test name
Test status
Simulation time 14686842 ps
CPU time 0.62 seconds
Started Jun 25 05:29:13 PM PDT 24
Finished Jun 25 05:29:15 PM PDT 24
Peak memory 196128 kb
Host smart-509009fb-5f81-4e87-9433-56892176b703
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135225705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3135225705
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1617380730
Short name T567
Test name
Test status
Simulation time 2831696607 ps
CPU time 36.04 seconds
Started Jun 25 05:29:14 PM PDT 24
Finished Jun 25 05:29:52 PM PDT 24
Peak memory 199980 kb
Host smart-559de136-6fc1-4141-b8c3-846a5930783c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1617380730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1617380730
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2565831178
Short name T150
Test name
Test status
Simulation time 4450662092 ps
CPU time 64.44 seconds
Started Jun 25 05:29:18 PM PDT 24
Finished Jun 25 05:30:25 PM PDT 24
Peak memory 200100 kb
Host smart-b3c3a48d-70ac-4b1e-88d9-704a4e7f5b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565831178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2565831178
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2291045350
Short name T394
Test name
Test status
Simulation time 3361856697 ps
CPU time 729.43 seconds
Started Jun 25 05:29:12 PM PDT 24
Finished Jun 25 05:41:23 PM PDT 24
Peak memory 707104 kb
Host smart-6650c4d0-427e-4c83-80fc-04f8534ba2e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2291045350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2291045350
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1053554692
Short name T52
Test name
Test status
Simulation time 1050417242 ps
CPU time 64.84 seconds
Started Jun 25 05:29:18 PM PDT 24
Finished Jun 25 05:30:25 PM PDT 24
Peak memory 199888 kb
Host smart-43f877ca-98d2-4098-b638-104095c76ef2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053554692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1053554692
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.3303802123
Short name T430
Test name
Test status
Simulation time 16943266296 ps
CPU time 64.41 seconds
Started Jun 25 05:29:14 PM PDT 24
Finished Jun 25 05:30:21 PM PDT 24
Peak memory 200208 kb
Host smart-47aa4205-8a88-4b05-a35f-b34b0dc27d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303802123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3303802123
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1638579855
Short name T466
Test name
Test status
Simulation time 195212999 ps
CPU time 8.72 seconds
Started Jun 25 05:29:15 PM PDT 24
Finished Jun 25 05:29:26 PM PDT 24
Peak memory 200012 kb
Host smart-b7218005-c9d6-4a5e-9cb6-85dcd758f296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638579855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1638579855
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2451578367
Short name T548
Test name
Test status
Simulation time 6355922465 ps
CPU time 321.76 seconds
Started Jun 25 05:29:15 PM PDT 24
Finished Jun 25 05:34:40 PM PDT 24
Peak memory 678456 kb
Host smart-6072caad-a463-4eb4-bca3-8329900b1de4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451578367 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2451578367
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.110543405
Short name T624
Test name
Test status
Simulation time 175340066 ps
CPU time 1.12 seconds
Started Jun 25 05:29:09 PM PDT 24
Finished Jun 25 05:29:11 PM PDT 24
Peak memory 199856 kb
Host smart-a9b4c9c8-abb7-48d3-a68e-36773056c68e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110543405 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_hmac_vectors.110543405
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha256_vectors.285817538
Short name T265
Test name
Test status
Simulation time 107116900889 ps
CPU time 438.3 seconds
Started Jun 25 05:28:55 PM PDT 24
Finished Jun 25 05:36:14 PM PDT 24
Peak memory 200032 kb
Host smart-98e6f7b9-9663-4c8e-b191-6108b91ef08c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=285817538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha256_vectors.285817538
Directory /workspace/13.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha384_vectors.170281636
Short name T388
Test name
Test status
Simulation time 238552010886 ps
CPU time 1814.88 seconds
Started Jun 25 05:29:15 PM PDT 24
Finished Jun 25 05:59:33 PM PDT 24
Peak memory 216404 kb
Host smart-34dd288f-3a8e-4293-b94a-d9ee3b1a06f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=170281636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha384_vectors.170281636
Directory /workspace/13.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha512_vectors.2635086791
Short name T442
Test name
Test status
Simulation time 125659075526 ps
CPU time 1762.21 seconds
Started Jun 25 05:29:11 PM PDT 24
Finished Jun 25 05:58:35 PM PDT 24
Peak memory 215976 kb
Host smart-851ad4d1-4f62-4840-aa28-4ab6c42497f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2635086791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha512_vectors.2635086791
Directory /workspace/13.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2786445242
Short name T516
Test name
Test status
Simulation time 3692449715 ps
CPU time 48.72 seconds
Started Jun 25 05:29:22 PM PDT 24
Finished Jun 25 05:30:12 PM PDT 24
Peak memory 200084 kb
Host smart-b6a70df9-01a0-4c52-a3e4-6b87c8aca9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786445242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2786445242
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2844547431
Short name T523
Test name
Test status
Simulation time 41028001 ps
CPU time 0.61 seconds
Started Jun 25 05:29:13 PM PDT 24
Finished Jun 25 05:29:16 PM PDT 24
Peak memory 195704 kb
Host smart-68d22e4c-811a-416b-8d12-d3cd14e0410b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844547431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2844547431
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.98456323
Short name T290
Test name
Test status
Simulation time 1660204918 ps
CPU time 34.89 seconds
Started Jun 25 05:29:24 PM PDT 24
Finished Jun 25 05:30:00 PM PDT 24
Peak memory 200080 kb
Host smart-3021e145-e2b2-4c7d-b595-17803ffb4645
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=98456323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.98456323
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.1834762685
Short name T589
Test name
Test status
Simulation time 3537170254 ps
CPU time 47.11 seconds
Started Jun 25 05:28:58 PM PDT 24
Finished Jun 25 05:29:47 PM PDT 24
Peak memory 200088 kb
Host smart-2d47585e-90a0-4d70-9e26-d02259399d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834762685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.1834762685
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2104150882
Short name T547
Test name
Test status
Simulation time 13540980107 ps
CPU time 789.79 seconds
Started Jun 25 05:29:15 PM PDT 24
Finished Jun 25 05:42:28 PM PDT 24
Peak memory 692504 kb
Host smart-872447cc-c99e-4dbb-8153-078f466057e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2104150882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2104150882
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1335960212
Short name T245
Test name
Test status
Simulation time 14560829023 ps
CPU time 202.6 seconds
Started Jun 25 05:29:10 PM PDT 24
Finished Jun 25 05:32:34 PM PDT 24
Peak memory 200064 kb
Host smart-2ff1bf06-9b11-42af-a3d0-2d311193bf86
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335960212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1335960212
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.3239406894
Short name T256
Test name
Test status
Simulation time 9108996310 ps
CPU time 43.45 seconds
Started Jun 25 05:29:09 PM PDT 24
Finished Jun 25 05:29:53 PM PDT 24
Peak memory 200120 kb
Host smart-34d4fe86-68a6-4cdc-b7c7-dded74a96f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239406894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3239406894
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3815656331
Short name T226
Test name
Test status
Simulation time 613743750 ps
CPU time 8.27 seconds
Started Jun 25 05:29:13 PM PDT 24
Finished Jun 25 05:29:23 PM PDT 24
Peak memory 200000 kb
Host smart-6c8bc2e8-0222-4882-ae47-5e1ade22c6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815656331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3815656331
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.1019552263
Short name T153
Test name
Test status
Simulation time 225428497 ps
CPU time 1.39 seconds
Started Jun 25 05:28:58 PM PDT 24
Finished Jun 25 05:29:02 PM PDT 24
Peak memory 200032 kb
Host smart-f7237743-d5d3-4c0c-8447-f825fb7ab34c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019552263 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_hmac_vectors.1019552263
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha256_vectors.1609188840
Short name T350
Test name
Test status
Simulation time 79859434381 ps
CPU time 518.81 seconds
Started Jun 25 05:29:06 PM PDT 24
Finished Jun 25 05:37:46 PM PDT 24
Peak memory 200040 kb
Host smart-9bde4c70-fb17-4e11-85e3-6bd624a84a14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1609188840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha256_vectors.1609188840
Directory /workspace/14.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha384_vectors.2025847515
Short name T650
Test name
Test status
Simulation time 31218585962 ps
CPU time 1725.72 seconds
Started Jun 25 05:29:08 PM PDT 24
Finished Jun 25 05:57:55 PM PDT 24
Peak memory 215504 kb
Host smart-25d37560-17ce-4b9a-b24d-60ff77684b3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2025847515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha384_vectors.2025847515
Directory /workspace/14.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha512_vectors.72606035
Short name T391
Test name
Test status
Simulation time 327769142620 ps
CPU time 2040.3 seconds
Started Jun 25 05:29:08 PM PDT 24
Finished Jun 25 06:03:10 PM PDT 24
Peak memory 216040 kb
Host smart-ea828b96-d64e-488e-8137-05e8c2ca6749
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=72606035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha512_vectors.72606035
Directory /workspace/14.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3464474560
Short name T625
Test name
Test status
Simulation time 4414942905 ps
CPU time 8.11 seconds
Started Jun 25 05:29:07 PM PDT 24
Finished Jun 25 05:29:16 PM PDT 24
Peak memory 200024 kb
Host smart-05eae870-ffee-49c2-aae8-dd3257267978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464474560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3464474560
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.811513561
Short name T398
Test name
Test status
Simulation time 36774330 ps
CPU time 0.59 seconds
Started Jun 25 05:29:14 PM PDT 24
Finished Jun 25 05:29:17 PM PDT 24
Peak memory 195912 kb
Host smart-7c0643f5-733d-4c48-b48e-abc0748717a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811513561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.811513561
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1236874355
Short name T620
Test name
Test status
Simulation time 45002273 ps
CPU time 2.72 seconds
Started Jun 25 05:29:35 PM PDT 24
Finished Jun 25 05:29:40 PM PDT 24
Peak memory 199888 kb
Host smart-e1573eb1-f0c6-4960-ae72-f461d3d6fc17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1236874355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1236874355
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.4151576371
Short name T511
Test name
Test status
Simulation time 1747081370 ps
CPU time 25.62 seconds
Started Jun 25 05:29:13 PM PDT 24
Finished Jun 25 05:29:40 PM PDT 24
Peak memory 199960 kb
Host smart-f311cb64-a121-41d5-bcbe-540147b3675e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151576371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.4151576371
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1096133184
Short name T440
Test name
Test status
Simulation time 1187265214 ps
CPU time 147.55 seconds
Started Jun 25 05:29:18 PM PDT 24
Finished Jun 25 05:31:48 PM PDT 24
Peak memory 448588 kb
Host smart-cad5ec49-d0a8-4d7b-a024-b24d301701bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1096133184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1096133184
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3489045638
Short name T362
Test name
Test status
Simulation time 8712792750 ps
CPU time 75.4 seconds
Started Jun 25 05:29:12 PM PDT 24
Finished Jun 25 05:30:30 PM PDT 24
Peak memory 200108 kb
Host smart-a43c9296-cb83-4559-811d-5dcc1f622fdb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489045638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3489045638
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.666828718
Short name T627
Test name
Test status
Simulation time 681513008 ps
CPU time 37.66 seconds
Started Jun 25 05:29:17 PM PDT 24
Finished Jun 25 05:29:57 PM PDT 24
Peak memory 200024 kb
Host smart-e99b5c7d-5bcc-4eef-829b-8b1e59bd1c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666828718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.666828718
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2478837493
Short name T223
Test name
Test status
Simulation time 767786104 ps
CPU time 9.85 seconds
Started Jun 25 05:29:10 PM PDT 24
Finished Jun 25 05:29:22 PM PDT 24
Peak memory 200024 kb
Host smart-901ef580-5827-438c-8026-68a7d7e102fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478837493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2478837493
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3553027072
Short name T128
Test name
Test status
Simulation time 23507671229 ps
CPU time 169.08 seconds
Started Jun 25 05:29:14 PM PDT 24
Finished Jun 25 05:32:06 PM PDT 24
Peak memory 216464 kb
Host smart-9f898d5c-57c7-4e16-b359-5700776ae051
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553027072 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3553027072
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.1634671573
Short name T108
Test name
Test status
Simulation time 61356613 ps
CPU time 1.28 seconds
Started Jun 25 05:29:21 PM PDT 24
Finished Jun 25 05:29:23 PM PDT 24
Peak memory 199960 kb
Host smart-fe728d00-7e23-4136-be8b-6f42016d2e80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634671573 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_hmac_vectors.1634671573
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha256_vectors.2363515164
Short name T293
Test name
Test status
Simulation time 28477295085 ps
CPU time 503.34 seconds
Started Jun 25 05:29:05 PM PDT 24
Finished Jun 25 05:37:29 PM PDT 24
Peak memory 200044 kb
Host smart-d24d8457-a048-4a9b-9e56-ce9fd3d874f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2363515164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha256_vectors.2363515164
Directory /workspace/15.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha384_vectors.1478561378
Short name T282
Test name
Test status
Simulation time 221076781271 ps
CPU time 1966.87 seconds
Started Jun 25 05:29:13 PM PDT 24
Finished Jun 25 06:02:02 PM PDT 24
Peak memory 215960 kb
Host smart-aeabafab-ca00-4a15-9a98-44324fdc8bee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1478561378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha384_vectors.1478561378
Directory /workspace/15.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha512_vectors.1920840748
Short name T506
Test name
Test status
Simulation time 33628812882 ps
CPU time 1843.34 seconds
Started Jun 25 05:29:14 PM PDT 24
Finished Jun 25 06:00:01 PM PDT 24
Peak memory 215540 kb
Host smart-8bda13df-9b5c-4f71-8c4e-8c6498ac86ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1920840748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha512_vectors.1920840748
Directory /workspace/15.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1678817773
Short name T19
Test name
Test status
Simulation time 1711040467 ps
CPU time 63.23 seconds
Started Jun 25 05:29:13 PM PDT 24
Finished Jun 25 05:30:19 PM PDT 24
Peak memory 200048 kb
Host smart-634fc129-9886-46e4-b50b-f30383efe5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678817773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1678817773
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.613015347
Short name T537
Test name
Test status
Simulation time 40214862 ps
CPU time 0.64 seconds
Started Jun 25 05:29:13 PM PDT 24
Finished Jun 25 05:29:16 PM PDT 24
Peak memory 196120 kb
Host smart-60e81a98-db75-42d1-95ad-9e48ff9ce4b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613015347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.613015347
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1211253771
Short name T20
Test name
Test status
Simulation time 2485690687 ps
CPU time 27.75 seconds
Started Jun 25 05:29:04 PM PDT 24
Finished Jun 25 05:29:33 PM PDT 24
Peak memory 200016 kb
Host smart-44852ea8-c846-43a7-8d86-2b0ff3e0576f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1211253771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1211253771
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.163131268
Short name T239
Test name
Test status
Simulation time 59652554318 ps
CPU time 69.57 seconds
Started Jun 25 05:29:10 PM PDT 24
Finished Jun 25 05:30:21 PM PDT 24
Peak memory 200076 kb
Host smart-514e5a8c-c9e5-49a1-83c0-8733d11b388c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163131268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.163131268
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.206304429
Short name T533
Test name
Test status
Simulation time 17213714315 ps
CPU time 1083.35 seconds
Started Jun 25 05:29:18 PM PDT 24
Finished Jun 25 05:47:24 PM PDT 24
Peak memory 747464 kb
Host smart-6c0244dc-f89a-42fc-b345-85c066a70033
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=206304429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.206304429
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1424021409
Short name T538
Test name
Test status
Simulation time 6646862546 ps
CPU time 93.99 seconds
Started Jun 25 05:29:26 PM PDT 24
Finished Jun 25 05:31:01 PM PDT 24
Peak memory 200040 kb
Host smart-bf53b81e-96ea-42d7-8e8c-5c07a079ade0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424021409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1424021409
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2676052324
Short name T297
Test name
Test status
Simulation time 10437517729 ps
CPU time 47.46 seconds
Started Jun 25 05:29:08 PM PDT 24
Finished Jun 25 05:29:56 PM PDT 24
Peak memory 200052 kb
Host smart-26524c29-e796-40ac-9828-6bc6534dab87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676052324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2676052324
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.274290330
Short name T552
Test name
Test status
Simulation time 231101104 ps
CPU time 10.34 seconds
Started Jun 25 05:29:14 PM PDT 24
Finished Jun 25 05:29:27 PM PDT 24
Peak memory 199944 kb
Host smart-5c9654ac-2d25-438f-a0f9-f4c305cb6781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274290330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.274290330
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2704817772
Short name T38
Test name
Test status
Simulation time 160692051 ps
CPU time 6.8 seconds
Started Jun 25 05:29:07 PM PDT 24
Finished Jun 25 05:29:14 PM PDT 24
Peak memory 200056 kb
Host smart-2a236252-07ce-4c0d-8674-e9adaa792201
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704817772 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2704817772
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.1903319526
Short name T288
Test name
Test status
Simulation time 180049252 ps
CPU time 1.04 seconds
Started Jun 25 05:29:14 PM PDT 24
Finished Jun 25 05:29:23 PM PDT 24
Peak memory 199704 kb
Host smart-f6a2c388-8464-4366-87fa-a441cde8c653
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903319526 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_hmac_vectors.1903319526
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha256_vectors.1418493604
Short name T207
Test name
Test status
Simulation time 14046777595 ps
CPU time 418.18 seconds
Started Jun 25 05:29:23 PM PDT 24
Finished Jun 25 05:36:22 PM PDT 24
Peak memory 199984 kb
Host smart-ca2b68ec-f3e2-45e5-82be-3394649664d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1418493604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha256_vectors.1418493604
Directory /workspace/16.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha384_vectors.1933190684
Short name T104
Test name
Test status
Simulation time 607657852100 ps
CPU time 1856.76 seconds
Started Jun 25 05:29:07 PM PDT 24
Finished Jun 25 06:00:05 PM PDT 24
Peak memory 216336 kb
Host smart-0cfd4b98-7b4d-49b6-893f-aa5c959105dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1933190684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha384_vectors.1933190684
Directory /workspace/16.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha512_vectors.4292415504
Short name T204
Test name
Test status
Simulation time 29464783926 ps
CPU time 1600.54 seconds
Started Jun 25 05:29:10 PM PDT 24
Finished Jun 25 05:55:51 PM PDT 24
Peak memory 216012 kb
Host smart-06603ab8-b584-45b5-8ffb-c1ba5d0155dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4292415504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha512_vectors.4292415504
Directory /workspace/16.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2224426404
Short name T525
Test name
Test status
Simulation time 12473064279 ps
CPU time 91.18 seconds
Started Jun 25 05:29:25 PM PDT 24
Finished Jun 25 05:30:57 PM PDT 24
Peak memory 200112 kb
Host smart-f39aa659-d534-422d-8853-c9e53192f9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224426404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2224426404
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1289127140
Short name T232
Test name
Test status
Simulation time 58732709 ps
CPU time 0.63 seconds
Started Jun 25 05:29:24 PM PDT 24
Finished Jun 25 05:29:25 PM PDT 24
Peak memory 196160 kb
Host smart-b6098711-1d1c-4a4a-8cbe-6cb5fa309414
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289127140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1289127140
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2149524078
Short name T26
Test name
Test status
Simulation time 2858958124 ps
CPU time 24.25 seconds
Started Jun 25 05:28:59 PM PDT 24
Finished Jun 25 05:29:25 PM PDT 24
Peak memory 200076 kb
Host smart-ee8a32d8-0bc5-4953-b6c7-be0ea734e3e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2149524078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2149524078
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.170823064
Short name T415
Test name
Test status
Simulation time 121860211 ps
CPU time 2.66 seconds
Started Jun 25 05:29:13 PM PDT 24
Finished Jun 25 05:29:17 PM PDT 24
Peak memory 200048 kb
Host smart-5bd42a72-7acf-471e-a67b-3ea5782d774f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170823064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.170823064
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1522088887
Short name T234
Test name
Test status
Simulation time 8220311601 ps
CPU time 144.12 seconds
Started Jun 25 05:28:58 PM PDT 24
Finished Jun 25 05:31:29 PM PDT 24
Peak memory 465264 kb
Host smart-393eb1cd-b4a9-4741-ac92-83368304ccaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1522088887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1522088887
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1692606123
Short name T609
Test name
Test status
Simulation time 5899804056 ps
CPU time 49.47 seconds
Started Jun 25 05:29:12 PM PDT 24
Finished Jun 25 05:30:03 PM PDT 24
Peak memory 200060 kb
Host smart-8549817d-bfe1-465e-94e0-87f10ba7967d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692606123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1692606123
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2954810716
Short name T259
Test name
Test status
Simulation time 3451100499 ps
CPU time 98.81 seconds
Started Jun 25 05:29:01 PM PDT 24
Finished Jun 25 05:30:42 PM PDT 24
Peak memory 200064 kb
Host smart-56012628-2993-4186-88d2-91eec0e91493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954810716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2954810716
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.1721267082
Short name T592
Test name
Test status
Simulation time 2011021007 ps
CPU time 4.9 seconds
Started Jun 25 05:29:15 PM PDT 24
Finished Jun 25 05:29:23 PM PDT 24
Peak memory 200004 kb
Host smart-d339548f-2db0-40f4-983a-36a2420fe71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721267082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1721267082
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.1051773057
Short name T209
Test name
Test status
Simulation time 33608427 ps
CPU time 1.32 seconds
Started Jun 25 05:29:27 PM PDT 24
Finished Jun 25 05:29:30 PM PDT 24
Peak memory 200028 kb
Host smart-9d5c911b-1581-4c58-bf37-6576a51fea28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051773057 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_hmac_vectors.1051773057
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha256_vectors.2312620619
Short name T577
Test name
Test status
Simulation time 33901611768 ps
CPU time 461.21 seconds
Started Jun 25 05:29:09 PM PDT 24
Finished Jun 25 05:36:52 PM PDT 24
Peak memory 200016 kb
Host smart-c698d157-38f7-4767-babf-b075bbad9fe2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2312620619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha256_vectors.2312620619
Directory /workspace/17.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha384_vectors.3696762222
Short name T557
Test name
Test status
Simulation time 124806536236 ps
CPU time 1720.06 seconds
Started Jun 25 05:29:15 PM PDT 24
Finished Jun 25 05:57:58 PM PDT 24
Peak memory 216072 kb
Host smart-ce056800-b775-474c-9959-987e6b765c02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3696762222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha384_vectors.3696762222
Directory /workspace/17.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha512_vectors.4094043241
Short name T579
Test name
Test status
Simulation time 150052532470 ps
CPU time 1985.97 seconds
Started Jun 25 05:29:11 PM PDT 24
Finished Jun 25 06:02:19 PM PDT 24
Peak memory 215708 kb
Host smart-eb6b1a19-f01b-40eb-bd55-3d05fca291ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4094043241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha512_vectors.4094043241
Directory /workspace/17.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3087105023
Short name T51
Test name
Test status
Simulation time 10980509596 ps
CPU time 31.44 seconds
Started Jun 25 05:29:06 PM PDT 24
Finished Jun 25 05:29:38 PM PDT 24
Peak memory 200128 kb
Host smart-5169367f-c692-4246-a88f-55e1efb6f1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087105023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3087105023
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.599197460
Short name T249
Test name
Test status
Simulation time 39209765 ps
CPU time 0.58 seconds
Started Jun 25 05:29:15 PM PDT 24
Finished Jun 25 05:29:19 PM PDT 24
Peak memory 196068 kb
Host smart-87d41714-1594-45c8-80e6-b6b535a0077f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599197460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.599197460
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2656211996
Short name T320
Test name
Test status
Simulation time 1195763792 ps
CPU time 15.22 seconds
Started Jun 25 05:29:23 PM PDT 24
Finished Jun 25 05:29:39 PM PDT 24
Peak memory 199924 kb
Host smart-fa9ca24b-542a-47e4-b385-f49fa1078330
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2656211996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2656211996
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1369752275
Short name T236
Test name
Test status
Simulation time 2858158784 ps
CPU time 51.04 seconds
Started Jun 25 05:29:08 PM PDT 24
Finished Jun 25 05:30:05 PM PDT 24
Peak memory 200080 kb
Host smart-d6944e38-d17d-4c5f-9b76-5b263c4dba56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369752275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1369752275
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2685960235
Short name T384
Test name
Test status
Simulation time 5010700615 ps
CPU time 1069.42 seconds
Started Jun 25 05:29:13 PM PDT 24
Finished Jun 25 05:47:05 PM PDT 24
Peak memory 756984 kb
Host smart-36a1cdc8-fc96-4486-a40c-8e58b8a05a0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2685960235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2685960235
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.388949680
Short name T130
Test name
Test status
Simulation time 49797543405 ps
CPU time 130.72 seconds
Started Jun 25 05:29:19 PM PDT 24
Finished Jun 25 05:31:32 PM PDT 24
Peak memory 200084 kb
Host smart-e0e6b75f-dc52-4f35-9bf3-053fd51fe338
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388949680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.388949680
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.3680584050
Short name T326
Test name
Test status
Simulation time 1674890675 ps
CPU time 102.45 seconds
Started Jun 25 05:29:12 PM PDT 24
Finished Jun 25 05:30:56 PM PDT 24
Peak memory 200080 kb
Host smart-669e0d4b-bbfd-437f-b693-255609a72264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680584050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3680584050
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.35754376
Short name T483
Test name
Test status
Simulation time 407092536 ps
CPU time 6.01 seconds
Started Jun 25 05:29:14 PM PDT 24
Finished Jun 25 05:29:23 PM PDT 24
Peak memory 199964 kb
Host smart-068c4786-1679-4081-b7b7-37d2563bbd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35754376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.35754376
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.2733309731
Short name T13
Test name
Test status
Simulation time 95802148 ps
CPU time 1.08 seconds
Started Jun 25 05:29:18 PM PDT 24
Finished Jun 25 05:29:21 PM PDT 24
Peak memory 199800 kb
Host smart-6e792efe-8f9b-4df1-9cf4-212263c9d923
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733309731 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_hmac_vectors.2733309731
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha256_vectors.3677994139
Short name T517
Test name
Test status
Simulation time 30874237054 ps
CPU time 553.13 seconds
Started Jun 25 05:29:17 PM PDT 24
Finished Jun 25 05:38:33 PM PDT 24
Peak memory 200056 kb
Host smart-63ea5386-a1ad-49c1-9c36-8f77ccc39541
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3677994139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha256_vectors.3677994139
Directory /workspace/18.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha384_vectors.4012595999
Short name T291
Test name
Test status
Simulation time 577207097430 ps
CPU time 1993.86 seconds
Started Jun 25 05:29:31 PM PDT 24
Finished Jun 25 06:02:47 PM PDT 24
Peak memory 214984 kb
Host smart-36f96961-f31c-4f01-b9dd-1a50f217775b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4012595999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha384_vectors.4012595999
Directory /workspace/18.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha512_vectors.2867482816
Short name T172
Test name
Test status
Simulation time 115132013577 ps
CPU time 1531.64 seconds
Started Jun 25 05:29:15 PM PDT 24
Finished Jun 25 05:54:50 PM PDT 24
Peak memory 215616 kb
Host smart-9c5a1e71-e12d-4c56-8e08-109dc972be09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2867482816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha512_vectors.2867482816
Directory /workspace/18.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2347501697
Short name T275
Test name
Test status
Simulation time 3289368289 ps
CPU time 46.37 seconds
Started Jun 25 05:29:26 PM PDT 24
Finished Jun 25 05:30:14 PM PDT 24
Peak memory 200092 kb
Host smart-07af304b-7c6d-4db2-98af-1448b0a860a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347501697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2347501697
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3159762524
Short name T543
Test name
Test status
Simulation time 13899985 ps
CPU time 0.63 seconds
Started Jun 25 05:29:28 PM PDT 24
Finished Jun 25 05:29:30 PM PDT 24
Peak memory 196120 kb
Host smart-95eb49bf-a2be-430c-8896-408a43b33a65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159762524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3159762524
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.1131325554
Short name T562
Test name
Test status
Simulation time 1190208031 ps
CPU time 16.27 seconds
Started Jun 25 05:29:25 PM PDT 24
Finished Jun 25 05:29:42 PM PDT 24
Peak memory 200052 kb
Host smart-796050e4-6634-4c45-91a2-bdf2d1cff2e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1131325554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1131325554
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.206930848
Short name T124
Test name
Test status
Simulation time 25209464012 ps
CPU time 88.25 seconds
Started Jun 25 05:29:26 PM PDT 24
Finished Jun 25 05:30:55 PM PDT 24
Peak memory 200120 kb
Host smart-27844a95-1b4f-47cb-9541-26296581aef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206930848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.206930848
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_error.908494336
Short name T135
Test name
Test status
Simulation time 64095009112 ps
CPU time 189.69 seconds
Started Jun 25 05:29:29 PM PDT 24
Finished Jun 25 05:32:40 PM PDT 24
Peak memory 200084 kb
Host smart-da49871b-61b7-4803-b358-6dd50ebef02f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908494336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.908494336
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2916469287
Short name T260
Test name
Test status
Simulation time 375477636 ps
CPU time 20.77 seconds
Started Jun 25 05:29:28 PM PDT 24
Finished Jun 25 05:29:50 PM PDT 24
Peak memory 200036 kb
Host smart-974ef1c5-34ab-4d78-84e3-dca50445264e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916469287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2916469287
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.3008868812
Short name T156
Test name
Test status
Simulation time 3554771955 ps
CPU time 17.52 seconds
Started Jun 25 05:29:17 PM PDT 24
Finished Jun 25 05:29:38 PM PDT 24
Peak memory 200112 kb
Host smart-571eef10-eaa0-415b-87f1-16b4d6c56c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008868812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3008868812
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.3605719471
Short name T281
Test name
Test status
Simulation time 260281164 ps
CPU time 1.39 seconds
Started Jun 25 05:29:16 PM PDT 24
Finished Jun 25 05:29:21 PM PDT 24
Peak memory 200100 kb
Host smart-041d3847-0490-40ec-88e4-1d4cfdaa0b1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605719471 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_hmac_vectors.3605719471
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha256_vectors.3993198353
Short name T357
Test name
Test status
Simulation time 100442385219 ps
CPU time 474.09 seconds
Started Jun 25 05:29:20 PM PDT 24
Finished Jun 25 05:37:16 PM PDT 24
Peak memory 200060 kb
Host smart-87572a3b-4fb6-414a-bc1e-acb5a08f1ea2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3993198353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha256_vectors.3993198353
Directory /workspace/19.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha384_vectors.648831882
Short name T518
Test name
Test status
Simulation time 30258740738 ps
CPU time 1693.93 seconds
Started Jun 25 05:29:30 PM PDT 24
Finished Jun 25 05:57:46 PM PDT 24
Peak memory 216108 kb
Host smart-86a58360-9eb0-4c60-86db-5ebb81e06970
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=648831882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha384_vectors.648831882
Directory /workspace/19.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha512_vectors.1573589828
Short name T378
Test name
Test status
Simulation time 191307024901 ps
CPU time 1734.66 seconds
Started Jun 25 05:29:26 PM PDT 24
Finished Jun 25 05:58:22 PM PDT 24
Peak memory 215488 kb
Host smart-2c3a6b13-0370-406c-af9a-33d0b821504d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1573589828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha512_vectors.1573589828
Directory /workspace/19.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.136778145
Short name T201
Test name
Test status
Simulation time 1609765979 ps
CPU time 14.11 seconds
Started Jun 25 05:29:17 PM PDT 24
Finished Jun 25 05:29:34 PM PDT 24
Peak memory 200020 kb
Host smart-d002312e-4731-4d9c-892c-cee5db95459a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136778145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.136778145
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1703545768
Short name T159
Test name
Test status
Simulation time 12172657 ps
CPU time 0.58 seconds
Started Jun 25 05:28:57 PM PDT 24
Finished Jun 25 05:29:00 PM PDT 24
Peak memory 196804 kb
Host smart-bc226c53-3844-409d-b472-ca4dfd04e55a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703545768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1703545768
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3947070374
Short name T7
Test name
Test status
Simulation time 1789758254 ps
CPU time 47.79 seconds
Started Jun 25 05:28:38 PM PDT 24
Finished Jun 25 05:29:28 PM PDT 24
Peak memory 200008 kb
Host smart-6b047849-a1e8-45d7-8061-ccbd27aa132c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3947070374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3947070374
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3113857727
Short name T604
Test name
Test status
Simulation time 18314859046 ps
CPU time 64.64 seconds
Started Jun 25 05:28:52 PM PDT 24
Finished Jun 25 05:29:57 PM PDT 24
Peak memory 200060 kb
Host smart-72d88825-0a0f-44f6-8209-9c4235a9bea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113857727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3113857727
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3215163262
Short name T367
Test name
Test status
Simulation time 24917654807 ps
CPU time 729.95 seconds
Started Jun 25 05:28:49 PM PDT 24
Finished Jun 25 05:41:00 PM PDT 24
Peak memory 746424 kb
Host smart-b046afd9-bbfb-4535-87f5-94ebc2afcf0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3215163262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3215163262
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.1718254801
Short name T581
Test name
Test status
Simulation time 145362177 ps
CPU time 3 seconds
Started Jun 25 05:29:02 PM PDT 24
Finished Jun 25 05:29:07 PM PDT 24
Peak memory 199908 kb
Host smart-24ee6799-05c7-4558-ab4a-ed64f5855ffb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718254801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1718254801
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2298661362
Short name T526
Test name
Test status
Simulation time 14894133917 ps
CPU time 72.01 seconds
Started Jun 25 05:28:55 PM PDT 24
Finished Jun 25 05:30:08 PM PDT 24
Peak memory 200116 kb
Host smart-427dd06d-c0a6-4fdb-b12a-289992b26017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298661362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2298661362
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.4262864283
Short name T43
Test name
Test status
Simulation time 138312225 ps
CPU time 0.86 seconds
Started Jun 25 05:29:00 PM PDT 24
Finished Jun 25 05:29:03 PM PDT 24
Peak memory 218132 kb
Host smart-a5bc872f-e3a7-420a-b0a3-4dce592b5b94
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262864283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.4262864283
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.680816961
Short name T527
Test name
Test status
Simulation time 97141992 ps
CPU time 1.74 seconds
Started Jun 25 05:28:40 PM PDT 24
Finished Jun 25 05:28:45 PM PDT 24
Peak memory 200104 kb
Host smart-ea0f68cc-9f88-499f-987d-a25b04abeb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680816961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.680816961
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.2083697331
Short name T10
Test name
Test status
Simulation time 29743928 ps
CPU time 1.13 seconds
Started Jun 25 05:28:47 PM PDT 24
Finished Jun 25 05:28:50 PM PDT 24
Peak memory 199904 kb
Host smart-65b14c66-ec0d-428e-b24a-c9d58b1cf634
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083697331 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac_vectors.2083697331
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.1964822809
Short name T331
Test name
Test status
Simulation time 23790584747 ps
CPU time 479.64 seconds
Started Jun 25 05:28:38 PM PDT 24
Finished Jun 25 05:36:41 PM PDT 24
Peak memory 200052 kb
Host smart-336fc5a4-f98e-43ba-991d-ae615bc7eff1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1964822809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.1964822809
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.3005835492
Short name T371
Test name
Test status
Simulation time 715806366513 ps
CPU time 2105.42 seconds
Started Jun 25 05:28:39 PM PDT 24
Finished Jun 25 06:03:48 PM PDT 24
Peak memory 215564 kb
Host smart-e1e6db36-7772-461c-82d3-bbc80cc78fcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3005835492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.3005835492
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.1013214805
Short name T462
Test name
Test status
Simulation time 325141607465 ps
CPU time 2067.23 seconds
Started Jun 25 05:28:39 PM PDT 24
Finished Jun 25 06:03:10 PM PDT 24
Peak memory 215916 kb
Host smart-6055c647-c008-42f0-9f5c-88fd9d77632f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1013214805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1013214805
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3530690460
Short name T341
Test name
Test status
Simulation time 1721565761 ps
CPU time 29.87 seconds
Started Jun 25 05:28:57 PM PDT 24
Finished Jun 25 05:29:28 PM PDT 24
Peak memory 199976 kb
Host smart-785d7c15-dcd3-489b-a318-d7d9108366cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530690460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3530690460
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1267696225
Short name T428
Test name
Test status
Simulation time 184535295 ps
CPU time 0.62 seconds
Started Jun 25 05:29:16 PM PDT 24
Finished Jun 25 05:29:20 PM PDT 24
Peak memory 196060 kb
Host smart-7cc056f2-2396-48d1-9fed-6a2ee2541093
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267696225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1267696225
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2986116389
Short name T422
Test name
Test status
Simulation time 10215936923 ps
CPU time 28.73 seconds
Started Jun 25 05:29:15 PM PDT 24
Finished Jun 25 05:29:46 PM PDT 24
Peak memory 200076 kb
Host smart-394871e3-b736-4cea-8955-bf1729eedbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986116389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2986116389
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3922085401
Short name T324
Test name
Test status
Simulation time 5591953735 ps
CPU time 264.66 seconds
Started Jun 25 05:29:30 PM PDT 24
Finished Jun 25 05:33:57 PM PDT 24
Peak memory 638360 kb
Host smart-7a61a39b-8dc5-4b99-b08d-bcf9051213a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3922085401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3922085401
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3090372438
Short name T134
Test name
Test status
Simulation time 39641101450 ps
CPU time 175.51 seconds
Started Jun 25 05:29:18 PM PDT 24
Finished Jun 25 05:32:16 PM PDT 24
Peak memory 200088 kb
Host smart-bc5580ee-f412-42ea-a3a9-504b8665b2e1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090372438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3090372438
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3707811737
Short name T542
Test name
Test status
Simulation time 4342670565 ps
CPU time 21.75 seconds
Started Jun 25 05:29:13 PM PDT 24
Finished Jun 25 05:29:37 PM PDT 24
Peak memory 200120 kb
Host smart-cef5e1fb-2bf4-451f-bf70-c1ed8eec269e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707811737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3707811737
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1698135955
Short name T510
Test name
Test status
Simulation time 2186313444 ps
CPU time 15.8 seconds
Started Jun 25 05:29:24 PM PDT 24
Finished Jun 25 05:29:41 PM PDT 24
Peak memory 200140 kb
Host smart-b97950a4-0f89-4d77-a3c2-92c35d886cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698135955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1698135955
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.3959973796
Short name T343
Test name
Test status
Simulation time 238447704 ps
CPU time 1.47 seconds
Started Jun 25 05:29:18 PM PDT 24
Finished Jun 25 05:29:22 PM PDT 24
Peak memory 199992 kb
Host smart-727b9e15-a4ee-43e5-9862-2ca525db79db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959973796 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_hmac_vectors.3959973796
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha256_vectors.2667897367
Short name T540
Test name
Test status
Simulation time 30965508132 ps
CPU time 390.79 seconds
Started Jun 25 05:29:16 PM PDT 24
Finished Jun 25 05:35:50 PM PDT 24
Peak memory 200096 kb
Host smart-ab505b73-8fc3-49dd-925e-2653a6218cad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2667897367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha256_vectors.2667897367
Directory /workspace/20.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha384_vectors.1437469394
Short name T401
Test name
Test status
Simulation time 32471841682 ps
CPU time 1829.33 seconds
Started Jun 25 05:29:27 PM PDT 24
Finished Jun 25 05:59:57 PM PDT 24
Peak memory 208272 kb
Host smart-c0a57289-7557-42bd-b387-18bb57d84f38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1437469394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha384_vectors.1437469394
Directory /workspace/20.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha512_vectors.1387009702
Short name T221
Test name
Test status
Simulation time 220653812560 ps
CPU time 1983.16 seconds
Started Jun 25 05:29:15 PM PDT 24
Finished Jun 25 06:02:21 PM PDT 24
Peak memory 215460 kb
Host smart-fae25c57-d851-4aef-991b-c89d14b6515a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1387009702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha512_vectors.1387009702
Directory /workspace/20.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2368682848
Short name T302
Test name
Test status
Simulation time 11431858915 ps
CPU time 44.29 seconds
Started Jun 25 05:29:25 PM PDT 24
Finished Jun 25 05:30:11 PM PDT 24
Peak memory 200144 kb
Host smart-6abe7deb-488f-4d17-bb66-426b9f05b0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368682848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2368682848
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2763725273
Short name T393
Test name
Test status
Simulation time 15267795 ps
CPU time 0.59 seconds
Started Jun 25 05:29:29 PM PDT 24
Finished Jun 25 05:29:32 PM PDT 24
Peak memory 195852 kb
Host smart-9ec7314d-0bb9-4a41-870c-cace26db75e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763725273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2763725273
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3209168133
Short name T541
Test name
Test status
Simulation time 1208421356 ps
CPU time 15.04 seconds
Started Jun 25 05:29:08 PM PDT 24
Finished Jun 25 05:29:24 PM PDT 24
Peak memory 199996 kb
Host smart-880c92fd-37ed-4b79-a9f9-93d5c4318e07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3209168133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3209168133
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3317005245
Short name T559
Test name
Test status
Simulation time 1684788275 ps
CPU time 12.37 seconds
Started Jun 25 05:29:20 PM PDT 24
Finished Jun 25 05:29:34 PM PDT 24
Peak memory 200028 kb
Host smart-c65295e0-e5d5-43b4-adec-2b4834d41c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317005245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3317005245
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1474840761
Short name T477
Test name
Test status
Simulation time 3849316779 ps
CPU time 69.27 seconds
Started Jun 25 05:29:22 PM PDT 24
Finished Jun 25 05:30:32 PM PDT 24
Peak memory 354252 kb
Host smart-6e97dc21-b98a-4202-9ce1-561781ef5412
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1474840761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1474840761
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2114650661
Short name T554
Test name
Test status
Simulation time 36908032 ps
CPU time 2.18 seconds
Started Jun 25 05:29:29 PM PDT 24
Finished Jun 25 05:29:34 PM PDT 24
Peak memory 199892 kb
Host smart-ae60854e-c305-413f-8325-e6742af9f9e5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114650661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2114650661
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.126755472
Short name T488
Test name
Test status
Simulation time 3826665591 ps
CPU time 77.21 seconds
Started Jun 25 05:29:16 PM PDT 24
Finished Jun 25 05:30:36 PM PDT 24
Peak memory 200476 kb
Host smart-17fa446b-627c-4c79-9efa-a1d1a6ba4c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126755472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.126755472
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3955048414
Short name T412
Test name
Test status
Simulation time 875641448 ps
CPU time 8.32 seconds
Started Jun 25 05:29:14 PM PDT 24
Finished Jun 25 05:29:25 PM PDT 24
Peak memory 200068 kb
Host smart-0ea69e32-f36a-4a6c-8b8c-f584bb81f752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955048414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3955048414
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.3315008247
Short name T56
Test name
Test status
Simulation time 103258970 ps
CPU time 1.4 seconds
Started Jun 25 05:29:14 PM PDT 24
Finished Jun 25 05:29:18 PM PDT 24
Peak memory 199988 kb
Host smart-51752425-5e6a-4872-af26-4d27ada990c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315008247 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_hmac_vectors.3315008247
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha256_vectors.227132643
Short name T306
Test name
Test status
Simulation time 370151045965 ps
CPU time 508.41 seconds
Started Jun 25 05:29:15 PM PDT 24
Finished Jun 25 05:37:46 PM PDT 24
Peak memory 200036 kb
Host smart-d71c0224-0b27-43ec-9e24-dd395fbf5380
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=227132643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha256_vectors.227132643
Directory /workspace/21.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha384_vectors.2752326262
Short name T471
Test name
Test status
Simulation time 152518802820 ps
CPU time 1867.39 seconds
Started Jun 25 05:29:18 PM PDT 24
Finished Jun 25 06:00:28 PM PDT 24
Peak memory 216400 kb
Host smart-40c8e7bd-94b0-4b28-86c2-93e5e2bfbcc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2752326262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha384_vectors.2752326262
Directory /workspace/21.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha512_vectors.629730195
Short name T197
Test name
Test status
Simulation time 114324735409 ps
CPU time 1893.98 seconds
Started Jun 25 05:29:25 PM PDT 24
Finished Jun 25 06:01:01 PM PDT 24
Peak memory 216228 kb
Host smart-bcabb76a-f868-4c1c-b38e-6bd5a6613f28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=629730195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha512_vectors.629730195
Directory /workspace/21.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.3472644219
Short name T309
Test name
Test status
Simulation time 4484168998 ps
CPU time 21.01 seconds
Started Jun 25 05:29:14 PM PDT 24
Finished Jun 25 05:29:37 PM PDT 24
Peak memory 200148 kb
Host smart-7af4bac9-8f29-4bd4-8ed0-625eb9cdf0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472644219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3472644219
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3976305904
Short name T329
Test name
Test status
Simulation time 13559515 ps
CPU time 0.58 seconds
Started Jun 25 05:29:24 PM PDT 24
Finished Jun 25 05:29:25 PM PDT 24
Peak memory 195820 kb
Host smart-fbe3067c-ccce-4971-81af-e2006b95fefc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976305904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3976305904
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3290464404
Short name T648
Test name
Test status
Simulation time 4964410470 ps
CPU time 58.14 seconds
Started Jun 25 05:29:28 PM PDT 24
Finished Jun 25 05:30:27 PM PDT 24
Peak memory 200100 kb
Host smart-43208623-1156-4c35-8fb0-2979b9fe85ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3290464404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3290464404
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2731885890
Short name T53
Test name
Test status
Simulation time 236062078 ps
CPU time 13.47 seconds
Started Jun 25 05:29:38 PM PDT 24
Finished Jun 25 05:29:53 PM PDT 24
Peak memory 200040 kb
Host smart-9802b9e4-92c8-4e1a-9a16-fef4c1f88f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731885890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2731885890
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3568492911
Short name T166
Test name
Test status
Simulation time 12919964977 ps
CPU time 1172.96 seconds
Started Jun 25 05:29:36 PM PDT 24
Finished Jun 25 05:49:11 PM PDT 24
Peak memory 738148 kb
Host smart-65447bbd-e67a-46f3-8fa6-a7c911a1f623
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3568492911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3568492911
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.1682271099
Short name T353
Test name
Test status
Simulation time 6933461554 ps
CPU time 87.33 seconds
Started Jun 25 05:29:29 PM PDT 24
Finished Jun 25 05:30:58 PM PDT 24
Peak memory 200080 kb
Host smart-d688b0d0-987f-4307-a6e3-5c1ef1fb03a9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682271099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1682271099
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1525911473
Short name T595
Test name
Test status
Simulation time 6070057920 ps
CPU time 90.61 seconds
Started Jun 25 05:29:29 PM PDT 24
Finished Jun 25 05:31:02 PM PDT 24
Peak memory 200072 kb
Host smart-5ad82347-69fd-46a2-aaa6-25f0815bf920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525911473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1525911473
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1389046447
Short name T79
Test name
Test status
Simulation time 276813005 ps
CPU time 5.84 seconds
Started Jun 25 05:29:21 PM PDT 24
Finished Jun 25 05:29:28 PM PDT 24
Peak memory 200028 kb
Host smart-6420a807-2ab6-479f-a199-43a59434fc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389046447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1389046447
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.3306983369
Short name T254
Test name
Test status
Simulation time 63456265 ps
CPU time 1.37 seconds
Started Jun 25 05:29:25 PM PDT 24
Finished Jun 25 05:29:28 PM PDT 24
Peak memory 200008 kb
Host smart-b8c4c4df-299e-4333-879c-593c623cd34d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306983369 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_hmac_vectors.3306983369
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha256_vectors.1295025698
Short name T395
Test name
Test status
Simulation time 143557156960 ps
CPU time 531.36 seconds
Started Jun 25 05:29:15 PM PDT 24
Finished Jun 25 05:38:10 PM PDT 24
Peak memory 200032 kb
Host smart-696dad7f-c11d-4edb-b035-bb3166730aa9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1295025698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha256_vectors.1295025698
Directory /workspace/22.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha384_vectors.427163903
Short name T168
Test name
Test status
Simulation time 308424909613 ps
CPU time 1999.95 seconds
Started Jun 25 05:29:29 PM PDT 24
Finished Jun 25 06:02:51 PM PDT 24
Peak memory 216464 kb
Host smart-ea6cbb2e-175d-45d1-8938-f28ec46b3cbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=427163903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha384_vectors.427163903
Directory /workspace/22.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha512_vectors.3422792933
Short name T248
Test name
Test status
Simulation time 65116223898 ps
CPU time 1819.79 seconds
Started Jun 25 05:29:16 PM PDT 24
Finished Jun 25 05:59:40 PM PDT 24
Peak memory 215656 kb
Host smart-59166df3-3b93-45a3-ba4e-8ca5c49ec0e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3422792933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha512_vectors.3422792933
Directory /workspace/22.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1281806846
Short name T629
Test name
Test status
Simulation time 6021269738 ps
CPU time 24.64 seconds
Started Jun 25 05:29:25 PM PDT 24
Finished Jun 25 05:29:51 PM PDT 24
Peak memory 200116 kb
Host smart-7e8355e0-35e7-46c0-a458-6b1305ec2fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281806846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1281806846
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1299147534
Short name T296
Test name
Test status
Simulation time 36445804 ps
CPU time 0.57 seconds
Started Jun 25 05:29:14 PM PDT 24
Finished Jun 25 05:29:18 PM PDT 24
Peak memory 196104 kb
Host smart-49007655-1edc-4e66-8b0b-3a0e18f3c15c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299147534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1299147534
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2783915426
Short name T241
Test name
Test status
Simulation time 654517351 ps
CPU time 29.39 seconds
Started Jun 25 05:29:30 PM PDT 24
Finished Jun 25 05:30:02 PM PDT 24
Peak memory 200032 kb
Host smart-db63934c-ed65-407e-8158-f48722680551
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2783915426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2783915426
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2374156942
Short name T266
Test name
Test status
Simulation time 2462135708 ps
CPU time 44.5 seconds
Started Jun 25 05:29:32 PM PDT 24
Finished Jun 25 05:30:20 PM PDT 24
Peak memory 200172 kb
Host smart-2fed1136-ab7a-445d-82d3-06511a8bcd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374156942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2374156942
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2578280265
Short name T335
Test name
Test status
Simulation time 977161950 ps
CPU time 118.77 seconds
Started Jun 25 05:29:32 PM PDT 24
Finished Jun 25 05:31:34 PM PDT 24
Peak memory 485212 kb
Host smart-7c6e67a2-8bd7-43d1-b1ea-8ba7e9f4df7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2578280265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2578280265
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.204229915
Short name T433
Test name
Test status
Simulation time 46535130784 ps
CPU time 154.48 seconds
Started Jun 25 05:29:30 PM PDT 24
Finished Jun 25 05:32:06 PM PDT 24
Peak memory 200120 kb
Host smart-040f80d3-e079-445a-a55d-eebf001b5390
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204229915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.204229915
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3224434654
Short name T443
Test name
Test status
Simulation time 23112427552 ps
CPU time 82.28 seconds
Started Jun 25 05:29:16 PM PDT 24
Finished Jun 25 05:30:41 PM PDT 24
Peak memory 200120 kb
Host smart-5f4537f9-4f6c-4fc7-bd21-0d33e4964076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224434654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3224434654
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.788925540
Short name T180
Test name
Test status
Simulation time 324484346 ps
CPU time 6.21 seconds
Started Jun 25 05:29:16 PM PDT 24
Finished Jun 25 05:29:25 PM PDT 24
Peak memory 199912 kb
Host smart-efa66fb8-5a09-4867-bb4c-5319ed0e6319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788925540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.788925540
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.100203920
Short name T9
Test name
Test status
Simulation time 125028241 ps
CPU time 1.37 seconds
Started Jun 25 05:29:27 PM PDT 24
Finished Jun 25 05:29:30 PM PDT 24
Peak memory 199972 kb
Host smart-bd436506-6c9d-4bf6-9906-ad7b5fd5e91d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100203920 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_hmac_vectors.100203920
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha256_vectors.615923982
Short name T360
Test name
Test status
Simulation time 91882332617 ps
CPU time 585.53 seconds
Started Jun 25 05:29:20 PM PDT 24
Finished Jun 25 05:39:07 PM PDT 24
Peak memory 200032 kb
Host smart-4bf51944-40d3-4974-903a-604831d418f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=615923982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha256_vectors.615923982
Directory /workspace/23.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha384_vectors.1993365219
Short name T632
Test name
Test status
Simulation time 668900845428 ps
CPU time 2122.86 seconds
Started Jun 25 05:29:26 PM PDT 24
Finished Jun 25 06:04:50 PM PDT 24
Peak memory 215600 kb
Host smart-23f3cfb7-2029-4f36-b502-28724dabb584
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1993365219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha384_vectors.1993365219
Directory /workspace/23.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha512_vectors.3209193968
Short name T319
Test name
Test status
Simulation time 422980394736 ps
CPU time 1832.32 seconds
Started Jun 25 05:29:15 PM PDT 24
Finished Jun 25 05:59:51 PM PDT 24
Peak memory 214928 kb
Host smart-9aee9e15-5894-490b-a1be-6095b2c35936
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3209193968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha512_vectors.3209193968
Directory /workspace/23.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.335011235
Short name T576
Test name
Test status
Simulation time 5539327804 ps
CPU time 75.31 seconds
Started Jun 25 05:29:27 PM PDT 24
Finished Jun 25 05:30:43 PM PDT 24
Peak memory 200132 kb
Host smart-1bbb1c4d-4590-463f-846d-2f0575071395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335011235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.335011235
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3397385450
Short name T36
Test name
Test status
Simulation time 12078018 ps
CPU time 0.58 seconds
Started Jun 25 05:29:26 PM PDT 24
Finished Jun 25 05:29:28 PM PDT 24
Peak memory 195684 kb
Host smart-46a10aeb-bbd8-4f1a-b66e-65b207f479f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397385450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3397385450
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1863788519
Short name T23
Test name
Test status
Simulation time 1784632506 ps
CPU time 40.39 seconds
Started Jun 25 05:29:31 PM PDT 24
Finished Jun 25 05:30:14 PM PDT 24
Peak memory 200056 kb
Host smart-4518debb-4adf-4573-9ee6-2d92924b8653
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1863788519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1863788519
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1766805118
Short name T509
Test name
Test status
Simulation time 559861939 ps
CPU time 31.19 seconds
Started Jun 25 05:29:18 PM PDT 24
Finished Jun 25 05:29:52 PM PDT 24
Peak memory 200044 kb
Host smart-58954086-a1a6-4d3b-b5f3-236450d04044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766805118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1766805118
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1371379117
Short name T574
Test name
Test status
Simulation time 2026211011 ps
CPU time 527.62 seconds
Started Jun 25 05:29:33 PM PDT 24
Finished Jun 25 05:38:23 PM PDT 24
Peak memory 678400 kb
Host smart-1eefad28-fd3e-471b-ac68-278eae3e1f55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1371379117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1371379117
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.380660391
Short name T355
Test name
Test status
Simulation time 6494331171 ps
CPU time 82.32 seconds
Started Jun 25 05:29:15 PM PDT 24
Finished Jun 25 05:30:40 PM PDT 24
Peak memory 200068 kb
Host smart-fb2d2e84-1feb-49ce-a2f8-cfb855b70d2d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380660391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.380660391
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3590409963
Short name T300
Test name
Test status
Simulation time 8269938280 ps
CPU time 108.41 seconds
Started Jun 25 05:29:26 PM PDT 24
Finished Jun 25 05:31:16 PM PDT 24
Peak memory 200136 kb
Host smart-39ab10be-d8a1-4e46-b541-0d48ae2c7fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590409963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3590409963
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.4077586251
Short name T339
Test name
Test status
Simulation time 677236990 ps
CPU time 12.67 seconds
Started Jun 25 05:29:30 PM PDT 24
Finished Jun 25 05:29:45 PM PDT 24
Peak memory 200024 kb
Host smart-a80b0278-f9c7-422e-8eb6-edd6d9db277f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077586251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.4077586251
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3576629452
Short name T655
Test name
Test status
Simulation time 23095289039 ps
CPU time 119.1 seconds
Started Jun 25 05:29:31 PM PDT 24
Finished Jun 25 05:31:33 PM PDT 24
Peak memory 200156 kb
Host smart-78e201a5-ff35-494b-aade-eec48cad47d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576629452 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3576629452
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.3471663311
Short name T565
Test name
Test status
Simulation time 238718096 ps
CPU time 1.4 seconds
Started Jun 25 05:29:29 PM PDT 24
Finished Jun 25 05:29:31 PM PDT 24
Peak memory 200004 kb
Host smart-c1379926-3e80-4150-8179-c0ceaddfc2b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471663311 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_hmac_vectors.3471663311
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha256_vectors.3725456352
Short name T598
Test name
Test status
Simulation time 69552157228 ps
CPU time 444.36 seconds
Started Jun 25 05:29:29 PM PDT 24
Finished Jun 25 05:36:55 PM PDT 24
Peak memory 199996 kb
Host smart-1ae9e958-1114-4433-b6cc-510681cb9639
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3725456352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha256_vectors.3725456352
Directory /workspace/24.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha384_vectors.4062343033
Short name T382
Test name
Test status
Simulation time 718987424815 ps
CPU time 2273.32 seconds
Started Jun 25 05:29:29 PM PDT 24
Finished Jun 25 06:07:25 PM PDT 24
Peak memory 216004 kb
Host smart-14005ed5-063c-46de-b7df-da941ec987dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4062343033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha384_vectors.4062343033
Directory /workspace/24.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha512_vectors.767495935
Short name T170
Test name
Test status
Simulation time 438700396953 ps
CPU time 1961.16 seconds
Started Jun 25 05:29:18 PM PDT 24
Finished Jun 25 06:02:02 PM PDT 24
Peak memory 215504 kb
Host smart-3c604093-e509-44fe-a6fd-66f54915b908
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=767495935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha512_vectors.767495935
Directory /workspace/24.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1227174444
Short name T115
Test name
Test status
Simulation time 2368864284 ps
CPU time 22.45 seconds
Started Jun 25 05:29:37 PM PDT 24
Finished Jun 25 05:30:02 PM PDT 24
Peak memory 200340 kb
Host smart-3df6a3de-a2b1-4b78-8ab7-95e5086f0e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227174444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1227174444
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3704568680
Short name T312
Test name
Test status
Simulation time 164067907 ps
CPU time 0.56 seconds
Started Jun 25 05:29:25 PM PDT 24
Finished Jun 25 05:29:27 PM PDT 24
Peak memory 195104 kb
Host smart-965cd1b8-4120-464a-8b93-6ddedf2eea67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704568680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3704568680
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2288151605
Short name T24
Test name
Test status
Simulation time 339736260 ps
CPU time 16.4 seconds
Started Jun 25 05:29:21 PM PDT 24
Finished Jun 25 05:29:38 PM PDT 24
Peak memory 200028 kb
Host smart-790175d8-ae0c-4d35-9ef7-b4953dd2968d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2288151605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2288151605
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2343613645
Short name T316
Test name
Test status
Simulation time 14627030118 ps
CPU time 57.64 seconds
Started Jun 25 05:29:16 PM PDT 24
Finished Jun 25 05:30:17 PM PDT 24
Peak memory 200172 kb
Host smart-5a7e1c25-bf11-4a78-ad3d-43bfe6b8898e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343613645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2343613645
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3623199025
Short name T191
Test name
Test status
Simulation time 3492375934 ps
CPU time 889.06 seconds
Started Jun 25 05:29:30 PM PDT 24
Finished Jun 25 05:44:22 PM PDT 24
Peak memory 687292 kb
Host smart-6661ac35-0d6f-4ca9-b068-439232ec1d16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3623199025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3623199025
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.256521504
Short name T33
Test name
Test status
Simulation time 12029078336 ps
CPU time 214.74 seconds
Started Jun 25 05:29:30 PM PDT 24
Finished Jun 25 05:33:07 PM PDT 24
Peak memory 200120 kb
Host smart-30e95391-73e3-418d-891b-7b13ed6a4a15
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256521504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.256521504
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.4212876830
Short name T475
Test name
Test status
Simulation time 30062053918 ps
CPU time 145.78 seconds
Started Jun 25 05:29:31 PM PDT 24
Finished Jun 25 05:32:00 PM PDT 24
Peak memory 200172 kb
Host smart-c6603b27-e2a9-409c-ba2a-9726f58959d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212876830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.4212876830
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.828227743
Short name T276
Test name
Test status
Simulation time 363508133 ps
CPU time 6.88 seconds
Started Jun 25 05:29:31 PM PDT 24
Finished Jun 25 05:29:41 PM PDT 24
Peak memory 200040 kb
Host smart-fb308830-1877-4af3-a683-5af2fda7e951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828227743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.828227743
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.845860854
Short name T338
Test name
Test status
Simulation time 302256074 ps
CPU time 1.41 seconds
Started Jun 25 05:29:15 PM PDT 24
Finished Jun 25 05:29:19 PM PDT 24
Peak memory 199972 kb
Host smart-b9f1426f-930b-4d61-aff5-3974d1000045
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845860854 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_hmac_vectors.845860854
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha256_vectors.1534858566
Short name T366
Test name
Test status
Simulation time 143015171112 ps
CPU time 466.29 seconds
Started Jun 25 05:29:42 PM PDT 24
Finished Jun 25 05:37:29 PM PDT 24
Peak memory 199988 kb
Host smart-301139fd-3e94-456d-854e-1b71f063ce70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1534858566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha256_vectors.1534858566
Directory /workspace/25.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha384_vectors.1421209727
Short name T578
Test name
Test status
Simulation time 140879113211 ps
CPU time 1751.87 seconds
Started Jun 25 05:29:17 PM PDT 24
Finished Jun 25 05:58:32 PM PDT 24
Peak memory 216364 kb
Host smart-922cf475-bec8-4a71-ac21-eed8f6a08db7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1421209727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha384_vectors.1421209727
Directory /workspace/25.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha512_vectors.3824696185
Short name T476
Test name
Test status
Simulation time 658250141687 ps
CPU time 2002.68 seconds
Started Jun 25 05:29:21 PM PDT 24
Finished Jun 25 06:02:45 PM PDT 24
Peak memory 215824 kb
Host smart-58adf460-702e-4959-9f7b-5339fdc2518a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3824696185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha512_vectors.3824696185
Directory /workspace/25.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3783195995
Short name T286
Test name
Test status
Simulation time 805003933 ps
CPU time 26.28 seconds
Started Jun 25 05:29:22 PM PDT 24
Finished Jun 25 05:29:49 PM PDT 24
Peak memory 199992 kb
Host smart-d627b182-1401-4dc3-8c18-50a632ba76ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783195995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3783195995
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3774910395
Short name T199
Test name
Test status
Simulation time 12593929 ps
CPU time 0.6 seconds
Started Jun 25 05:29:37 PM PDT 24
Finished Jun 25 05:29:40 PM PDT 24
Peak memory 195452 kb
Host smart-89c90328-39b6-4ae1-9702-2ed19c0ff5e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774910395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3774910395
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3750204286
Short name T216
Test name
Test status
Simulation time 1864373638 ps
CPU time 24.42 seconds
Started Jun 25 05:29:30 PM PDT 24
Finished Jun 25 05:29:57 PM PDT 24
Peak memory 200016 kb
Host smart-559adcf4-556a-4735-b58e-c6ae2c59a04d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3750204286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3750204286
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1418026103
Short name T120
Test name
Test status
Simulation time 13514225857 ps
CPU time 65 seconds
Started Jun 25 05:29:30 PM PDT 24
Finished Jun 25 05:30:38 PM PDT 24
Peak memory 200152 kb
Host smart-ec65bfeb-cca5-44ee-8ca0-e9cf03a5fa67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418026103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1418026103
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1152600454
Short name T253
Test name
Test status
Simulation time 5189521131 ps
CPU time 1414.13 seconds
Started Jun 25 05:29:21 PM PDT 24
Finished Jun 25 05:52:57 PM PDT 24
Peak memory 761376 kb
Host smart-227a8e90-1f18-46ad-8fb5-4be191e1ca51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1152600454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1152600454
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3006848361
Short name T229
Test name
Test status
Simulation time 19865647349 ps
CPU time 100.77 seconds
Started Jun 25 05:29:33 PM PDT 24
Finished Jun 25 05:31:16 PM PDT 24
Peak memory 200092 kb
Host smart-379be16f-77d7-439b-9c23-d9883c8ee086
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006848361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3006848361
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.4073654900
Short name T451
Test name
Test status
Simulation time 2062705493 ps
CPU time 9.92 seconds
Started Jun 25 05:29:28 PM PDT 24
Finished Jun 25 05:29:40 PM PDT 24
Peak memory 200080 kb
Host smart-1a737b72-0e69-4bc2-aa8e-fbe87ed83ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073654900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.4073654900
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.1938680281
Short name T444
Test name
Test status
Simulation time 966784703 ps
CPU time 13.63 seconds
Started Jun 25 05:29:17 PM PDT 24
Finished Jun 25 05:29:33 PM PDT 24
Peak memory 200320 kb
Host smart-6e003f38-c4dd-41e5-8105-e387db858699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938680281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1938680281
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.1202225131
Short name T109
Test name
Test status
Simulation time 220506686 ps
CPU time 1.28 seconds
Started Jun 25 05:29:18 PM PDT 24
Finished Jun 25 05:29:22 PM PDT 24
Peak memory 199956 kb
Host smart-a6dc3f20-a879-45e2-99f4-4008a67b36a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202225131 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_hmac_vectors.1202225131
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha256_vectors.1189363284
Short name T539
Test name
Test status
Simulation time 8260450886 ps
CPU time 454.73 seconds
Started Jun 25 05:29:30 PM PDT 24
Finished Jun 25 05:37:06 PM PDT 24
Peak memory 200044 kb
Host smart-c91b52de-d734-448b-aa5f-d0cc86c2a07e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1189363284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha256_vectors.1189363284
Directory /workspace/26.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.4166583464
Short name T618
Test name
Test status
Simulation time 12825958682 ps
CPU time 52.98 seconds
Started Jun 25 05:29:29 PM PDT 24
Finished Jun 25 05:30:23 PM PDT 24
Peak memory 200164 kb
Host smart-7dcce5a7-4cfd-4008-b71d-66cd96c764bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166583464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.4166583464
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.102023750
Short name T467
Test name
Test status
Simulation time 11658112 ps
CPU time 0.6 seconds
Started Jun 25 05:29:25 PM PDT 24
Finished Jun 25 05:29:27 PM PDT 24
Peak memory 195828 kb
Host smart-9a913fd2-f176-444d-9126-d37a3e1abf6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102023750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.102023750
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2876062647
Short name T263
Test name
Test status
Simulation time 484110523 ps
CPU time 21.17 seconds
Started Jun 25 05:29:31 PM PDT 24
Finished Jun 25 05:29:56 PM PDT 24
Peak memory 200044 kb
Host smart-2f7bbaf5-22be-45ee-9958-b7a5e135e90c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2876062647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2876062647
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.36849457
Short name T436
Test name
Test status
Simulation time 405445509 ps
CPU time 23 seconds
Started Jun 25 05:29:46 PM PDT 24
Finished Jun 25 05:30:10 PM PDT 24
Peak memory 199972 kb
Host smart-8918af72-abc2-40c7-b560-9f0128189266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36849457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.36849457
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.229214679
Short name T78
Test name
Test status
Simulation time 10121520744 ps
CPU time 737.87 seconds
Started Jun 25 05:29:38 PM PDT 24
Finished Jun 25 05:41:58 PM PDT 24
Peak memory 728992 kb
Host smart-542d7f05-fef9-459a-936f-b9e390cc1d70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=229214679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.229214679
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.4208649064
Short name T77
Test name
Test status
Simulation time 432066234 ps
CPU time 5.59 seconds
Started Jun 25 05:29:39 PM PDT 24
Finished Jun 25 05:29:46 PM PDT 24
Peak memory 199936 kb
Host smart-a2b2d828-c040-46c1-9e23-f129a420f64e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208649064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.4208649064
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.4271721441
Short name T373
Test name
Test status
Simulation time 4893719180 ps
CPU time 92.74 seconds
Started Jun 25 05:29:31 PM PDT 24
Finished Jun 25 05:31:06 PM PDT 24
Peak memory 216472 kb
Host smart-4593fbbd-4f51-48f9-bbf9-d79c40a0ad71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271721441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.4271721441
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2081070993
Short name T472
Test name
Test status
Simulation time 310767149 ps
CPU time 3.06 seconds
Started Jun 25 05:29:35 PM PDT 24
Finished Jun 25 05:29:40 PM PDT 24
Peak memory 200040 kb
Host smart-6509ffa4-3511-481b-bc4d-a4e167abf523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081070993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2081070993
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.1414493072
Short name T211
Test name
Test status
Simulation time 29255202 ps
CPU time 1.12 seconds
Started Jun 25 05:29:38 PM PDT 24
Finished Jun 25 05:29:41 PM PDT 24
Peak memory 199928 kb
Host smart-e9835f26-bbd4-4c48-8a46-1a70ba6363fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414493072 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_hmac_vectors.1414493072
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha256_vectors.4237617805
Short name T251
Test name
Test status
Simulation time 7505359213 ps
CPU time 415.45 seconds
Started Jun 25 05:29:43 PM PDT 24
Finished Jun 25 05:36:40 PM PDT 24
Peak memory 199984 kb
Host smart-63f63b1e-d058-4103-b245-85280686ac71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4237617805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha256_vectors.4237617805
Directory /workspace/27.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha384_vectors.2946059993
Short name T174
Test name
Test status
Simulation time 32172603418 ps
CPU time 1738.3 seconds
Started Jun 25 05:29:36 PM PDT 24
Finished Jun 25 05:58:36 PM PDT 24
Peak memory 215432 kb
Host smart-4528dfb5-6409-4f8c-8438-5da9c26a027f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2946059993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha384_vectors.2946059993
Directory /workspace/27.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha512_vectors.1464014321
Short name T622
Test name
Test status
Simulation time 61238335750 ps
CPU time 1608.73 seconds
Started Jun 25 05:29:23 PM PDT 24
Finished Jun 25 05:56:13 PM PDT 24
Peak memory 216308 kb
Host smart-32e96e59-bf1d-4d55-aadd-b40e5672b28f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1464014321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha512_vectors.1464014321
Directory /workspace/27.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.451440313
Short name T464
Test name
Test status
Simulation time 1059781802 ps
CPU time 53.5 seconds
Started Jun 25 05:29:43 PM PDT 24
Finished Jun 25 05:30:38 PM PDT 24
Peak memory 199996 kb
Host smart-529d9257-97a1-406a-ae1e-d79bb57ae98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451440313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.451440313
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.3059893153
Short name T270
Test name
Test status
Simulation time 53037145 ps
CPU time 0.6 seconds
Started Jun 25 05:29:40 PM PDT 24
Finished Jun 25 05:29:42 PM PDT 24
Peak memory 196108 kb
Host smart-b04ff2ce-5fb6-4fbc-9728-dcd655628a1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059893153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3059893153
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.204182404
Short name T25
Test name
Test status
Simulation time 1009268821 ps
CPU time 46.73 seconds
Started Jun 25 05:29:34 PM PDT 24
Finished Jun 25 05:30:23 PM PDT 24
Peak memory 199992 kb
Host smart-57e99560-bf4c-448a-a5b7-aacd526a108f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=204182404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.204182404
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3180749508
Short name T119
Test name
Test status
Simulation time 28435388832 ps
CPU time 64.31 seconds
Started Jun 25 05:29:33 PM PDT 24
Finished Jun 25 05:30:40 PM PDT 24
Peak memory 200140 kb
Host smart-437dd2b8-6b2d-4f19-b4e9-fbc70cf42451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180749508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3180749508
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.651812960
Short name T117
Test name
Test status
Simulation time 3473396258 ps
CPU time 943.43 seconds
Started Jun 25 05:29:32 PM PDT 24
Finished Jun 25 05:45:18 PM PDT 24
Peak memory 744792 kb
Host smart-55dced81-fe90-49c6-a5d4-0c4174a15cc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=651812960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.651812960
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3197694572
Short name T377
Test name
Test status
Simulation time 1425656788 ps
CPU time 82.8 seconds
Started Jun 25 05:29:30 PM PDT 24
Finished Jun 25 05:30:55 PM PDT 24
Peak memory 200024 kb
Host smart-3b0cb3ed-40f7-4870-a452-904c6ae5c35e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197694572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3197694572
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2937261187
Short name T505
Test name
Test status
Simulation time 11230003799 ps
CPU time 71.59 seconds
Started Jun 25 05:29:38 PM PDT 24
Finished Jun 25 05:30:51 PM PDT 24
Peak memory 200028 kb
Host smart-96359431-079a-4c0e-b91b-141bf4cf8acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937261187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2937261187
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1441426707
Short name T421
Test name
Test status
Simulation time 105659358 ps
CPU time 2.12 seconds
Started Jun 25 05:29:31 PM PDT 24
Finished Jun 25 05:29:35 PM PDT 24
Peak memory 200072 kb
Host smart-028f8022-98c9-4930-a50b-6ad1c009f2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441426707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1441426707
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.121660460
Short name T235
Test name
Test status
Simulation time 44497338 ps
CPU time 1.07 seconds
Started Jun 25 05:29:44 PM PDT 24
Finished Jun 25 05:29:47 PM PDT 24
Peak memory 199944 kb
Host smart-34b82767-c4b0-43be-b288-37470c000b1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121660460 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_hmac_vectors.121660460
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha256_vectors.3888361148
Short name T368
Test name
Test status
Simulation time 36620032256 ps
CPU time 525.64 seconds
Started Jun 25 05:29:34 PM PDT 24
Finished Jun 25 05:38:22 PM PDT 24
Peak memory 200060 kb
Host smart-4b08b330-bba0-44ab-bc1d-d2536406c188
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3888361148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha256_vectors.3888361148
Directory /workspace/28.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha384_vectors.2709442252
Short name T308
Test name
Test status
Simulation time 71244421441 ps
CPU time 1707.04 seconds
Started Jun 25 05:29:38 PM PDT 24
Finished Jun 25 05:58:07 PM PDT 24
Peak memory 216052 kb
Host smart-136c914a-8c44-4cd6-9310-268f21299f57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2709442252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha384_vectors.2709442252
Directory /workspace/28.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha512_vectors.2815095265
Short name T334
Test name
Test status
Simulation time 110849927199 ps
CPU time 1902.72 seconds
Started Jun 25 05:29:43 PM PDT 24
Finished Jun 25 06:01:27 PM PDT 24
Peak memory 216060 kb
Host smart-924989c3-028f-4695-8e47-f1b6b6bca20b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2815095265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha512_vectors.2815095265
Directory /workspace/28.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3220985291
Short name T379
Test name
Test status
Simulation time 12041587926 ps
CPU time 87.69 seconds
Started Jun 25 05:29:37 PM PDT 24
Finished Jun 25 05:31:06 PM PDT 24
Peak memory 199872 kb
Host smart-43fddbf0-50ed-4d79-8ec8-a3b3055e71e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220985291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3220985291
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1125112626
Short name T431
Test name
Test status
Simulation time 110142122 ps
CPU time 0.63 seconds
Started Jun 25 05:29:44 PM PDT 24
Finished Jun 25 05:29:46 PM PDT 24
Peak memory 196120 kb
Host smart-ea594ed4-f566-467f-a7e2-593019cf3b5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125112626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1125112626
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.297794548
Short name T400
Test name
Test status
Simulation time 7948006497 ps
CPU time 50.83 seconds
Started Jun 25 05:29:31 PM PDT 24
Finished Jun 25 05:30:24 PM PDT 24
Peak memory 215552 kb
Host smart-41ead1fb-9879-4352-a145-b9d24590200f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=297794548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.297794548
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2163570579
Short name T151
Test name
Test status
Simulation time 1951925857 ps
CPU time 27.48 seconds
Started Jun 25 05:29:29 PM PDT 24
Finished Jun 25 05:29:58 PM PDT 24
Peak memory 200048 kb
Host smart-87242e41-feb2-4958-8275-8c05978109ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163570579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2163570579
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.616845351
Short name T215
Test name
Test status
Simulation time 3109891863 ps
CPU time 848.41 seconds
Started Jun 25 05:29:40 PM PDT 24
Finished Jun 25 05:43:50 PM PDT 24
Peak memory 744220 kb
Host smart-8e12ae95-0b5c-4f2d-80c8-1e344e875009
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=616845351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.616845351
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1436078187
Short name T571
Test name
Test status
Simulation time 14070670449 ps
CPU time 163.85 seconds
Started Jun 25 05:29:31 PM PDT 24
Finished Jun 25 05:32:17 PM PDT 24
Peak memory 208320 kb
Host smart-eaca500a-047c-4172-bd12-5af21272bf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436078187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1436078187
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2814041491
Short name T450
Test name
Test status
Simulation time 921407807 ps
CPU time 5.37 seconds
Started Jun 25 05:29:45 PM PDT 24
Finished Jun 25 05:29:52 PM PDT 24
Peak memory 200048 kb
Host smart-ec6ca041-2fa9-419e-9c88-401a55c6ac2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814041491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2814041491
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.1915785293
Short name T636
Test name
Test status
Simulation time 193762049 ps
CPU time 1.25 seconds
Started Jun 25 05:29:27 PM PDT 24
Finished Jun 25 05:29:29 PM PDT 24
Peak memory 199952 kb
Host smart-819f62cf-5f4b-45d2-94e1-49b97409f6db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915785293 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_hmac_vectors.1915785293
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha256_vectors.1458532258
Short name T646
Test name
Test status
Simulation time 38246989913 ps
CPU time 463.88 seconds
Started Jun 25 05:29:34 PM PDT 24
Finished Jun 25 05:37:21 PM PDT 24
Peak memory 199984 kb
Host smart-5b4a5513-47e2-431f-87c4-3c2a4f5bd956
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1458532258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha256_vectors.1458532258
Directory /workspace/29.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha384_vectors.2934045238
Short name T165
Test name
Test status
Simulation time 209038784949 ps
CPU time 2267.74 seconds
Started Jun 25 05:29:34 PM PDT 24
Finished Jun 25 06:07:24 PM PDT 24
Peak memory 215440 kb
Host smart-15b963d2-585e-47af-9cdb-651ea3b7821f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2934045238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha384_vectors.2934045238
Directory /workspace/29.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha512_vectors.1211010417
Short name T218
Test name
Test status
Simulation time 224055215511 ps
CPU time 2040.26 seconds
Started Jun 25 05:29:37 PM PDT 24
Finished Jun 25 06:03:39 PM PDT 24
Peak memory 215264 kb
Host smart-e59c73f1-1d8d-4b7f-b12f-f1ad6c863238
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1211010417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha512_vectors.1211010417
Directory /workspace/29.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1331032901
Short name T112
Test name
Test status
Simulation time 6245209247 ps
CPU time 67.35 seconds
Started Jun 25 05:29:31 PM PDT 24
Finished Jun 25 05:30:41 PM PDT 24
Peak memory 200080 kb
Host smart-436b4718-1aa6-491c-80f5-fe4c61dbe904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331032901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1331032901
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.768429067
Short name T414
Test name
Test status
Simulation time 72175565 ps
CPU time 0.59 seconds
Started Jun 25 05:28:39 PM PDT 24
Finished Jun 25 05:28:42 PM PDT 24
Peak memory 196116 kb
Host smart-fa5856b2-0fef-482c-b3a2-bfc52538cd75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768429067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.768429067
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.1022055546
Short name T407
Test name
Test status
Simulation time 115407506 ps
CPU time 3.87 seconds
Started Jun 25 05:28:54 PM PDT 24
Finished Jun 25 05:28:59 PM PDT 24
Peak memory 200004 kb
Host smart-7b2dec54-b2b0-48cc-be7e-c24a6d38b4b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1022055546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1022055546
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3108710960
Short name T30
Test name
Test status
Simulation time 11720562101 ps
CPU time 45.89 seconds
Started Jun 25 05:28:45 PM PDT 24
Finished Jun 25 05:29:33 PM PDT 24
Peak memory 200208 kb
Host smart-9f9380f9-8970-4b37-965a-4cc36261a247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108710960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3108710960
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2686821484
Short name T591
Test name
Test status
Simulation time 4960923245 ps
CPU time 1757.97 seconds
Started Jun 25 05:28:39 PM PDT 24
Finished Jun 25 05:58:00 PM PDT 24
Peak memory 771664 kb
Host smart-cd5f8e56-1fd5-4973-bf0d-10dfaa163a5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2686821484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2686821484
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1836006999
Short name T458
Test name
Test status
Simulation time 6421140942 ps
CPU time 189.68 seconds
Started Jun 25 05:28:36 PM PDT 24
Finished Jun 25 05:31:47 PM PDT 24
Peak memory 200104 kb
Host smart-5066ee4a-e1d0-4af4-920e-28062226d393
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836006999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1836006999
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3316575754
Short name T449
Test name
Test status
Simulation time 3306649991 ps
CPU time 105.64 seconds
Started Jun 25 05:28:56 PM PDT 24
Finished Jun 25 05:30:42 PM PDT 24
Peak memory 200040 kb
Host smart-96f7ba1b-2e3d-42bd-ac37-714afe228ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316575754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3316575754
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1094160768
Short name T45
Test name
Test status
Simulation time 161868698 ps
CPU time 0.99 seconds
Started Jun 25 05:28:46 PM PDT 24
Finished Jun 25 05:28:48 PM PDT 24
Peak memory 219276 kb
Host smart-24356c10-4202-4f2e-b6e5-1e8abda55f76
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094160768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1094160768
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.2646319544
Short name T333
Test name
Test status
Simulation time 82559093 ps
CPU time 3.4 seconds
Started Jun 25 05:28:52 PM PDT 24
Finished Jun 25 05:28:56 PM PDT 24
Peak memory 200044 kb
Host smart-52d55c44-fb17-41d1-8379-5cea91df15c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646319544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2646319544
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.808274615
Short name T573
Test name
Test status
Simulation time 3445766824 ps
CPU time 57.33 seconds
Started Jun 25 05:28:40 PM PDT 24
Finished Jun 25 05:29:40 PM PDT 24
Peak memory 200136 kb
Host smart-d0aad49e-1787-40a0-8a52-c666a36df9d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808274615 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.808274615
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.671157255
Short name T521
Test name
Test status
Simulation time 108707302 ps
CPU time 1.27 seconds
Started Jun 25 05:28:57 PM PDT 24
Finished Jun 25 05:29:00 PM PDT 24
Peak memory 199972 kb
Host smart-10325c7d-32c6-4495-a261-67f1d9e205d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671157255 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac_vectors.671157255
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.265535555
Short name T455
Test name
Test status
Simulation time 193061144395 ps
CPU time 555.18 seconds
Started Jun 25 05:28:44 PM PDT 24
Finished Jun 25 05:38:02 PM PDT 24
Peak memory 200036 kb
Host smart-6278b664-eb3c-40a1-9315-92a097e7fb75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=265535555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.265535555
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.3785864329
Short name T452
Test name
Test status
Simulation time 727706763983 ps
CPU time 1860.95 seconds
Started Jun 25 05:28:54 PM PDT 24
Finished Jun 25 05:59:56 PM PDT 24
Peak memory 216404 kb
Host smart-141feca1-8c2a-4e0e-aec2-b026a52b98bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3785864329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.3785864329
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.802219337
Short name T637
Test name
Test status
Simulation time 146195125272 ps
CPU time 1998.03 seconds
Started Jun 25 05:28:41 PM PDT 24
Finished Jun 25 06:02:02 PM PDT 24
Peak memory 216076 kb
Host smart-c4974190-752f-4820-a5e0-0638d9d071b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=802219337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.802219337
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.786758588
Short name T222
Test name
Test status
Simulation time 1142466599 ps
CPU time 12.6 seconds
Started Jun 25 05:29:04 PM PDT 24
Finished Jun 25 05:29:18 PM PDT 24
Peak memory 199992 kb
Host smart-981ef64f-cbf5-4b92-bd1f-8d3ece81779b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786758588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.786758588
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2943426509
Short name T486
Test name
Test status
Simulation time 14359476 ps
CPU time 0.61 seconds
Started Jun 25 05:29:45 PM PDT 24
Finished Jun 25 05:29:47 PM PDT 24
Peak memory 196108 kb
Host smart-214ca4dc-75af-4fac-9798-de0b92b4a479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943426509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2943426509
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.3907323189
Short name T662
Test name
Test status
Simulation time 1490655981 ps
CPU time 14.34 seconds
Started Jun 25 05:29:41 PM PDT 24
Finished Jun 25 05:29:56 PM PDT 24
Peak memory 199888 kb
Host smart-2dac69bd-529e-498b-962f-9da1b86b09ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3907323189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3907323189
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.2949020835
Short name T447
Test name
Test status
Simulation time 2465848725 ps
CPU time 33.68 seconds
Started Jun 25 05:29:32 PM PDT 24
Finished Jun 25 05:30:08 PM PDT 24
Peak memory 200148 kb
Host smart-c8b41f34-08cd-4dd6-8a51-72ca8e7ace7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949020835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2949020835
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1998450395
Short name T508
Test name
Test status
Simulation time 26014760862 ps
CPU time 866.07 seconds
Started Jun 25 05:29:37 PM PDT 24
Finished Jun 25 05:44:06 PM PDT 24
Peak memory 714904 kb
Host smart-fc1ae940-5b2b-4668-ab42-da241300f1d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1998450395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1998450395
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3609274702
Short name T176
Test name
Test status
Simulation time 39343394506 ps
CPU time 124.14 seconds
Started Jun 25 05:29:37 PM PDT 24
Finished Jun 25 05:31:43 PM PDT 24
Peak memory 200072 kb
Host smart-e3b9583d-3222-4eac-980f-911702c7ee43
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609274702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3609274702
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3083961978
Short name T587
Test name
Test status
Simulation time 434892587 ps
CPU time 25.58 seconds
Started Jun 25 05:29:37 PM PDT 24
Finished Jun 25 05:30:05 PM PDT 24
Peak memory 199936 kb
Host smart-9bd5e55a-135e-4d6f-9bdc-891a5800be19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083961978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3083961978
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.133838417
Short name T318
Test name
Test status
Simulation time 115164463 ps
CPU time 5.68 seconds
Started Jun 25 05:29:30 PM PDT 24
Finished Jun 25 05:29:38 PM PDT 24
Peak memory 200012 kb
Host smart-934a0421-238e-4d60-a1b9-5ec8e19c42bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133838417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.133838417
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.306411807
Short name T494
Test name
Test status
Simulation time 32863842 ps
CPU time 1.29 seconds
Started Jun 25 05:29:38 PM PDT 24
Finished Jun 25 05:29:41 PM PDT 24
Peak memory 200020 kb
Host smart-b24cb9f5-2040-4f9a-a846-f9ca709cc4ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306411807 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_hmac_vectors.306411807
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha256_vectors.1477125430
Short name T203
Test name
Test status
Simulation time 159925773405 ps
CPU time 530.26 seconds
Started Jun 25 05:29:43 PM PDT 24
Finished Jun 25 05:38:35 PM PDT 24
Peak memory 199080 kb
Host smart-be7bf381-2dd9-4255-a901-75afd890e5fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1477125430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha256_vectors.1477125430
Directory /workspace/30.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha384_vectors.4168089456
Short name T230
Test name
Test status
Simulation time 289857757705 ps
CPU time 1771.13 seconds
Started Jun 25 05:29:45 PM PDT 24
Finished Jun 25 05:59:18 PM PDT 24
Peak memory 215392 kb
Host smart-a0124ca0-6579-493c-92c0-f1a8b3b5c0f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4168089456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha384_vectors.4168089456
Directory /workspace/30.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha512_vectors.3640825329
Short name T17
Test name
Test status
Simulation time 116668358305 ps
CPU time 1699.66 seconds
Started Jun 25 05:29:42 PM PDT 24
Finished Jun 25 05:58:02 PM PDT 24
Peak memory 215996 kb
Host smart-8899caf9-c704-4f18-8b0f-946ad452616e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3640825329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha512_vectors.3640825329
Directory /workspace/30.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.1294372982
Short name T295
Test name
Test status
Simulation time 4031189910 ps
CPU time 47.66 seconds
Started Jun 25 05:29:34 PM PDT 24
Finished Jun 25 05:30:24 PM PDT 24
Peak memory 200116 kb
Host smart-205542c3-15fe-4170-9279-96fe082e76ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294372982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1294372982
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1573358455
Short name T227
Test name
Test status
Simulation time 37239549 ps
CPU time 0.58 seconds
Started Jun 25 05:29:33 PM PDT 24
Finished Jun 25 05:29:36 PM PDT 24
Peak memory 196124 kb
Host smart-bde3fd92-4e24-4b77-879d-9b329cf2c3ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573358455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1573358455
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.750494311
Short name T593
Test name
Test status
Simulation time 528670544 ps
CPU time 24.15 seconds
Started Jun 25 05:29:28 PM PDT 24
Finished Jun 25 05:29:53 PM PDT 24
Peak memory 200080 kb
Host smart-7d7faf87-2408-425e-837d-2ac7c6b70fe9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=750494311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.750494311
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.4247377788
Short name T169
Test name
Test status
Simulation time 4567837606 ps
CPU time 24.78 seconds
Started Jun 25 05:29:36 PM PDT 24
Finished Jun 25 05:30:03 PM PDT 24
Peak memory 200100 kb
Host smart-3224bd19-cfd1-4336-b18f-b4e23a74b403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247377788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.4247377788
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.876714599
Short name T246
Test name
Test status
Simulation time 1851923705 ps
CPU time 480.13 seconds
Started Jun 25 05:29:33 PM PDT 24
Finished Jun 25 05:37:36 PM PDT 24
Peak memory 701832 kb
Host smart-bc48c4d2-e286-4901-92ff-a6447d244273
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=876714599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.876714599
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3741094229
Short name T48
Test name
Test status
Simulation time 1159168341 ps
CPU time 7.6 seconds
Started Jun 25 05:29:50 PM PDT 24
Finished Jun 25 05:30:00 PM PDT 24
Peak memory 199884 kb
Host smart-2fbd57f1-ff0c-466c-9246-7890fae007d8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741094229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3741094229
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.2108080610
Short name T381
Test name
Test status
Simulation time 700703334 ps
CPU time 21.12 seconds
Started Jun 25 05:29:45 PM PDT 24
Finished Jun 25 05:30:07 PM PDT 24
Peak memory 200064 kb
Host smart-115206ba-a612-48b1-b43c-f3cf6612f2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108080610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.2108080610
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3488613137
Short name T356
Test name
Test status
Simulation time 233513235 ps
CPU time 11.31 seconds
Started Jun 25 05:29:37 PM PDT 24
Finished Jun 25 05:29:50 PM PDT 24
Peak memory 199980 kb
Host smart-4c899151-2800-4b46-a91d-2fc668ef7fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488613137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3488613137
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.1764647716
Short name T233
Test name
Test status
Simulation time 379632577 ps
CPU time 1.39 seconds
Started Jun 25 05:29:31 PM PDT 24
Finished Jun 25 05:29:35 PM PDT 24
Peak memory 200072 kb
Host smart-5b366210-4aa8-4a46-8eac-b7070b5f26fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764647716 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_hmac_vectors.1764647716
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha256_vectors.2661177465
Short name T615
Test name
Test status
Simulation time 18628529277 ps
CPU time 537.97 seconds
Started Jun 25 05:29:33 PM PDT 24
Finished Jun 25 05:38:34 PM PDT 24
Peak memory 200052 kb
Host smart-bf76e786-e315-40d5-9496-5dfff52df35d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2661177465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha256_vectors.2661177465
Directory /workspace/31.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha384_vectors.837476362
Short name T386
Test name
Test status
Simulation time 371746401481 ps
CPU time 1826.14 seconds
Started Jun 25 05:29:42 PM PDT 24
Finished Jun 25 06:00:10 PM PDT 24
Peak memory 216244 kb
Host smart-dc66fb6b-a9ad-449e-88cd-37241b968fcb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=837476362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha384_vectors.837476362
Directory /workspace/31.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha512_vectors.2911929945
Short name T28
Test name
Test status
Simulation time 103283385335 ps
CPU time 1775.8 seconds
Started Jun 25 05:29:42 PM PDT 24
Finished Jun 25 05:59:19 PM PDT 24
Peak memory 216144 kb
Host smart-7a5bda5c-c90c-4492-a9c0-fa5e0d93fc8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2911929945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha512_vectors.2911929945
Directory /workspace/31.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1290019972
Short name T448
Test name
Test status
Simulation time 5956134426 ps
CPU time 82.83 seconds
Started Jun 25 05:29:35 PM PDT 24
Finished Jun 25 05:31:00 PM PDT 24
Peak memory 200112 kb
Host smart-859cfd30-cffa-428f-901f-2ab36eab82d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290019972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1290019972
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1419077412
Short name T163
Test name
Test status
Simulation time 18747599 ps
CPU time 0.64 seconds
Started Jun 25 05:29:38 PM PDT 24
Finished Jun 25 05:29:40 PM PDT 24
Peak memory 195724 kb
Host smart-efc8894a-2f5c-408d-b393-2311014bada7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419077412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1419077412
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1367717876
Short name T459
Test name
Test status
Simulation time 1015410391 ps
CPU time 47.7 seconds
Started Jun 25 05:29:43 PM PDT 24
Finished Jun 25 05:30:32 PM PDT 24
Peak memory 200096 kb
Host smart-c0cbd7b2-ffff-4931-a2eb-63bec743e01a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1367717876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1367717876
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.388885230
Short name T55
Test name
Test status
Simulation time 3285618559 ps
CPU time 26.99 seconds
Started Jun 25 05:29:40 PM PDT 24
Finished Jun 25 05:30:08 PM PDT 24
Peak memory 200064 kb
Host smart-4ac1d237-2f02-4765-bfc1-453428153057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388885230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.388885230
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1352078217
Short name T261
Test name
Test status
Simulation time 18016368536 ps
CPU time 1250.1 seconds
Started Jun 25 05:29:33 PM PDT 24
Finished Jun 25 05:50:26 PM PDT 24
Peak memory 739344 kb
Host smart-7ac6d02a-473b-4eb0-bf48-42bba3adec03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1352078217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1352078217
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.244420571
Short name T575
Test name
Test status
Simulation time 1252865044 ps
CPU time 20.69 seconds
Started Jun 25 05:29:33 PM PDT 24
Finished Jun 25 05:29:56 PM PDT 24
Peak memory 199940 kb
Host smart-d72fe510-6a29-4ad3-a078-30e352b4f248
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244420571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.244420571
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1510376165
Short name T512
Test name
Test status
Simulation time 4787140244 ps
CPU time 64.46 seconds
Started Jun 25 05:29:51 PM PDT 24
Finished Jun 25 05:30:58 PM PDT 24
Peak memory 200140 kb
Host smart-03d3126b-a553-4985-ac32-035660851728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510376165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1510376165
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2812470111
Short name T198
Test name
Test status
Simulation time 1417971000 ps
CPU time 7.81 seconds
Started Jun 25 05:29:49 PM PDT 24
Finished Jun 25 05:29:58 PM PDT 24
Peak memory 200032 kb
Host smart-b5a55a8c-8c28-4b63-b488-83ca439385bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812470111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2812470111
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.88915044
Short name T37
Test name
Test status
Simulation time 93614183 ps
CPU time 0.69 seconds
Started Jun 25 05:29:36 PM PDT 24
Finished Jun 25 05:29:38 PM PDT 24
Peak memory 195684 kb
Host smart-93668b2c-cd9f-4ed8-94ff-cd9c9ca0eb8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88915044 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.88915044
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.2720598312
Short name T659
Test name
Test status
Simulation time 49150066 ps
CPU time 1.13 seconds
Started Jun 25 05:29:35 PM PDT 24
Finished Jun 25 05:29:39 PM PDT 24
Peak memory 200020 kb
Host smart-6aae8082-122f-422c-9b4a-0d617899aedc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720598312 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_hmac_vectors.2720598312
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha256_vectors.52341369
Short name T383
Test name
Test status
Simulation time 115251066079 ps
CPU time 466.28 seconds
Started Jun 25 05:29:30 PM PDT 24
Finished Jun 25 05:37:18 PM PDT 24
Peak memory 200072 kb
Host smart-7ed393fa-3c19-485f-b761-949783b2311c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=52341369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha256_vectors.52341369
Directory /workspace/32.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha384_vectors.1188304373
Short name T607
Test name
Test status
Simulation time 56921538188 ps
CPU time 1740.74 seconds
Started Jun 25 05:29:49 PM PDT 24
Finished Jun 25 05:58:52 PM PDT 24
Peak memory 216424 kb
Host smart-087f74af-5a53-4d92-9f9c-d145bae288a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1188304373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha384_vectors.1188304373
Directory /workspace/32.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha512_vectors.2139563877
Short name T666
Test name
Test status
Simulation time 526146120440 ps
CPU time 2115.33 seconds
Started Jun 25 05:29:29 PM PDT 24
Finished Jun 25 06:04:47 PM PDT 24
Peak memory 216472 kb
Host smart-172c5e51-88c5-44eb-a212-096f66e1f6eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2139563877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha512_vectors.2139563877
Directory /workspace/32.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3356272502
Short name T461
Test name
Test status
Simulation time 33245237037 ps
CPU time 74.46 seconds
Started Jun 25 05:29:49 PM PDT 24
Finished Jun 25 05:31:06 PM PDT 24
Peak memory 200056 kb
Host smart-b17407bf-c5a6-4e13-9c6a-4060f487f5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356272502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3356272502
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1674066697
Short name T317
Test name
Test status
Simulation time 18274656 ps
CPU time 0.6 seconds
Started Jun 25 05:29:44 PM PDT 24
Finished Jun 25 05:29:46 PM PDT 24
Peak memory 195832 kb
Host smart-fedac2be-eabe-4ce3-a1fa-0fbc60512be4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674066697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1674066697
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.2367576556
Short name T623
Test name
Test status
Simulation time 1529132042 ps
CPU time 34.5 seconds
Started Jun 25 05:29:35 PM PDT 24
Finished Jun 25 05:30:12 PM PDT 24
Peak memory 200036 kb
Host smart-b688a152-2c95-427e-8aad-50c631d77b74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2367576556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2367576556
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.4105543210
Short name T434
Test name
Test status
Simulation time 1407647471 ps
CPU time 36.85 seconds
Started Jun 25 05:29:29 PM PDT 24
Finished Jun 25 05:30:07 PM PDT 24
Peak memory 200136 kb
Host smart-dd5d440c-e589-43c1-9e98-ed2f53900604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105543210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.4105543210
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3598514363
Short name T49
Test name
Test status
Simulation time 18248155918 ps
CPU time 375.99 seconds
Started Jun 25 05:29:32 PM PDT 24
Finished Jun 25 05:35:51 PM PDT 24
Peak memory 513844 kb
Host smart-7d711ef7-49ba-4b13-8193-450d7240d256
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3598514363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3598514363
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1865756721
Short name T641
Test name
Test status
Simulation time 30155892157 ps
CPU time 129.42 seconds
Started Jun 25 05:29:42 PM PDT 24
Finished Jun 25 05:31:53 PM PDT 24
Peak memory 200032 kb
Host smart-34f346db-7588-4293-99df-c406b1e1a725
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865756721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1865756721
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2734229998
Short name T399
Test name
Test status
Simulation time 22703342715 ps
CPU time 108.72 seconds
Started Jun 25 05:29:41 PM PDT 24
Finished Jun 25 05:31:31 PM PDT 24
Peak memory 200164 kb
Host smart-99432e24-9a98-4676-81d0-d23bc85c0efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734229998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2734229998
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3468112601
Short name T619
Test name
Test status
Simulation time 299432460 ps
CPU time 3.98 seconds
Started Jun 25 05:29:40 PM PDT 24
Finished Jun 25 05:29:45 PM PDT 24
Peak memory 200024 kb
Host smart-614cbf6b-08a3-4c2f-b59c-4545cbd13788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468112601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3468112601
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.4183899644
Short name T396
Test name
Test status
Simulation time 77265655 ps
CPU time 1.37 seconds
Started Jun 25 05:29:29 PM PDT 24
Finished Jun 25 05:29:33 PM PDT 24
Peak memory 200056 kb
Host smart-4c91ba29-80ce-4698-9dda-5d141b807f00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183899644 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_hmac_vectors.4183899644
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha256_vectors.744765918
Short name T154
Test name
Test status
Simulation time 43728892277 ps
CPU time 543.28 seconds
Started Jun 25 05:29:43 PM PDT 24
Finished Jun 25 05:38:48 PM PDT 24
Peak memory 199160 kb
Host smart-89da1014-034e-4071-930c-0e319aa7fff6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=744765918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha256_vectors.744765918
Directory /workspace/33.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha384_vectors.480086071
Short name T469
Test name
Test status
Simulation time 75809008225 ps
CPU time 1733.08 seconds
Started Jun 25 05:29:34 PM PDT 24
Finished Jun 25 05:58:30 PM PDT 24
Peak memory 215584 kb
Host smart-3d9097cb-725e-4cc9-b95e-5d5243ae12de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=480086071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha384_vectors.480086071
Directory /workspace/33.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha512_vectors.872066450
Short name T298
Test name
Test status
Simulation time 113847099131 ps
CPU time 1793.16 seconds
Started Jun 25 05:29:34 PM PDT 24
Finished Jun 25 05:59:30 PM PDT 24
Peak memory 215588 kb
Host smart-cb4a9755-7af5-4db5-91d8-f5f1dbcd4355
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=872066450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha512_vectors.872066450
Directory /workspace/33.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3295849323
Short name T200
Test name
Test status
Simulation time 3732620907 ps
CPU time 72.04 seconds
Started Jun 25 05:29:42 PM PDT 24
Finished Jun 25 05:30:55 PM PDT 24
Peak memory 200096 kb
Host smart-80a956d1-9b67-437d-a741-2818ab594ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295849323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3295849323
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1471337806
Short name T429
Test name
Test status
Simulation time 33549315 ps
CPU time 0.58 seconds
Started Jun 25 05:29:37 PM PDT 24
Finished Jun 25 05:29:39 PM PDT 24
Peak memory 195844 kb
Host smart-d8531444-e25a-4035-98d3-74fcb0fead11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471337806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1471337806
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.529912938
Short name T340
Test name
Test status
Simulation time 603157336 ps
CPU time 4.25 seconds
Started Jun 25 05:29:30 PM PDT 24
Finished Jun 25 05:29:37 PM PDT 24
Peak memory 200064 kb
Host smart-f37e4d32-c77c-4a81-8981-fd0b25bbdf99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=529912938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.529912938
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.803601992
Short name T387
Test name
Test status
Simulation time 1751040436 ps
CPU time 459.24 seconds
Started Jun 25 05:29:35 PM PDT 24
Finished Jun 25 05:37:17 PM PDT 24
Peak memory 685156 kb
Host smart-0029f77b-be46-4bb5-8e8e-f3fa71951483
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=803601992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.803601992
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.914395952
Short name T131
Test name
Test status
Simulation time 2353837207 ps
CPU time 134.3 seconds
Started Jun 25 05:29:45 PM PDT 24
Finished Jun 25 05:32:01 PM PDT 24
Peak memory 200124 kb
Host smart-d79cadea-2f36-4070-b210-2d292de8bdb7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914395952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.914395952
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1322299978
Short name T347
Test name
Test status
Simulation time 5628933703 ps
CPU time 103.86 seconds
Started Jun 25 05:29:45 PM PDT 24
Finished Jun 25 05:31:30 PM PDT 24
Peak memory 200108 kb
Host smart-3bd7cd37-4f94-4f53-965b-f2f7b2e21b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322299978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1322299978
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2818525803
Short name T612
Test name
Test status
Simulation time 216567599 ps
CPU time 9.84 seconds
Started Jun 25 05:29:46 PM PDT 24
Finished Jun 25 05:29:57 PM PDT 24
Peak memory 200084 kb
Host smart-3351f64c-c7d9-434d-884b-e51016b64dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818525803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2818525803
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.1453721678
Short name T164
Test name
Test status
Simulation time 329605386 ps
CPU time 1.33 seconds
Started Jun 25 05:29:32 PM PDT 24
Finished Jun 25 05:29:36 PM PDT 24
Peak memory 199992 kb
Host smart-f332c722-3c9a-4e33-a30c-a80cc8c04a25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453721678 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_hmac_vectors.1453721678
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha256_vectors.1384589708
Short name T12
Test name
Test status
Simulation time 20381732513 ps
CPU time 444.32 seconds
Started Jun 25 05:29:30 PM PDT 24
Finished Jun 25 05:36:57 PM PDT 24
Peak memory 200060 kb
Host smart-57b9a299-3cc3-4110-9467-d0aa3f6a9036
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1384589708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha256_vectors.1384589708
Directory /workspace/34.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha384_vectors.304279684
Short name T336
Test name
Test status
Simulation time 135045962157 ps
CPU time 1819.8 seconds
Started Jun 25 05:29:32 PM PDT 24
Finished Jun 25 05:59:55 PM PDT 24
Peak memory 216420 kb
Host smart-fa6d0c7b-7ae4-4c5c-8344-deb1b6cf721b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=304279684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha384_vectors.304279684
Directory /workspace/34.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha512_vectors.1865179446
Short name T490
Test name
Test status
Simulation time 339385352256 ps
CPU time 2050.16 seconds
Started Jun 25 05:29:37 PM PDT 24
Finished Jun 25 06:03:49 PM PDT 24
Peak memory 215272 kb
Host smart-835598a8-52bc-4c4f-aee4-1f6f99acbacb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1865179446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha512_vectors.1865179446
Directory /workspace/34.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1062937397
Short name T463
Test name
Test status
Simulation time 2003134443 ps
CPU time 36.45 seconds
Started Jun 25 05:29:34 PM PDT 24
Finished Jun 25 05:30:13 PM PDT 24
Peak memory 200048 kb
Host smart-53cf8b93-b30e-4564-9874-70217d088057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062937397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1062937397
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.1751854646
Short name T566
Test name
Test status
Simulation time 25486396 ps
CPU time 0.6 seconds
Started Jun 25 05:29:47 PM PDT 24
Finished Jun 25 05:29:49 PM PDT 24
Peak memory 196120 kb
Host smart-31f83d16-7f6a-43a5-9cc6-db0d577b2e52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751854646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1751854646
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3125964393
Short name T6
Test name
Test status
Simulation time 133534062 ps
CPU time 1.89 seconds
Started Jun 25 05:29:42 PM PDT 24
Finished Jun 25 05:29:45 PM PDT 24
Peak memory 199984 kb
Host smart-3a6efade-e435-41da-86c1-15d06808d8db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3125964393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3125964393
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.387574040
Short name T352
Test name
Test status
Simulation time 7474021869 ps
CPU time 41.22 seconds
Started Jun 25 05:29:33 PM PDT 24
Finished Jun 25 05:30:17 PM PDT 24
Peak memory 200084 kb
Host smart-9fc2a109-e2bd-4f81-88f3-c99008394448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387574040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.387574040
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1994898408
Short name T1
Test name
Test status
Simulation time 9664370903 ps
CPU time 623.02 seconds
Started Jun 25 05:29:30 PM PDT 24
Finished Jun 25 05:39:56 PM PDT 24
Peak memory 741588 kb
Host smart-ca79e144-0930-4b6d-9e58-f89a29e02e64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1994898408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1994898408
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.372905187
Short name T31
Test name
Test status
Simulation time 3802933761 ps
CPU time 103.7 seconds
Started Jun 25 05:29:51 PM PDT 24
Finished Jun 25 05:31:37 PM PDT 24
Peak memory 200108 kb
Host smart-07a68383-f872-427b-bfca-960fea3b93bb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372905187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.372905187
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1502788874
Short name T240
Test name
Test status
Simulation time 4553309033 ps
CPU time 69.67 seconds
Started Jun 25 05:29:31 PM PDT 24
Finished Jun 25 05:30:43 PM PDT 24
Peak memory 200120 kb
Host smart-a1c40a14-d5bf-433d-b77b-6747bff87c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502788874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1502788874
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2755243493
Short name T182
Test name
Test status
Simulation time 24506101 ps
CPU time 1.11 seconds
Started Jun 25 05:29:32 PM PDT 24
Finished Jun 25 05:29:36 PM PDT 24
Peak memory 199956 kb
Host smart-3cc26a2b-2a7c-403f-bc07-2055381f419c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755243493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2755243493
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1781604140
Short name T311
Test name
Test status
Simulation time 1414516111 ps
CPU time 76.91 seconds
Started Jun 25 05:29:50 PM PDT 24
Finished Jun 25 05:31:10 PM PDT 24
Peak memory 200224 kb
Host smart-f6a3b3cd-f58d-4759-863e-fbb41329679c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781604140 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1781604140
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.2367676811
Short name T342
Test name
Test status
Simulation time 319240370 ps
CPU time 1.39 seconds
Started Jun 25 05:29:42 PM PDT 24
Finished Jun 25 05:29:44 PM PDT 24
Peak memory 200036 kb
Host smart-1a72df66-e695-48fa-85d7-6441fbe95162
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367676811 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_hmac_vectors.2367676811
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha256_vectors.223269246
Short name T376
Test name
Test status
Simulation time 33864000486 ps
CPU time 462.13 seconds
Started Jun 25 05:29:51 PM PDT 24
Finished Jun 25 05:37:36 PM PDT 24
Peak memory 200056 kb
Host smart-9eead36d-d900-4a17-8da3-5868d8d8dfb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=223269246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha256_vectors.223269246
Directory /workspace/35.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha384_vectors.1809745203
Short name T441
Test name
Test status
Simulation time 66901871720 ps
CPU time 1937.78 seconds
Started Jun 25 05:29:41 PM PDT 24
Finished Jun 25 06:02:00 PM PDT 24
Peak memory 215692 kb
Host smart-f347b509-20b5-4934-94c7-559c05ab7f60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1809745203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha384_vectors.1809745203
Directory /workspace/35.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha512_vectors.2883125345
Short name T572
Test name
Test status
Simulation time 345047362631 ps
CPU time 2037.51 seconds
Started Jun 25 05:29:37 PM PDT 24
Finished Jun 25 06:03:37 PM PDT 24
Peak memory 216328 kb
Host smart-054984f8-2f5c-46d9-954f-94dbad61f057
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2883125345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha512_vectors.2883125345
Directory /workspace/35.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.526048213
Short name T18
Test name
Test status
Simulation time 11613313220 ps
CPU time 83.33 seconds
Started Jun 25 05:29:43 PM PDT 24
Finished Jun 25 05:31:07 PM PDT 24
Peak memory 200128 kb
Host smart-b4de50ca-6e93-4e6f-8968-8ea4c249fecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526048213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.526048213
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.154152138
Short name T171
Test name
Test status
Simulation time 11632228 ps
CPU time 0.57 seconds
Started Jun 25 05:29:40 PM PDT 24
Finished Jun 25 05:29:42 PM PDT 24
Peak memory 195080 kb
Host smart-2168429e-a5f4-434a-81a5-bf9d3eadfb09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154152138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.154152138
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1592513849
Short name T129
Test name
Test status
Simulation time 961651233 ps
CPU time 44.22 seconds
Started Jun 25 05:29:52 PM PDT 24
Finished Jun 25 05:30:38 PM PDT 24
Peak memory 200044 kb
Host smart-e0049973-059d-4574-9ee8-77ed67e0ea9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1592513849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1592513849
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.338338730
Short name T127
Test name
Test status
Simulation time 1963014629 ps
CPU time 37.78 seconds
Started Jun 25 05:29:50 PM PDT 24
Finished Jun 25 05:30:29 PM PDT 24
Peak memory 200008 kb
Host smart-817928b6-0fa6-4c08-b6cd-b618b9f35f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338338730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.338338730
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1718859685
Short name T480
Test name
Test status
Simulation time 4303141077 ps
CPU time 1153.94 seconds
Started Jun 25 05:29:43 PM PDT 24
Finished Jun 25 05:48:59 PM PDT 24
Peak memory 749272 kb
Host smart-964dd008-d6fc-4266-8f91-8119f6a550dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1718859685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1718859685
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2149572236
Short name T255
Test name
Test status
Simulation time 2201601902 ps
CPU time 30.29 seconds
Started Jun 25 05:29:51 PM PDT 24
Finished Jun 25 05:30:23 PM PDT 24
Peak memory 199964 kb
Host smart-a423380f-4fc1-4afd-a203-d484f1ea60e3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149572236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2149572236
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3051856279
Short name T504
Test name
Test status
Simulation time 6478467543 ps
CPU time 103.46 seconds
Started Jun 25 05:29:38 PM PDT 24
Finished Jun 25 05:31:23 PM PDT 24
Peak memory 200124 kb
Host smart-ee789514-2516-488f-842e-d452ea794670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051856279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3051856279
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.1157128593
Short name T588
Test name
Test status
Simulation time 195541322 ps
CPU time 4.27 seconds
Started Jun 25 05:29:42 PM PDT 24
Finished Jun 25 05:29:48 PM PDT 24
Peak memory 200064 kb
Host smart-2f3fbbbf-ac39-4963-8f8c-1a3ceb1291cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157128593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1157128593
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.2349749619
Short name T190
Test name
Test status
Simulation time 132637892 ps
CPU time 1.36 seconds
Started Jun 25 05:29:50 PM PDT 24
Finished Jun 25 05:29:53 PM PDT 24
Peak memory 199964 kb
Host smart-342a9d9d-a7ce-4103-bcf9-cbed1cf1d5e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349749619 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_hmac_vectors.2349749619
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha256_vectors.3769065438
Short name T630
Test name
Test status
Simulation time 175495545112 ps
CPU time 507.35 seconds
Started Jun 25 05:29:44 PM PDT 24
Finished Jun 25 05:38:12 PM PDT 24
Peak memory 199996 kb
Host smart-8b577336-c475-4231-8ea9-09667c4d928a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3769065438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha256_vectors.3769065438
Directory /workspace/36.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha384_vectors.3689764572
Short name T553
Test name
Test status
Simulation time 179004553432 ps
CPU time 2179.8 seconds
Started Jun 25 05:29:50 PM PDT 24
Finished Jun 25 06:06:12 PM PDT 24
Peak memory 216044 kb
Host smart-7ab797dd-3e8e-4443-9a92-28c20de92358
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3689764572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha384_vectors.3689764572
Directory /workspace/36.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha512_vectors.1691876529
Short name T289
Test name
Test status
Simulation time 63564673184 ps
CPU time 1797.69 seconds
Started Jun 25 05:29:51 PM PDT 24
Finished Jun 25 05:59:51 PM PDT 24
Peak memory 216444 kb
Host smart-5dc88586-9ad1-4089-9d99-9db3dfa77b74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1691876529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha512_vectors.1691876529
Directory /workspace/36.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.3249287634
Short name T116
Test name
Test status
Simulation time 5424923989 ps
CPU time 103.47 seconds
Started Jun 25 05:29:35 PM PDT 24
Finished Jun 25 05:31:21 PM PDT 24
Peak memory 200128 kb
Host smart-3408ca98-4d26-492a-9ed0-f3bd8dc04312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249287634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3249287634
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.513044119
Short name T446
Test name
Test status
Simulation time 17190947 ps
CPU time 0.61 seconds
Started Jun 25 05:29:52 PM PDT 24
Finished Jun 25 05:29:55 PM PDT 24
Peak memory 196104 kb
Host smart-85df84a4-ed7f-4bf4-940c-f63de9e1d011
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513044119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.513044119
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3652560127
Short name T310
Test name
Test status
Simulation time 1619354360 ps
CPU time 51.87 seconds
Started Jun 25 05:29:43 PM PDT 24
Finished Jun 25 05:30:37 PM PDT 24
Peak memory 199968 kb
Host smart-11d8a895-e2a8-4c75-8526-017a11274539
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3652560127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3652560127
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2355575130
Short name T585
Test name
Test status
Simulation time 4947078897 ps
CPU time 46.3 seconds
Started Jun 25 05:29:48 PM PDT 24
Finished Jun 25 05:30:36 PM PDT 24
Peak memory 200040 kb
Host smart-f3486759-fc45-457d-a828-609d174055ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355575130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2355575130
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2240345854
Short name T196
Test name
Test status
Simulation time 3275705660 ps
CPU time 871.16 seconds
Started Jun 25 05:29:43 PM PDT 24
Finished Jun 25 05:44:16 PM PDT 24
Peak memory 638776 kb
Host smart-4cf91af0-1e29-494e-9794-8e7ec62dfe0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2240345854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2240345854
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2736739555
Short name T354
Test name
Test status
Simulation time 2471673116 ps
CPU time 139.6 seconds
Started Jun 25 05:29:41 PM PDT 24
Finished Jun 25 05:32:01 PM PDT 24
Peak memory 200092 kb
Host smart-2a8ff860-7d6f-49a3-b240-adfd9d628c16
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736739555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2736739555
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2802033957
Short name T507
Test name
Test status
Simulation time 1891976630 ps
CPU time 37.16 seconds
Started Jun 25 05:29:52 PM PDT 24
Finished Jun 25 05:30:31 PM PDT 24
Peak memory 200272 kb
Host smart-896a4e0b-1edc-4f50-9f55-6c702674bb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802033957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2802033957
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3732931760
Short name T32
Test name
Test status
Simulation time 403244947 ps
CPU time 5.16 seconds
Started Jun 25 05:29:46 PM PDT 24
Finished Jun 25 05:29:52 PM PDT 24
Peak memory 200028 kb
Host smart-57eed511-fc9d-48a6-85bd-8e2e93a16fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732931760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3732931760
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.2749878669
Short name T513
Test name
Test status
Simulation time 88643686 ps
CPU time 1.24 seconds
Started Jun 25 05:29:43 PM PDT 24
Finished Jun 25 05:29:45 PM PDT 24
Peak memory 200092 kb
Host smart-8fc37576-e546-4411-9808-14868c8adf4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749878669 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_hmac_vectors.2749878669
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha256_vectors.317728147
Short name T11
Test name
Test status
Simulation time 55846905372 ps
CPU time 502.2 seconds
Started Jun 25 05:29:46 PM PDT 24
Finished Jun 25 05:38:09 PM PDT 24
Peak memory 200040 kb
Host smart-2cb7a26d-18b6-4dbc-86cc-db4ffc72b859
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=317728147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha256_vectors.317728147
Directory /workspace/37.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha384_vectors.1081052677
Short name T661
Test name
Test status
Simulation time 246294066258 ps
CPU time 1710.17 seconds
Started Jun 25 05:29:49 PM PDT 24
Finished Jun 25 05:58:21 PM PDT 24
Peak memory 216460 kb
Host smart-ca018c6d-6d81-4137-ba82-05407936972b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1081052677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha384_vectors.1081052677
Directory /workspace/37.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2005758799
Short name T536
Test name
Test status
Simulation time 11714016552 ps
CPU time 83.84 seconds
Started Jun 25 05:29:48 PM PDT 24
Finished Jun 25 05:31:13 PM PDT 24
Peak memory 200088 kb
Host smart-ad1edc48-b06e-440e-b5ad-2c67192fa6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005758799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2005758799
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3974237852
Short name T602
Test name
Test status
Simulation time 28568207 ps
CPU time 0.61 seconds
Started Jun 25 05:29:51 PM PDT 24
Finished Jun 25 05:29:54 PM PDT 24
Peak memory 196116 kb
Host smart-fc73c0fd-88e2-4999-ab3f-b62aa3b39dd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974237852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3974237852
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2089040513
Short name T551
Test name
Test status
Simulation time 3117414729 ps
CPU time 28.96 seconds
Started Jun 25 05:29:48 PM PDT 24
Finished Jun 25 05:30:18 PM PDT 24
Peak memory 200020 kb
Host smart-d32a6d35-fcfb-4c84-aa9e-b375d02ec993
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2089040513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2089040513
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1880408896
Short name T359
Test name
Test status
Simulation time 2192844473 ps
CPU time 11.13 seconds
Started Jun 25 05:29:55 PM PDT 24
Finished Jun 25 05:30:08 PM PDT 24
Peak memory 200108 kb
Host smart-085de4dd-cc4c-48cf-9977-dbf481110fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880408896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1880408896
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2487635754
Short name T663
Test name
Test status
Simulation time 2666923035 ps
CPU time 646.44 seconds
Started Jun 25 05:29:48 PM PDT 24
Finished Jun 25 05:40:36 PM PDT 24
Peak memory 727368 kb
Host smart-9dacba69-e046-4df0-86e9-05ee3bfa537b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2487635754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2487635754
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2812415313
Short name T284
Test name
Test status
Simulation time 3318354553 ps
CPU time 13.78 seconds
Started Jun 25 05:29:49 PM PDT 24
Finished Jun 25 05:30:04 PM PDT 24
Peak memory 200032 kb
Host smart-58bc621e-97a5-473f-a0d3-82b8a0d6b9db
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812415313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2812415313
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.353105983
Short name T654
Test name
Test status
Simulation time 806174401 ps
CPU time 51.86 seconds
Started Jun 25 05:29:50 PM PDT 24
Finished Jun 25 05:30:44 PM PDT 24
Peak memory 200068 kb
Host smart-157d4c82-6287-4b90-b04c-f8986a660efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353105983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.353105983
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1053419796
Short name T175
Test name
Test status
Simulation time 323150859 ps
CPU time 6.54 seconds
Started Jun 25 05:29:50 PM PDT 24
Finished Jun 25 05:29:59 PM PDT 24
Peak memory 199992 kb
Host smart-1ddfd5af-c0fb-49b3-a368-11a60c298807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053419796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1053419796
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.3028059500
Short name T520
Test name
Test status
Simulation time 35815784 ps
CPU time 1.3 seconds
Started Jun 25 05:29:46 PM PDT 24
Finished Jun 25 05:29:49 PM PDT 24
Peak memory 200064 kb
Host smart-789b7e3d-1a1b-434b-a5e9-178ea05d16ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028059500 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_hmac_vectors.3028059500
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha256_vectors.3576700784
Short name T194
Test name
Test status
Simulation time 271916812915 ps
CPU time 476.16 seconds
Started Jun 25 05:29:55 PM PDT 24
Finished Jun 25 05:37:52 PM PDT 24
Peak memory 200040 kb
Host smart-cf2879cc-50fe-4d7c-8939-fb8ac7e3aa38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3576700784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha256_vectors.3576700784
Directory /workspace/38.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha384_vectors.4282003914
Short name T621
Test name
Test status
Simulation time 34208201533 ps
CPU time 1792.66 seconds
Started Jun 25 05:29:55 PM PDT 24
Finished Jun 25 05:59:49 PM PDT 24
Peak memory 208304 kb
Host smart-1508c62a-5632-4258-b7cd-fb29e28dc08f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4282003914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha384_vectors.4282003914
Directory /workspace/38.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha512_vectors.2080333809
Short name T425
Test name
Test status
Simulation time 212607841652 ps
CPU time 2267.68 seconds
Started Jun 25 05:29:50 PM PDT 24
Finished Jun 25 06:07:40 PM PDT 24
Peak memory 215536 kb
Host smart-753863a3-6512-4415-942d-07e77206e68c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2080333809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha512_vectors.2080333809
Directory /workspace/38.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.397533329
Short name T519
Test name
Test status
Simulation time 16194870112 ps
CPU time 81.62 seconds
Started Jun 25 05:29:50 PM PDT 24
Finished Jun 25 05:31:13 PM PDT 24
Peak memory 200112 kb
Host smart-735e2494-b190-4830-a9b0-1f6cad2d5af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397533329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.397533329
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.805961483
Short name T409
Test name
Test status
Simulation time 29229695 ps
CPU time 0.61 seconds
Started Jun 25 05:29:53 PM PDT 24
Finished Jun 25 05:29:55 PM PDT 24
Peak memory 196100 kb
Host smart-2988c9ec-8231-4fb8-a351-b8df77affda2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805961483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.805961483
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.724831666
Short name T80
Test name
Test status
Simulation time 47463101 ps
CPU time 2.5 seconds
Started Jun 25 05:29:51 PM PDT 24
Finished Jun 25 05:29:56 PM PDT 24
Peak memory 199980 kb
Host smart-524c49e9-fb66-4c1f-b0b1-c31f3766ee71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=724831666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.724831666
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3070208019
Short name T278
Test name
Test status
Simulation time 8773486416 ps
CPU time 33.48 seconds
Started Jun 25 05:29:49 PM PDT 24
Finished Jun 25 05:30:24 PM PDT 24
Peak memory 200116 kb
Host smart-3ae14f1f-16e0-4f8c-8aee-9ebd5391eb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070208019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3070208019
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3805378866
Short name T626
Test name
Test status
Simulation time 5188590728 ps
CPU time 1518.52 seconds
Started Jun 25 05:29:46 PM PDT 24
Finished Jun 25 05:55:06 PM PDT 24
Peak memory 796076 kb
Host smart-21de4b5e-ab23-463a-98d3-df53134634f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3805378866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3805378866
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1346932646
Short name T358
Test name
Test status
Simulation time 16758768482 ps
CPU time 58.84 seconds
Started Jun 25 05:29:52 PM PDT 24
Finished Jun 25 05:30:53 PM PDT 24
Peak memory 200080 kb
Host smart-ee0dfa19-4d67-4456-9e00-47bc1d2fed89
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346932646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1346932646
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.262909153
Short name T608
Test name
Test status
Simulation time 409996546 ps
CPU time 23.22 seconds
Started Jun 25 05:29:51 PM PDT 24
Finished Jun 25 05:30:16 PM PDT 24
Peak memory 200052 kb
Host smart-f1790fb4-c6b8-4194-92bf-886be4a97183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262909153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.262909153
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1710048620
Short name T155
Test name
Test status
Simulation time 534342900 ps
CPU time 10.19 seconds
Started Jun 25 05:29:49 PM PDT 24
Finished Jun 25 05:30:00 PM PDT 24
Peak memory 200048 kb
Host smart-911f9936-d9f4-4cc9-b133-701f6ddbb7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710048620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1710048620
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.3767031223
Short name T656
Test name
Test status
Simulation time 701958585 ps
CPU time 1.34 seconds
Started Jun 25 05:29:50 PM PDT 24
Finished Jun 25 05:29:54 PM PDT 24
Peak memory 200040 kb
Host smart-be436eaa-eb51-4493-bad7-4b5c523f954f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767031223 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_hmac_vectors.3767031223
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha256_vectors.467610289
Short name T332
Test name
Test status
Simulation time 175088835392 ps
CPU time 483.07 seconds
Started Jun 25 05:29:52 PM PDT 24
Finished Jun 25 05:37:57 PM PDT 24
Peak memory 200068 kb
Host smart-37f94c0a-f1cf-4ccd-9d4f-597f3c750422
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=467610289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha256_vectors.467610289
Directory /workspace/39.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha384_vectors.1748480144
Short name T495
Test name
Test status
Simulation time 204713529375 ps
CPU time 1852.28 seconds
Started Jun 25 05:29:44 PM PDT 24
Finished Jun 25 06:00:38 PM PDT 24
Peak memory 216456 kb
Host smart-407a2b6e-94b2-4887-9141-ea2f99525006
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1748480144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha384_vectors.1748480144
Directory /workspace/39.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha512_vectors.1188283091
Short name T569
Test name
Test status
Simulation time 584662194749 ps
CPU time 1838.97 seconds
Started Jun 25 05:29:47 PM PDT 24
Finished Jun 25 06:00:28 PM PDT 24
Peak memory 216424 kb
Host smart-a1a0e921-b317-4e9d-8af3-195e57669c70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1188283091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha512_vectors.1188283091
Directory /workspace/39.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3293225247
Short name T262
Test name
Test status
Simulation time 11536453763 ps
CPU time 34.99 seconds
Started Jun 25 05:29:44 PM PDT 24
Finished Jun 25 05:30:21 PM PDT 24
Peak memory 200116 kb
Host smart-cb5e1d5d-0527-4bd9-83ac-82937ba318fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293225247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3293225247
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.91508335
Short name T35
Test name
Test status
Simulation time 13064783 ps
CPU time 0.59 seconds
Started Jun 25 05:28:53 PM PDT 24
Finished Jun 25 05:28:55 PM PDT 24
Peak memory 195056 kb
Host smart-69b0b518-a4f4-4852-9ae2-e91aea44110f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91508335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.91508335
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1690926746
Short name T437
Test name
Test status
Simulation time 363613949 ps
CPU time 9.7 seconds
Started Jun 25 05:28:46 PM PDT 24
Finished Jun 25 05:28:57 PM PDT 24
Peak memory 200012 kb
Host smart-aa540005-19b4-41fd-a459-7e96d04d379e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1690926746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1690926746
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3928217849
Short name T220
Test name
Test status
Simulation time 1704527210 ps
CPU time 30.91 seconds
Started Jun 25 05:28:43 PM PDT 24
Finished Jun 25 05:29:16 PM PDT 24
Peak memory 200056 kb
Host smart-2d9ec0c1-b727-4726-9595-8064b675593f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928217849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3928217849
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1783199588
Short name T611
Test name
Test status
Simulation time 9816957675 ps
CPU time 83.6 seconds
Started Jun 25 05:29:04 PM PDT 24
Finished Jun 25 05:30:29 PM PDT 24
Peak memory 339024 kb
Host smart-14df05ec-3aab-4556-b159-cd11a64552ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1783199588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1783199588
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1702876277
Short name T605
Test name
Test status
Simulation time 40876701755 ps
CPU time 148.14 seconds
Started Jun 25 05:28:47 PM PDT 24
Finished Jun 25 05:31:16 PM PDT 24
Peak memory 200032 kb
Host smart-497b9700-469f-4a6f-9cd9-75678aa67c4a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702876277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1702876277
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.529682428
Short name T76
Test name
Test status
Simulation time 50255155211 ps
CPU time 88.97 seconds
Started Jun 25 05:28:48 PM PDT 24
Finished Jun 25 05:30:18 PM PDT 24
Peak memory 200100 kb
Host smart-88f857b4-27f4-4bc1-b643-5b675114db17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529682428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.529682428
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.298323911
Short name T46
Test name
Test status
Simulation time 72266963 ps
CPU time 0.82 seconds
Started Jun 25 05:28:53 PM PDT 24
Finished Jun 25 05:28:55 PM PDT 24
Peak memory 218312 kb
Host smart-6652c1bc-0cc4-40b3-a4d2-a98d25ad2b44
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298323911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.298323911
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.2199738091
Short name T651
Test name
Test status
Simulation time 359721473 ps
CPU time 8.71 seconds
Started Jun 25 05:28:40 PM PDT 24
Finished Jun 25 05:28:52 PM PDT 24
Peak memory 200072 kb
Host smart-c5989f77-4f3c-4504-a738-449af279e27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199738091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2199738091
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.1178672110
Short name T173
Test name
Test status
Simulation time 442425662 ps
CPU time 1.39 seconds
Started Jun 25 05:28:46 PM PDT 24
Finished Jun 25 05:28:49 PM PDT 24
Peak memory 200020 kb
Host smart-2c7409ec-867d-44ef-b61e-9bc1caeb106c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178672110 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac_vectors.1178672110
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.1622077954
Short name T279
Test name
Test status
Simulation time 41645423636 ps
CPU time 567.44 seconds
Started Jun 25 05:28:40 PM PDT 24
Finished Jun 25 05:38:11 PM PDT 24
Peak memory 200068 kb
Host smart-b042f83b-9ce3-4022-8a98-b1524043ad5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1622077954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.1622077954
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.1672447961
Short name T160
Test name
Test status
Simulation time 589517545436 ps
CPU time 1964.93 seconds
Started Jun 25 05:28:43 PM PDT 24
Finished Jun 25 06:01:31 PM PDT 24
Peak memory 216180 kb
Host smart-ca8678be-5524-4a24-b1b6-a6f21491904b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1672447961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.1672447961
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.2803362778
Short name T653
Test name
Test status
Simulation time 453271248660 ps
CPU time 1942.81 seconds
Started Jun 25 05:28:39 PM PDT 24
Finished Jun 25 06:01:04 PM PDT 24
Peak memory 215600 kb
Host smart-f7627e20-9cdc-4ca9-8bb8-a90abc7efeaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2803362778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.2803362778
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.778832820
Short name T330
Test name
Test status
Simulation time 22569510110 ps
CPU time 80.79 seconds
Started Jun 25 05:28:49 PM PDT 24
Finished Jun 25 05:30:11 PM PDT 24
Peak memory 200084 kb
Host smart-c3aa3796-9c03-424d-b199-6bb3d2e8e19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778832820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.778832820
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3281563169
Short name T242
Test name
Test status
Simulation time 101131915 ps
CPU time 0.58 seconds
Started Jun 25 05:29:57 PM PDT 24
Finished Jun 25 05:29:59 PM PDT 24
Peak memory 195004 kb
Host smart-d4456fa5-3177-48f4-9cd9-a7ee033408d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281563169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3281563169
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1621368526
Short name T406
Test name
Test status
Simulation time 1388376070 ps
CPU time 12.14 seconds
Started Jun 25 05:29:58 PM PDT 24
Finished Jun 25 05:30:11 PM PDT 24
Peak memory 200032 kb
Host smart-00894db3-20b7-47ce-954d-5606267513b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1621368526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1621368526
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.631382918
Short name T634
Test name
Test status
Simulation time 1601303874 ps
CPU time 20.64 seconds
Started Jun 25 05:29:56 PM PDT 24
Finished Jun 25 05:30:18 PM PDT 24
Peak memory 199916 kb
Host smart-895c64f9-6cda-4b0e-a411-930f2d88f45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631382918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.631382918
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3084566406
Short name T479
Test name
Test status
Simulation time 13404284884 ps
CPU time 968.97 seconds
Started Jun 25 05:29:55 PM PDT 24
Finished Jun 25 05:46:05 PM PDT 24
Peak memory 747580 kb
Host smart-bea0a2b9-87b9-4343-ba29-79e938d25043
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3084566406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3084566406
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.967635546
Short name T403
Test name
Test status
Simulation time 30933700108 ps
CPU time 111 seconds
Started Jun 25 05:29:55 PM PDT 24
Finished Jun 25 05:31:47 PM PDT 24
Peak memory 200092 kb
Host smart-7e5fdf26-a8b1-4f56-b876-d2317e2274a0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967635546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.967635546
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3620777201
Short name T583
Test name
Test status
Simulation time 1551994739 ps
CPU time 89.92 seconds
Started Jun 25 05:30:00 PM PDT 24
Finished Jun 25 05:31:30 PM PDT 24
Peak memory 200040 kb
Host smart-28a918c9-3117-4ac1-b4d7-171fdd9df0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620777201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3620777201
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2875428549
Short name T550
Test name
Test status
Simulation time 132323761 ps
CPU time 2.03 seconds
Started Jun 25 05:29:50 PM PDT 24
Finished Jun 25 05:29:54 PM PDT 24
Peak memory 200004 kb
Host smart-acc17d58-21f6-4352-8314-1aa051718fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875428549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2875428549
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.327272810
Short name T432
Test name
Test status
Simulation time 79297624 ps
CPU time 1.45 seconds
Started Jun 25 05:29:57 PM PDT 24
Finished Jun 25 05:29:59 PM PDT 24
Peak memory 199984 kb
Host smart-32e55d2a-fe25-4ce0-90ed-594d890faf0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327272810 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_hmac_vectors.327272810
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha256_vectors.2493452986
Short name T485
Test name
Test status
Simulation time 39302427845 ps
CPU time 490.41 seconds
Started Jun 25 05:29:58 PM PDT 24
Finished Jun 25 05:38:09 PM PDT 24
Peak memory 200016 kb
Host smart-d65ebd64-02aa-46d1-8304-8dcbc31e0131
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2493452986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha256_vectors.2493452986
Directory /workspace/40.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha512_vectors.1022564725
Short name T178
Test name
Test status
Simulation time 625666994297 ps
CPU time 1982.98 seconds
Started Jun 25 05:29:54 PM PDT 24
Finished Jun 25 06:02:59 PM PDT 24
Peak memory 215768 kb
Host smart-3ae9c919-84b1-4f7f-ad58-3605df4ce525
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1022564725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha512_vectors.1022564725
Directory /workspace/40.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.305101278
Short name T411
Test name
Test status
Simulation time 1195891779 ps
CPU time 18.97 seconds
Started Jun 25 05:30:00 PM PDT 24
Finished Jun 25 05:30:20 PM PDT 24
Peak memory 199992 kb
Host smart-32ae73da-5986-494e-831c-49b07219afc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305101278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.305101278
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.219316328
Short name T105
Test name
Test status
Simulation time 12759423 ps
CPU time 0.6 seconds
Started Jun 25 05:30:02 PM PDT 24
Finished Jun 25 05:30:04 PM PDT 24
Peak memory 195848 kb
Host smart-ea78034d-41af-4dec-9324-b76c1a856589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219316328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.219316328
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1669426633
Short name T389
Test name
Test status
Simulation time 158101033 ps
CPU time 5.43 seconds
Started Jun 25 05:29:57 PM PDT 24
Finished Jun 25 05:30:03 PM PDT 24
Peak memory 200032 kb
Host smart-6933a5c5-ade0-4628-adf2-58e533831b13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1669426633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1669426633
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2048357055
Short name T193
Test name
Test status
Simulation time 393828110 ps
CPU time 2.64 seconds
Started Jun 25 05:30:02 PM PDT 24
Finished Jun 25 05:30:07 PM PDT 24
Peak memory 200024 kb
Host smart-173ca4af-4876-48d6-9517-16908a429779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048357055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2048357055
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2119557937
Short name T600
Test name
Test status
Simulation time 10199012838 ps
CPU time 821.69 seconds
Started Jun 25 05:30:03 PM PDT 24
Finished Jun 25 05:43:47 PM PDT 24
Peak memory 697064 kb
Host smart-488ddc84-be40-4957-b080-96fbe905ba4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2119557937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2119557937
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2123450531
Short name T292
Test name
Test status
Simulation time 18532130822 ps
CPU time 162.97 seconds
Started Jun 25 05:30:08 PM PDT 24
Finished Jun 25 05:32:52 PM PDT 24
Peak memory 200104 kb
Host smart-03e84ed7-9646-4f8a-a4b2-cbe276f1da9f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123450531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2123450531
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.823545542
Short name T642
Test name
Test status
Simulation time 1485751444 ps
CPU time 15.77 seconds
Started Jun 25 05:29:58 PM PDT 24
Finished Jun 25 05:30:15 PM PDT 24
Peak memory 200044 kb
Host smart-b77d077a-9983-4085-95b5-7931d6e28e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823545542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.823545542
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3766172785
Short name T402
Test name
Test status
Simulation time 893794007 ps
CPU time 10.16 seconds
Started Jun 25 05:29:54 PM PDT 24
Finished Jun 25 05:30:05 PM PDT 24
Peak memory 199968 kb
Host smart-c7b65270-1a8d-4d1c-8762-f22439c6b825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766172785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3766172785
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.1997347543
Short name T534
Test name
Test status
Simulation time 48034658 ps
CPU time 1.13 seconds
Started Jun 25 05:30:03 PM PDT 24
Finished Jun 25 05:30:06 PM PDT 24
Peak memory 199888 kb
Host smart-e38eb16b-8efa-4ece-95c0-b759982ba4ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997347543 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_hmac_vectors.1997347543
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha256_vectors.4019419933
Short name T272
Test name
Test status
Simulation time 79252905535 ps
CPU time 518.18 seconds
Started Jun 25 05:30:04 PM PDT 24
Finished Jun 25 05:38:44 PM PDT 24
Peak memory 200036 kb
Host smart-1d1bb982-afed-4415-b407-350f09f04e06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4019419933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha256_vectors.4019419933
Directory /workspace/41.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha384_vectors.1664642374
Short name T213
Test name
Test status
Simulation time 873754661001 ps
CPU time 1885.11 seconds
Started Jun 25 05:30:04 PM PDT 24
Finished Jun 25 06:01:31 PM PDT 24
Peak memory 215648 kb
Host smart-951c3b0a-9b46-4c3c-8f13-6a5b8e54cbd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1664642374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha384_vectors.1664642374
Directory /workspace/41.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha512_vectors.1402769154
Short name T162
Test name
Test status
Simulation time 132339160510 ps
CPU time 1812.38 seconds
Started Jun 25 05:30:04 PM PDT 24
Finished Jun 25 06:00:18 PM PDT 24
Peak memory 216008 kb
Host smart-3d55b25e-694b-431b-864e-9689e674262e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1402769154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha512_vectors.1402769154
Directory /workspace/41.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.479711822
Short name T113
Test name
Test status
Simulation time 16842231551 ps
CPU time 31.76 seconds
Started Jun 25 05:30:04 PM PDT 24
Finished Jun 25 05:30:37 PM PDT 24
Peak memory 200112 kb
Host smart-61db5e43-fa17-4b88-be50-26960ce901b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479711822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.479711822
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2820292844
Short name T212
Test name
Test status
Simulation time 34675463 ps
CPU time 0.61 seconds
Started Jun 25 05:30:00 PM PDT 24
Finished Jun 25 05:30:02 PM PDT 24
Peak memory 196088 kb
Host smart-b925ecf1-80f7-4037-b757-dab9e31f47b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820292844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2820292844
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.328067130
Short name T558
Test name
Test status
Simulation time 1105998442 ps
CPU time 56.7 seconds
Started Jun 25 05:30:04 PM PDT 24
Finished Jun 25 05:31:02 PM PDT 24
Peak memory 199976 kb
Host smart-9668501e-5972-411c-8689-d102924ce35d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=328067130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.328067130
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1619232904
Short name T369
Test name
Test status
Simulation time 13813204652 ps
CPU time 39.52 seconds
Started Jun 25 05:30:05 PM PDT 24
Finished Jun 25 05:30:46 PM PDT 24
Peak memory 200088 kb
Host smart-dcffa266-3aa0-4df0-a387-3fcb3006d17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619232904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1619232904
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1034367425
Short name T498
Test name
Test status
Simulation time 2895507809 ps
CPU time 367.61 seconds
Started Jun 25 05:30:05 PM PDT 24
Finished Jun 25 05:36:14 PM PDT 24
Peak memory 696280 kb
Host smart-2b530c52-673e-4bf1-8d0b-fea31fc7dd67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1034367425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1034367425
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.4010412879
Short name T189
Test name
Test status
Simulation time 13002165709 ps
CPU time 135.27 seconds
Started Jun 25 05:30:05 PM PDT 24
Finished Jun 25 05:32:22 PM PDT 24
Peak memory 200032 kb
Host smart-c698488b-48cc-4b0e-9fa7-c50f8265e45e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010412879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.4010412879
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.249773223
Short name T303
Test name
Test status
Simulation time 1851767979 ps
CPU time 25.61 seconds
Started Jun 25 05:30:05 PM PDT 24
Finished Jun 25 05:30:32 PM PDT 24
Peak memory 200012 kb
Host smart-ae3ae506-f174-4565-89b7-3e35891c12a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249773223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.249773223
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1055779097
Short name T219
Test name
Test status
Simulation time 249699364 ps
CPU time 4.32 seconds
Started Jun 25 05:30:04 PM PDT 24
Finished Jun 25 05:30:10 PM PDT 24
Peak memory 200060 kb
Host smart-17693dad-1f80-47f1-9afe-241432ac7a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055779097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1055779097
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.3757343866
Short name T375
Test name
Test status
Simulation time 68561179 ps
CPU time 1.17 seconds
Started Jun 25 05:30:01 PM PDT 24
Finished Jun 25 05:30:04 PM PDT 24
Peak memory 199932 kb
Host smart-e7f90044-56a3-4a27-9acf-03f3cb14d0ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757343866 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_hmac_vectors.3757343866
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha256_vectors.1310671923
Short name T202
Test name
Test status
Simulation time 8938687760 ps
CPU time 526.13 seconds
Started Jun 25 05:30:08 PM PDT 24
Finished Jun 25 05:38:56 PM PDT 24
Peak memory 200036 kb
Host smart-efb46ceb-4585-4439-a536-4f2ed1c59c4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1310671923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha256_vectors.1310671923
Directory /workspace/42.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha384_vectors.3854325623
Short name T649
Test name
Test status
Simulation time 157418322452 ps
CPU time 1904.05 seconds
Started Jun 25 05:30:02 PM PDT 24
Finished Jun 25 06:01:48 PM PDT 24
Peak memory 215824 kb
Host smart-9e9d67fb-d4f1-4ce4-bb7d-df438a5c82f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3854325623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha384_vectors.3854325623
Directory /workspace/42.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha512_vectors.4250724603
Short name T325
Test name
Test status
Simulation time 152765278069 ps
CPU time 1895.73 seconds
Started Jun 25 05:30:07 PM PDT 24
Finished Jun 25 06:01:44 PM PDT 24
Peak memory 215844 kb
Host smart-85333573-1451-4a6a-8c62-697ee9cfb9f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4250724603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha512_vectors.4250724603
Directory /workspace/42.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2169927115
Short name T337
Test name
Test status
Simulation time 9958584947 ps
CPU time 95.52 seconds
Started Jun 25 05:30:04 PM PDT 24
Finished Jun 25 05:31:42 PM PDT 24
Peak memory 200116 kb
Host smart-784be235-a83f-4828-8c9a-43da0abcb053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169927115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2169927115
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.810966706
Short name T514
Test name
Test status
Simulation time 44884019 ps
CPU time 0.6 seconds
Started Jun 25 05:30:05 PM PDT 24
Finished Jun 25 05:30:07 PM PDT 24
Peak memory 196088 kb
Host smart-11b12e78-224f-4706-83ef-62b6a4b30a9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810966706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.810966706
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2562121915
Short name T21
Test name
Test status
Simulation time 861670178 ps
CPU time 43.04 seconds
Started Jun 25 05:30:04 PM PDT 24
Finished Jun 25 05:30:49 PM PDT 24
Peak memory 200060 kb
Host smart-7dc6d44a-7926-481e-81f2-8f69caa5c9e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2562121915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2562121915
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2250336097
Short name T491
Test name
Test status
Simulation time 106320055 ps
CPU time 2.96 seconds
Started Jun 25 05:30:05 PM PDT 24
Finished Jun 25 05:30:09 PM PDT 24
Peak memory 200040 kb
Host smart-3c6b988d-c4dc-4408-bf6a-dbbd8e171f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250336097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2250336097
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.3825670696
Short name T323
Test name
Test status
Simulation time 99771364 ps
CPU time 12.33 seconds
Started Jun 25 05:30:05 PM PDT 24
Finished Jun 25 05:30:19 PM PDT 24
Peak memory 229748 kb
Host smart-d6b02823-cad4-4ddb-b95c-579f40563734
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3825670696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3825670696
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3631072960
Short name T470
Test name
Test status
Simulation time 5312209680 ps
CPU time 66.86 seconds
Started Jun 25 05:30:03 PM PDT 24
Finished Jun 25 05:31:11 PM PDT 24
Peak memory 199976 kb
Host smart-55ee44da-e3fe-4055-b5fe-ff0289ba86d8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631072960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3631072960
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.111539442
Short name T157
Test name
Test status
Simulation time 225484910 ps
CPU time 3.86 seconds
Started Jun 25 05:30:07 PM PDT 24
Finished Jun 25 05:30:12 PM PDT 24
Peak memory 199992 kb
Host smart-89d35cb9-7bb0-49a1-8ed2-de7a20786644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111539442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.111539442
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2457279050
Short name T237
Test name
Test status
Simulation time 288324502 ps
CPU time 8.35 seconds
Started Jun 25 05:30:03 PM PDT 24
Finished Jun 25 05:30:13 PM PDT 24
Peak memory 200064 kb
Host smart-8c0c2ed7-5075-41e3-975c-e6aecf81987b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457279050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2457279050
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.3142390222
Short name T445
Test name
Test status
Simulation time 74265526 ps
CPU time 1.45 seconds
Started Jun 25 05:30:02 PM PDT 24
Finished Jun 25 05:30:05 PM PDT 24
Peak memory 200032 kb
Host smart-5cdb0cdf-7789-4812-ad5b-cde2635060d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142390222 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_hmac_vectors.3142390222
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha256_vectors.2371815885
Short name T439
Test name
Test status
Simulation time 30673089089 ps
CPU time 438.74 seconds
Started Jun 25 05:30:05 PM PDT 24
Finished Jun 25 05:37:25 PM PDT 24
Peak memory 200056 kb
Host smart-1fed8cb1-9ef3-4541-956b-6112a19559a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2371815885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha256_vectors.2371815885
Directory /workspace/43.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha384_vectors.340035685
Short name T273
Test name
Test status
Simulation time 60235696819 ps
CPU time 1716.19 seconds
Started Jun 25 05:30:03 PM PDT 24
Finished Jun 25 05:58:41 PM PDT 24
Peak memory 215508 kb
Host smart-f941e859-fffc-4e41-b6de-cd7439e720a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=340035685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha384_vectors.340035685
Directory /workspace/43.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha512_vectors.1801002310
Short name T161
Test name
Test status
Simulation time 841208566881 ps
CPU time 1640.71 seconds
Started Jun 25 05:30:02 PM PDT 24
Finished Jun 25 05:57:25 PM PDT 24
Peak memory 216188 kb
Host smart-7dd3ddf9-06c4-44ef-ad9a-97cc68fa6e0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1801002310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha512_vectors.1801002310
Directory /workspace/43.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2577377610
Short name T638
Test name
Test status
Simulation time 2521650738 ps
CPU time 12.15 seconds
Started Jun 25 05:30:08 PM PDT 24
Finished Jun 25 05:30:21 PM PDT 24
Peak memory 200036 kb
Host smart-ea2f633b-83ec-4040-a835-8969a07f9d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577377610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2577377610
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2816124811
Short name T285
Test name
Test status
Simulation time 14092121 ps
CPU time 0.62 seconds
Started Jun 25 05:30:10 PM PDT 24
Finished Jun 25 05:30:12 PM PDT 24
Peak memory 195100 kb
Host smart-ef373cc7-fd08-4a02-b576-4779696de528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816124811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2816124811
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.1240953159
Short name T81
Test name
Test status
Simulation time 3268138551 ps
CPU time 44.63 seconds
Started Jun 25 05:30:12 PM PDT 24
Finished Jun 25 05:30:58 PM PDT 24
Peak memory 216352 kb
Host smart-8d448bd9-fc27-4554-b3d4-f47dc82ef61c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1240953159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1240953159
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1288384568
Short name T188
Test name
Test status
Simulation time 11545255479 ps
CPU time 869.55 seconds
Started Jun 25 05:30:13 PM PDT 24
Finished Jun 25 05:44:43 PM PDT 24
Peak memory 735576 kb
Host smart-1ef28a4f-768f-487e-afc6-67ac07195af7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1288384568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1288384568
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3512841790
Short name T456
Test name
Test status
Simulation time 108146826994 ps
CPU time 147.46 seconds
Started Jun 25 05:30:11 PM PDT 24
Finished Jun 25 05:32:40 PM PDT 24
Peak memory 200088 kb
Host smart-802dabb6-bcfc-4a1c-a52d-519c4a6a771d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512841790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3512841790
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.921522418
Short name T390
Test name
Test status
Simulation time 3272680413 ps
CPU time 50.9 seconds
Started Jun 25 05:30:11 PM PDT 24
Finished Jun 25 05:31:03 PM PDT 24
Peak memory 208320 kb
Host smart-5ef7f402-ac7b-46ca-ae73-fbb00609e04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921522418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.921522418
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2031191458
Short name T361
Test name
Test status
Simulation time 1828964370 ps
CPU time 12 seconds
Started Jun 25 05:30:03 PM PDT 24
Finished Jun 25 05:30:17 PM PDT 24
Peak memory 200068 kb
Host smart-20bebaf8-b5d7-4f48-9bc4-d5ed62410488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031191458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2031191458
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.4203325230
Short name T404
Test name
Test status
Simulation time 59980692 ps
CPU time 1.41 seconds
Started Jun 25 05:30:13 PM PDT 24
Finished Jun 25 05:30:15 PM PDT 24
Peak memory 200028 kb
Host smart-9c4b63f9-d24f-431b-b68d-42d9db0b84e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203325230 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_hmac_vectors.4203325230
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha256_vectors.2215339657
Short name T210
Test name
Test status
Simulation time 85889283178 ps
CPU time 543.02 seconds
Started Jun 25 05:30:10 PM PDT 24
Finished Jun 25 05:39:14 PM PDT 24
Peak memory 199960 kb
Host smart-ce7e2eea-6fc1-49dd-a0da-b7b22bc5276b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2215339657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha256_vectors.2215339657
Directory /workspace/44.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha384_vectors.3245681008
Short name T597
Test name
Test status
Simulation time 31472033800 ps
CPU time 1793.53 seconds
Started Jun 25 05:30:10 PM PDT 24
Finished Jun 25 06:00:05 PM PDT 24
Peak memory 216432 kb
Host smart-b14ee3a8-b36e-440f-bac4-3753b33fa66c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3245681008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha384_vectors.3245681008
Directory /workspace/44.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha512_vectors.1880861846
Short name T561
Test name
Test status
Simulation time 116595447456 ps
CPU time 2121.04 seconds
Started Jun 25 05:30:10 PM PDT 24
Finished Jun 25 06:05:33 PM PDT 24
Peak memory 215576 kb
Host smart-dd387e16-f41f-4f21-8b54-af01d5fa93e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1880861846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha512_vectors.1880861846
Directory /workspace/44.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2630411612
Short name T74
Test name
Test status
Simulation time 2421979268 ps
CPU time 34.59 seconds
Started Jun 25 05:30:13 PM PDT 24
Finished Jun 25 05:30:49 PM PDT 24
Peak memory 200060 kb
Host smart-b36b0427-6c8b-4d6c-b130-c5c758de1a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630411612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2630411612
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3042584322
Short name T181
Test name
Test status
Simulation time 25717403 ps
CPU time 0.6 seconds
Started Jun 25 05:30:12 PM PDT 24
Finished Jun 25 05:30:14 PM PDT 24
Peak memory 195756 kb
Host smart-9ede6683-536d-4b69-820e-1ada8d0e8339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042584322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3042584322
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.2442040428
Short name T419
Test name
Test status
Simulation time 1153699323 ps
CPU time 57.7 seconds
Started Jun 25 05:30:09 PM PDT 24
Finished Jun 25 05:31:08 PM PDT 24
Peak memory 199928 kb
Host smart-223b1cc0-5855-4942-9f8c-b6ceb4dcf4ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2442040428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2442040428
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.1887544440
Short name T500
Test name
Test status
Simulation time 3690795149 ps
CPU time 65.78 seconds
Started Jun 25 05:30:11 PM PDT 24
Finished Jun 25 05:31:18 PM PDT 24
Peak memory 200100 kb
Host smart-193c6507-0626-458f-80fa-527ee59f5233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887544440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1887544440
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1258219334
Short name T529
Test name
Test status
Simulation time 11355459886 ps
CPU time 764.58 seconds
Started Jun 25 05:30:12 PM PDT 24
Finished Jun 25 05:42:58 PM PDT 24
Peak memory 737160 kb
Host smart-2a9d139e-2600-4571-8a68-3ac626b10a1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1258219334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1258219334
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1686197295
Short name T208
Test name
Test status
Simulation time 2652926673 ps
CPU time 16.98 seconds
Started Jun 25 05:30:16 PM PDT 24
Finished Jun 25 05:30:33 PM PDT 24
Peak memory 200004 kb
Host smart-b14579fb-29f6-4706-b66d-de11b4f7f073
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686197295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1686197295
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.4025546247
Short name T280
Test name
Test status
Simulation time 11964022323 ps
CPU time 139.8 seconds
Started Jun 25 05:30:08 PM PDT 24
Finished Jun 25 05:32:29 PM PDT 24
Peak memory 200072 kb
Host smart-2c39149b-e307-485b-9755-bbf65e52d5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025546247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.4025546247
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3483366035
Short name T385
Test name
Test status
Simulation time 3125881036 ps
CPU time 16.99 seconds
Started Jun 25 05:30:10 PM PDT 24
Finished Jun 25 05:30:29 PM PDT 24
Peak memory 200132 kb
Host smart-db20f9df-ba3f-4f00-b77e-b22c9919b3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483366035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3483366035
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.268661703
Short name T531
Test name
Test status
Simulation time 126273190 ps
CPU time 1.06 seconds
Started Jun 25 05:30:13 PM PDT 24
Finished Jun 25 05:30:15 PM PDT 24
Peak memory 199848 kb
Host smart-655cf30a-22e9-4777-bd10-ea7b40c21ee7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268661703 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_hmac_vectors.268661703
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha256_vectors.2372740679
Short name T652
Test name
Test status
Simulation time 16737036713 ps
CPU time 459.01 seconds
Started Jun 25 05:30:15 PM PDT 24
Finished Jun 25 05:37:55 PM PDT 24
Peak memory 200036 kb
Host smart-1bea77b5-aa64-42e7-b192-557dbd37fa4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2372740679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha256_vectors.2372740679
Directory /workspace/45.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha384_vectors.3952694933
Short name T205
Test name
Test status
Simulation time 33248814718 ps
CPU time 1810.93 seconds
Started Jun 25 05:30:11 PM PDT 24
Finished Jun 25 06:00:24 PM PDT 24
Peak memory 215568 kb
Host smart-c75dd79b-7a4e-4380-be4e-31b652e947f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3952694933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha384_vectors.3952694933
Directory /workspace/45.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha512_vectors.365181895
Short name T374
Test name
Test status
Simulation time 31741662939 ps
CPU time 1769.66 seconds
Started Jun 25 05:30:11 PM PDT 24
Finished Jun 25 05:59:42 PM PDT 24
Peak memory 215988 kb
Host smart-ca0a3e63-1bb3-4096-a374-17fafa3cd4c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=365181895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha512_vectors.365181895
Directory /workspace/45.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2991050853
Short name T468
Test name
Test status
Simulation time 4137786644 ps
CPU time 47.69 seconds
Started Jun 25 05:30:10 PM PDT 24
Finished Jun 25 05:30:59 PM PDT 24
Peak memory 200168 kb
Host smart-79038fa8-d737-4ad3-8575-e820a95759a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991050853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2991050853
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3200942484
Short name T522
Test name
Test status
Simulation time 24659082 ps
CPU time 0.65 seconds
Started Jun 25 05:30:23 PM PDT 24
Finished Jun 25 05:30:25 PM PDT 24
Peak memory 196096 kb
Host smart-afc303c1-0fe9-457c-a728-5e7c33429416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200942484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3200942484
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.858234192
Short name T426
Test name
Test status
Simulation time 590942870 ps
CPU time 14.95 seconds
Started Jun 25 05:30:11 PM PDT 24
Finished Jun 25 05:30:28 PM PDT 24
Peak memory 200020 kb
Host smart-e7415480-0a08-49a2-a06b-74ea563886d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=858234192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.858234192
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.22250955
Short name T271
Test name
Test status
Simulation time 1367118083 ps
CPU time 25.84 seconds
Started Jun 25 05:30:12 PM PDT 24
Finished Jun 25 05:30:39 PM PDT 24
Peak memory 199980 kb
Host smart-c94c6869-3d48-4ec2-9e4b-bee4c5261043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22250955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.22250955
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2575720002
Short name T122
Test name
Test status
Simulation time 1359068834 ps
CPU time 307.72 seconds
Started Jun 25 05:30:10 PM PDT 24
Finished Jun 25 05:35:19 PM PDT 24
Peak memory 659732 kb
Host smart-57741091-9832-4253-ae44-dd6be9d87b8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2575720002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2575720002
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1601544870
Short name T345
Test name
Test status
Simulation time 44847060695 ps
CPU time 195.55 seconds
Started Jun 25 05:30:13 PM PDT 24
Finished Jun 25 05:33:30 PM PDT 24
Peak memory 200032 kb
Host smart-19903c36-e44c-4d0f-b032-8ced9eb5af19
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601544870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1601544870
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1112896196
Short name T418
Test name
Test status
Simulation time 5213466505 ps
CPU time 98.8 seconds
Started Jun 25 05:30:15 PM PDT 24
Finished Jun 25 05:31:55 PM PDT 24
Peak memory 200156 kb
Host smart-9d3f3075-62d8-4991-a673-31a764130955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112896196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1112896196
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.685800493
Short name T556
Test name
Test status
Simulation time 253563172 ps
CPU time 3.34 seconds
Started Jun 25 05:30:10 PM PDT 24
Finished Jun 25 05:30:15 PM PDT 24
Peak memory 200004 kb
Host smart-df80538e-2866-40d2-8000-a1db9c799f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685800493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.685800493
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.897738371
Short name T107
Test name
Test status
Simulation time 36419563 ps
CPU time 1.35 seconds
Started Jun 25 05:30:21 PM PDT 24
Finished Jun 25 05:30:24 PM PDT 24
Peak memory 200068 kb
Host smart-646892d0-82f8-4ade-bff2-d56ccb878a7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897738371 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_hmac_vectors.897738371
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha256_vectors.3049568426
Short name T417
Test name
Test status
Simulation time 27427354290 ps
CPU time 487.42 seconds
Started Jun 25 05:30:11 PM PDT 24
Finished Jun 25 05:38:19 PM PDT 24
Peak memory 200040 kb
Host smart-7ca13943-48b8-452a-9f60-d7d6bb5b7a75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3049568426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha256_vectors.3049568426
Directory /workspace/46.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha384_vectors.4167567872
Short name T183
Test name
Test status
Simulation time 133082100787 ps
CPU time 1734.98 seconds
Started Jun 25 05:30:21 PM PDT 24
Finished Jun 25 05:59:18 PM PDT 24
Peak memory 215584 kb
Host smart-ac82dafe-c305-453a-9f56-9c2c37da0343
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4167567872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha384_vectors.4167567872
Directory /workspace/46.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha512_vectors.1898122184
Short name T364
Test name
Test status
Simulation time 166357557965 ps
CPU time 2135.69 seconds
Started Jun 25 05:30:21 PM PDT 24
Finished Jun 25 06:05:58 PM PDT 24
Peak memory 215872 kb
Host smart-28c2e837-5389-416e-8763-ccd8a5ca0f38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1898122184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha512_vectors.1898122184
Directory /workspace/46.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.3818305992
Short name T363
Test name
Test status
Simulation time 10593069390 ps
CPU time 47.49 seconds
Started Jun 25 05:30:09 PM PDT 24
Finished Jun 25 05:30:57 PM PDT 24
Peak memory 200136 kb
Host smart-1d652f9a-f1cb-4f83-a249-5d68c049d9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818305992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.3818305992
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.666959939
Short name T397
Test name
Test status
Simulation time 3951514610 ps
CPU time 46.44 seconds
Started Jun 25 05:30:22 PM PDT 24
Finished Jun 25 05:31:10 PM PDT 24
Peak memory 200300 kb
Host smart-e4f2579f-55e0-4488-89b0-1ddc266434fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=666959939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.666959939
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3504697961
Short name T268
Test name
Test status
Simulation time 2161791793 ps
CPU time 33.92 seconds
Started Jun 25 05:30:19 PM PDT 24
Finished Jun 25 05:30:53 PM PDT 24
Peak memory 200108 kb
Host smart-8c89c2d3-b628-4540-b5d2-92f2fcb6336c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504697961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3504697961
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2145168686
Short name T106
Test name
Test status
Simulation time 3014421041 ps
CPU time 636.88 seconds
Started Jun 25 05:30:20 PM PDT 24
Finished Jun 25 05:40:58 PM PDT 24
Peak memory 670124 kb
Host smart-35941ab0-236e-4057-bec9-5a16bb2caf65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2145168686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2145168686
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.505635802
Short name T645
Test name
Test status
Simulation time 37276865063 ps
CPU time 232.13 seconds
Started Jun 25 05:30:20 PM PDT 24
Finished Jun 25 05:34:14 PM PDT 24
Peak memory 200092 kb
Host smart-04c91f03-ec69-42cc-b458-527b843519e6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505635802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.505635802
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.702340649
Short name T616
Test name
Test status
Simulation time 2656836206 ps
CPU time 27.31 seconds
Started Jun 25 05:30:20 PM PDT 24
Finished Jun 25 05:30:48 PM PDT 24
Peak memory 200168 kb
Host smart-925f1d04-1a41-4e57-ae95-f8fd6731002a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702340649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.702340649
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1630852683
Short name T372
Test name
Test status
Simulation time 912097980 ps
CPU time 13.04 seconds
Started Jun 25 05:30:22 PM PDT 24
Finished Jun 25 05:30:36 PM PDT 24
Peak memory 200044 kb
Host smart-69067e24-dce4-485c-a12c-831188c4e41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630852683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1630852683
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.3909340784
Short name T244
Test name
Test status
Simulation time 313639708 ps
CPU time 1.42 seconds
Started Jun 25 05:30:21 PM PDT 24
Finished Jun 25 05:30:23 PM PDT 24
Peak memory 199888 kb
Host smart-d473e6c5-07db-46fc-890f-80065aa251bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909340784 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_hmac_vectors.3909340784
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha256_vectors.4023023060
Short name T192
Test name
Test status
Simulation time 30238637212 ps
CPU time 511.74 seconds
Started Jun 25 05:30:20 PM PDT 24
Finished Jun 25 05:38:52 PM PDT 24
Peak memory 200044 kb
Host smart-04b5adbe-eff3-4bc2-a24e-b1eae0a1fa17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4023023060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha256_vectors.4023023060
Directory /workspace/47.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha384_vectors.1063645791
Short name T16
Test name
Test status
Simulation time 135576620926 ps
CPU time 1974.02 seconds
Started Jun 25 05:30:21 PM PDT 24
Finished Jun 25 06:03:17 PM PDT 24
Peak memory 215716 kb
Host smart-8e7475b1-8be2-4429-bd73-ce44d5f7edf9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1063645791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha384_vectors.1063645791
Directory /workspace/47.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha512_vectors.2075934728
Short name T610
Test name
Test status
Simulation time 227126302281 ps
CPU time 1986.55 seconds
Started Jun 25 05:30:21 PM PDT 24
Finished Jun 25 06:03:29 PM PDT 24
Peak memory 215388 kb
Host smart-3285a575-5770-4393-aa0e-e840be26f1b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2075934728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha512_vectors.2075934728
Directory /workspace/47.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.853174512
Short name T555
Test name
Test status
Simulation time 1312677675 ps
CPU time 64.59 seconds
Started Jun 25 05:30:23 PM PDT 24
Finished Jun 25 05:31:28 PM PDT 24
Peak memory 199776 kb
Host smart-cba18c42-243f-4361-92ee-ed81b8090209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853174512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.853174512
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1745056302
Short name T307
Test name
Test status
Simulation time 49131297 ps
CPU time 0.59 seconds
Started Jun 25 05:30:22 PM PDT 24
Finished Jun 25 05:30:24 PM PDT 24
Peak memory 195080 kb
Host smart-da943c62-b945-4628-afe9-f22b799590c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745056302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1745056302
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.642429932
Short name T322
Test name
Test status
Simulation time 904909599 ps
CPU time 45.64 seconds
Started Jun 25 05:30:21 PM PDT 24
Finished Jun 25 05:31:08 PM PDT 24
Peak memory 200028 kb
Host smart-56222b62-bfea-4eae-a8d2-432d271d38ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=642429932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.642429932
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1734311649
Short name T243
Test name
Test status
Simulation time 1562976809 ps
CPU time 30.2 seconds
Started Jun 25 05:30:19 PM PDT 24
Finished Jun 25 05:30:49 PM PDT 24
Peak memory 200260 kb
Host smart-7ef7be2e-79a8-4d51-8339-9b6c50ecb852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734311649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1734311649
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.12895697
Short name T2
Test name
Test status
Simulation time 2878311642 ps
CPU time 327.85 seconds
Started Jun 25 05:30:22 PM PDT 24
Finished Jun 25 05:35:51 PM PDT 24
Peak memory 663896 kb
Host smart-3eebc4b4-98b1-4a31-871d-627bd7d4d705
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=12895697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.12895697
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.122368549
Short name T132
Test name
Test status
Simulation time 3170357809 ps
CPU time 186.83 seconds
Started Jun 25 05:30:21 PM PDT 24
Finished Jun 25 05:33:29 PM PDT 24
Peak memory 200104 kb
Host smart-0ca235dd-0075-4bb0-a57c-e74cc78d4ba9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122368549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.122368549
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.94967073
Short name T257
Test name
Test status
Simulation time 6250594832 ps
CPU time 83.85 seconds
Started Jun 25 05:30:21 PM PDT 24
Finished Jun 25 05:31:46 PM PDT 24
Peak memory 216400 kb
Host smart-073bbae9-1bf6-4f30-9c14-048653a99f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94967073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.94967073
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2719044973
Short name T435
Test name
Test status
Simulation time 184986406 ps
CPU time 8.43 seconds
Started Jun 25 05:30:20 PM PDT 24
Finished Jun 25 05:30:30 PM PDT 24
Peak memory 200080 kb
Host smart-9e299754-877b-496a-855c-e65bcca56ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719044973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2719044973
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.3300214659
Short name T665
Test name
Test status
Simulation time 365640040 ps
CPU time 1.52 seconds
Started Jun 25 05:30:23 PM PDT 24
Finished Jun 25 05:30:26 PM PDT 24
Peak memory 199976 kb
Host smart-bf7587b7-266c-423b-b0a3-dd11005ee0a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300214659 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_hmac_vectors.3300214659
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha256_vectors.2607587330
Short name T250
Test name
Test status
Simulation time 32309545858 ps
CPU time 562.16 seconds
Started Jun 25 05:30:23 PM PDT 24
Finished Jun 25 05:39:46 PM PDT 24
Peak memory 200060 kb
Host smart-8d4f1b27-6e69-49d0-b49a-465b1b588d8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2607587330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha256_vectors.2607587330
Directory /workspace/48.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha384_vectors.1206558353
Short name T570
Test name
Test status
Simulation time 712105741618 ps
CPU time 2162.16 seconds
Started Jun 25 05:30:23 PM PDT 24
Finished Jun 25 06:06:27 PM PDT 24
Peak memory 215268 kb
Host smart-ff2ed408-eca7-4ca9-ba8a-bebcd5a17142
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1206558353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha384_vectors.1206558353
Directory /workspace/48.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha512_vectors.3040816567
Short name T530
Test name
Test status
Simulation time 223732618896 ps
CPU time 1989.42 seconds
Started Jun 25 05:30:24 PM PDT 24
Finished Jun 25 06:03:35 PM PDT 24
Peak memory 216400 kb
Host smart-11cda9b4-de82-4b6d-9902-253f3489dabd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3040816567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha512_vectors.3040816567
Directory /workspace/48.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1126884445
Short name T73
Test name
Test status
Simulation time 944543653 ps
CPU time 42.01 seconds
Started Jun 25 05:30:20 PM PDT 24
Finished Jun 25 05:31:02 PM PDT 24
Peak memory 200048 kb
Host smart-29eb2767-2f12-45cf-af09-6fe3f0fed70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126884445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1126884445
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.447411154
Short name T499
Test name
Test status
Simulation time 28754577 ps
CPU time 0.61 seconds
Started Jun 25 05:30:29 PM PDT 24
Finished Jun 25 05:30:31 PM PDT 24
Peak memory 195940 kb
Host smart-b5dd4383-6158-47bc-84e5-22f733480ad4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447411154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.447411154
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.4102704548
Short name T535
Test name
Test status
Simulation time 8833303653 ps
CPU time 36.3 seconds
Started Jun 25 05:30:19 PM PDT 24
Finished Jun 25 05:30:56 PM PDT 24
Peak memory 200072 kb
Host smart-50fc3778-262d-4e4b-a4f3-e233fedf6bc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4102704548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.4102704548
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.765005064
Short name T586
Test name
Test status
Simulation time 445792848 ps
CPU time 7 seconds
Started Jun 25 05:30:21 PM PDT 24
Finished Jun 25 05:30:29 PM PDT 24
Peak memory 200052 kb
Host smart-5cefd0ca-4436-4009-a448-dd65a5997e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765005064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.765005064
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1268760619
Short name T563
Test name
Test status
Simulation time 2895640284 ps
CPU time 411.22 seconds
Started Jun 25 05:30:24 PM PDT 24
Finished Jun 25 05:37:16 PM PDT 24
Peak memory 677344 kb
Host smart-a06bfaaf-d825-49c5-b195-ec98c76ffb25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1268760619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1268760619
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.977889868
Short name T501
Test name
Test status
Simulation time 3190714832 ps
CPU time 168.7 seconds
Started Jun 25 05:30:20 PM PDT 24
Finished Jun 25 05:33:09 PM PDT 24
Peak memory 200108 kb
Host smart-13c77aa8-1586-4b8f-b412-fb82fb192035
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977889868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.977889868
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3414257759
Short name T167
Test name
Test status
Simulation time 19862674227 ps
CPU time 152.83 seconds
Started Jun 25 05:30:20 PM PDT 24
Finished Jun 25 05:32:54 PM PDT 24
Peak memory 200164 kb
Host smart-d41f4f7a-f5d4-4623-bb28-c0d651390a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414257759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3414257759
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2052845802
Short name T482
Test name
Test status
Simulation time 717426689 ps
CPU time 9.04 seconds
Started Jun 25 05:30:21 PM PDT 24
Finished Jun 25 05:30:31 PM PDT 24
Peak memory 200056 kb
Host smart-7a255677-b437-40d4-95ae-b8e92e0c3bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052845802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2052845802
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.4063009340
Short name T158
Test name
Test status
Simulation time 125207549 ps
CPU time 1.18 seconds
Started Jun 25 05:30:20 PM PDT 24
Finished Jun 25 05:30:22 PM PDT 24
Peak memory 200072 kb
Host smart-cc5e3d79-94bf-4cbb-bba1-69eb331f7fd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063009340 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_hmac_vectors.4063009340
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha256_vectors.2938711596
Short name T225
Test name
Test status
Simulation time 34564790862 ps
CPU time 526.44 seconds
Started Jun 25 05:30:22 PM PDT 24
Finished Jun 25 05:39:10 PM PDT 24
Peak memory 200036 kb
Host smart-142c2ccf-b8b8-4929-8b38-ebdfd0dc34fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2938711596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha256_vectors.2938711596
Directory /workspace/49.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha384_vectors.4241502245
Short name T528
Test name
Test status
Simulation time 458844722318 ps
CPU time 2091.19 seconds
Started Jun 25 05:30:21 PM PDT 24
Finished Jun 25 06:05:14 PM PDT 24
Peak memory 215384 kb
Host smart-724f0c48-fabc-4f30-9540-a1e537ae36a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4241502245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha384_vectors.4241502245
Directory /workspace/49.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha512_vectors.3301952712
Short name T410
Test name
Test status
Simulation time 215028208236 ps
CPU time 1875.21 seconds
Started Jun 25 05:30:20 PM PDT 24
Finished Jun 25 06:01:36 PM PDT 24
Peak memory 216460 kb
Host smart-c246de6f-f2d3-47cb-916e-12e77f54dc72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3301952712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha512_vectors.3301952712
Directory /workspace/49.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3384329498
Short name T111
Test name
Test status
Simulation time 11477936404 ps
CPU time 64.15 seconds
Started Jun 25 05:30:24 PM PDT 24
Finished Jun 25 05:31:29 PM PDT 24
Peak memory 199844 kb
Host smart-b9fbdec7-c1c1-4920-9870-1781dfcd248a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384329498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3384329498
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3926613341
Short name T365
Test name
Test status
Simulation time 16673417 ps
CPU time 0.61 seconds
Started Jun 25 05:28:56 PM PDT 24
Finished Jun 25 05:28:59 PM PDT 24
Peak memory 196868 kb
Host smart-eb34da0d-6789-488c-b5e3-1a8eed278c4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926613341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3926613341
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1429319558
Short name T628
Test name
Test status
Simulation time 232924432 ps
CPU time 12.43 seconds
Started Jun 25 05:29:02 PM PDT 24
Finished Jun 25 05:29:16 PM PDT 24
Peak memory 199968 kb
Host smart-cf054399-58cd-4707-a800-afc81744709b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1429319558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1429319558
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3326143325
Short name T408
Test name
Test status
Simulation time 676064262 ps
CPU time 35.94 seconds
Started Jun 25 05:28:57 PM PDT 24
Finished Jun 25 05:29:34 PM PDT 24
Peak memory 200080 kb
Host smart-131ad7ae-e99b-4758-ba8d-7e2a17b7fe83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326143325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3326143325
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.100305557
Short name T313
Test name
Test status
Simulation time 931519010 ps
CPU time 120.69 seconds
Started Jun 25 05:28:59 PM PDT 24
Finished Jun 25 05:31:01 PM PDT 24
Peak memory 444084 kb
Host smart-9097e31b-d0f3-4007-8433-0af56229c5a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100305557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.100305557
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3019255363
Short name T544
Test name
Test status
Simulation time 1769063465 ps
CPU time 50.38 seconds
Started Jun 25 05:29:06 PM PDT 24
Finished Jun 25 05:29:57 PM PDT 24
Peak memory 199968 kb
Host smart-0f7c596d-a4b0-4407-85d4-d4ea10147cb8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019255363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3019255363
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.890972472
Short name T549
Test name
Test status
Simulation time 12604039365 ps
CPU time 119.22 seconds
Started Jun 25 05:29:15 PM PDT 24
Finished Jun 25 05:31:17 PM PDT 24
Peak memory 200160 kb
Host smart-90b88be7-5e06-4ccb-b94c-9eddb185a7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890972472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.890972472
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3401823015
Short name T304
Test name
Test status
Simulation time 117378474 ps
CPU time 5.23 seconds
Started Jun 25 05:28:57 PM PDT 24
Finished Jun 25 05:29:04 PM PDT 24
Peak memory 200040 kb
Host smart-eaca43ea-5724-4fb5-8878-1d919c649c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401823015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3401823015
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.866249155
Short name T644
Test name
Test status
Simulation time 63673892464 ps
CPU time 1990.62 seconds
Started Jun 25 05:28:53 PM PDT 24
Finished Jun 25 06:02:05 PM PDT 24
Peak memory 778616 kb
Host smart-885f4ed0-00e1-47bd-904b-afb606683aeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866249155 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.866249155
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.4114383511
Short name T545
Test name
Test status
Simulation time 526209418 ps
CPU time 1.41 seconds
Started Jun 25 05:29:11 PM PDT 24
Finished Jun 25 05:29:14 PM PDT 24
Peak memory 199992 kb
Host smart-3fe03115-26e3-42ed-831f-dbc15a1a5fc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114383511 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_hmac_vectors.4114383511
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha256_vectors.2308556451
Short name T460
Test name
Test status
Simulation time 215378287377 ps
CPU time 522.62 seconds
Started Jun 25 05:28:56 PM PDT 24
Finished Jun 25 05:37:39 PM PDT 24
Peak memory 199932 kb
Host smart-f782d502-eda3-43d6-9fa8-029c26878008
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2308556451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha256_vectors.2308556451
Directory /workspace/5.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha384_vectors.2067991782
Short name T631
Test name
Test status
Simulation time 302790032681 ps
CPU time 2152.94 seconds
Started Jun 25 05:29:09 PM PDT 24
Finished Jun 25 06:05:03 PM PDT 24
Peak memory 215504 kb
Host smart-2051844b-c8dc-4501-8a23-5183b6bc67b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2067991782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha384_vectors.2067991782
Directory /workspace/5.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha512_vectors.2806426985
Short name T349
Test name
Test status
Simulation time 155237236516 ps
CPU time 1980.14 seconds
Started Jun 25 05:29:07 PM PDT 24
Finished Jun 25 06:02:08 PM PDT 24
Peak memory 216436 kb
Host smart-8b73c82e-78d6-4646-a223-ef879e1ac0bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2806426985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha512_vectors.2806426985
Directory /workspace/5.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2341696826
Short name T269
Test name
Test status
Simulation time 2566267233 ps
CPU time 34 seconds
Started Jun 25 05:28:56 PM PDT 24
Finished Jun 25 05:29:31 PM PDT 24
Peak memory 200128 kb
Host smart-1802020a-3d1e-4aa9-919f-4ad40ca04b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341696826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2341696826
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1082096902
Short name T274
Test name
Test status
Simulation time 13105630 ps
CPU time 0.6 seconds
Started Jun 25 05:29:05 PM PDT 24
Finished Jun 25 05:29:07 PM PDT 24
Peak memory 195028 kb
Host smart-5464b13a-ef8c-4234-8887-ab3198363593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082096902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1082096902
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.471525211
Short name T380
Test name
Test status
Simulation time 2497306436 ps
CPU time 42.9 seconds
Started Jun 25 05:29:10 PM PDT 24
Finished Jun 25 05:29:54 PM PDT 24
Peak memory 200104 kb
Host smart-6e45c481-4e2e-4ef3-bd33-2e98d42811d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=471525211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.471525211
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3308351673
Short name T496
Test name
Test status
Simulation time 4689902921 ps
CPU time 57.85 seconds
Started Jun 25 05:29:02 PM PDT 24
Finished Jun 25 05:30:02 PM PDT 24
Peak memory 200036 kb
Host smart-4e9c4845-de33-470f-bd1b-aeee4599f2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308351673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3308351673
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1160574361
Short name T228
Test name
Test status
Simulation time 654314537 ps
CPU time 178.91 seconds
Started Jun 25 05:28:58 PM PDT 24
Finished Jun 25 05:31:59 PM PDT 24
Peak memory 485260 kb
Host smart-bf04be75-7eaa-4c73-b240-bc668d9a0527
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1160574361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1160574361
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.814189526
Short name T328
Test name
Test status
Simulation time 17262090616 ps
CPU time 129.25 seconds
Started Jun 25 05:29:09 PM PDT 24
Finished Jun 25 05:31:20 PM PDT 24
Peak memory 200120 kb
Host smart-99ae85fd-d069-424a-9126-b9787d762905
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814189526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.814189526
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.4138580775
Short name T478
Test name
Test status
Simulation time 1348035175 ps
CPU time 78.26 seconds
Started Jun 25 05:28:58 PM PDT 24
Finished Jun 25 05:30:18 PM PDT 24
Peak memory 200112 kb
Host smart-cab92da0-85a5-404b-838a-cb48e685e41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138580775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.4138580775
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2946065915
Short name T67
Test name
Test status
Simulation time 20904265 ps
CPU time 0.66 seconds
Started Jun 25 05:29:02 PM PDT 24
Finished Jun 25 05:29:15 PM PDT 24
Peak memory 195760 kb
Host smart-99724d13-5ed8-4621-b48a-4767de149a14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946065915 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2946065915
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.2632848229
Short name T603
Test name
Test status
Simulation time 178151610 ps
CPU time 1.13 seconds
Started Jun 25 05:28:54 PM PDT 24
Finished Jun 25 05:28:56 PM PDT 24
Peak memory 199896 kb
Host smart-b429b488-eada-470e-9ce3-84bd99821818
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632848229 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_hmac_vectors.2632848229
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha256_vectors.3071278487
Short name T29
Test name
Test status
Simulation time 23084046247 ps
CPU time 394.48 seconds
Started Jun 25 05:29:01 PM PDT 24
Finished Jun 25 05:35:38 PM PDT 24
Peak memory 200076 kb
Host smart-ac94cf86-ea8e-4529-964f-1f4e3e58c907
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3071278487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha256_vectors.3071278487
Directory /workspace/6.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha384_vectors.2221497867
Short name T27
Test name
Test status
Simulation time 654517160801 ps
CPU time 1946.86 seconds
Started Jun 25 05:29:03 PM PDT 24
Finished Jun 25 06:01:31 PM PDT 24
Peak memory 208404 kb
Host smart-b7441194-77de-4dbd-8c66-82850edf60ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2221497867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha384_vectors.2221497867
Directory /workspace/6.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha512_vectors.3104416175
Short name T524
Test name
Test status
Simulation time 217258756357 ps
CPU time 1644.05 seconds
Started Jun 25 05:28:59 PM PDT 24
Finished Jun 25 05:56:25 PM PDT 24
Peak memory 216344 kb
Host smart-32e0240d-9112-4e2c-8293-b03495862308
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3104416175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha512_vectors.3104416175
Directory /workspace/6.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.3296618006
Short name T497
Test name
Test status
Simulation time 8799882055 ps
CPU time 36.15 seconds
Started Jun 25 05:28:59 PM PDT 24
Finished Jun 25 05:29:37 PM PDT 24
Peak memory 200096 kb
Host smart-55645c1e-fb7c-4b6d-98b7-cb4a0dc5436e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296618006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3296618006
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.954409504
Short name T195
Test name
Test status
Simulation time 57757511 ps
CPU time 0.59 seconds
Started Jun 25 05:29:10 PM PDT 24
Finished Jun 25 05:29:12 PM PDT 24
Peak memory 196788 kb
Host smart-8974804c-1f07-4ecb-ba66-2e699b34ace2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954409504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.954409504
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.738782608
Short name T617
Test name
Test status
Simulation time 1444844171 ps
CPU time 33.04 seconds
Started Jun 25 05:29:02 PM PDT 24
Finished Jun 25 05:29:37 PM PDT 24
Peak memory 200008 kb
Host smart-9f04fe67-4e83-460e-9af3-7354102bf82f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=738782608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.738782608
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2730522211
Short name T392
Test name
Test status
Simulation time 15963044223 ps
CPU time 27.16 seconds
Started Jun 25 05:29:05 PM PDT 24
Finished Jun 25 05:29:33 PM PDT 24
Peak memory 200128 kb
Host smart-e6cef80f-1c19-43d9-904f-5475013d522f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730522211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2730522211
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.316352702
Short name T660
Test name
Test status
Simulation time 2350644434 ps
CPU time 566.47 seconds
Started Jun 25 05:28:55 PM PDT 24
Finished Jun 25 05:38:23 PM PDT 24
Peak memory 631472 kb
Host smart-5921981a-7778-449f-b42b-09574a803ddd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=316352702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.316352702
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2611378168
Short name T405
Test name
Test status
Simulation time 6086526529 ps
CPU time 81.79 seconds
Started Jun 25 05:29:00 PM PDT 24
Finished Jun 25 05:30:24 PM PDT 24
Peak memory 200344 kb
Host smart-18887e3e-d092-4992-8f67-5efb6815c4e6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611378168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2611378168
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.545163208
Short name T454
Test name
Test status
Simulation time 6739099869 ps
CPU time 67.06 seconds
Started Jun 25 05:28:56 PM PDT 24
Finished Jun 25 05:30:05 PM PDT 24
Peak memory 208320 kb
Host smart-04bc9a4b-54f4-4e50-ae9c-dd8f4854179e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545163208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.545163208
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1440565049
Short name T186
Test name
Test status
Simulation time 1443424227 ps
CPU time 10.21 seconds
Started Jun 25 05:29:03 PM PDT 24
Finished Jun 25 05:29:15 PM PDT 24
Peak memory 200024 kb
Host smart-5de14b73-f356-4057-bf75-b0e014d7764a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440565049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1440565049
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.2702148882
Short name T287
Test name
Test status
Simulation time 32986062 ps
CPU time 1.34 seconds
Started Jun 25 05:29:07 PM PDT 24
Finished Jun 25 05:29:10 PM PDT 24
Peak memory 200008 kb
Host smart-c72dff10-b1e5-4813-8503-0fd707354cf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702148882 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_hmac_vectors.2702148882
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha256_vectors.3920707503
Short name T658
Test name
Test status
Simulation time 16486117377 ps
CPU time 448.12 seconds
Started Jun 25 05:28:58 PM PDT 24
Finished Jun 25 05:36:28 PM PDT 24
Peak memory 200040 kb
Host smart-69ba3dc1-ea48-4525-b49d-d6660554dd3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3920707503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha256_vectors.3920707503
Directory /workspace/7.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha384_vectors.3515459101
Short name T599
Test name
Test status
Simulation time 100967707186 ps
CPU time 1870.23 seconds
Started Jun 25 05:29:05 PM PDT 24
Finished Jun 25 06:00:17 PM PDT 24
Peak memory 216304 kb
Host smart-899e2187-1d07-4fb5-a115-31f9e8fe57b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3515459101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha384_vectors.3515459101
Directory /workspace/7.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha512_vectors.2816803108
Short name T515
Test name
Test status
Simulation time 95296231328 ps
CPU time 1662.32 seconds
Started Jun 25 05:28:57 PM PDT 24
Finished Jun 25 05:56:41 PM PDT 24
Peak memory 216048 kb
Host smart-e921c9fa-6b3a-4985-b808-93ee26f6a353
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2816803108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha512_vectors.2816803108
Directory /workspace/7.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.746641284
Short name T283
Test name
Test status
Simulation time 19697675831 ps
CPU time 72 seconds
Started Jun 25 05:28:59 PM PDT 24
Finished Jun 25 05:30:13 PM PDT 24
Peak memory 200148 kb
Host smart-45ed3a20-48b6-4cc1-9bf9-6d185cabb2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746641284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.746641284
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3037755940
Short name T420
Test name
Test status
Simulation time 39583196 ps
CPU time 0.58 seconds
Started Jun 25 05:28:59 PM PDT 24
Finished Jun 25 05:29:02 PM PDT 24
Peak memory 195760 kb
Host smart-d9d8bff3-9981-4a0e-a822-f609b9e3446a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037755940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3037755940
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.217973892
Short name T481
Test name
Test status
Simulation time 14214666399 ps
CPU time 36.92 seconds
Started Jun 25 05:28:55 PM PDT 24
Finished Jun 25 05:29:33 PM PDT 24
Peak memory 200104 kb
Host smart-b92e0836-bbfe-4e5e-911c-423617d2b749
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=217973892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.217973892
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2265150746
Short name T305
Test name
Test status
Simulation time 18114868317 ps
CPU time 53.91 seconds
Started Jun 25 05:29:08 PM PDT 24
Finished Jun 25 05:30:03 PM PDT 24
Peak memory 200120 kb
Host smart-bd3a9bb2-f84d-4d6e-804c-e919530e7a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265150746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2265150746
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_error.299722021
Short name T546
Test name
Test status
Simulation time 5891294714 ps
CPU time 83.82 seconds
Started Jun 25 05:28:56 PM PDT 24
Finished Jun 25 05:30:22 PM PDT 24
Peak memory 200136 kb
Host smart-e18d9aab-1701-484b-a979-74039964deba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299722021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.299722021
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.2474127409
Short name T457
Test name
Test status
Simulation time 7957071656 ps
CPU time 54.02 seconds
Started Jun 25 05:29:05 PM PDT 24
Finished Jun 25 05:30:00 PM PDT 24
Peak memory 200104 kb
Host smart-b80697cd-2fe8-4310-a843-2a211aa42d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474127409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2474127409
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1234900312
Short name T184
Test name
Test status
Simulation time 775369466 ps
CPU time 5.35 seconds
Started Jun 25 05:28:58 PM PDT 24
Finished Jun 25 05:29:06 PM PDT 24
Peak memory 199972 kb
Host smart-ea548d8c-45d9-4359-8f2e-1658ecfcf375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234900312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1234900312
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.1594909617
Short name T238
Test name
Test status
Simulation time 29156536 ps
CPU time 1.06 seconds
Started Jun 25 05:29:13 PM PDT 24
Finished Jun 25 05:29:17 PM PDT 24
Peak memory 199936 kb
Host smart-430b9351-a181-473f-bb08-de9d720bfa11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594909617 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_hmac_vectors.1594909617
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha256_vectors.1893853131
Short name T321
Test name
Test status
Simulation time 19063258441 ps
CPU time 494.54 seconds
Started Jun 25 05:28:57 PM PDT 24
Finished Jun 25 05:37:19 PM PDT 24
Peak memory 200024 kb
Host smart-780e0a47-aac4-4421-b96b-12f3071d8a38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1893853131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha256_vectors.1893853131
Directory /workspace/8.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha384_vectors.2353721478
Short name T647
Test name
Test status
Simulation time 67522096903 ps
CPU time 1834.48 seconds
Started Jun 25 05:29:01 PM PDT 24
Finished Jun 25 05:59:38 PM PDT 24
Peak memory 216080 kb
Host smart-497c0898-e6d6-42fb-b48c-53e47f4cf7ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2353721478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha384_vectors.2353721478
Directory /workspace/8.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha512_vectors.1877242295
Short name T315
Test name
Test status
Simulation time 167733415843 ps
CPU time 2008.63 seconds
Started Jun 25 05:29:00 PM PDT 24
Finished Jun 25 06:02:31 PM PDT 24
Peak memory 215732 kb
Host smart-4b3c1c19-6212-465c-aff2-fc45098766b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1877242295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha512_vectors.1877242295
Directory /workspace/8.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.425880700
Short name T114
Test name
Test status
Simulation time 818954688 ps
CPU time 13.77 seconds
Started Jun 25 05:29:07 PM PDT 24
Finished Jun 25 05:29:22 PM PDT 24
Peak memory 199972 kb
Host smart-f8adf11d-3301-44b9-a979-ce0aa0fa39fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425880700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.425880700
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2239591464
Short name T635
Test name
Test status
Simulation time 12585370 ps
CPU time 0.61 seconds
Started Jun 25 05:29:03 PM PDT 24
Finished Jun 25 05:29:05 PM PDT 24
Peak memory 196196 kb
Host smart-93c4bde4-08b4-4815-a5fc-0f23153422df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239591464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2239591464
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2944200466
Short name T484
Test name
Test status
Simulation time 955661835 ps
CPU time 36.45 seconds
Started Jun 25 05:29:11 PM PDT 24
Finished Jun 25 05:29:48 PM PDT 24
Peak memory 199984 kb
Host smart-b32c9647-9ede-49ad-bc3b-7166f546e5bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2944200466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2944200466
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.4248658833
Short name T125
Test name
Test status
Simulation time 710044334 ps
CPU time 36.91 seconds
Started Jun 25 05:29:12 PM PDT 24
Finished Jun 25 05:29:51 PM PDT 24
Peak memory 200060 kb
Host smart-cec4548f-5549-47b6-8c9e-c46963b05708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248658833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.4248658833
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_error.2654646389
Short name T596
Test name
Test status
Simulation time 3036057203 ps
CPU time 26.58 seconds
Started Jun 25 05:28:51 PM PDT 24
Finished Jun 25 05:29:18 PM PDT 24
Peak memory 200008 kb
Host smart-c5e289f2-90c5-40c7-8fca-db5da5a516ed
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654646389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2654646389
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3875717233
Short name T179
Test name
Test status
Simulation time 4721291674 ps
CPU time 50.04 seconds
Started Jun 25 05:29:08 PM PDT 24
Finished Jun 25 05:29:59 PM PDT 24
Peak memory 200152 kb
Host smart-8334dfe4-b3ba-4e6b-899c-6ee34c8df0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875717233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3875717233
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.669540995
Short name T564
Test name
Test status
Simulation time 1163761193 ps
CPU time 8.84 seconds
Started Jun 25 05:29:12 PM PDT 24
Finished Jun 25 05:29:23 PM PDT 24
Peak memory 200048 kb
Host smart-d058f586-8cc9-455a-8074-903f323d5cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669540995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.669540995
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.3099737269
Short name T277
Test name
Test status
Simulation time 115187535 ps
CPU time 1.37 seconds
Started Jun 25 05:29:09 PM PDT 24
Finished Jun 25 05:29:12 PM PDT 24
Peak memory 199956 kb
Host smart-f42465c3-3ea5-4f2b-a71b-065c18ecbf52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099737269 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_hmac_vectors.3099737269
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha256_vectors.1720232073
Short name T206
Test name
Test status
Simulation time 34204873645 ps
CPU time 441.4 seconds
Started Jun 25 05:29:11 PM PDT 24
Finished Jun 25 05:36:34 PM PDT 24
Peak memory 200020 kb
Host smart-d3c666b9-fccf-4907-9265-67ad8a528cc8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1720232073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha256_vectors.1720232073
Directory /workspace/9.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha384_vectors.476555478
Short name T413
Test name
Test status
Simulation time 599056606997 ps
CPU time 2197.73 seconds
Started Jun 25 05:29:00 PM PDT 24
Finished Jun 25 06:05:41 PM PDT 24
Peak memory 215940 kb
Host smart-95f864b8-2376-410c-b672-e1c4909e19f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=476555478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha384_vectors.476555478
Directory /workspace/9.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha512_vectors.670805421
Short name T639
Test name
Test status
Simulation time 477392892897 ps
CPU time 1998.44 seconds
Started Jun 25 05:29:02 PM PDT 24
Finished Jun 25 06:02:23 PM PDT 24
Peak memory 215936 kb
Host smart-fdd76708-8a5d-4a8c-b56d-064db09e4430
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=670805421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha512_vectors.670805421
Directory /workspace/9.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1053784186
Short name T502
Test name
Test status
Simulation time 1671920204 ps
CPU time 21.98 seconds
Started Jun 25 05:28:58 PM PDT 24
Finished Jun 25 05:29:22 PM PDT 24
Peak memory 199996 kb
Host smart-a83ab89c-4db5-4446-b19e-2ed454c49ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053784186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1053784186
Directory /workspace/9.hmac_wipe_secret/latest
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