Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	34709993	1			T1	13719		T2	293545		T3	992
all_values[1]	34709993	1			T1	13719		T2	293545		T3	992
all_values[2]	34709993	1			T1	13719		T2	293545		T3	992

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56557

1

T5

2

T114

2

T13

196

auto[1]

104073422

1

T1

41157

T2

880635

T3

2976

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86452834

1

T1

36318

T2

734965

T3

1993

auto[1]

17677145

1

T1

4839

T2

145670

T3

983

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	23255	1			T16	13		T35	20		T14	33
all_values[0]	auto[0]	auto[1]	176	1			T14	2		T30	2		T20	2
all_values[0]	auto[1]	auto[0]	34634635	1			T1	13687		T2	293159		T3	991
all_values[0]	auto[1]	auto[1]	51927	1			T1	32		T2	386		T3	1
all_values[1]	auto[0]	auto[0]	16031	1			T5	2		T132	37		T128	39
all_values[1]	auto[0]	auto[1]	173	1			T19	42		T81	34		T111	1
all_values[1]	auto[1]	auto[0]	34690693	1			T1	13719		T2	293545		T3	992
all_values[1]	auto[1]	auto[1]	3096	1			T5	42		T6	84		T14	2
all_values[2]	auto[0]	auto[0]	6422	1			T114	2		T13	196		T14	35
all_values[2]	auto[0]	auto[1]	10500	1			T29	2		T105	302		T48	1
all_values[2]	auto[1]	auto[0]	17081798	1			T1	8912		T2	148261		T3	10
all_values[2]	auto[1]	auto[1]	17611273	1			T1	4807		T2	145284		T3	982