Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	2	16	88.89
Crosses	32	9	23	71.88

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	1	14	93.33	100	1	1	0
msg_len_upper_cp	1	1	0	0.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	7	23	76.67	100	1	1	0
msg_len_upper_cross	2	2	0	0.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

92556

1

T1

30

T2

372

T3

4

auto[1]

46270

1

T1

36

T5

8

T15

6

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	1	14	93.33

User Defined Bins for msg_len_lower_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_511	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	22462	1			T1	19		T2	49		T4	25
len_1026_2046	14292	1			T1	10		T2	6		T5	1
len_514_1022	4049	1			T1	2		T2	2		T5	1
len_2_510	22281	1			T1	1		T2	126		T5	2
len_2049	5	1			T126	1		T127	1		T61	2
len_2048	20	1			T128	2		T129	1		T38	1
len_2047	1	1			T130	1		-	-		-	-
len_1025	1	1			T131	1		-	-		-	-
len_1024	34	1			T14	1		T132	1		T128	4
len_1023	1	1			T133	1		-	-		-	-
len_513	1	1			T134	1		-	-		-	-
len_512	51	1			T26	1		T14	1		T27	2
len_1	652	1			T2	2		T9	1		T10	1
len_0	5563	1			T1	1		T2	1		T3	2

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for msg_len_upper_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_upper	0	1	1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	7	23	76.67	7

Automatically Generated Cross Bins for msg_len_lower_cross

Uncovered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[len_2049]	0	1	1
[auto[0]]	[len_2047]	0	1	1
[auto[0]]	[len_513]	0	1	1
[auto[0]]	[len_511]	0	1	1
[auto[1]]	[len_1025]	0	1	1
[auto[1]]	[len_1023]	0	1	1
[auto[1]]	[len_511]	0	1	1

Covered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	15313	1			T1	7		T2	49		T4	25
auto[0]	len_1026_2046	7280	1			T1	5		T2	6		T4	4
auto[0]	len_514_1022	2647	1			T1	2		T2	2		T5	1
auto[0]	len_2_510	18817	1			T1	1		T2	126		T4	67
auto[0]	len_2048	12	1			T128	1		T129	1		T135	2
auto[0]	len_1025	1	1			T131	1		-	-		-	-
auto[0]	len_1024	19	1			T132	1		T128	2		T136	1
auto[0]	len_1023	1	1			T133	1		-	-		-	-
auto[0]	len_512	32	1			T26	1		T27	1		T137	1
auto[0]	len_1	136	1			T2	2		T9	1		T10	1
auto[0]	len_0	2020	1			T2	1		T3	2		T5	2
auto[1]	len_2050_plus	7149	1			T1	12		T6	12		T13	4
auto[1]	len_1026_2046	7012	1			T1	5		T5	1		T6	9
auto[1]	len_514_1022	1402	1			T14	18		T7	4		T27	52
auto[1]	len_2_510	3464	1			T5	2		T15	3		T6	2
auto[1]	len_2049	5	1			T126	1		T127	1		T61	2
auto[1]	len_2048	8	1			T128	1		T38	1		T138	1
auto[1]	len_2047	1	1			T130	1		-	-		-	-
auto[1]	len_1024	15	1			T14	1		T128	2		T137	1
auto[1]	len_513	1	1			T134	1		-	-		-	-
auto[1]	len_512	19	1			T14	1		T27	1		T128	1
auto[1]	len_1	516	1			T28	7		T29	16		T139	8
auto[1]	len_0	3543	1			T1	1		T5	1		T26	9

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	2	0	0.00	2

Automatically Generated Cross Bins for msg_len_upper_cross

Uncovered bins

hmac_en	msg_len_upper_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	2