Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17187870

1

T1

5772

T2

147874

T3

5

auto[1]

1307621

1

T1

7701

T3

2

T5

3

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1243576

1

T1

8089

T3

6

T5

7

auto[1]

17251915

1

T1

5384

T2

147874

T3

1

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16593417

1

T1

5096

T2

147874

T3

5

auto[1]

1902074

1

T1

8377

T3

2

T5

3

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	16034960	1			T1	9535		T2	141850		T3	7
fifo_depth[1]	495255	1			T1	358		T2	3351		T4	877
fifo_depth[2]	381760	1			T1	364		T2	1621		T4	246
fifo_depth[3]	307014	1			T1	383		T2	683		T4	70
fifo_depth[4]	240473	1			T1	373		T2	243		T4	13
fifo_depth[5]	189080	1			T1	362		T2	89		T4	2
fifo_depth[6]	163941	1			T1	384		T2	28		T10	1082
fifo_depth[7]	147104	1			T1	340		T2	7		T10	775

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2460531

1

T1

3938

T2

6024

T5

3

auto[1]

16034960

1

T1

9535

T2

141850

T3

7

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18491627

1

T1

13473

T2

147874

T3

7

auto[1]

3864

1

T6

1

T14

70

T132

120

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

31204

1

T1

552

T6

3

T114

146

auto[0]

auto[0]

auto[0]

auto[1]

34211

1

T1

245

T5

1

T6

4

auto[0]

auto[0]

auto[1]

auto[0]

2077735

1

T1

334

T2

6024

T4

1208

auto[0]

auto[0]

auto[1]

auto[1]

43501

1

T1

575

T6

3

T26

66

auto[0]

auto[1]

auto[0]

auto[0]

66559

1

T1

209

T5

2

T6

2

auto[0]

auto[1]

auto[0]

auto[1]

52820

1

T1

1142

T6

4

T35

563

auto[0]

auto[1]

auto[1]

auto[0]

71569

1

T1

329

T15

10

T6

1

auto[0]

auto[1]

auto[1]

auto[1]

82932

1

T1

552

T6

5

T13

19

auto[1]

auto[0]

auto[0]

auto[0]

141402

1

T1

1368

T3

4

T5

2

auto[1]

auto[0]

auto[0]

auto[1]

132847

1

T1

603

T3

1

T5

1

auto[1]

auto[0]

auto[1]

auto[0]

13995424

1

T1

546

T2

141850

T4

36088

auto[1]

auto[0]

auto[1]

auto[1]

137093

1

T1

873

T5

1

T6

1

auto[1]

auto[1]

auto[0]

auto[0]

377395

1

T1

1958

T5

1

T6

4

auto[1]

auto[1]

auto[0]

auto[1]

407138

1

T1

2012

T3

1

T6

6

auto[1]

auto[1]

auto[1]

auto[0]

426582

1

T1

476

T3

1

T15

18

auto[1]

auto[1]

auto[1]

auto[1]

417079

1

T1

1699

T6

7

T26

50

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

172288

1

T1

1920

T3

4

T5

2

auto[0]

auto[0]

auto[0]

auto[1]

165666

1

T1

848

T3

1

T5

2

auto[0]

auto[0]

auto[1]

auto[0]

16072572

1

T1

880

T2

147874

T4

37296

auto[0]

auto[0]

auto[1]

auto[1]

179745

1

T1

1448

T5

1

T6

4

auto[0]

auto[1]

auto[0]

auto[0]

443907

1

T1

2167

T5

3

T6

5

auto[0]

auto[1]

auto[0]

auto[1]

459877

1

T1

3154

T3

1

T6

10

auto[0]

auto[1]

auto[1]

auto[0]

497789

1

T1

805

T3

1

T15

28

auto[0]

auto[1]

auto[1]

auto[1]

499783

1

T1

2251

T6

12

T26

50

auto[1]

auto[0]

auto[0]

auto[0]

318

1

T14

31

T137

7

T25

1

auto[1]

auto[0]

auto[0]

auto[1]

1392

1

T14

5

T137

57

T136

47

auto[1]

auto[0]

auto[1]

auto[0]

587

1

T14

16

T132

100

T137

28

auto[1]

auto[0]

auto[1]

auto[1]

849

1

T14

16

T132

8

T19

1

auto[1]

auto[1]

auto[0]

auto[0]

47

1

T6

1

T14

2

T19

1

auto[1]

auto[1]

auto[0]

auto[1]

81

1

T131

18

T81

1

T111

19

auto[1]

auto[1]

auto[1]

auto[0]

362

1

T132

12

T137

168

T155

1

auto[1]

auto[1]

auto[1]

auto[1]

228

1

T19

1

T137

54

T156

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	141402	1			T1	1368		T3	4		T5	2
fifo_depth[0]	auto[0]	auto[0]	auto[1]	132847	1			T1	603		T3	1		T5	1
fifo_depth[0]	auto[0]	auto[1]	auto[0]	13995424	1			T1	546		T2	141850		T4	36088
fifo_depth[0]	auto[0]	auto[1]	auto[1]	137093	1			T1	873		T5	1		T6	1
fifo_depth[0]	auto[1]	auto[0]	auto[0]	377395	1			T1	1958		T5	1		T6	4
fifo_depth[0]	auto[1]	auto[0]	auto[1]	407138	1			T1	2012		T3	1		T6	6
fifo_depth[0]	auto[1]	auto[1]	auto[0]	426582	1			T1	476		T3	1		T15	18
fifo_depth[0]	auto[1]	auto[1]	auto[1]	417079	1			T1	1699		T6	7		T26	50
fifo_depth[1]	auto[0]	auto[0]	auto[0]	4060	1			T1	47		T114	11		T35	16
fifo_depth[1]	auto[0]	auto[0]	auto[1]	3565	1			T1	24		T13	7		T35	92
fifo_depth[1]	auto[0]	auto[1]	auto[0]	455994	1			T1	27		T2	3351		T4	877
fifo_depth[1]	auto[0]	auto[1]	auto[1]	3487	1			T1	58		T26	12		T13	12
fifo_depth[1]	auto[1]	auto[0]	auto[0]	6663	1			T1	14		T16	6		T14	9
fifo_depth[1]	auto[1]	auto[0]	auto[1]	5474	1			T1	102		T35	58		T27	2
fifo_depth[1]	auto[1]	auto[1]	auto[0]	7200	1			T1	29		T15	2		T13	59
fifo_depth[1]	auto[1]	auto[1]	auto[1]	8812	1			T1	57		T13	9		T16	3
fifo_depth[2]	auto[0]	auto[0]	auto[0]	3150	1			T1	45		T114	14		T16	1
fifo_depth[2]	auto[0]	auto[0]	auto[1]	3236	1			T1	16		T13	3		T35	96
fifo_depth[2]	auto[0]	auto[1]	auto[0]	345933	1			T1	35		T2	1621		T4	246
fifo_depth[2]	auto[0]	auto[1]	auto[1]	3043	1			T1	54		T26	15		T13	5
fifo_depth[2]	auto[1]	auto[0]	auto[0]	6580	1			T1	17		T16	3		T14	6
fifo_depth[2]	auto[1]	auto[0]	auto[1]	5114	1			T1	121		T35	51		T28	101
fifo_depth[2]	auto[1]	auto[1]	auto[0]	6615	1			T1	28		T15	3		T13	33
fifo_depth[2]	auto[1]	auto[1]	auto[1]	8089	1			T1	48		T13	6		T16	1
fifo_depth[3]	auto[0]	auto[0]	auto[0]	2397	1			T1	43		T114	12		T35	14
fifo_depth[3]	auto[0]	auto[0]	auto[1]	2383	1			T1	24		T26	2		T16	1
fifo_depth[3]	auto[0]	auto[1]	auto[0]	275948	1			T1	28		T2	683		T4	70
fifo_depth[3]	auto[0]	auto[1]	auto[1]	2372	1			T1	63		T26	12		T13	2
fifo_depth[3]	auto[1]	auto[0]	auto[0]	5785	1			T1	18		T14	11		T27	6
fifo_depth[3]	auto[1]	auto[0]	auto[1]	4586	1			T1	125		T35	55		T27	1
fifo_depth[3]	auto[1]	auto[1]	auto[0]	6185	1			T1	28		T15	2		T13	12
fifo_depth[3]	auto[1]	auto[1]	auto[1]	7358	1			T1	54		T13	4		T35	17
fifo_depth[4]	auto[0]	auto[0]	auto[0]	2132	1			T1	55		T114	11		T35	12
fifo_depth[4]	auto[0]	auto[0]	auto[1]	2352	1			T1	23		T26	20		T35	106
fifo_depth[4]	auto[0]	auto[1]	auto[0]	211051	1			T1	29		T2	243		T4	13
fifo_depth[4]	auto[0]	auto[1]	auto[1]	2060	1			T1	47		T26	11		T13	4
fifo_depth[4]	auto[1]	auto[0]	auto[0]	5715	1			T1	22		T16	1		T14	35
fifo_depth[4]	auto[1]	auto[0]	auto[1]	4344	1			T1	106		T35	60		T27	12
fifo_depth[4]	auto[1]	auto[1]	auto[0]	5839	1			T1	35		T15	1		T13	3
fifo_depth[4]	auto[1]	auto[1]	auto[1]	6980	1			T1	56		T35	24		T27	3
fifo_depth[5]	auto[0]	auto[0]	auto[0]	1761	1			T1	38		T114	14		T35	12
fifo_depth[5]	auto[0]	auto[0]	auto[1]	1755	1			T1	17		T26	1		T35	110
fifo_depth[5]	auto[0]	auto[1]	auto[0]	162024	1			T1	35		T2	89		T4	2
fifo_depth[5]	auto[0]	auto[1]	auto[1]	1723	1			T1	64		T26	11		T14	17
fifo_depth[5]	auto[1]	auto[0]	auto[0]	5459	1			T1	20		T14	11		T27	2
fifo_depth[5]	auto[1]	auto[0]	auto[1]	4089	1			T1	106		T35	58		T28	102
fifo_depth[5]	auto[1]	auto[1]	auto[0]	5619	1			T1	24		T15	2		T35	11
fifo_depth[5]	auto[1]	auto[1]	auto[1]	6650	1			T1	58		T35	23		T27	2
fifo_depth[6]	auto[0]	auto[0]	auto[0]	1630	1			T1	48		T114	10		T35	18
fifo_depth[6]	auto[0]	auto[0]	auto[1]	1865	1			T1	26		T35	96		T27	5
fifo_depth[6]	auto[0]	auto[1]	auto[0]	137412	1			T1	31		T2	28		T10	1082
fifo_depth[6]	auto[0]	auto[1]	auto[1]	1657	1			T1	58		T26	5		T35	1
fifo_depth[6]	auto[1]	auto[0]	auto[0]	5241	1			T1	16		T14	6		T27	2
fifo_depth[6]	auto[1]	auto[0]	auto[1]	4117	1			T1	124		T35	52		T27	1
fifo_depth[6]	auto[1]	auto[1]	auto[0]	5374	1			T1	25		T35	15		T27	1
fifo_depth[6]	auto[1]	auto[1]	auto[1]	6645	1			T1	56		T35	23		T29	275
fifo_depth[7]	auto[0]	auto[0]	auto[0]	1458	1			T1	52		T114	10		T35	15
fifo_depth[7]	auto[0]	auto[0]	auto[1]	1635	1			T1	21		T35	102		T27	2
fifo_depth[7]	auto[0]	auto[1]	auto[0]	121855	1			T1	24		T2	7		T10	775
fifo_depth[7]	auto[0]	auto[1]	auto[1]	1614	1			T1	49		T35	1		T14	50
fifo_depth[7]	auto[1]	auto[0]	auto[0]	5009	1			T1	16		T14	9		T27	2
fifo_depth[7]	auto[1]	auto[0]	auto[1]	3905	1			T1	87		T35	40		T28	87
fifo_depth[7]	auto[1]	auto[1]	auto[0]	5211	1			T1	32		T35	6		T132	11
fifo_depth[7]	auto[1]	auto[1]	auto[1]	6417	1			T1	59		T35	25		T29	266