Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	34709993	1			T1	13719		T2	293545		T3	992
all_pins[1]	34709993	1			T1	13719		T2	293545		T3	992
all_pins[2]	34709993	1			T1	13719		T2	293545		T3	992

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	86463126	1			T1	36316		T2	734965		T3	1993
values[0x1]	17666853	1			T1	4841		T2	145670		T3	983
transitions[0x0=>0x1]	17666683	1			T1	4841		T2	145670		T3	983
transitions[0x1=>0x0]	17666688	1			T1	4841		T2	145670		T3	983

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	34657588	1			T1	13685		T2	293159		T3	991
all_pins[0]	values[0x1]	52405	1			T1	34		T2	386		T3	1
all_pins[0]	transitions[0x0=>0x1]	52381	1			T1	34		T2	386		T3	1
all_pins[0]	transitions[0x1=>0x0]	17611254	1			T1	4807		T2	145284		T3	982
all_pins[1]	values[0x0]	34706818	1			T1	13719		T2	293545		T3	992
all_pins[1]	values[0x1]	3175	1			T5	43		T6	86		T14	2
all_pins[1]	transitions[0x0=>0x1]	3049	1			T5	42		T6	83		T14	2
all_pins[1]	transitions[0x1=>0x0]	52279	1			T1	34		T2	386		T3	1
all_pins[2]	values[0x0]	17098720	1			T1	8912		T2	148261		T3	10
all_pins[2]	values[0x1]	17611273	1			T1	4807		T2	145284		T3	982
all_pins[2]	transitions[0x0=>0x1]	17611253	1			T1	4807		T2	145284		T3	982
all_pins[2]	transitions[0x1=>0x0]	3155	1			T5	43		T6	86		T14	2